| * |
| * ****************************************************************************** |
| * * * |
| * * Copyright (C) 2004-2010, Nangate Inc. * |
| * * All rights reserved. * |
| * * * |
| * * Nangate and the Nangate logo are trademarks of Nangate Inc. * |
| * * * |
| * * All trademarks, logos, software marks, and trade names (collectively the * |
| * * "Marks") in this program are proprietary to Nangate or other respective * |
| * * owners that have granted Nangate the right and license to use such Marks. * |
| * * You are not permitted to use the Marks without the prior written consent * |
| * * of Nangate or such third party that may own the Marks. * |
| * * * |
| * * This file has been provided pursuant to a License Agreement containing * |
| * * restrictions on its use. This file contains valuable trade secrets and * |
| * * proprietary information of Nangate Inc., and is protected by U.S. and * |
| * * international laws and/or treaties. * |
| * * * |
| * * The copyright notice(s) in this file does not indicate actual or intended * |
| * * publication of this file. * |
| * * * |
| * * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * |
| * * * |
| * ****************************************************************************** |
| * |
| * |
| * Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). |
| * Local time is now Fri, 3 Dec 2010, 18:55:07. |
| * Main process id is 28006. |
| * |
| ******************************************************************************** |
| * * |
| * Cellname: TLAT_X1. * |
| * * |
| * Technology: NCSU FreePDK 45nm. * |
| * Format: Cdl. * |
| * * |
| * Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) * |
| * at 18:55:07 on Fri, 3 Dec 2010. * |
| * * |
| ******************************************************************************** |
| .SUBCKT TLAT_X1 D G OE Q VDD VSS |
| *.PININFO D:I G:I OE:I Q:O VDD:P VSS:G |
| M_i_0 VSS G net_000 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_7 net_001 net_000 VSS VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_13 net_002 D VSS VSS NMOS_VTL W=0.275000U L=0.050000U |
| M_i_18 net_003 net_001 net_002 VSS NMOS_VTL W=0.275000U L=0.050000U |
| M_i_24 net_004 net_000 net_003 VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_28 VSS net_006 net_004 VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_40 VSS net_003 net_006 VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_34 net_005 OE VSS VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_47 net_007 net_003 VSS VSS NMOS_VTL W=0.355000U L=0.050000U |
| M_i_51 Q OE net_007 VSS NMOS_VTL W=0.355000U L=0.050000U |
| M_i_57 VDD G net_000 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_64 net_001 net_000 VDD VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_70 net_008 D VDD VDD PMOS_VTL W=0.420000U L=0.050000U |
| M_i_75 net_003 net_000 net_008 VDD PMOS_VTL W=0.420000U L=0.050000U |
| M_i_81 net_009 net_001 net_003 VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_85 VDD net_006 net_009 VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_99 VDD net_003 net_006 VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_91 net_005 OE VDD VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_106 net_010 net_003 VDD VDD PMOS_VTL W=0.540000U L=0.050000U |
| M_i_111 Q net_005 net_010 VDD PMOS_VTL W=0.540000U L=0.050000U |
| .ENDS |
| |
| ******************************************************************************** |
| * |
| * END |
| * |
| ******************************************************************************** |
