| * |
| * ****************************************************************************** |
| * * * |
| * * Copyright (C) 2004-2010, Nangate Inc. * |
| * * All rights reserved. * |
| * * * |
| * * Nangate and the Nangate logo are trademarks of Nangate Inc. * |
| * * * |
| * * All trademarks, logos, software marks, and trade names (collectively the * |
| * * "Marks") in this program are proprietary to Nangate or other respective * |
| * * owners that have granted Nangate the right and license to use such Marks. * |
| * * You are not permitted to use the Marks without the prior written consent * |
| * * of Nangate or such third party that may own the Marks. * |
| * * * |
| * * This file has been provided pursuant to a License Agreement containing * |
| * * restrictions on its use. This file contains valuable trade secrets and * |
| * * proprietary information of Nangate Inc., and is protected by U.S. and * |
| * * international laws and/or treaties. * |
| * * * |
| * * The copyright notice(s) in this file does not indicate actual or intended * |
| * * publication of this file. * |
| * * * |
| * * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * |
| * * * |
| * ****************************************************************************** |
| * |
| * |
| * Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). |
| * Local time is now Fri, 3 Dec 2010, 18:56:22. |
| * Main process id is 28006. |
| * |
| ******************************************************************************** |
| * * |
| * Cellname: SDFFS_X2. * |
| * * |
| * Technology: NCSU FreePDK 45nm. * |
| * Format: Cdl. * |
| * * |
| * Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) * |
| * at 18:56:22 on Fri, 3 Dec 2010. * |
| * * |
| ******************************************************************************** |
| .SUBCKT SDFFS_X2 D SE SI SN CK Q QN VDD VSS |
| *.PININFO D:I SE:I SI:I SN:I CK:I Q:O QN:O VDD:P VSS:G |
| M_i_0 VSS SE net_000 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_21 VSS D net_003 VSS NMOS_VTL W=0.275000U L=0.050000U |
| M_i_17 net_003 net_000 net_002 VSS NMOS_VTL W=0.275000U L=0.050000U |
| M_i_11 net_002 SE net_001 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_7 net_001 SI VSS VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_27 VSS CK net_004 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_34 net_005 net_004 VSS VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_40 net_006 net_002 VSS VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_45 net_007 net_004 net_006 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_51 net_008 net_005 net_007 VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_56 net_009 net_010 net_008 VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_60 VSS SN net_009 VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_73 net_011 net_007 VSS VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_77 net_012 net_005 net_011 VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_83 net_013 net_004 net_012 VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_87 VSS net_015 net_013 VSS NMOS_VTL W=0.090000U L=0.050000U |
| M_i_66 net_010 net_007 VSS VSS NMOS_VTL W=0.210000U L=0.050000U |
| M_i_93 net_014 SN net_015 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_97 VSS net_012 net_014 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_110_2 Q net_012 VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_110 Q net_012 VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_103 VSS net_015 QN VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_103_26 VSS net_015 QN VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_116 VDD SE net_000 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_123 net_016 D VDD VDD PMOS_VTL W=0.420000U L=0.050000U |
| M_i_127 net_002 SE net_016 VDD PMOS_VTL W=0.420000U L=0.050000U |
| M_i_133 net_017 net_000 net_002 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_137 VDD SI net_017 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_143 VDD CK net_004 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_150 net_005 net_004 VDD VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_157 net_018 net_002 VDD VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_162 net_007 net_005 net_018 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_168 net_019 net_004 net_007 VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_172 VDD net_010 net_019 VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_178 net_019 SN VDD VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_197 net_021 net_007 VDD VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_201 net_012 net_004 net_021 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_208 net_022 net_005 net_012 VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_212 VDD net_015 net_022 VDD PMOS_VTL W=0.090000U L=0.050000U |
| M_i_189 VDD net_007 net_010 VDD PMOS_VTL W=0.315000U L=0.050000U |
| M_i_218 net_015 SN VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_224 VDD net_012 net_015 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_237_1 Q net_012 VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_237 Q net_012 VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_230 VDD net_015 QN VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_230_17 VDD net_015 QN VDD PMOS_VTL W=0.630000U L=0.050000U |
| .ENDS |
| |
| ******************************************************************************** |
| * |
| * END |
| * |
| ******************************************************************************** |
