blob: 779e0044b3bd7a271da82accbf97a66c742a59c7 [file] [log] [blame]
*
* ******************************************************************************
* * *
* * Copyright (C) 2004-2010, Nangate Inc. *
* * All rights reserved. *
* * *
* * Nangate and the Nangate logo are trademarks of Nangate Inc. *
* * *
* * All trademarks, logos, software marks, and trade names (collectively the *
* * "Marks") in this program are proprietary to Nangate or other respective *
* * owners that have granted Nangate the right and license to use such Marks. *
* * You are not permitted to use the Marks without the prior written consent *
* * of Nangate or such third party that may own the Marks. *
* * *
* * This file has been provided pursuant to a License Agreement containing *
* * restrictions on its use. This file contains valuable trade secrets and *
* * proprietary information of Nangate Inc., and is protected by U.S. and *
* * international laws and/or treaties. *
* * *
* * The copyright notice(s) in this file does not indicate actual or intended *
* * publication of this file. *
* * *
* * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 *
* * *
* ******************************************************************************
*
*
* Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr).
* Local time is now Fri, 3 Dec 2010, 19:06:53.
* Main process id is 28006.
*
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* *
* Cellname: OAI221_X2. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:06:53 on Fri, 3 Dec 2010. *
* *
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.SUBCKT OAI221_X2 A B1 B2 C1 C2 ZN VDD VSS
*.PININFO A:I B1:I B2:I C1:I C2:I ZN:O VDD:P VSS:G
*.EQN ZN=!(((C1 + C2) * A) * (B1 + B2))
M_i_1__m0 ZN C2 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m0 net_0 C1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_0__m1 ZN C1 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_1__m1 net_0 C2 ZN VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_1 net_1 A net_0 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m0 VSS B1 net_1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4__m1 net_1 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_4__m0 VSS B2 net_1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_3__m1 net_1 B1 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_2_0 net_0 A net_1 VSS NMOS_VTL W=0.415000U L=0.050000U
M_i_6__m0 net_2__m0_0 C2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m0 ZN C1 net_2__m0_0 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_5__m1 net_2__m1 C1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_6__m1 VDD C2 net_2__m1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7_0 ZN A VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8__m1 net_3__m1 B1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9__m1 VDD B2 net_3__m1 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_9__m0 net_3__m0_0 B2 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_8__m0 ZN B1 net_3__m0_0 VDD PMOS_VTL W=0.630000U L=0.050000U
M_i_7_1 VDD A ZN VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
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*
* END
*
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