blob: 6ec324150a81740e74e227ac087fefa9bcd2a6a8 [file] [log] [blame]
*
* ******************************************************************************
* * *
* * Copyright (C) 2004-2010, Nangate Inc. *
* * All rights reserved. *
* * *
* * Nangate and the Nangate logo are trademarks of Nangate Inc. *
* * *
* * All trademarks, logos, software marks, and trade names (collectively the *
* * "Marks") in this program are proprietary to Nangate or other respective *
* * owners that have granted Nangate the right and license to use such Marks. *
* * You are not permitted to use the Marks without the prior written consent *
* * of Nangate or such third party that may own the Marks. *
* * *
* * This file has been provided pursuant to a License Agreement containing *
* * restrictions on its use. This file contains valuable trade secrets and *
* * proprietary information of Nangate Inc., and is protected by U.S. and *
* * international laws and/or treaties. *
* * *
* * The copyright notice(s) in this file does not indicate actual or intended *
* * publication of this file. *
* * *
* * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 *
* * *
* ******************************************************************************
*
*
* Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr).
* Local time is now Fri, 3 Dec 2010, 19:17:24.
* Main process id is 28034.
*
********************************************************************************
* *
* Cellname: FA_X1. *
* *
* Technology: NCSU FreePDK 45nm. *
* Format: Cdl. *
* *
* Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) *
* at 19:17:24 on Fri, 3 Dec 2010. *
* *
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.SUBCKT FA_X1 A B CI CO S VDD VSS
*.PININFO A:I B:I CI:I CO:O S:O VDD:P VSS:G
*.EQN CO=((A * B) + (CI * (A + B)));S=(CI ^ (A ^ B))
M_instance_159 CO net_001 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_instance_166 VSS B net_000 VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_170 net_000 A net_001 VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_176 net_001 CI net_002 VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_188 net_002 A VSS VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_182 VSS B net_002 VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_227 net_006 B VSS VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_215 VSS CI net_006 VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_221 net_006 A VSS VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_209 net_005 net_001 net_006 VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_203 net_004 CI net_005 VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_199 net_003 B net_004 VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_194 VSS A net_003 VSS NMOS_VTL W=0.210000U L=0.050000U
M_instance_233 S net_005 VSS VSS NMOS_VTL W=0.415000U L=0.050000U
M_instance_239 CO net_001 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
M_instance_246 VDD B net_007 VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_251 net_007 A net_001 VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_257 net_001 CI net_008 VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_269 net_008 A VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_263 VDD B net_008 VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_309 net_011 B VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_297 VDD CI net_011 VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_303 net_011 A VDD VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_290 net_005 net_001 net_011 VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_284 net_010 CI net_005 VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_280 net_009 B net_010 VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_275 VDD A net_009 VDD PMOS_VTL W=0.315000U L=0.050000U
M_instance_315 S net_005 VDD VDD PMOS_VTL W=0.630000U L=0.050000U
.ENDS
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*
* END
*
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