| * |
| * ****************************************************************************** |
| * * * |
| * * Copyright (C) 2004-2010, Nangate Inc. * |
| * * All rights reserved. * |
| * * * |
| * * Nangate and the Nangate logo are trademarks of Nangate Inc. * |
| * * * |
| * * All trademarks, logos, software marks, and trade names (collectively the * |
| * * "Marks") in this program are proprietary to Nangate or other respective * |
| * * owners that have granted Nangate the right and license to use such Marks. * |
| * * You are not permitted to use the Marks without the prior written consent * |
| * * of Nangate or such third party that may own the Marks. * |
| * * * |
| * * This file has been provided pursuant to a License Agreement containing * |
| * * restrictions on its use. This file contains valuable trade secrets and * |
| * * proprietary information of Nangate Inc., and is protected by U.S. and * |
| * * international laws and/or treaties. * |
| * * * |
| * * The copyright notice(s) in this file does not indicate actual or intended * |
| * * publication of this file. * |
| * * * |
| * * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * |
| * * * |
| * ****************************************************************************** |
| * |
| * |
| * Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). |
| * Local time is now Fri, 3 Dec 2010, 19:17:48. |
| * Main process id is 28006. |
| * |
| ******************************************************************************** |
| * * |
| * Cellname: AOI21_X4. * |
| * * |
| * Technology: NCSU FreePDK 45nm. * |
| * Format: Cdl. * |
| * * |
| * Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) * |
| * at 19:17:48 on Fri, 3 Dec 2010. * |
| * * |
| ******************************************************************************** |
| .SUBCKT AOI21_X4 A B1 B2 ZN VDD VSS |
| *.PININFO A:I B1:I B2:I ZN:O VDD:P VSS:G |
| *.EQN ZN=!(A + (B1 * B2)) |
| M_i_2_0 ZN A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_1 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_2 ZN A VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2_3 VSS A ZN VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_1__m0 net_0__m0_0 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0__m0 ZN B1 net_0__m0_0 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0__m1 net_0__m1 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_1__m1 VSS B2 net_0__m1 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_1__m2 net_0__m2 B2 VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0__m2 ZN B1 net_0__m2 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_0__m3 net_0__m3 B1 ZN VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_1__m3 VSS B2 net_0__m3 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_5_0 VDD A net_1 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_5_1 net_1 A VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_5_2 VDD A net_1 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_5_3 net_1 A VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_4__m0 ZN B2 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3__m0 net_1 B1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3__m1 ZN B1 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_4__m1 net_1 B2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_4__m2 ZN B2 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3__m2 net_1 B1 ZN VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_3__m3 ZN B1 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_4__m3 net_1 B2 ZN VDD PMOS_VTL W=0.630000U L=0.050000U |
| .ENDS |
| |
| ******************************************************************************** |
| * |
| * END |
| * |
| ******************************************************************************** |
