| * |
| * ****************************************************************************** |
| * * * |
| * * Copyright (C) 2004-2010, Nangate Inc. * |
| * * All rights reserved. * |
| * * * |
| * * Nangate and the Nangate logo are trademarks of Nangate Inc. * |
| * * * |
| * * All trademarks, logos, software marks, and trade names (collectively the * |
| * * "Marks") in this program are proprietary to Nangate or other respective * |
| * * owners that have granted Nangate the right and license to use such Marks. * |
| * * You are not permitted to use the Marks without the prior written consent * |
| * * of Nangate or such third party that may own the Marks. * |
| * * * |
| * * This file has been provided pursuant to a License Agreement containing * |
| * * restrictions on its use. This file contains valuable trade secrets and * |
| * * proprietary information of Nangate Inc., and is protected by U.S. and * |
| * * international laws and/or treaties. * |
| * * * |
| * * The copyright notice(s) in this file does not indicate actual or intended * |
| * * publication of this file. * |
| * * * |
| * * buildcell, v2010.08-HR32-SP3-2010-08-05 - build 1009061800 * |
| * * * |
| * ****************************************************************************** |
| * |
| * |
| * Running on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr). |
| * Local time is now Fri, 3 Dec 2010, 19:12:03. |
| * Main process id is 28034. |
| * |
| ******************************************************************************** |
| * * |
| * Cellname: AOI211_X4. * |
| * * |
| * Technology: NCSU FreePDK 45nm. * |
| * Format: Cdl. * |
| * * |
| * Written on brazil06.nangate.com.br for user Giancarlo Franciscatto (gfr) * |
| * at 19:12:03 on Fri, 3 Dec 2010. * |
| * * |
| ******************************************************************************** |
| .SUBCKT AOI211_X4 A B C1 C2 ZN VDD VSS |
| *.PININFO A:I B:I C1:I C2:I ZN:O VDD:P VSS:G |
| *.EQN ZN=!(!(!(((C1 * C2) + B) + A))) |
| M_i_0 net_0 C1 ZN_3 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_1 VSS C2 net_0 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_2 ZN_3 B VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_3 VSS A ZN_3 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_8_0 ZN_4 ZN_3 VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_8_1 VSS ZN_3 ZN_4 VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_10_0 ZN ZN_4 VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_10_1 VSS ZN_4 ZN VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_10_2 ZN ZN_4 VSS VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_10_3 VSS ZN_4 ZN VSS NMOS_VTL W=0.415000U L=0.050000U |
| M_i_4 ZN_3 C1 net_1 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_5 net_1 C2 ZN_3 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_6 net_2 B net_1 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_7 VDD A net_2 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_9_0 ZN_4 ZN_3 VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_9_1 VDD ZN_3 ZN_4 VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_11_0 ZN ZN_4 VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_11_1 VDD ZN_4 ZN VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_11_2 ZN ZN_4 VDD VDD PMOS_VTL W=0.630000U L=0.050000U |
| M_i_11_3 VDD ZN_4 ZN VDD PMOS_VTL W=0.630000U L=0.050000U |
| .ENDS |
| |
| ******************************************************************************** |
| * |
| * END |
| * |
| ******************************************************************************** |
