Nangate 45nm Open Cell Library
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The Nangate Open Cell Library is an open-source, standard-cell library provided for the purposes of testing and exploring EDA flows.

Nangate has developed and donated this library to Si2.org for open use. The library is intended to aid university research programs
and organizations such as Si2 in developing flows, developing circuits and exercising new algorithms. In its first release the 
Open Cell Library contains 38 different functions ranging from buffers to scan flip-flops with set and reset. All the different 
cell functions come in multiple drive strength variants end up with more than 100 different cells in the library. 

The library was generated using Nangate's Library Creator™ and the 45nm FreePDK Base Kit from North Carolina State University (NCSU) 
and characterization was done using the Predictive Technology Model (PTM) from Arizona State University (ASU). 

The library will be enhanced over time based on user suggestions and requests. If you have suggestions for development of 
the library then please fill out the request form you can find at www.opencelllibrary.org with your suggestions.

The Open Cell Library contains the following views:

    * Liberty (.lib) with NLDM/NLPM, CCS Timing and ECSM Timing data
    * LEF View
    * Verilog(R)
    * VITAL (VHDL Initiative Towards ASIC Libraries)
    * Spice netlists (pre and post extraction)
    * GDSII
    * Schematics
    * Library databook in HTML/XML format
    * OpenAccess library databases with layouts and netlists

See the LICENSE file for information on license terms.

Revision History:
----------------------------------------------------

Version v2010_12 (released August 2011)
- Improved sizing of all cells
- Included VITAL (VHDL Initiative Towards ASIC Libraries) views
- Included Cadence Virtuoso database
- Added a set of low power cells
- New IP release directory structure

Version v2009_07 (released July 2009)
- Updated to support FreePDK v1.3 package from NCSU released March 4, 2009
- Changed manufacturing grid size from 2.5nm to 5nm as the previous size is not supported in some P&R tools
- Changed via definitions in Calibre rule files in order to have more realistic values out of extraction
- Added capacitance tables (PTF and CapTbl) for wire load extraction
- Added two corners covering temperature inversion effects (low temperature and worst low temperature)
- Added schematic views in EDIF format
- Added wire load tables in Liberty views
- Added conditional rules in LEF views

Version v2008_10_SP1 (Service Pack 1 for the October 2008 relese)
- Updated LEF views to solve problems of vias not being create for Metal 3 wires

Version v2008_10 (released October 2008)
- Added clock gates with and without test as new functions to the library
- Added taps to all filler cells
- Updated OpenAccess views to support Cadence SoC Encounter 6.2 platform
- Updated layouts (GDS) to ensure all ports were on grid
- Updated LEF views to avoid issues seen with various Place & Route flows

Version v2008_05 (released May 2008)
- Updated to support FreePDK45 version 1.2 from NCSU released March 10, 2008
- Added additional layer definitions in LEF views
- Added Tri-state buffers, latches and inverters 
- Added Half and Full adder
- Added Clock buffers
- Added CCS Timing and ECSM Timing characterization results in Liberty format
- Added 3 corners characterization (slow, typical and fast)
- Added OpenAccess library databases
- Added technology directory containing:
 - Spice models used for Characterization (HSpice/Nanspice compatible)
 - Calibre Runset files for DRC/LVS and xRC
 - DFM kit for use with Ponte Solutions (now Mentor Graphics) Yield Analyzer
 
Version 1.00 (released February 2008)
Initial release of the Open Cell Library using:
- FreePDK45 version 1.1 from NCSU released 2007-09-19
- The 45nm BSIM4 model card for bulk CMOS V1.0 from ASU released 2006-02-22 (http://www.eas.asu.edu/~ptm/modelcard/2006/45nm_bulk.pm)