

// ********************************************************
// Copyright (c) 2020 by SkyWater Technology
// SkyWater Confidential Information
// ********************************************************

////////////////////////////////////////////////////////////////////////////////
//
// =========================
// Comments / Update Section
// =========================
//
// ========== ======== ========================================================
// Date       Modifier Notes
// ========== ======== ========================================================
//  3/24/2020  JAG     New DRC runset
//              &
//              RY
//  6/17/2020  JAG     Corrected message for met2.ENC.2 to read 0.085 (was 0.06)
//                     Updated lonely via/contact code to correct errors
//                     Improved latchup error messages
//  6/25/2020  JAG     Added layer thkox - v5 is now only a marker layer
//                       and thkox is a mask layer for thick oxide.
//                     Adjusted numerous rules for this change.
//  6/29/2020  JAG     Changed licon.ENC.6 to use polyi rather than poly to
//                       avoid false flag in HP/HS poly res
//                     Changed pwres.CON.5 to use nw_hole rather than pwell to
//                       avoid false flag in pwres pcell
//                     Changed non-manhatten check on poly to ignore poly in
//                       npn to avoid error
//                     Changed poly.OVL.3 to not flag 5v npn
//  6/30/2020  JAG     Modified nsdm.ENC.1 to avoid checking the 5v npn's 
//                       internal octagonal nsdm
//                     Rewrote v5.SP.1 to remove false flags
//  7/09/2020  JAG     Updated seal ring rules to accomodate new seal ring pcell
//  7/10/2020  JAG     Updated pad rules
//  7/13/2020  JAG     Updated valid pads to include S8 definition for backwards
//                       compatibility
//  7/20/2020   RY     Revamped the DENMOS and DEPMOS checks
//  7/20/2020  JAG     Changed definition of pwellSigPadNtr to include ptub
//  7/23/2020  JAG     Removed old latchup rule numbers from latchup rules
//  7/24/2020  JAG     Added new lonely via contact checks
//  7/26/2020  JAG     Finished adding supplemental recommended lonely via rules
//                     Fixed some syntax and spelling issues
//                     Standardized many rules with cap first letter and value
//                       following rule text
//  7/29/2020  JAG     Converted latchup rules from verbatim to TVF 
//  7/30/2020  JAG     Implemented new floating net rule and removed old
//  	       	         floating layer rules (now based on devices from LVS)
//  8/04/2020  JAG     Removed redundant "difftap.SP.6" from rule message
//                     Removed "m2.3c" from met2.CON.8 message
//                     Added missing message to latchup.1
//                     Updated definition of bond pad recognition for stress
//		         checks
//  8/07/2020  JAG     Removed a debug output statement
//  8/12/2020  JAG     Updated some via enclosure messages to include "by met"
//  8/14/2020  JAG     Added rule name back to message at request of layout
//  	       	         design
//  8/20/2020  JAG     Removed use of areaid/extDrain20 and replaced any usage
//  	       	         with ENID as areaid/extDrain20 was removed from the
//			 tech file as obsolete
//                     Corrected rule v20.ENC.2 to correct spelling error
//  8/27/2020  JAG     Added 20V net identification
//                     Enhanced net idenification by voltage markers
//                     Added some but not all voltage rules
//  9/02/2020  JAG     Reverted net identification by enclosed marker
//  9/04/2020  JAG     Started adding new 20v denmos/depmos rules
//  9/10/2020  JAG     Removed V20.ENC.2 as it is not needed
//                     Removed pad.CON.2 text pad must have text "plastic"
//  9/11/2020  JAG     Changed definition of diffHV to use diffi not diff
//  9/14/2020  JAG     Changed v12.OVL.7 to use polyi and avoid poly inside v12
//                     Added rule to check that v20 doesn't straddle poly
//                     Changed some pad rules to not false flag probe pads
//                     Changed rule v20.ENC.3 to v20.ENC.2 and rewrote to
//                       check for dnw interact v20 must be covered by v20
//  9/15/2020  JAG     Rewrote Hdifftap.WID.3/4 as they were not flagging
//  	       	         testcases
//  9/23/2020  JAG     Added rules to enforce proper use of areaid/pad_io,
//  	       	         pad_pwr and pad_gnd
//                     Added substrateCut softcheck - sub cut with no ptap
//  9/24/2020  JAG     Changed lvtn.SP.3 from 0.235 to 0.19 per Xena ticket #282
// 10/12/2020  JAG     Added illegal device checks originally coded in the LVS
// 10/19/2020  JAG     Finished updating and testing illegal device code
// 11/05/2020  JAG     Revised all Latch-Up checks to new document
//                     Removed dnw not over ptub from ptap definition
// 11/13/2020  JAG     Updated denmos_20.SP.8 to redefine ptap def for iso nmos
//                       20v
// 11/14/2020  JAG     Updated the ILLEGAL DEVICE rules (WIP) up to NMOS
//  	       	         The remainder are in dev
// 11/24/2020  JAG     Updated Device rules from Device Table
// 11/30/2020  JAG     Updated latch-up rules
// 12/01/2020  JAG     Changed via to via1
//
// -----
// Q4.02
// -----
// 12/03/2020  JAG     Updates for Q4.02:
//                       Changed via to via in relevent places
//                   	 Changed li1 to li
//                   	 Changed licon1 to licon
//                   	 Changed illegal device check for dnsd_pw_nat to allow
//			   thkox
//                   	 Changed illegal device check for pad to disallow met4
//                   	 Changed illegal device check for pnp to allow hvtp
//                   	 Changed illegal device check for npn to allow ldntm
//                   	 Changed illegal device check for pwres to allow npn/pnp
//                   	 Added CON rule to insure npn/pnp are only in allowed
//			   cells
//		     	 Updated rules to use new layer names
//                       Rewrote li.WID.3 to fix false errors
//			 Updated cap2m.SP.2 as it was flagging cap2m to unrelated
//			   met4
// 12/26/2020  JAG     Merged in fill layers with dwg layers
// ---------------------------------------------------------------------------
// 01/04/2021  JAG     Corrected met4_block layer number
//                     Added definition for diff/poly block and added to 
//                       predicitive fill so it will NOT generate predictive
//                       poly or diff fill inside respective block layers.
// 01/07/2021  JAG     Added new checks for LVS_exclude layer
// 01/08/2021   RY     Revamped the diffTap checks to diff checks to remove the
// 		         old tap layer references
// 01/11/2021  JAG     Renamed HdifHtap rules to diff_v5.
// 01/18/2021  JAG     Added new fill rules
//                     Updated prune.CON.1 and renamed LVS_exclude.OVL.1
// 01/19/2021  JAG     Renamed psd/nsd.ENC.4 to psd/nsd.ENC.3
// 01/20/2021  JAG     Removed references to pwelliso and pwell_dg
// 01/21/2021  JAG     Removed licon.SP.13 as duplicate of licon.SP.11
// 01/22/2021  JAG     Updated cap/cap2m to prohibit L-shaped capm/cap2m 
//                      (modified capm.CON.5 & cap2m.CON.4)
// 01/25/2021  JAG     Added rule pwbm.OVL.1
//                     Added rules met2.AR.2 and met1.AR.2
// 01/28/2021  JAG     Added urpm.ANG.3
// 02/01/2021  JAG     Modified licon.ANG.1 as it referenced li not licon in msg
//                      and changed name from licon_not_seal.ANG.1 to licon.ANG.1
//                     Removed fuse.CON.4 (check of tap over target as it is checked for diff already)
//                     Changed fuse.SP.1 spacing from 3.295 to 2.75 
// 02/03/2021  JAG     Added pad.SP.6 and pad.AR.1
//                     Added v5.OVL.12
// 02/05/2021  JAG     Combined rules metx.SP.2a and metxSP.2b into metx.SP.2 
//                      for met1-met4
// 02/09/2021  JAG     Renamed all DRC checks with "OVLP" to "OVL" such as:
//                      rule_name.OVLP.num to rule_name.OVL.num
//                      to standardize 
//                     Removed rule PAD.AR.1 per Pete and Sam
// 02/26/2021  JAG     Changed instances of "inside core" or "in core" to areaid:core
//                     Changed instances of "inside seal" or "in seal" to areaid:seal
// 03/02/2021  JAG     Updated the pad rules to account for Pcell change in 
//                      areaid:padLength rect.
// 03/02/2021  JAG     Renamed rule met2.CON.8 to met2.ANT.2 and moved to antenna
//                      section as a recommended antenna rule. Also inverted the
//                      ratios to improve readibility.
// 03/08/2021  JAG     Corrected pad.SP.11 as it was checking met1 under pad which
//                      was cut by met1/res - changed to check met1 input
//                     Changed diff_5v definition of hv_diff to be NOT tap
//                      after comparing IO Lib results btw s8 and s130
//                     Corrected poly res term definition for float checks
// 03/09/2021  JAG     Rewrote v5.OVL.3 as it was just plain wrong
// 03/10/2021  JAG     Made same corrections to v12.OVL.3
//                     Removed rule v5.OVL.3 as it was coded in error.
// 03/11/2021  JAG     Added poly check for anchor min width
// 03/12/2021  JAG     Modified two diff_5v rules to remove tap which should not
//                      have been checked after getting false errors in IO Libs
// 03/12/2021  JAG     Rewrote wide metal spacing checks after consult with SV to verify code
//                      and added a keep layer for wide metal derivation
//                     Renamed metals.WID.stress.1 and created 5 rules as metx_stress.WID.1
// 03/15/2021  JAG     Removed thkox from rndiff_v5 rpdiff_v5 illegal device list
//                     Added code to illegal device checks to use areaid names
//                     Combined stress.CON.7 and stress.CON.8 to 1 rule
// 03/16/2021  JAG     Updated verbiage in messages for stress.SP.1 stress.ENC.2 & stress.CON.9
//                     Changed viax.viay.stress.CON.1 rules to viax.viay.anchor.CON.2 rules
//                      because it makes more sense as they tested via overlap in anchors
// 03/17/2021  JAG     Renamed metx.stress.CON.9 to metx.SLOT.CON.9
// 03/18/2021  JAG     Removed non-octagonal check for pnp as it is checked to be in pcell
// 03/24/2021  JAG     Renamed pwbm.OVL.1 as pwbm.ENC.2 after review showed
//                      pwbm.OVL.1 was flagging legal 20v de devices
// 03/25/2021  JAG     Removed poly endcaps from lonely licon checks
//                     Exempted poly, li, m1-m5 inside text_pcell from
//                      floating net checks
// 03/26/2021  JAG     Removed checks for poly and diff boundary layer
//                      since these were removed from the tech file
// 02/28/2021  JAG     Modified poly.SP.7 to only check HP/HP2K res to diff
// 03/31/2021  JAG     Added missing licon.anchor.SP.1 rule
// 04/14/2021  JAG     SWT changed device table to allow devices under pad
//                      and other changes (eg met res over other layers)
//                      so created skip_pad, skip_res and skip_dnw to
//                      skip checking some devices and clean up IO Lib. 
// 04/14/2021  JAG     Added nmos_esd to illegal device checks
//
// -----
// Q5.01
// -----
//
// 04/16/2021  JAG     Removed old hv checks based on diff:hv marker and put in new
//                      hv checks based on v12 or v20 over diff (src/drn)
// 04/20/2021  JAG     Removed check npc.ENC.1 per PM
// 04/22/2021  JAG     Removed core from met1.ENC.1 and 1a
//                     Added licon.SP.13 for poly licon space to diff in core
//                     Added licon.SP.14 licon min space in core
//                     Added licon.CON.12 for core psdm prohibited over poly licon
//                     Added met2.ENC.3 min enclosure of via1 by met2 in core
//                     Changed rule diff_5v.WID.2 to thkox.WID.2 for diff width 
//                      inside thkox inside core
//                     Split rule li.WID.1 into two rules li.WID.1/2/3 for
//                       width of li in/out of vpp/core
//                       and moved old li.WID.3 to li.WID.4
// 04/23/2021  JAG     Modified v5/v12/v20.CON.9 to include diff in check to 
//                       ensure they are over thkox.
//                     Changed  via.CON.10 to check all vias and deleted via ring
//                       check in seal ring
//                     Deleted via size in seal ring checks (no via/conts in seal)
//                     Removed construction checks which ensure rings shaped vias
//                      and contacts are only in the seal ring
//                     Renamed npc.ENC.1 as licon.ENC.8 for consistency
// 04/28/2021  JAG     Exempted LATCHUP.generic.2a/b for areas covered by areaid:ESD
//                     Corrected latchup.misc.4 to removed gates under areaid:ESD
//
// -----
// Q6.01
// -----
//
// 05/03/2021  JAG     Updated exemptions for floating metals/poly to include anchor
//                      areas to avoid flagging anchors.
// 05/05/2021  JAG     Removed nsd in isolated p-substrate from rule latchup.signal.12g 
//                      per PM @ SWT
//                     Rewrote latchup.signal.2.1b as it was false flagging the level
//                      shifter design
// 05/05/2021  JAG     Rewrote latchup.shv.1 based on work done on latchup.signal.2.1b
//                     Changed fill construction checks for non-floating fill to not check
//                      anchor region in the unlikely event that users put in fill layers
//                      rather than drawing layers in for anchors.
// 05/10/2021  JAG     Modified the v5/v12/v20 nwell derivation to find the highest
//                      voltage marker over an nwell to use it to identify nwell voltage
//                     Added word "WARNING" to nwell of one voltage must not be connected
//                      to nwell of another voltage
// 05/17/2021  JAG     Removed rule v12.SP.1 NW 12V check for 11.24u per PM
//                     Removed use of DFM commands in pad rules
// 05/19/2021  JAG     Updated dnwell.CON.2 to check all P+ diff not just P+ src/drns
//                      Added REGION to many ENC checks to improve visibility
// 05/20/2021  JAG     Removed s8_plowvt exemptions from poly.LEN.1
//                     Removed M5RDL via pcell exemption from bond pad checks
//                     Removed psoc4*_top exemption from from bond pad checks
//                     Removed tsg5_m_tcg5_top exemption from from bond pad checks
//                     Removed s8hpbtoolkit_dual_rx_2* exemption from from bond pad checks
//                     Removed s8hpbtoolkit_dual_rx_inv* exemption from from bond pad checks
//                     Removed s8bio_top_biocmux_vccio* exemption from from bond pad checks
//                     Removed k2_east_pads_top* & k2_west_pads_top* exemption from from bond pad checks
//                     Removed krypton_io_pframe* & krypton2_toplevel* exemption from from bond pad checks
//                     Removed s8ppscio_top_vca_2*, s8ppscio_top_vcd_2*, s8ppscio_top_vda_2*,
//                       s8ppscio_top_vdd_3*, s8ppscio_top_vssa_2*, s8ppscio_top_vddabuf*,
//                       s8ppscio_top_vio*, s8ppscio_top_vssd_2*, s8ppscio_top_vssio_2*,
//                       s8ppscio_top_vssio_3*, s8ppscio_top_vssio_2*, s8tsg4io_top_vssd_2,
//                       s8ppscio_top_vssabuf*, s8ppscio_top_vusb_2 exemption from from bond pad checks
//                     Removed s8esdg4_net_io_b*, s8ppscio_top_vcd_2*, s8ppscio_top_vdd_2*,
//                       s8tsg4io_top_vio*, s8tsg4io_top_vssio_2*, s8tkm0s8_corner_tp2
//                       exemption from from bond pad checks
//                     Removed exemptions for s8cell_ee_plus_sseln_a, s8cell_ee_plus_sseln_b,
//                       s8cell_ee_plus_sselp_a, s8cell_ee_plus_sselp_b & s8fpls_pl8 s8fs_cmux4_fm
//                       from met1.ENC.1
//                     REMOVED s8usbpdv2_csa_top, s8usbpdv2_20vconn_sw_300ma_ovp_ngate_unit
//                       s8usbpdv2_20vconn_sw_300ma_ovp, s8usbpdv2_20sbu_sw_300ma_ovp cell
//                       exemptions from rpm rules
//                     Check coreID.CON.1 needs to be revamped when memory is supported (no change)
// 05/23/2021  JAG     Updated gate definition for lvtn.ENC.1
// 05/26/2021  JAG     Corrected message for ubm.SP.2 (had value for ubm.SP.1) but check was OK
// 06/08/2021  JAG     Added ptap.FL.1 and ntap.FL.1 to check for p+ tap or n+ tap which is
//                       not connected to a pad to RECOMMENDED rules
// 06/14/2021  JAG     Fixed issue in latchup where m4 was shorting through caps to m3 and m5 was
//                       shorting through caps to m4.
// 06/16/2021  JAG     Tightened slot definitions for stress using the following assumptions
//                        due to a design with a ptap ring around the entire chip which caused
//                        false metal slotting errors:
//                        1. a metal hole of interest will have an area < 5000 sq um
//                        2. a metal slot will have a width < 20.0 um
// 06/24/2021  JAG     Added warnings for insufficient vias in anchor cells
//             JAG     Commented out fuse rules and implemented two rules to flag polygons on
//                       fuse and target layers
//                     Commented out illegal device fuse checks
// 06/25/2021  JAG     Exempted rule latchup.signal.12e for n+ diff inside an isolated ptub
//                     Exempted rule latchup.signal.2.1b for dnw tied to gnd with n+ diff inside 
//                      tied to ground (back-to-back diodes protecting separate ground supplies)
// 06/29/2021  JAG     Removed (commented out) the following fuse related rules: diff_fill.CON.2, 
//                      diff_fill.SP.3 and LVS_exclude.CON.15 at request of Linda A. 
// 07/01/2021  JAG     Added rule to output any shapes on areaid:NotCritSide - stress.CON.8
// 07/02/2021  JAG     Changed rule name of photo.WID.2 to photo.ENC.2
//                     Changed rule name of lonely.via to lonely.via1 (2 rules)
// 07/08/2021  JAG     nwell_missing_tap.1 deleted as duplicate of nwell.OVL.1
//                     dnwell_missing_nwell.1 deleted as duplicate of dnwell.CON.4
//                     Moved remaining "SOFT" checks to floating checks:
//                       pwell_missing_tap.1 became floating.net.pwell.R
//                       ptub_missing_tap.1 became floating.net.ptub.R
//                       subcut_missing_tap.1 became floating.net.localsub.R
//                     Renamed ptap.FL.1.R as floating.net.ptap.R for consistancy with other float checks
//                     Renamed ntap.FL.1.R as floating.net.ntap.R for consistancy with other float checks
//                     Removed SKIP_SOFT_CONNECT_CHECKS switch as all rules were moved to recommended rules
// 07/09/2021  JAG     Rewrote hnwell section to NOT use areaid:hvnwell
//                     Removed v5.SP.1 as it was a duplicate of hnwell.SP.1
//                     Removed hv.nwell.SP.1 as it was a duplicate of hnwell.SP.1
// 07/15/2021  JAG     Moved all nwell checks to nwell section (removed hnwell) 
// 07/21/2021   RY     Removed v20.CON.5 as it was a duplicate of v20.CON.2
//
////////////////////////////////////////////////////////////////////////////////

// ********************************************************
// Begin control statements
// ********************************************************

PRECISION 1000

UNIT LENGTH u

DRC INCREMENTAL CONNECT YES

DRC MAXIMUM RESULTS ALL

// Tolerance for round-off errors on skew edges
DRC TOLERANCE FACTOR 0.001

// ********************************************************
// End control statements
// ********************************************************

// ********************************************************
// Begin layer definitions
// ********************************************************

LAYER nwell			1000
   LAYER MAP 64 DATATYPE 20 	1000 // nwell drawing

LAYER tunm			1001
   LAYER MAP 80 DATATYPE 20	1001 // tunm drawing

LAYER diffii  			1002
   LAYER MAP 65 DATATYPE 20	1002 // diff drawing

LAYER polyii			1003
   LAYER MAP 66 DATATYPE 20	1003 // poly drawing

LAYER lvtn			1004
   LAYER MAP 125 DATATYPE 44 	1004 // lvtn drawing

LAYER hvtp			1005
   LAYER MAP 78 DATATYPE 44 	1005 // hvtp drawing

LAYER npc			1006
   LAYER MAP 95 DATATYPE 20	1006 // npc drawing

LAYER nsdm			1007
   LAYER MAP 93 DATATYPE 44	1007 // nsdm drawing

LAYER psdm			1008
   LAYER MAP 94 DATATYPE 20	1008 // psdm drawing

LAYER mcon			1009
   LAYER MAP 67 DATATYPE 44	1009 // mcon drawing

LAYER met1ii			1010
   LAYER MAP 68 DATATYPE 20	1010 // met1 drawing

LAYER m1res			1011
   LAYER MAP 68 DATATYPE 13	1011 // met1 res

LAYER via1			1012
   LAYER MAP 68 DATATYPE 44	1012 // via1 drawing

LAYER met2ii			1013
   LAYER MAP 69 DATATYPE 20	1013 // met2 drawing

LAYER m2res			1014
   LAYER MAP 69 DATATYPE 13	1014 // met2 res

LAYER via2			1015
   LAYER MAP 69 DATATYPE 44	1015 // via2 drawing

LAYER met3ii			1016
   LAYER MAP 70 DATATYPE 20	1016 // met3 drawing

LAYER m3res			1017
   LAYER MAP 70 DATATYPE 13 	1017 // met3 res

LAYER via3			1018
   LAYER MAP 70 DATATYPE 44	1018 // via3 drawing

LAYER met4ii			1019
   LAYER MAP 71 DATATYPE 20 	1019 // met4 drawing

LAYER m4res			1020
   LAYER MAP 71 DATATYPE 13	1020 // met4 res

LAYER via4			1021
   LAYER MAP 71 DATATYPE 44 	1021 // via4 drawing

LAYER met5ii			1022
   LAYER MAP 72 DATATYPE 20 	1022 // met5 drawing

LAYER m5res			1023
   LAYER MAP 72 DATATYPE 13 	1023 // met5 res

LAYER pad			1024
   LAYER MAP 76 DATATYPE 20 	1024 // pad drawing

LAYER licon			1025
   LAYER MAP 66 DATATYPE 44 	1025 // licon drawing

LAYER li_ii			1026
   LAYER MAP 67 DATATYPE 20 	1026 // li drawing

LAYER pnp			1028
   LAYER MAP 82 DATATYPE 44 	1028 // pnp drawing

LAYER npn			1029
   LAYER MAP 82 DATATYPE 20 	1029 // npn drawing

LAYER v5			1030
   LAYER MAP 75 DATATYPE 20 	1030 // hvi drawing

LAYER ldntm			1031
   LAYER MAP 11 DATATYPE 44 	1031 // ldntm drawing

LAYER capacitor			1032
   LAYER MAP 82 DATATYPE 64 	1032 // capacitor drawing

LAYER ncm			1033
   LAYER MAP 92 DATATYPE 44 	1033 // ncm drawing

LAYER rdl			1034
   LAYER MAP 74 DATATYPE 20 	1034 // rdl drawing

LAYER rpm			1035
   LAYER MAP 86 DATATYPE 20 	1035 // rpm drawing

LAYER inductor			1036
   LAYER MAP 82 DATATYPE 24 	1036 // inductor drawing

LAYER pmm			1037
   LAYER MAP 85 DATATYPE 44 	1037 // pmm drawing

LAYER ubm			1038
   LAYER MAP 127 DATATYPE 21 	1038 // ubm drawing

LAYER bump			1039
   LAYER MAP 127 DATATYPE 22 	1039 // bump drawing

LAYER cviam			1040
   LAYER MAP 105 DATATYPE 20	1040 // cviam drawing

LAYER cmm1			1041
   LAYER MAP 62 DATATYPE 20	1041 // cmm1 drawing

LAYER cmm2			1042
   LAYER MAP 105 DATATYPE 44	1042 // cmm2 drawing

LAYER cmm3			1043
   LAYER MAP 107 DATATYPE 20	1043 // cmm3 drawing

LAYER metop1			1044
   LAYER MAP 70 DATATYPE 32	1044 // met3 option1

LAYER metop2			1045
   LAYER MAP 70 DATATYPE 33	1045 // met3 option2

LAYER metop3			1046
   LAYER MAP 70 DATATYPE 34	1046 // met3 option3

LAYER metop4			1047
   LAYER MAP 70 DATATYPE 35	1047 // met3 option4

LAYER metop5			1048
   LAYER MAP 70 DATATYPE 36	1048 // met3 option5

LAYER metop6			1049
   LAYER MAP 70 DATATYPE 37	1049 // met3 option6

LAYER metop7			1050
   LAYER MAP 70 DATATYPE 38	1050 // met3 option7

LAYER metop8			1051
   LAYER MAP 70 DATATYPE 39	1051 // met3 option8

LAYER dnwell			1052
   LAYER MAP 64 DATATYPE 18	1052 // dnwell drawing

LAYER DiodeID			1053
   LAYER MAP 81 DATATYPE 23 	1053 // areaid diode

LAYER ESDID			1054
   LAYER MAP 81 DATATYPE 19 	1054 // areaid esd

LAYER ENID			1055
   LAYER MAP 81 DATATYPE 57 	1055 // areaid extendedDrain

LAYER COREID			1056
   LAYER MAP 81 DATATYPE 2 	1056 // areaid core

LAYER SEALID			1057
   LAYER MAP 81 DATATYPE 1 	1057 // areaid seal

LAYER FRAMEID			1058
   LAYER MAP 81 DATATYPE 3 	1058 // areaid frame

LAYER LVID			1059
   LAYER MAP 81 DATATYPE 60 	1059 // areaid lvNative

LAYER STDCID			1060
   LAYER MAP 81 DATATYPE 4 	1060 // areaid standardc

LAYER localSub			1061
   LAYER MAP 81 DATATYPE 53 	1061 // areaid substrateCut

LAYER PHdiodeID			1062
   LAYER MAP 81 DATATYPE 81 	1062 // areaid photo

LAYER diffRes			1063
   LAYER MAP 65 DATATYPE 13	1063 // diff res

LAYER fuse			1064
   LAYER MAP 71 DATATYPE 17 	1064 // met4 fuse

//LAYER padCenter			1065
//   LAYER MAP 81 DATATYPE 20 	1065 // padCenter drawing

//LAYER prune			1066
//   LAYER MAP 84 DATATYPE 44 	1066 // prune drawing

LAYER polyres			1067
   LAYER MAP 66 DATATYPE 13 	1067 // poly res

LAYER lires			1068
   LAYER MAP 67 DATATYPE 13 	1068 // li res

LAYER pwres			1069
   LAYER MAP 64 DATATYPE 13 	1069 // pwell res

LAYER clvom			1070
   LAYER MAP 45 DATATYPE 20	1070 // clvom drawing

LAYER cntm			1071
   LAYER MAP 26 DATATYPE 20	1071 // cntm drawing

LAYER chvntm			1072
   LAYER MAP 38 DATATYPE 20	1072 // chvntm drawing

LAYER cnpc			1073
   LAYER MAP 44 DATATYPE 20	1073 // cnpc drawing

LAYER cnsdm			1074
   LAYER MAP 29 DATATYPE 20	1074 // cnsdm drawing

LAYER cpsdm			1075
   LAYER MAP 31 DATATYPE 20	1075 // cpsdm drawing

LAYER cli1m			1076
   LAYER MAP 115 DATATYPE 44	1076 // cli1m drawing

LAYER cviam3			1077
   LAYER MAP 112 DATATYPE 20	1077 // cviam3 drawing

LAYER cviam4			1078
   LAYER MAP 117 DATATYPE 20	1078 // cviam4 drawing

LAYER pmm2			1079
   LAYER MAP 77 DATATYPE 20	1079 // pmm2 drawing

LAYER conom			1080
   LAYER MAP 87 DATATYPE 44	1080 // conom drawing

LAYER chvtpm			1081
   LAYER MAP 88 DATATYPE 44	1081 // chvtpm drawing

LAYER clvtnm			1082
   LAYER MAP 25 DATATYPE 44	1082

LAYER cfom			1083
   LAYER MAP 22 DATATYPE 20	1083

LAYER hvtr			1084
   LAYER MAP 18 DATATYPE 20	1084

LAYER hvntm			1085
   LAYER MAP 125 DATATYPE 20	1085

LAYER nsm			1086
   LAYER MAP 61 DATATYPE 20	1086

LAYER padtt			1087 1088
   LAYER MAP 76 TEXTTYPE 20 	1087 // pad drawing
   LAYER MAP 76 TEXTTYPE 5 	1088 // pad label

LAYER rdltt			1089 1090
   LAYER MAP 74 TEXTTYPE 20 	1089 // rdl drawing
   LAYER MAP 74 TEXTTYPE 5 	1090 // rdl label

LAYER met5tt			1091 
   LAYER MAP 72 TEXTTYPE 5 	1091 // met5 label

LAYER met4tt			1092 
   LAYER MAP 71 TEXTTYPE 5 	1092 // met4 label

LAYER met3tt			1093 
   LAYER MAP 70 TEXTTYPE 5 	1093 // met3 label

LAYER met2tt			1094 
   LAYER MAP 69 TEXTTYPE 5 	1094 // met2 label

LAYER met1tt			1095 
   LAYER MAP 68 TEXTTYPE 5 	1095 // met1 label

LAYER litt			1096 
   LAYER MAP 67 TEXTTYPE 5 	1096 // li label

LAYER polytt			1097 
   LAYER MAP 66 TEXTTYPE 5 	1097 // poly label

LAYER difftt			1098 
   LAYER MAP 65 TEXTTYPE 6 	1098 // diff label

LAYER pwelltt			1099
   LAYER MAP 64 TEXTTYPE 59 	1099 // pwell label

//LAYER pwellisott		1100
//   LAYER MAP 44 TEXTTYPE 5 	1100 // pwelliso label

LAYER nwelltt			1101 
   LAYER MAP 64 TEXTTYPE 5 	1101 // nwell label

LAYER textdraw			1102
   LAYER MAP 83 TEXTTYPE 44 	1102 // text drawing

LAYER pwell_pin			1103
   LAYER MAP 122 DATATYPE 16 	1103 // pwell pin

//LAYER pwelliso_pin		1104
//   LAYER MAP 44 DATATYPE 16 	1104 // pwelliso pin

LAYER nwell_pin			1105
   LAYER MAP 64 DATATYPE 16 	1105 // nwell pin

LAYER diff_pin			1106
   LAYER MAP 65 DATATYPE 16 	1106 // diff pin

LAYER poly_pin			1107
   LAYER MAP 66 DATATYPE 16 	1107 // poly pin

LAYER li_pin			1108
   LAYER MAP 67 DATATYPE 16 	1108 // li pin

LAYER met1_pin			1109
   LAYER MAP 68 DATATYPE 16 	1109 // met1 pin

LAYER met2_pin			1110
   LAYER MAP 69 DATATYPE 16 	1110 // met2 pin

LAYER met3_pin			1111
   LAYER MAP 70 DATATYPE 16 	1111 // met3 pin

LAYER met4_pin			1112
   LAYER MAP 71 DATATYPE 16 	1112 // met4 pin

LAYER met5_pin			1113
   LAYER MAP 72 DATATYPE 16 	1113 // met5 pin

LAYER rdl_pin			1114
   LAYER MAP 74 DATATYPE 16 	1114 // rdl pin

LAYER pad_pin			1115
   LAYER MAP 76 DATATYPE 16 	1115 // pad pin

LAYER pwellpt			1116
   LAYER MAP 122 TEXTTYPE 16 	1116 // pwell pin
   LAYER MAP 122 TEXTTYPE 0 	1116 // pwell pin

//LAYER pwellisopt		1117
//   LAYER MAP 44 TEXTTYPE 16 	1117 // pwelliso pin
//   LAYER MAP 44 TEXTTYPE 0 	1117 // pwelliso pin

LAYER nwellpt			1118
   LAYER MAP 64 TEXTTYPE 16 	1118 // nwell pin
   LAYER MAP 64 TEXTTYPE 0 	1118 // nwell pin

LAYER diffpt			1119
   LAYER MAP 65 TEXTTYPE 16 	1119 // diff pin
   LAYER MAP 65 TEXTTYPE 0 	1119 // diff pin

LAYER polypt			1120
   LAYER MAP 66 TEXTTYPE 16 	1120 // poly pin
   LAYER MAP 66 TEXTTYPE 0 	1120 // poly pin

LAYER lipt			1121
   LAYER MAP 67 TEXTTYPE 16 	1121 // li pin
   LAYER MAP 67 TEXTTYPE 0 	1121 // li pin

LAYER met1pt			1122
   LAYER MAP 68 TEXTTYPE 16 	1122 // met1 pin
   LAYER MAP 68 TEXTTYPE 0 	1122 // met1 pin

LAYER met2pt			1123
   LAYER MAP 69 TEXTTYPE 16 	1123 // met2 pin
   LAYER MAP 69 TEXTTYPE 0 	1123 // met2 pin

LAYER met3pt			1124
   LAYER MAP 70 TEXTTYPE 16 	1124 // met3 pin
   LAYER MAP 70 TEXTTYPE 0 	1124 // met3 pin

LAYER met4pt			1125
   LAYER MAP 71 TEXTTYPE 16 	1125 // met4 pin
   LAYER MAP 71 TEXTTYPE 0 	1125 // met4 pin

LAYER met5pt			1126
   LAYER MAP 72 TEXTTYPE 16 	1126 // met5 pin
   LAYER MAP 72 TEXTTYPE 0 	1126 // met5 pin

LAYER rdlpt			1127
   LAYER MAP 74 TEXTTYPE 16 	1127 // rdl pin
   LAYER MAP 74 TEXTTYPE 0 	1127 // rdl pin

LAYER padpt			1128
   LAYER MAP 76 TEXTTYPE 16 	1128 // pad pin
   LAYER MAP 76 TEXTTYPE 0 	1128 // pad pin

LAYER met5probe			1129
   LAYER MAP 72 TEXTTYPE 25	1129 // met5 probe

LAYER met4probe			1130
   LAYER MAP 71 TEXTTYPE 25	1130 // met4 probe

LAYER met3probe			1131
   LAYER MAP 70 TEXTTYPE 25	1131 // met3 probe

LAYER met2probe			1132
   LAYER MAP 69 TEXTTYPE 25	1132 // met2 probe

LAYER met1probe			1133
   LAYER MAP 68 TEXTTYPE 25	1133 // met1 probe

LAYER liprobe			1134
   LAYER MAP 67 TEXTTYPE 25	1134 // li probe

LAYER polyprobe			1135
   LAYER MAP 66 TEXTTYPE 25	1135 // poly probe

LAYER fomWaffDrop		1136
   LAYER MAP 22 DATATYPE 24	1136 // cfom waffleDrop

LAYER moduleCutAREA		1137
   LAYER MAP 81 DATATYPE 10 	1137 // areaid moduleCut

LAYER indLabel			1138
   LAYER MAP 82 TEXTTYPE 25 	1138 // inductor label

LAYER indTerm1			1139
   LAYER MAP 82 DATATYPE 26 	1139 // inductor term1

LAYER indTerm2			1140
   LAYER MAP 82 DATATYPE 27 	1140 // inductor term2

LAYER indTerm3			1141
   LAYER MAP 82 DATATYPE 28 	1141 // inductor term3

LAYER capm			1142
   LAYER MAP 89 DATATYPE 44 	1142 // capm drawing

LAYER cap2m			1143
   LAYER MAP 97 DATATYPE 44 	1143 // cap2m drawing

LAYER urpm			1144
   LAYER MAP 79 DATATYPE 20 	1144 // urpm drawing

//LAYER EXTDRAIN20		1145
//   LAYER MAP 81 DATATYPE 58 	1145 // extd20v drawing

LAYER pwbm			1146
   LAYER MAP 19 DATATYPE 44 	1146 // pwbm drawing

LAYER pwde			1147
   LAYER MAP 124 DATATYPE 20 	1147 // pwbm drawing

LAYER LOWVTID			1148
   LAYER MAP 81 DATATYPE 108 	1148 // areaid low_vt drawing

LAYER v20			1149
   LAYER MAP 74 DATATYPE 22 	1149 // uhvi drawing

LAYER v12			1150
   LAYER MAP 74 DATATYPE 21 	1150 // vhvi drawing

LAYER LVTNMdg			1151
   // 1151 -> clvtnm drawing

LAYER HVTPMdg			1152
   // 1152 -> chvtpm drawing

LAYER HVNTMdg			1153
   // 1153 -> chvntm drawing

//LAYER NTMdg			1154
   // 1154 -> cntm drawing

LAYER NTMdrop			1155
   LAYER MAP 26 DATATYPE 22	1155 // cntm maskDrop

LAYER LVTNMdrop			1156
   LAYER MAP 25 DATATYPE 42	1156 // clvtnm maskDrop

LAYER HVTPMdrop			1157
   LAYER MAP 97 DATATYPE 42	1157 // chvtpm maskDrop

LAYER LI1Mdrop			1158
   LAYER MAP 115 DATATYPE 42	1158 // cli1m maskDrop

LAYER LICM1drop			1159
   LAYER MAP 106 DATATYPE 42	1159 // clicm1 maskDrop

LAYER PSDMdrop			1160
   LAYER MAP 31 DATATYPE 22	1160 // cpsdm maskDrop

LAYER NSDMdrop			1161
   LAYER MAP 29 DATATYPE 22	1161 // cnsdm maskDrop

LAYER P1Mdrop			1162
   LAYER MAP 33 DATATYPE 42	1162 // cp1m maskDrop

LAYER FOMdrop			1163
   LAYER MAP 22 DATATYPE 22	1163 // cfom maskDrop

LAYER NTMadd			1164
   LAYER MAP 26 DATATYPE 21	1164 // cntm maskAdd

LAYER LVTNMadd			1165
   LAYER MAP 25 DATATYPE 43	1165 // clvtnm maskAdd

LAYER HVTPMadd			1166
   LAYER MAP 97 DATATYPE 43	1166 // chvtpm maskAdd

LAYER LI1Madd			1167
   LAYER MAP 115 DATATYPE 43	1167 // cli1m maskAdd

LAYER LICM1add			1168
   LAYER MAP 106 DATATYPE 43	1168 // clicm1 maskAdd

LAYER PSDMadd			1169
   LAYER MAP 31 DATATYPE 21	1169 // cpsdm maskAdd

LAYER NSDMadd			1170
   LAYER MAP 29 DATATYPE 21	1170 // cnsdm maskAdd

LAYER P1Madd			1171
   LAYER MAP 33 DATATYPE 43	1171 // cp1m maskAdd

LAYER FOMadd			1172
   LAYER MAP 22 DATATYPE 21	1172 // cfom maskAdd

LAYER PMM2mk			1173
   LAYER MAP 94 DATATYPE 0	1173	// cpmm2 mask

LAYER CU1Mmk			1174
   LAYER MAP 93 DATATYPE 0 	1174	// ccu1m mask

LAYER RPMmk			1175
   LAYER MAP 96 DATATYPE 0	1175	// crpm mask

LAYER PBOmk			1176
   LAYER MAP 99 DATATYPE 0	1176 // cpbo mask

LAYER PDMmk			1177
   LAYER MAP 37 DATATYPE 0	1177 // cpdm mask

LAYER NSMmk			1178
   LAYER MAP 22 DATATYPE 0	1178 // cnsm mask

LAYER MM5mk			1179
   LAYER MAP 59 DATATYPE 0	1179 // cmm5 mask

LAYER VIM4mk			1180
   LAYER MAP 58 DATATYPE 0	1180 // cviam4 mask

LAYER MM4mk			1181
   LAYER MAP 51 DATATYPE 0	1181 // cmm4 mask

LAYER VIM3mk			1182
   LAYER MAP 50 DATATYPE 0	1182 // cviam3 mask

LAYER MM3mk			1183
   LAYER MAP 34 DATATYPE 0	1183 // cmm3 mask

LAYER VIM2mk			1184
   LAYER MAP 44 DATATYPE 0	1184 // cviam2 mask

LAYER MM2mk			1185
   LAYER MAP 41 DATATYPE 0	1185 // cmm2 mask

LAYER VIMmk			1186
   LAYER MAP 40 DATATYPE 0	1186 // cviam mask

LAYER MM1mk			1187
   LAYER MAP 36 DATATYPE 0	1187 // cmm1 mask

LAYER CTM1mk			1188
   LAYER MAP 35 DATATYPE 0	1188 // cctm1 mask

LAYER LI1Mmk			1189
   LAYER MAP 56 DATATYPE 0	1189 // cli1m mask

LAYER LICM1mk			1190
   LAYER MAP 43 DATATYPE 0	1190 // clicm1 mask

LAYER PSDMmk			1191
   LAYER MAP 32 DATATYPE 0	1191 // cpsdm mask

LAYER NSDMmk			1192
   LAYER MAP 30 DATATYPE 0	1192 // cnsdm mask

LAYER LDNTMmk			1193
   LAYER MAP 11 DATATYPE 0	1193 // cldntm mask

LAYER NPCMmk			1194
   LAYER MAP 49 DATATYPE 0	1194 // cnpc mask

LAYER HVNTMmk			1195
   LAYER MAP 39 DATATYPE 0	1195 // chvntm mask

LAYER NTMmk			1196
   LAYER MAP 27 DATATYPE 0	1196 // cntm mask

LAYER P1Mmk			1197
   LAYER MAP 28 DATATYPE 0	1197 // cp1m mask

LAYER LVOMmk			1198
   LAYER MAP 46 DATATYPE 0	1198 // clvom mask

LAYER ONOMmk			1199
   LAYER MAP 88 DATATYPE 0	1199 // conom mask

LAYER TUNMmk			1200
   LAYER MAP 20 DATATYPE 0	1200 // ctunm mask

LAYER HVTRMmk			1201
   LAYER MAP 98 DATATYPE 0	1201 // chvtrm mask

LAYER HVTPMmk			1202
   LAYER MAP 97 DATATYPE 0	1202 // chvtpm mask

LAYER LVTNMmk			1203
   LAYER MAP 25 DATATYPE 0	1203 // clvtnm mask

LAYER NWMmk			1204
   LAYER MAP 21 DATATYPE 0	1204 // cnwm mask

LAYER DNMmk			1205
   LAYER MAP 48 DATATYPE 0	1205 // cdnm mask

LAYER FOMmk			1206
   LAYER MAP 23 DATATYPE 0	1206 // cfom mask

LAYER met5Pin			1207 // met5 pin
   LAYER MAP 72 DATATYPE 16 	1207 // met5 pin

LAYER met4Pin			1208 // met4 pin
   LAYER MAP 71 DATATYPE 16 	1208 // met4 pin

LAYER met3Pin			1209 // met3 pin
   LAYER MAP 70 DATATYPE 16 	1209 // met3 pin

LAYER met2Pin			1210 // met2 pin
   LAYER MAP 69 DATATYPE 16 	1210 // met2 pin

LAYER met1Pin			1211 // met1 pin
   LAYER MAP 68 DATATYPE 16 	1211 // met1 pin

LAYER liPin			1212 // li pin
   LAYER MAP 67 DATATYPE 16 	1212 // li pin

LAYER polyPin			1213 // poly pin
   LAYER MAP 66 DATATYPE 16 	1213 // poly pin

LAYER diffPin			1214 // diff pin
   LAYER MAP 65 DATATYPE 16	1214 // diff pin

LAYER cmm4WaffleDrop		1215
   LAYER MAP 112 DATATYPE 4	1215 // cmm4 waffleDrop

LAYER cmm3WaffleDrop		1216
   LAYER MAP 107 DATATYPE 24	1216 // cmm3 waffleDrop

LAYER cmm2WaffleDrop		1217
   LAYER MAP 105 DATATYPE 52	1217 // cmm2 waffleDrop

LAYER cmm1WaffleDrop		1218
   LAYER MAP 62 DATATYPE 24	1218 // cmm1 waffleDrop

LAYER cp1mWaffleDrop		1219
   LAYER MAP 33 DATATYPE 24	1219 // cp1m waffleDrop

LAYER cfomWaffleDrop		1220
   LAYER MAP 22 DATATYPE 24	1220 // cfom waffleDrop

LAYER pwellLabel		1221
   LAYER MAP 64 DATATYPE 5	1221 // pwell label

//LAYER fomDummyDRC		1222
//   LAYER MAP 22 DATATYPE 23	1222 // fom dummy

LAYER viatop			1224
   LAYER MAP 203 DATATYPE 2	1224 // viatop drawing

LAYER ccorner			1225
   LAYER MAP 81 DATATYPE 51	1225 // areaid critCorner

LAYER critside			1226
   LAYER MAP 81 DATATYPE 52	1226 // areaid critSid

LAYER ANALOGID			1227
   LAYER MAP 81 DATATYPE 79     1227 // areaid analog

//LAYER pwell_dg			1228 // pwell drawing
//   LAYER MAP 64 DATATYPE 44	1228

LAYER dieCut			1229 // areaid dieCut
   LAYER MAP 81 DATATYPE 11	1229

LAYER frameBndr			1230
   LAYER MAP 81 DATATYPE 12	1230 // areaid frameRect

LAYER padText			1231
   LAYER MAP 76 TEXTTYPE 5	1231 // pad label

LAYER ETESTID			1232
   LAYER MAP 81 DATATYPE 101	1232 // areaid etest

LAYER ccapm			1233
   LAYER MAP 89 DATATYPE 45	1233 // capm mask

LAYER target			1234
   LAYER MAP 76 DATATYPE 44	1234 // capm mask

LAYER HVNID                     1235
   LAYER MAP 81 DATATYPE 63     1235 // areaid hvnwell

LAYER met1_block		1236
   LAYER MAP 68 DATATYPE 10	1236 // metal1 blockage

LAYER met2_block		1237
   LAYER MAP 69 DATATYPE 10	1237 // metal2 blockage

LAYER met3_block		1238
   LAYER MAP 70 DATATYPE 10	1238 // metal3 blockage

LAYER met4_block		1239
   LAYER MAP 71 DATATYPE 10	1239 // metal4 blockage

LAYER met5_block		1240
   LAYER MAP 72 DATATYPE 10	1240 // metal5 blockage

LAYER li_block			1241
   LAYER MAP 67 DATATYPE 10	1241 // li blockage

LAYER cmm5WaffleDrop		1242
   LAYER MAP 117 DATATYPE 4	1242 // cmm5 waffleDrop

LAYER tap_old			1243
   LAYER MAP 65 DATATYPE 44	1243 // read in layer tap from S8 datatbases

LAYER diffhvp                   1244
   LAYER MAP 65 DATATYPE 8      1244 // diff hv

LAYER polyGate                  1245
   LAYER MAP 66 DATATYPE 9      1245 // poly gate

LAYER prBndry                   1246
   LAYER MAP 235 DATATYPE 4     1246 // prBoundary boundary

//LAYER polyBndry                 1247
//   LAYER MAP 66 DATATYPE 4      1247 // poly boundary

//LAYER diffBndry                 1248
//   LAYER MAP 65 DATATYPE 4      1248 // diff boundary

LAYER sigPadMetNtr              1249
   LAYER MAP 81 DATATYPE 8      1249 // areaid sig_pad_met_not_res

LAYER sigPadWell                1250
   LAYER MAP 81 DATATYPE 7      1250 // areaid sig_pad_well

LAYER sigPadDiff                1251
   LAYER MAP 81 DATATYPE 6      1251 // areaid sig_pad_diff

LAYER LTDID                     1252
   LAYER MAP 81 DATATYPE 14     1252 // areaid lowTapDensity

LAYER NTMdg			1253 // cntm drawing
   LAYER MAP 26 DATATYPE 20	1253

LAYER pwcut			1254 // pwell cut
   LAYER MAP 64 DATATYPE 14	1254

LAYER deadzoneID	 	1255
   LAYER MAP 81 DATATYPE 50	1255 // areaid deadZon

LAYER notCritSideID	 	1256
   LAYER MAP 81 DATATYPE 15	1256 // areaid notCritSide

LAYER met1Block  	 	1257
   LAYER MAP 68 DATATYPE 10	1257 // met1 blockage

LAYER met2Block  	 	1258
   LAYER MAP 69 DATATYPE 10	1258 // met2 blockage

LAYER met3Block  	 	1259
   LAYER MAP 70 DATATYPE 10	1259 // met3 blockage

LAYER met4Block  	 	1260
   LAYER MAP 71 DATATYPE 10	1260 // met4 blockage

LAYER met5Block  	 	1261
   LAYER MAP 72 DATATYPE 10	1261 // met5 blockage

LAYER liBlock  	 		1262
   LAYER MAP 67 DATATYPE 10	1262 // li blockage

LAYER thkox			1263
   LAYER MAP 75 DATATYPE 21 	1263 // thick oxide drawing

LAYER pad_length		1264
   LAYER MAP 81 DATATYPE 67 	1264 // pad length marker

LAYER polyModeltt		1265 
   LAYER MAP 66 TEXTTYPE 83	1265

LAYER pad_io			1266 
   LAYER MAP 81 DATATYPE 70	1266

LAYER pad_pwr			1267 
   LAYER MAP 81 DATATYPE 71	1267

LAYER pad_gnd			1268 
   LAYER MAP 81 DATATYPE 72	1268

LAYER polyModel			1269 
   LAYER MAP 66 DATATYPE 83	1269

LAYER rrpm                      1270
   LAYER MAP 102 DATATYPE 20    1270 // rrpm drawing

LAYER diff_fill                 1271
   LAYER MAP 65 DATATYPE 99     1271 // diff fill 

LAYER poly_fill                 1272
   LAYER MAP 66 DATATYPE 99     1272 // poly fill 

LAYER li_fill                   1273
   LAYER MAP 67 DATATYPE 99     1273 // li fill 

LAYER m1_fill                   1274
   LAYER MAP 68 DATATYPE 99     1274 // m1 fill 

LAYER m2_fill                   1275
   LAYER MAP 69 DATATYPE 99     1275 // m2 fill 

LAYER m3_fill                   1276
   LAYER MAP 70 DATATYPE 99     1276 // m3 fill 

LAYER m4_fill                   1277
   LAYER MAP 71 DATATYPE 99     1277 // m4 fill 

LAYER m5_fill                   1278
   LAYER MAP 72 DATATYPE 99     1278 // m5 fill 

LAYER LVS_exclude               1279
   LAYER MAP 84 DATATYPE 44     1279 // LVS_exclude drawing

LAYER poly_block                1280
   LAYER MAP 66 DATATYPE 98     1280 // poly fill block

LAYER diff_block                1281
   LAYER MAP 65 DATATYPE 98     1281 // diff fill block

boundary = EXTENT DRAWN ORIGINAL

LAYOUT BASE LAYER diffii polyii pnp npn nsdm psdm thkox v5 v12 v20 lvtn hvtp

// ********************************************************
// End layer definitions
// ********************************************************

// ********************************************************
// Begin merge of fill layers with design layers
// ********************************************************


diffi = OR diff_fill diffii tap_old
polyi = poly_fill OR polyii
li_i = li_fill OR li_ii
met1i = m1_fill OR met1ii
met2i = m2_fill OR met2ii
met3i = m3_fill OR met3ii
met4i = m4_fill OR met4ii
met5i = m5_fill OR met5ii


// ********************************************************
// Begin base logical operations 
// ********************************************************


exempt_tech_CD = EXTENT CELL "*_tech_CD_top*"
nikon_1 = HOLES LDNTMmk
nikon_2 = LDNTMmk OR nikon_1
nikon_3 = VERTEX nikon_2 == 8
nikon_cross = nikon_3 ENCLOSE (((VIMmk AND VIM2mk) AND VIM3mk) AND VIM4mk)
dnwell_touch_pwbm_touch_extd20 = dnwell AND ((pwbm OR (HOLES pwbm)) INTERACT ENID)
dnwell_not_extended_drain = dnwell NOT dnwell_touch_pwbm_touch_extd20
localSub_not_size_localSub = localSub NOT (SIZE localSub BY -0.005)
dnwell_not_dnwell_ext_drain = dnwell_not_extended_drain AND nwell
sub_iso_other = boundary NOT ((dnwell_not_extended_drain NOT (SIZE dnwell_not_extended_drain BY -0.01)) OR dnwell_not_dnwell_ext_drain)
sub_local = sub_iso_other NOT localSub_not_size_localSub
substrate_not_npn = sub_local NOT npn
pwellresistor = pwres AND dnwell
pwell1 = substrate_not_npn NOT pwellresistor
iso_pw_basic = ((dnwell INTERACT nwell) NOT nwell) NOT INTERACT ENID
dnw_not_nw = dnwell NOT nwell
nw_hole = HOLES nwell
nw_hole_not_nw = nw_hole NOT nwell
nw_hole_outside_dnw = XOR nw_hole_not_nw dnw_not_nw
dnw_to_remove_iso_pw = dnw_not_nw INTERACT nw_hole_outside_dnw
ptub = iso_pw_basic NOT dnw_to_remove_iso_pw
pwell = pwell1 NOT (OR pwbm ptub nwell localSub)
ntap = ((nsdm AND diffi) AND nwell) NOT (polyi AND ENID)
ptap = (((psdm AND diffi) NOT nwell) NOT (polyi AND ENID)) NOT (dnwell NOT ptub)
tap = OR ptap ntap
diff1 = diffi NOT tap
pdiff = (diffi AND nwell) AND psdm
ndiff = (diffi NOT nwell) AND nsdm
nsd = (((diffi AND nsdm) NOT polyi) NOT diffres) NOT ntap
psd = (((diffi AND psdm) NOT polyi) NOT diffres) NOT ptap
ptubtap = (diffi and psdm) AND ptub
diffTap = OR tap diff1
srcdrn = (OR psd nsd) NOT polyi
nsrcdrn = srcdrn AND ndiff
psrcdrn = srcdrn AND pdiff
polyAndDiff = polyi AND diff1
gate = COPY POLYandDIFF
ngate = gate NOT nwell
pgate = gate AND nwell
gateside = GATE INSIDE EDGE diff1
gateend = GATE COINCIDENT INSIDE EDGE diff1
diffTapEdge = diff1 COINCIDENT OUTSIDE EDGE tap
MOSGATE = COPY GATE
EMOSGATE = COPY MOSGATE
nDiffTap = NDIFF OR NTAP
pDiffTap = PDIFF OR PTAP
gate_PERI = GATE NOT COREID
pdiff_PERI = PDIFF NOT COREID
pdiff_CORE = PDIFF AND COREID
ndiff_CORE = NDIFF AND COREID
ndiff_PERI = NDIFF NOT COREID
emosgate_PERI = EMOSGATE NOT COREID
emosgate_CORE = EMOSGATE AND COREID
poly_PERI = polyi NOT COREID
poly_CORE = polyi AND COREID
li1_PERI = li_i NOT COREID
li1_CORE = li_i AND COREID
licon1_PERI = licon NOT COREID
licon1_CORE = licon AND COREID
diff_PERI = diff1 NOT COREID
diff_CORE = diff1 AND COREID
tap_PERI = tap NOT COREID
tap_CORE = tap AND COREID
diffTap_CORE = diffTap AND COREID
diffTap_PERI = diffTap NOT COREID
mcon_PERI = mcon NOT COREID
mcon_CORE = mcon AND COREID
hvtp_PERI = hvtp NOT COREID
hvtp_CORE = hvtp AND COREID
lvtn_PERI = lvtn NOT COREID
lvtn_CORE = lvtn AND COREID
nsdm_PERI = nsdm NOT COREID
nsdm_CORE = nsdm AND COREID
psdm_PERI = psdm NOT COREID
psdm_CORE = psdm AND COREID
PTAP_PERI = PTAP NOT COREID
PTAP_CORE = PTAP AND COREID
NTAP_PERI = NTAP NOT COREID
NTAP_CORE = NTAP AND COREID
via_PERI = via1 NOT COREID
via_CORE = via1 AND COREID
via2_PERI = via2 NOT COREID
via2_CORE = via2 AND COREID
diff = diff1 NOT diffres
poly = polyi NOT polyres
li = li_i NOT lires
met1 = met1i NOT m1res
met2 = met2i NOT m2res
met3 = met3i NOT m3res
met4 = met4i NOT m4res
met5 = met5i NOT m5res
m3_bot_plate = SIZE (capm AND met3) BY 0.14
capm_cont_dmy = capm AND met3
m4_bot_plate = SIZE (cap2m AND met4) BY 0.14
cap2m_cont_dmy = cap2m AND met4
HVSrcDrnProp = diff NOT (diffres OR poly)
HVSrcDrn = HVSrcDrnProp INTERACT (HVSrcDrnProp AND diffhvp)
HVnSrcDrn = HVSrcDrn NOT nwell
HVpolyNotRes = poly NOT polyres
lcTapnw = INTERACT licon (licon AND (tap AND nwell))
npccon = npc AND licon
nwellring = DONUT nwell
nwellHoles = HOLES nwell
dnwell_v20 = AND dnwell v20
rndiff = (diffi AND nsdm) AND diffres
rpdiff = (diffi AND psdm) AND diffres
cap_34 = (met3 AND met4) AND capm
cap_45 = (met4 AND met5) AND cap2m
via3_c = via3 NOT cap_34
via4_c = via4 NOT cap_45


// ********************************************************
// Begin connectivity statements
// ********************************************************

CONNECT met5 met4 BY via4_c
CONNECT met4 met3 BY via3_c
CONNECT met4 m4_bot_plate BY cap2m_cont_dmy
CONNECT met3 met2 BY via2


CONNECT met3 m3_bot_plate BY capm_cont_dmy
CONNECT met2 met1 BY via1
CONNECT met1 li    BY mcon
CONNECT li nsd     BY licon
CONNECT li psd     BY licon
CONNECT li ntap    BY licon
CONNECT li ptap    BY licon
CONNECT li ptubtap BY licon
CONNECT li poly    BY licon
CONNECT gate poly

CONNECT ntap nwell
CONNECT ptap pwell
CONNECT ptubtap ptub
CONNECT nwell dnwell

CONNECT met5 pad
CONNECT rdl pad
CONNECT pwde v20 BY ptap

//
// Off Grid checks
//


nwell.GR {
    @ nwell.GR: nwell off 0.005 grid vertex
    OFFGRID nwell 5
}
diff.GR {
    @ diff.GR: diff off 0.005 grid vertex
    OFFGRID diffi 5
}
dnwell.GR {
    @ dnwell.GR: dnwell off 0.005 grid vertex
    OFFGRID dnwell 5
}
lvtn.GR {
    @ lvtn.GR: lvtn off 0.005 grid vertex
    OFFGRID lvtn 5
}
hvtp.GR {
    @ hvtp.GR: hvtp off 0.005 grid vertex
    OFFGRID hvtp 5
}
thkox.GR {
    @ thkox.GR: thkox off 0.005 grid vertex
    OFFGRID thkox 5
}
v5.GR {
    @ v5.GR: v5 off 0.005 grid vertex
    OFFGRID v5 5
}
v12.GR {
    @ v12.GR: v12 off 0.005 grid vertex
    OFFGRID v12 5
}
v20.GR {
    @ v20.GR: v20 off 0.005 grid vertex
    OFFGRID v20 5
}
tunm.GR {
    @ tunm.GR: tunm off 0.005 grid vertex
    OFFGRID tunm 5
}
poly.GR {
    @ poly.GR: poly off 0.005 grid vertex
    OFFGRID polyi 5
}
npc.GR {
    @ npc.GR: npc off 0.005 grid vertex
    OFFGRID npc 5
}
nsdm.GR {
    @ nsdm.GR: nsdm off 0.005 grid vertex
    OFFGRID nsdm 5
}
psdm.GR {
    @ psdm.GR: psdm off 0.005 grid vertex
    OFFGRID psdm 5
}
licon.GR {
    @ licon.GR: licon off 0.005 grid vertex
    OFFGRID licon 5
}
li.GR {
    @ li.GR: li off 0.005 grid vertex
    OFFGRID li_i 5
}
mcon.GR {
    @ mcon.GR: mcon off 0.005 grid vertex
    OFFGRID mcon 5
}
met1.GR {
    @ met1.GR: met1 off 0.005 grid vertex
    OFFGRID met1i 5
}
via1.GR {
    @ via1.GR: via1 off 0.005 grid vertex
    OFFGRID via1 5
}
met2.GR {
    @ met2.GR: met2 off 0.005 grid vertex
    OFFGRID met2i 5
}
via2.GR {
    @ via2.GR: via2 off 0.005 grid vertex
    OFFGRID via2 5
}
met3.GR {
    @ met3.GR: met3 off 0.005 grid vertex
    OFFGRID met3i 5
}
via3.GR {
    @ via3.GR: via3 off 0.005 grid vertex
    OFFGRID via3 5
}
met4.GR {
    @ met4.GR: met4 off 0.005 grid vertex
    OFFGRID met4i 5
}
via4.GR {
    @ via4.GR: via4 off 0.005 grid vertex
    OFFGRID via4 5
}
met5.GR {
    @ met5.GR: met5 off 0.005 grid vertex
    OFFGRID met5i 5
}
nsm.GR {
    @ nsm.GR: nsm off 0.005 grid vertex
    OFFGRID nsm 5
}
pad.GR {
    @ pad.GR: pad off 0.005 grid vertex
    OFFGRID pad 5
}
ldntm.GR {
    @ ldntm.GR: ldntm off 0.005 grid vertex
    OFFGRID ldntm 5
}
hvntm.GR {
    @ hvntm.GR: hvntm off 0.005 grid vertex
    OFFGRID hvntm 5
}
pnp.GR {
    @ pnp.GR: pnp off 0.005 grid vertex
    OFFGRID pnp 5
}
capacitor.GR {
    @ capacitor.GR: capacitor off 0.005 grid vertex
    OFFGRID capacitor 5
}
ncm.GR {
    @ ncm.GR: ncm off 0.005 grid vertex
    OFFGRID ncm 5
}
inductor.GR {
    @ inductor.GR: inductor off 0.005 grid vertex
    OFFGRID inductor 5
}
rpm.GR {
    @ rpm.GR: rpm off 0.005 grid vertex
    OFFGRID rpm 5
}
hvtr.GR {
    @ hvtr.GR: hvtr off 0.005 grid vertex
    OFFGRID hvtr 5
}
NTMdrop.GR {
    @ NTMdrop.GR: NTMdrop off 0.005 grid vertex
    OFFGRID NTMdrop 5
}
LVTNMdrop.GR {
    @ LVTNMdrop.GR: LVTNMdrop off 0.005 grid vertex
    OFFGRID LVTNMdrop 5
}
HVTPMdrop.GR {
    @ HVTPMdrop.GR: HVTPMdrop off 0.005 grid vertex
    OFFGRID HVTPMdrop 5
}
LI1Mdrop.GR {
    @ LI1Mdrop.GR: LI1Mdrop off 0.005 grid vertex
    OFFGRID LI1Mdrop 5
}
LICM1drop.GR {
    @ LICM1drop.GR: LICM1drop off 0.005 grid vertex
    OFFGRID LICM1drop 5
}
PSDMdrop.GR {
    @ PSDMdrop.GR: PSDMdrop off 0.005 grid vertex
    OFFGRID PSDMdrop 5
}
NSDMdrop.GR {
    @ NSDMdrop.GR: NSDMdrop off 0.005 grid vertex
    OFFGRID NSDMdrop 5
}
FOMdrop.GR {
    @ FOMdrop.GR: FOMdrop off 0.005 grid vertex
    OFFGRID FOMdrop 5
}
NTMadd.GR {
    @ NTMadd.GR: NTMadd off 0.005 grid vertex
    OFFGRID NTMadd 5
}
LVTNMadd.GR {
    @ LVTNMadd.GR: LVTNMadd off 0.005 grid vertex
    OFFGRID LVTNMadd 5
}
HVTPMadd.GR {
    @ HVTPMadd.GR: HVTPMadd off 0.005 grid vertex
    OFFGRID HVTPMadd 5
}
LI1Madd.GR {
    @ LI1Madd.GR: LI1Madd off 0.005 grid vertex
    OFFGRID LI1Madd 5
}
LICM1add.GR {
    @ LICM1add.GR: LICM1add off 0.005 grid vertex
    OFFGRID LICM1add 5
}
PSDMadd.GR {
    @ PSDMadd.GR: PSDMadd off 0.005 grid vertex
    OFFGRID PSDMadd 5
}
NSDMadd.GR {
    @ NSDMadd.GR: NSDMadd off 0.005 grid vertex
    OFFGRID NSDMadd 5
}
FOMadd.GR {
    @ FOMadd.GR: FOMadd off 0.005 grid vertex
    OFFGRID FOMadd 5
}
PMM2mk.GR {
    @ PMM2mk.GR: PMM2mk off 0.005 grid vertex
    OFFGRID PMM2mk 5
}
CU1Mmk.GR {
    @ CU1Mmk.GR: CU1Mmk off 0.005 grid vertex
    OFFGRID CU1Mmk 5
}
RPMmk.GR {
    @ RPMmk.GR: RPMmk off 0.005 grid vertex
    OFFGRID RPMmk 5
}
PBOmk.GR {
    @ PBOmk.GR: PBOmk off 0.005 grid vertex
    OFFGRID PBOmk 5
}
PDMmk.GR {
    @ PDMmk.GR: PDMmk off 0.005 grid vertex
    OFFGRID PDMmk 5
}
NSMmk.GR {
    @ NSMmk.GR: NSMmk off 0.005 grid vertex
    OFFGRID NSMmk 5
}
MM5mk.GR {
    @ MM5mk.GR: MM5mk off 0.005 grid vertex
    OFFGRID MM5mk 5
}
VIM4mk.GR {
    @ VIM4mk.GR: VIM4mk off 0.005 grid vertex
    OFFGRID VIM4mk 5
}
MM4mk.GR {
    @ MM4mk.GR: MM4mk off 0.005 grid vertex
    OFFGRID MM4mk 5
}
VIM3mk.GR {
    @ VIM3mk.GR: VIM3mk off 0.005 grid vertex
    OFFGRID VIM3mk 5
}
MM3mk.GR {
    @ MM3mk.GR: MM3mk off 0.005 grid vertex
    OFFGRID MM3mk 5
}
VIM2mk.GR {
    @ VIM2mk.GR: VIM2mk off 0.005 grid vertex
    OFFGRID VIM2mk 5
}
CTM1mk.GR {
    @ CTM1mk.GR: CTM1mk off 0.005 grid vertex
    OFFGRID CTM1mk 5
}
LI1Mmk.GR {
    @ LI1Mmk.GR: LI1Mmk off 0.005 grid vertex
    OFFGRID LI1Mmk 5
}
LICM1mk.GR {
    @ LICM1mk.GR: LICM1mk off 0.005 grid vertex
    OFFGRID LICM1mk 5
}
PSDMmk.GR {
    @ PSDMmk.GR: PSDMmk off 0.005 grid vertex
    OFFGRID PSDMmk 5
}
NSDMmk.GR {
    @ NSDMmk.GR: NSDMmk off 0.005 grid vertex
    OFFGRID NSDMmk 5
}
LDNTMmk.GR {
    @ LDNTMmk.GR: LDNTMmk off 0.005 grid vertex
    OFFGRID LDNTMmk 5
}
NPCMmk.GR {
    @ NPCMmk.GR: NPCMmk off 0.005 grid vertex
    OFFGRID NPCMmk 5
}
HVNTMmk.GR {
    @ HVNTMmk.GR: HVNTMmk off 0.005 grid vertex
    OFFGRID HVNTMmk 5
}
NTMmk.GR {
    @ NTMmk.GR: NTMmk off 0.005 grid vertex
    OFFGRID NTMmk 5
}
LVOMmk.GR {
    @ LVOMmk.GR: LVOMmk off 0.005 grid vertex
    OFFGRID LVOMmk 5
}
ONOMmk.GR {
    @ ONOMmk.GR: ONOMmk off 0.005 grid vertex
    OFFGRID ONOMmk 5
}
TUNMmk.GR {
    @ TUNMmk.GR: TUNMmk off 0.005 grid vertex
    OFFGRID TUNMmk 5
}
HVTRMmk.GR {
    @ HVTRMmk.GR: HVTRMmk off 0.005 grid vertex
    OFFGRID HVTRMmk 5
}
HVTPMmk.GR {
    @ HVTPMmk.GR: HVTPMmk off 0.005 grid vertex
    OFFGRID HVTPMmk 5
}
LVTNMmk.GR {
    @ LVTNMmk.GR: LVTNMmk off 0.005 grid vertex
    OFFGRID LVTNMmk 5
}
NWMmk.GR {
    @ NWMmk.GR: NWMmk off 0.005 grid vertex
    OFFGRID NWMmk 5
}
DNMmk.GR {
    @ DNMmk.GR: DNMmk off 0.005 grid vertex
    OFFGRID DNMmk 5
}
FOMmk.GR {
    @ FOMmk.GR: FOMmk off 0.005 grid vertex
    OFFGRID FOMmk 5
}
cfom.GR {
    @ cfom.GR: cfom off 0.005 grid vertex
    OFFGRID cfom 5
}
clvtnm.GR {
    @ clvtnm.GR: clvtnm off 0.005 grid vertex
    OFFGRID clvtnm 5
}
chvtpm.GR {
    @ chvtpm.GR: chvtpm off 0.005 grid vertex
    OFFGRID chvtpm 5
}
conom.GR {
    @ conom.GR: conom off 0.005 grid vertex
    OFFGRID conom 5
}
clvom.GR {
    @ clvom.GR: clvom off 0.005 grid vertex
    OFFGRID clvom 5
}
cntm.GR {
    @ cntm.GR: cntm off 0.005 grid vertex
    OFFGRID cntm 5
}
chvntm.GR {
    @ chvntm.GR: chvntm off 0.005 grid vertex
    OFFGRID chvntm 5
}
cnpc.GR {
    @ cnpc.GR: cnpc off 0.005 grid vertex
    OFFGRID cnpc 5
}
cnsdm.GR {
    @ cnsdm.GR: cnsdm off 0.005 grid vertex
    OFFGRID cnsdm 5
}
cpsdm.GR {
    @ cpsdm.GR: cpsdm off 0.005 grid vertex
    OFFGRID cpsdm 5
}
cli1m.GR {
    @ cli1m.GR: cli1m off 0.005 grid vertex
    OFFGRID cli1m 5
}
cviam3.GR {
    @ cviam3.GR: cviam3 off 0.005 grid vertex
    OFFGRID cviam3 5
}
cviam4.GR {
    @ cviam4.GR: cviam4 off 0.005 grid vertex
    OFFGRID cviam4 5
}
pmm.GR {
    @ pmm.GR: pmm off 0.005 grid vertex
    OFFGRID pmm 5
}
rdl.GR {
    @ rdl.GR: rdl off 0.005 grid vertex
    OFFGRID rdl 5
}
pmm2.GR {
    @ pmm2.GR: pmm2 off 0.005 grid vertex
    OFFGRID pmm2 5
}
ubm.GR {
    @ ubm.GR: ubm off 0.005 grid vertex
    OFFGRID ubm 5
}
bump.GR {
    @ bump.GR: bump off 0.005 grid vertex
    OFFGRID bump 5
}
capm.GR {
    @ capm.GR: capm off 0.005 grid vertex
    OFFGRID capm 5
}
cap2m.GR {
    @ cap2m.GR: cap2m off 0.005 grid vertex
    OFFGRID cap2m 5
}
SEALID_6um_1 = EXTENT CELL "advSeal_6um*" ORIGINAL
SEALID_6um_2 = EXTENT CELL "cuPillarAdvSeal_6um*" ORIGINAL
SEALID_6um_3 = EXTENT CELL "sealring*" ORIGINAL
SEALID_6um = SEALID AND (OR SEALID_6um_1 SEALID_6um_2 SEALID_6um_3)
diffOfA1K = diffi INTERACT (EXPAND EDGE (LENGTH (DONUT DIFF) > 1000) INSIDE BY 0.005)
diffRingSeal = (diffi INTERACT (INTERNAL diffOfA1K == 0.3 ABUT < 90 SINGULAR REGION)) INTERACT SEALID
diffNotAdvSeal6um = diffi NOT (SEALID_6um OR diffRingSeal)
diffNOtSealUHVI = diffNotAdvSeal6um NOT (OR v5 v12 v20)
polyAnc = polyi AND anchor
ESDID_sz = SIZE ESDID BY 0.2
poly_ESD = polyi AND ESDID_sz
poly_nonESD = polyi NOT ESDID_sz
gated_npn = EXTENT CELL "s8rf_npn_1x1_2p0_HV" ORIGINAL
poly_noESD_noAnch = poly_nonESD NOT polyAnc
critArea = (critside OR ccorner) AND (HOLES SEALID)
p_and_c = polyi AND critArea
l_and_c = li_i AND critArea
m1_and_c = met1i AND critArea
m2_and_c = met1i AND critArea
m3_and_c = met3i AND critArea
m4_and_c = met4i AND critArea
anch1 = p_and_c AND (l_and_c AND (m1_and_c AND (m2_and_c AND (m3_and_c AND m4_and_c))))
anch2 = (p_and_c AND (l_and_c AND (m1_and_c AND (m2_and_c AND (m3_and_c AND m4_and_c))))) AND critArea
anchLayers = anch1 INTERACT anch2
amcon = mcon AND anchLayers
alicon1 = licon AND anchLayers
avia = via1 AND anchLayers
avia2 = via2 AND anchLayers
avia3 = via3 AND anchLayers
anchmcon = amcon OUTSIDE (OR avia3 avia2 avia alicon1)
anchlicon1 = alicon1 OUTSIDE (OR avia3 avia2 avia amcon)
anchvia = avia OUTSIDE (OR avia3 avia2 alicon1 amcon)
anchvia2 = avia2 OUTSIDE (OR avia3 avia alicon1 amcon)
anchvia3 = avia3 OUTSIDE (OR avia2 avia alicon1 amcon)
acontacts = OR amcon alicon1 avia avia2 avia3 
anchcontacts = OR anchmcon anchlicon1 anchvia anchvia2 anchvia3
overlapCon = acontacts NOT anchcontacts
anchorTmp = ((((anchLayers ENCLOSE mcon) ENCLOSE licon) ENCLOSE via1) ENCLOSE via2) ENCLOSE via3
falseAnch = CUT poly anchLayers
anchor = anchorTmp OUTSIDE (overlapCon OR falseAnch)
li1Anc = li AND anchor
li1_PERI_nonSEAL = li1_PERI NOT SEALID
li1Peri_noSEAL_noAnch = li1_PERI_nonSEAL NOT (li1Anc OR falseAnch)
licon_nonSEAL = licon NOT SEALID
mcon_nonSEAL = mcon NOT SEALID
via_nonSEAL = via1 NOT SEALID
via2_nonSEAL = via2 NOT SEALID
via3_nonSEAL = via3 NOT SEALID
via4_nonSEAL = via4 NOT SEALID
tap_SEAL = tap AND SEALID
tap_ENID = (tap NOT SEALID) AND ENID
tap_nonSEAL = tap NOT (SEALID OR ENID)
li_SEAL = li_i AND SEALID
li_CORE = li_i AND COREID
licon_SEAL = licon AND SEALID
mcon_SEAL = mcon AND SEALID
via1_SEAL = via1 AND SEALID
via2_SEAL = via2 AND SEALID
via3_SEAL = via3 AND SEALID
sealRing = DONUT SEALID
sealHoles = HOLES SEALID
FOMdrop_noSeal = FOMdrop NOT SEALID_6um


//
// Angle checks
//


poly_noESD_noAnch_no_npn = poly_noESD_noAnch NOT npn
diff.ANG.1 {
    @ diff.ANG.1: diffusion not in areaid:seal or 20v device non-manhattan edge
    ANGLE diffNOtSealUHVI > 0 < 90
}
poly_not_in_ESD.ANG.1 {
    @ poly_not_in_ESD.ANG.1: poly not in NPN, ESD or anchor non-manhattan edge
    ANGLE poly_noESD_noAnch_no_npn > 0 < 90
}
li.ANG.1 {
    @ li.ANG.1: local interconnect not in areaid:seal or achnor non-manhattan edge
    ANGLE li1Peri_noSEAL_noAnch > 0 < 90
}
licon.ANG.1 {
    @ licon.ANG.1: licon interconnect not in areaid:seal non-manhattan edge
    ANGLE licon_nonSEAL > 0 < 90
}
mcon.ANG.1 {
    @ mcon.ANG.1: metal contact not in areaid:seal non-manhattan edge
    ANGLE mcon_nonSEAL > 0 < 90
}
via1.ANG.1 {
    @ via1.ANG.1: via contact not in areaid:seal non-manhattan edge
    ANGLE via_nonSEAL > 0 < 90
}
via2.ANG.1 {
    @ via2.ANG.1: via2 contact not in areaid:seal non-manhattan edge
    ANGLE via2_nonSEAL > 0 < 90
}
via3.ANG.1 {
    @ via3.ANG.1: via3 contact not in areaid:seal non-manhattan edge
    ANGLE via3_nonSEAL > 0 < 90
}
via4.ANG.1 {
    @ via4.ANG.1: via4 contact not in areaid:seal non-manhattan edge
    ANGLE via4_nonSEAL > 0 < 90
}
analog_difftap = diffTap INSIDE ANALOGID
non_ring_difftap = analog_difftap NOT INTERACT (DONUT analog_difftap)
bad_analog_difftap = NOT RECTANGLE non_ring_difftap
diff.ANG.2 {
    @ diff.ANG.2: A diff or tap shape enclosed in areaid:analog must be rectangular
    COPY bad_analog_difftap
}
licon.ANG.2 {
    @ licon.ANG.2: licon must be a rectangle
    not_donut_lay = licon NOT (licon INTERACT (DONUT licon))
    NOT RECTANGLE not_donut_lay
}
mcon.ANG.2 {
    @ mcon.ANG.2: mcon must be a rectangle
    not_donut_lay = mcon NOT (mcon INTERACT (DONUT mcon))
    NOT RECTANGLE not_donut_lay
}
via1.ANG.2 {
    @ via1.ANG.2: via1 must be a rectangle
    not_donut_lay = via1 NOT (via1 INTERACT (DONUT via1))
    NOT RECTANGLE not_donut_lay
}
via2.ANG.2 {
    @ via2.ANG.2: via2 must be a rectangle
    not_donut_lay = via2 NOT (via2 INTERACT (DONUT via2))
    NOT RECTANGLE not_donut_lay
}
via3.ANG.2 {
    @ via3.ANG.2: via3 must be a rectangle
    not_donut_lay = via3 NOT (via3 INTERACT (DONUT via3))
    NOT RECTANGLE not_donut_lay
}
via4.ANG.2 {
    @ via4.ANG.2: via4 must be a rectangle
    not_donut_lay = via4 NOT (via4 INTERACT (DONUT via4))
    NOT RECTANGLE not_donut_lay
}
nwell.ANG.3 {
    @ nwell.ANG.3: nwell non-octagonal edge
    ANGLE nwell > 0 < 45
    ANGLE nwell > 45 < 90
}
diff.ANG.3 {
    @ diff.ANG.3: diff non-octagonal edge
    ANGLE diff > 0 < 45
    ANGLE diff > 45 < 90
}
dnwell.ANG.3 {
    @ dnwell.ANG.3: dnwell non-octagonal edge
    ANGLE dnwell > 0 < 45
    ANGLE dnwell > 45 < 90
}
lvtn.ANG.3 {
    @ lvtn.ANG.3: lvtn non-octagonal edge
    ANGLE lvtn > 0 < 45
    ANGLE lvtn > 45 < 90
}
hvtp.ANG.3 {
    @ hvtp.ANG.3: hvtp non-octagonal edge
    ANGLE hvtp > 0 < 45
    ANGLE hvtp > 45 < 90
}
thkox.ANG.3 {
    @ thkox.ANG.3: thkox non-octagonal edge
    ANGLE thkox > 0 < 45
    ANGLE thkox > 45 < 90
}
tunm.ANG.3 {
    @ tunm.ANG.3: tunm non-octagonal edge
    ANGLE tunm > 0 < 45
    ANGLE tunm > 45 < 90
}
npc.ANG.3 {
    @ npc.ANG.3: npc non-octagonal edge
    ANGLE npc > 0 < 45
    ANGLE npc > 45 < 90
}
nsdm.ANG.3 {
    @ nsdm.ANG.3: nsdm non-octagonal edge
    ANGLE nsdm > 0 < 45
    ANGLE nsdm > 45 < 90
}
psdm.ANG.3 {
    @ psdm.ANG.3: psdm non-octagonal edge
    ANGLE psdm > 0 < 45
    ANGLE psdm > 45 < 90
}
met1.ANG.3 {
    @ met1.ANG.3: met1 non-octagonal edge
    ANGLE met1 > 0 < 45
    ANGLE met1 > 45 < 90
}
met2.ANG.3 {
    @ met2.ANG.3: met2 non-octagonal edge
    ANGLE met2 > 0 < 45
    ANGLE met2 > 45 < 90
}
v12.ANG.3 {
    @ v12.ANG.3: v12 non-octagonal edge
    ANGLE v12 > 0 < 45
    ANGLE v12 > 45 < 90
}
met3.ANG.3 {
    @ met3.ANG.3: met3 non-octagonal edge
    ANGLE met3 > 0 < 45
    ANGLE met3 > 45 < 90
}
met4.ANG.3 {
    @ met4.ANG.3: met4 non-octagonal edge
    ANGLE met4 > 0 < 45
    ANGLE met4 > 45 < 90
}
met5.ANG.3 {
    @ met5.ANG.3: met5 non-octagonal edge
    ANGLE met5 > 0 < 45
    ANGLE met5 > 45 < 90
}
nsm.ANG.3 {
    @ nsm.ANG.3: nsm non-octagonal edge
    ANGLE nsm > 0 < 45
    ANGLE nsm > 45 < 90
}
pad.ANG.3 {
    @ pad.ANG.3: pad non-octagonal edge
    ANGLE pad > 0 < 45
    ANGLE pad > 45 < 90
}
ldntm.ANG.3 {
    @ ldntm.ANG.3: ldntm non-octagonal edge
    ANGLE ldntm > 0 < 45
    ANGLE ldntm > 45 < 90
}
hvntm.ANG.3 {
    @ hvntm.ANG.3: hvntm non-octagonal edge
    ANGLE hvntm > 0 < 45
    ANGLE hvntm > 45 < 90
}
capacitor.ANG.3 {
    @ capacitor.ANG.3: capacitor non-octagonal edge
    ANGLE capacitor > 0 < 45
    ANGLE capacitor > 45 < 90
}
ncm.ANG.3 {
    @ ncm.ANG.3: ncm non-octagonal edge
    ANGLE ncm > 0 < 45
    ANGLE ncm > 45 < 90
}
inductor.ANG.3 {
    @ inductor.ANG.3: inductor non-octagonal edge
    ANGLE inductor > 0 < 45
    ANGLE inductor > 45 < 90
}
rpm.ANG.3 {
    @ rpm.ANG.3: rpm non-octagonal edge
    ANGLE rpm > 0 < 45
    ANGLE rpm > 45 < 90
}
urpm.ANG.3 {
    @ urpm.ANG.3: urpm non-octagonal edge
    ANGLE urpm > 0 < 45
    ANGLE urpm > 45 < 90
}
hvtr.ANG.3 {
    @ hvtr.ANG.3: hvtr non-octagonal edge
    ANGLE hvtr > 0 < 45
    ANGLE hvtr > 45 < 90
}
metop1.ANG.3 {
    @ metop1.ANG.3: metop1 non-octagonal edge
    ANGLE metop1 > 0 < 45
    ANGLE metop1 > 45 < 90
}
metop2.ANG.3 {
    @ metop2.ANG.3: metop2 non-octagonal edge
    ANGLE metop2 > 0 < 45
    ANGLE metop2 > 45 < 90
}
metop3.ANG.3 {
    @ metop3.ANG.3: metop3 non-octagonal edge
    ANGLE metop3 > 0 < 45
    ANGLE metop3 > 45 < 90
}
metop4.ANG.3 {
    @ metop4.ANG.3: metop4 non-octagonal edge
    ANGLE metop4 > 0 < 45
    ANGLE metop4 > 45 < 90
}
metop5.ANG.3 {
    @ metop5.ANG.3: metop5 non-octagonal edge
    ANGLE metop5 > 0 < 45
    ANGLE metop5 > 45 < 90
}
metop6.ANG.3 {
    @ metop6.ANG.3: metop6 non-octagonal edge
    ANGLE metop6 > 0 < 45
    ANGLE metop6 > 45 < 90
}
metop7.ANG.3 {
    @ metop7.ANG.3: metop7 non-octagonal edge
    ANGLE metop7 > 0 < 45
    ANGLE metop7 > 45 < 90
}
metop8.ANG.3 {
    @ metop8.ANG.3: metop8 non-octagonal edge
    ANGLE metop8 > 0 < 45
    ANGLE metop8 > 45 < 90
}
NTMdrop.ANG.3 {
    @ NTMdrop.ANG.3: NTMdrop non-octagonal edge
    ANGLE NTMdrop > 0 < 45
    ANGLE NTMdrop > 45 < 90
}
LVTNMdrop.ANG.3 {
    @ LVTNMdrop.ANG.3: LVTNMdrop non-octagonal edge
    ANGLE LVTNMdrop > 0 < 45
    ANGLE LVTNMdrop > 45 < 90
}
HVTPMdrop.ANG.3 {
    @ HVTPMdrop.ANG.3: HVTPMdrop non-octagonal edge
    ANGLE HVTPMdrop > 0 < 45
    ANGLE HVTPMdrop > 45 < 90
}
LI1Mdrop.ANG.3 {
    @ LI1Mdrop.ANG.3: LI1Mdrop non-octagonal edge
    ANGLE LI1Mdrop > 0 < 45
    ANGLE LI1Mdrop > 45 < 90
}
LICM1drop.ANG.3 {
    @ LICM1drop.ANG.3: LICM1drop non-octagonal edge
    ANGLE LICM1drop > 0 < 45
    ANGLE LICM1drop > 45 < 90
}
PSDMdrop.ANG.3 {
    @ PSDMdrop.ANG.3: PSDMdrop non-octagonal edge
    ANGLE PSDMdrop > 0 < 45
    ANGLE PSDMdrop > 45 < 90
}
NSDMdrop.ANG.3 {
    @ NSDMdrop.ANG.3: NSDMdrop non-octagonal edge
    ANGLE NSDMdrop > 0 < 45
    ANGLE NSDMdrop > 45 < 90
}
P1Mdrop.ANG.3 {
    @ P1Mdrop.ANG.3: P1Mdrop non-octagonal edge
    ANGLE P1Mdrop > 0 < 45
    ANGLE P1Mdrop > 45 < 90
}
FOMdrop.ANG.3 {
    @ FOMdrop.ANG.3: FOMdrop non-octagonal edge
    ANGLE FOMdrop > 0 < 45
    ANGLE FOMdrop > 45 < 90
}
NTMadd.ANG.3 {
    @ NTMadd.ANG.3: NTMadd non-octagonal edge
    ANGLE NTMadd > 0 < 45
    ANGLE NTMadd > 45 < 90
}
LVTNMadd.ANG.3 {
    @ LVTNMadd.ANG.3: LVTNMadd non-octagonal edge
    ANGLE LVTNMadd > 0 < 45
    ANGLE LVTNMadd > 45 < 90
}
HVTPMadd.ANG.3 {
    @ HVTPMadd.ANG.3: HVTPMadd non-octagonal edge
    ANGLE HVTPMadd > 0 < 45
    ANGLE HVTPMadd > 45 < 90
}
LI1Madd.ANG.3 {
    @ LI1Madd.ANG.3: LI1Madd non-octagonal edge
    ANGLE LI1Madd > 0 < 45
    ANGLE LI1Madd > 45 < 90
}
LICM1add.ANG.3 {
    @ LICM1add.ANG.3: LICM1add non-octagonal edge
    ANGLE LICM1add > 0 < 45
    ANGLE LICM1add > 45 < 90
}
PSDMadd.ANG.3 {
    @ PSDMadd.ANG.3: PSDMadd non-octagonal edge
    ANGLE PSDMadd > 0 < 45
    ANGLE PSDMadd > 45 < 90
}
NSDMadd.ANG.3 {
    @ NSDMadd.ANG.3: NSDMadd non-octagonal edge
    ANGLE NSDMadd > 0 < 45
    ANGLE NSDMadd > 45 < 90
}
P1Madd.ANG.3 {
    @ P1Madd.ANG.3: P1Madd non-octagonal edge
    ANGLE P1Madd > 0 < 45
    ANGLE P1Madd > 45 < 90
}
FOMadd.ANG.3 {
    @ FOMadd.ANG.3: FOMadd non-octagonal edge
    ANGLE FOMadd > 0 < 45
    ANGLE FOMadd > 45 < 90
}
cfom.ANG.3 {
    @ cfom.ANG.3: cfom non-octagonal edge
    ANGLE cfom > 0 < 45
    ANGLE cfom > 45 < 90
}
clvtnm.ANG.3 {
    @ clvtnm.ANG.3: clvtnm non-octagonal edge
    ANGLE clvtnm > 0 < 45
    ANGLE clvtnm > 45 < 90
}
chvtpm.ANG.3 {
    @ chvtpm.ANG.3: chvtpm non-octagonal edge
    ANGLE chvtpm > 0 < 45
    ANGLE chvtpm > 45 < 90
}
conom.ANG.3 {
    @ conom.ANG.3: conom non-octagonal edge
    ANGLE conom > 0 < 45
    ANGLE conom > 45 < 90
}
clvom.ANG.3 {
    @ clvom.ANG.3: clvom non-octagonal edge
    ANGLE clvom > 0 < 45
    ANGLE clvom > 45 < 90
}
cntm.ANG.3 {
    @ cntm.ANG.3: cntm non-octagonal edge
    ANGLE cntm > 0 < 45
    ANGLE cntm > 45 < 90
}
chvntm.ANG.3 {
    @ chvntm.ANG.3: chvntm non-octagonal edge
    ANGLE chvntm > 0 < 45
    ANGLE chvntm > 45 < 90
}
cnpc.ANG.3 {
    @ cnpc.ANG.3: cnpc non-octagonal edge
    ANGLE cnpc > 0 < 45
    ANGLE cnpc > 45 < 90
}
cnsdm.ANG.3 {
    @ cnsdm.ANG.3: cnsdm non-octagonal edge
    ANGLE cnsdm > 0 < 45
    ANGLE cnsdm > 45 < 90
}
cpsdm.ANG.3 {
    @ cpsdm.ANG.3: cpsdm non-octagonal edge
    ANGLE cpsdm > 0 < 45
    ANGLE cpsdm > 45 < 90
}
cli1m.ANG.3 {
    @ cli1m.ANG.3: cli1m non-octagonal edge
    ANGLE cli1m > 0 < 45
    ANGLE cli1m > 45 < 90
}
cviam3.ANG.3 {
    @ cviam3.ANG.3: cviam3 non-octagonal edge
    ANGLE cviam3 > 0 < 45
    ANGLE cviam3 > 45 < 90
}
cviam4.ANG.3 {
    @ cviam4.ANG.3: cviam4 non-octagonal edge
    ANGLE cviam4 > 0 < 45
    ANGLE cviam4 > 45 < 90
}
PMM2mk.ANG.3 {
    @ PMM2mk.ANG.3: PMM2mk non-octagonal edge
    ANGLE PMM2mk > 0 < 45
    ANGLE PMM2mk > 45 < 90
}
CU1Mmk.ANG.3 {
    @ CU1Mmk.ANG.3: CU1Mmk non-octagonal edge
    ANGLE CU1Mmk > 0 < 45
    ANGLE CU1Mmk > 45 < 90
}
RPMmk.ANG.3 {
    @ RPMmk.ANG.3: RPMmk non-octagonal edge
    ANGLE RPMmk > 0 < 45
    ANGLE RPMmk > 45 < 90
}
PBOmk.ANG.3 {
    @ PBOmk.ANG.3: PBOmk non-octagonal edge
    ANGLE PBOmk > 0 < 45
    ANGLE PBOmk > 45 < 90
}
PDMmk.ANG.3 {
    @ PDMmk.ANG.3: PDMmk non-octagonal edge
    ANGLE PDMmk > 0 < 45
    ANGLE PDMmk > 45 < 90
}
NSMmk.ANG.3 {
    @ NSMmk.ANG.3: NSMmk non-octagonal edge
    ANGLE NSMmk > 0 < 45
    ANGLE NSMmk > 45 < 90
}
MM5mk.ANG.3 {
    @ MM5mk.ANG.3: MM5mk non-octagonal edge
    ANGLE MM5mk > 0 < 45
    ANGLE MM5mk > 45 < 90
}
VIM4mk.ANG.3 {
    @ VIM4mk.ANG.3: VIM4mk non-octagonal edge
    ANGLE VIM4mk > 0 < 45
    ANGLE VIM4mk > 45 < 90
}
MM4mk.ANG.3 {
    @ MM4mk.ANG.3: MM4mk non-octagonal edge
    ANGLE MM4mk > 0 < 45
    ANGLE MM4mk > 45 < 90
}
VIM3mk.ANG.3 {
    @ VIM3mk.ANG.3: VIM3mk non-octagonal edge
    ANGLE VIM3mk > 0 < 45
    ANGLE VIM3mk > 45 < 90
}
MM3mk.ANG.3 {
    @ MM3mk.ANG.3: MM3mk non-octagonal edge
    ANGLE MM3mk > 0 < 45
    ANGLE MM3mk > 45 < 90
}
VIM2mk.ANG.3 {
    @ VIM2mk.ANG.3: VIM2mk non-octagonal edge
    ANGLE VIM2mk > 0 < 45
    ANGLE VIM2mk > 45 < 90
}
MM2mk.ANG.3 {
    @ MM2mk.ANG.3: MM2mk non-octagonal edge
    ANGLE MM2mk > 0 < 45
    ANGLE MM2mk > 45 < 90
}
VIMmk.ANG.3 {
    @ VIMmk.ANG.3: VIMmk non-octagonal edge
    ANGLE VIMmk > 0 < 45
    ANGLE VIMmk > 45 < 90
}
MM1mk.ANG.3 {
    @ MM1mk.ANG.3: MM1mk non-octagonal edge
    ANGLE MM1mk > 0 < 45
    ANGLE MM1mk > 45 < 90
}
CTM1mk.ANG.3 {
    @ CTM1mk.ANG.3: CTM1mk non-octagonal edge
    ANGLE CTM1mk > 0 < 45
    ANGLE CTM1mk > 45 < 90
}
LI1Mmk.ANG.3 {
    @ LI1Mmk.ANG.3: LI1Mmk non-octagonal edge
    ANGLE LI1Mmk > 0 < 45
    ANGLE LI1Mmk > 45 < 90
}
LICM1mk.ANG.3 {
    @ LICM1mk.ANG.3: LICM1mk non-octagonal edge
    ANGLE LICM1mk > 0 < 45
    ANGLE LICM1mk > 45 < 90
}
PSDMmk.ANG.3 {
    @ PSDMmk.ANG.3: PSDMmk non-octagonal edge
    ANGLE PSDMmk > 0 < 45
    ANGLE PSDMmk > 45 < 90
}
NSDMmk.ANG.3 {
    @ NSDMmk.ANG.3: NSDMmk non-octagonal edge
    ANGLE NSDMmk > 0 < 45
    ANGLE NSDMmk > 45 < 90
}
LDNTMmk.ANG.3 {
    @ LDNTMmk.ANG.3: LDNTMmk non-octagonal edge
    ANGLE LDNTMmk > 0 < 45
    ANGLE LDNTMmk > 45 < 90
}
NPCMmk.ANG.3 {
    @ NPCMmk.ANG.3: NPCMmk non-octagonal edge
    ANGLE NPCMmk > 0 < 45
    ANGLE NPCMmk > 45 < 90
}
HVNTMmk.ANG.3 {
    @ HVNTMmk.ANG.3: HVNTMmk non-octagonal edge
    ANGLE HVNTMmk > 0 < 45
    ANGLE HVNTMmk > 45 < 90
}
NTMmk.ANG.3 {
    @ NTMmk.ANG.3: NTMmk non-octagonal edge
    ANGLE NTMmk > 0 < 45
    ANGLE NTMmk > 45 < 90
}
P1Mmk.ANG.3 {
    @ P1Mmk.ANG.3: P1Mmk non-octagonal edge
    ANGLE P1Mmk > 0 < 45
    ANGLE P1Mmk > 45 < 90
}
LVOMmk.ANG.3 {
    @ LVOMmk.ANG.3: LVOMmk non-octagonal edge
    ANGLE LVOMmk > 0 < 45
    ANGLE LVOMmk > 45 < 90
}
ONOMmk.ANG.3 {
    @ ONOMmk.ANG.3: ONOMmk non-octagonal edge
    ANGLE ONOMmk > 0 < 45
    ANGLE ONOMmk > 45 < 90
}
TUNMmk.ANG.3 {
    @ TUNMmk.ANG.3: TUNMmk non-octagonal edge
    ANGLE TUNMmk > 0 < 45
    ANGLE TUNMmk > 45 < 90
}
HVTRMmk.ANG.3 {
    @ HVTRMmk.ANG.3: HVTRMmk non-octagonal edge
    ANGLE HVTRMmk > 0 < 45
    ANGLE HVTRMmk > 45 < 90
}
HVTPMmk.ANG.3 {
    @ HVTPMmk.ANG.3: HVTPMmk non-octagonal edge
    ANGLE HVTPMmk > 0 < 45
    ANGLE HVTPMmk > 45 < 90
}
LVTNMmk.ANG.3 {
    @ LVTNMmk.ANG.3: LVTNMmk non-octagonal edge
    ANGLE LVTNMmk > 0 < 45
    ANGLE LVTNMmk > 45 < 90
}
NWMmk.ANG.3 {
    @ NWMmk.ANG.3: NWMmk non-octagonal edge
    ANGLE NWMmk > 0 < 45
    ANGLE NWMmk > 45 < 90
}
DNMmk.ANG.3 {
    @ DNMmk.ANG.3: DNMmk non-octagonal edge
    ANGLE DNMmk > 0 < 45
    ANGLE DNMmk > 45 < 90
}
FOMmk.ANG.3 {
    @ FOMmk.ANG.3: FOMmk non-octagonal edge
    ANGLE FOMmk > 0 < 45
    ANGLE FOMmk > 45 < 90
}
tap_seal.ANG.3 {
    @ tap_seal.ANG.3: tap in areaid:seal non-octagonal edge
    ANGLE tap_SEAL > 0 < 45
    ANGLE tap_SEAL > 45 < 90
}
tap_extended_drain.ANG.3 {
    @ tap_extended_drain.ANG.3: tap in areaid:extendedDrain non-octagonal edge
    ANGLE tap_ENID > 0 < 45
    ANGLE tap_ENID > 45 < 90
}
poly_ESD.ANG.3 {
    @ poly_ESD.ANG.3: poly edge inside areaid:esd non-octagonal edge
    ANGLE poly_ESD > 0 < 45
    ANGLE poly_ESD > 45 < 90
}
li_core.ANG.3 {
    @ li_core.ANG.3: li in areaid:core non-octagonal edge
    ANGLE li_CORE > 0 < 45
    ANGLE li_CORE > 45 < 90
}
li_seal.ANG.3 {
    @ li_seal.ANG.3: li in areaid:seal non-octagonal edge
    ANGLE li_SEAL > 0 < 45
    ANGLE li_SEAL > 45 < 90
}
capm.ANG.3 {
    @ capm.ANG.3: capm non-octagonal edge
    ANGLE capm > 0 < 45
    ANGLE capm > 45 < 90
}
cap2m.ANG.3 {
    @ cap2m.ANG.3: cap2m non-octagonal edge
    ANGLE cap2m > 0 < 45
    ANGLE cap2m > 45 < 90
}


//
// Construction checks
//


diff.WARN.1 {
    @ diff.WARN.1: diffusion without implant
    ((diffi NOT (nsdm or psdm)) NOT SEALID) NOT npn
}
met5Pin.CON.1 {
    @ met5Pin.CON.1: met5/pin must be enclosed by met5
    NOT met5Pin met5i
}
met4Pin.CON.1 {
    @ met4Pin.CON.1: met4/pin must be enclosed by met4
    NOT met4Pin met4i
}
met3Pin.CON.1 {
    @ met3Pin.CON.1: met3/pin must be enclosed by met3
    NOT met3Pin met3i
}
met2Pin.CON.1 {
    @ met2Pin.CON.1: met2/pin must be enclosed by met2
    NOT met2Pin met2i
}
met1Pin.CON.1 {
    @ met1Pin.CON.1: met1/pin must be enclosed by met1
    NOT met1Pin met1i
}
liPin.CON.1 {
    @ liPin.CON.1: li/pin must be enclosed by li
    NOT liPin li_i
}
polyPin.CON.1 {
    @ polyPin.CON.1: poly/pin must be enclosed by poly
    NOT polyPin polyi
}
diffPin.CON.1 {
    @ diffPin.CON.1: diff/pin must be enclosed by diff
    NOT diffPin diffi
}
mcon.CON.2 {
    @ mcon.CON.2: mcon must be inside met1 and li
    NOT mcon li_i
    NOT mcon met1i
}
via1.CON.2 {
    @ via1.CON.2: via1 must be inside met2 and met1
    NOT via1 met1i
    NOT via1 met2i
}
via2.CON.2 {
    @ via2.CON.2: via2 must be inside met3 and met2
    NOT via2 met2i
    NOT via2 met3i
}
via3.CON.2 {
    @ via3.CON.2: via3 must be inside met4 and met3
    NOT via3 met3i
    NOT via3 met4i
}
via4.CON.2 {
    @ via4.CON.2: via4 must be inside met5 and met4
    NOT via4 met4i
    NOT via4 met5i
}
licon.CON.2 {
    @ licon.CON.2: licon must be inside li as well as diff or poly
    NOT licon (AND li (OR diffi polyi))
}
NTMdrop.CON.3 {
    @ NTMdrop.CON.3: NTMdrop must be enclosed by COREID
    NOT NTMdrop COREID
}
LVTNMdrop.CON.3 {
    @ LVTNMdrop.CON.3: LVTNMdrop must be enclosed by COREID
    NOT LVTNMdrop COREID
}
HVTPMdrop.CON.3 {
    @ HVTPMdrop.CON.3: HVTPMdrop must be enclosed by COREID
    NOT HVTPMdrop COREID
}
LI1Mdrop.CON.3 {
    @ LI1Mdrop.CON.3: LI1Mdrop must be enclosed by COREID
    NOT LI1Mdrop COREID
}
LICM1drop.CON.3 {
    @ LICM1drop.CON.3: LICM1drop must be enclosed by COREID
    NOT LICM1drop COREID
}
PSDMdrop.CON.3 {
    @ PSDMdrop.CON.3: PSDMdrop must be enclosed by COREID
    NOT PSDMdrop COREID
}
NSDMdrop.CON.3 {
    @ NSDMdrop.CON.3: NSDMdrop must be enclosed by COREID
    NOT NSDMdrop COREID
}
P1Mdrop.CON.3 {
    @ P1Mdrop.CON.3: P1Mdrop must be enclosed by COREID
    NOT P1Mdrop COREID
}
NTMadd.CON.3 {
    @ NTMadd.CON.3: NTMadd must be enclosed by COREID
    NOT NTMadd COREID
}
LVTNMadd.CON.3 {
    @ LVTNMadd.CON.3: LVTNMadd must be enclosed by COREID
    NOT LVTNMadd COREID
}
HVTPMadd.CON.3 {
    @ HVTPMadd.CON.3: HVTPMadd must be enclosed by COREID
    NOT HVTPMadd COREID
}
LI1Madd.CON.3 {
    @ LI1Madd.CON.3: LI1Madd must be enclosed by COREID
    NOT LI1Madd COREID
}
LICM1add.CON.3 {
    @ LICM1add.CON.3: LICM1add must be enclosed by COREID
    NOT LICM1add COREID
}
PSDMadd.CON.3 {
    @ PSDMadd.CON.3: PSDMadd must be enclosed by COREID
    NOT PSDMadd COREID
}
NSDMadd.CON.3 {
    @ NSDMadd.CON.3: NSDMadd must be enclosed by COREID
    NOT NSDMadd COREID
}
P1Madd.CON.3 {
    @ P1Madd.CON.3: P1Madd must be enclosed by COREID
    NOT P1Madd COREID
}
FOMadd.CON.3 {
    @ FOMadd.CON.3: FOMadd must be enclosed by COREID
    NOT FOMadd COREID
}
FOMdrop_noSeal.CON.3 {
    @ FOMdrop_noSeal.CON.3: FOMdrop_noSeal must be enclosed by COREID
    NOT FOMdrop_noSeal COREID
}
diffres.CON.4 {
    @ diffres.CON.4: diffres must not overlap licon
    AND diffres licon
}
polyres.CON.4 {
    @ polyres.CON.4: polyres must not overlap licon
    AND polyres licon
}
pwres.CON.5 {
    @ pwres.CON.5: pwres must fit exactly inside nw_hole and break it into two nets
    NOT pwres nw_hole
    conn_lay_not_res_lay = nw_hole NOT pwres
    pwres NOT TOUCH conn_lay_not_res_lay == 2
    res_touch_conn = pwres COINCIDENT INSIDE EDGE nw_hole
    res_touch_conn_exp = EXPAND EDGE res_touch_conn INSIDE BY 0.005
    res_touch_conn_exp_size = SIZE res_touch_conn_exp BY 0.05
    good_res = pwres INTERACT res_touch_conn_exp_size == 2
    NOT pwres good_res
}
diffres.CON.5 {
    @ diffres.CON.5: diffres must fit exactly inside diff and break it into two nets
    NOT diffres diffi
    conn_lay_not_res_lay = diffi NOT diffres
    diffres NOT TOUCH conn_lay_not_res_lay == 2
    res_touch_conn = diffres COINCIDENT INSIDE EDGE diffi
    res_touch_conn_exp = EXPAND EDGE res_touch_conn INSIDE BY 0.005
    res_touch_conn_exp_size = SIZE res_touch_conn_exp BY 0.05
    good_res = diffres INTERACT res_touch_conn_exp_size == 2
    NOT diffres good_res
}
polyres.CON.5 {
    @ polyres.CON.5: polyres must fit exactly inside poly and break it into two nets
    NOT polyres polyi
    conn_lay_not_res_lay = polyi NOT polyres
    polyres NOT TOUCH conn_lay_not_res_lay == 2
    res_touch_conn = polyres COINCIDENT INSIDE EDGE polyi
    res_touch_conn_exp = EXPAND EDGE res_touch_conn INSIDE BY 0.005
    res_touch_conn_exp_size = SIZE res_touch_conn_exp BY 0.05
    good_res = polyres INTERACT res_touch_conn_exp_size == 2
    NOT polyres good_res
}
lires.CON.5 {
    @ lires.CON.5: lires must fit exactly inside li and break it into two nets
    NOT lires li_i
    conn_lay_not_res_lay = li_i NOT lires
    lires NOT TOUCH conn_lay_not_res_lay == 2
    res_touch_conn = lires COINCIDENT INSIDE EDGE li_i
    res_touch_conn_exp = EXPAND EDGE res_touch_conn INSIDE BY 0.005
    res_touch_conn_exp_size = SIZE res_touch_conn_exp BY 0.05
    good_res = lires INTERACT res_touch_conn_exp_size == 2
    NOT lires good_res
}
met1res.CON.5 {
    @ m1res.CON.5: m1res must fit exactly inside met1 and break it into two nets
    NOT m1res met1i
    conn_lay_not_res_lay = met1i NOT m1res
    m1res NOT TOUCH conn_lay_not_res_lay == 2
    res_touch_conn = m1res COINCIDENT INSIDE EDGE met1i
    res_touch_conn_exp = EXPAND EDGE res_touch_conn INSIDE BY 0.005
    res_touch_conn_exp_size = SIZE res_touch_conn_exp BY 0.05
    good_res = m1res INTERACT res_touch_conn_exp_size == 2
    NOT m1res good_res
}
met2res.CON.5 {
    @ m2res.CON.5: m2res must fit exactly inside met2 and break it into two nets
    NOT m2res met2i
    conn_lay_not_res_lay = met2i NOT m2res
    m2res NOT TOUCH conn_lay_not_res_lay == 2
    res_touch_conn = m2res COINCIDENT INSIDE EDGE met2i
    res_touch_conn_exp = EXPAND EDGE res_touch_conn INSIDE BY 0.005
    res_touch_conn_exp_size = SIZE res_touch_conn_exp BY 0.05
    good_res = m2res INTERACT res_touch_conn_exp_size == 2
    NOT m2res good_res
}
met3res.CON.5 {
    @ m3res.CON.5: m3res must fit exactly inside met3 and break it into two nets
    NOT m3res met3i
    conn_lay_not_res_lay = met3i NOT m3res
    m3res NOT TOUCH conn_lay_not_res_lay == 2
    res_touch_conn = m3res COINCIDENT INSIDE EDGE met3i
    res_touch_conn_exp = EXPAND EDGE res_touch_conn INSIDE BY 0.005
    res_touch_conn_exp_size = SIZE res_touch_conn_exp BY 0.05
    good_res = m3res INTERACT res_touch_conn_exp_size == 2
    NOT m3res good_res
}
met4res.CON.5 {
    @ m4res.CON.5: m4res must fit exactly inside met4 and break it into two nets
    NOT m4res met4i
    conn_lay_not_res_lay = met4i NOT m4res
    m4res NOT TOUCH conn_lay_not_res_lay == 2
    res_touch_conn = m4res COINCIDENT INSIDE EDGE met4i
    res_touch_conn_exp = EXPAND EDGE res_touch_conn INSIDE BY 0.005
    res_touch_conn_exp_size = SIZE res_touch_conn_exp BY 0.05
    good_res = m4res INTERACT res_touch_conn_exp_size == 2
    NOT m4res good_res
}
met5res.CON.5 {
    @ m5res.CON.5: m5res must fit exactly inside met5 and break it into two nets
    NOT m5res met5i
    conn_lay_not_res_lay = met5i NOT m5res
    m5res NOT TOUCH conn_lay_not_res_lay == 2
    res_touch_conn = m5res COINCIDENT INSIDE EDGE met5i
    res_touch_conn_exp = EXPAND EDGE res_touch_conn INSIDE BY 0.005
    res_touch_conn_exp_size = SIZE res_touch_conn_exp BY 0.05
    good_res = m5res INTERACT res_touch_conn_exp_size == 2
    NOT m5res good_res
}
licon.CON.6 {
    @ licon.CON.6: licon must not overlap gate
    AND licon gate
}
psdm.CON.6 {
    @ psdm.CON.6: psdm must not overlap nsdm
    AND psdm nsdm
}
tap.CON.7 {
    @ tap.CON.7: a tap must not overlap areaid:seal
    AND tap SEALID
}
poly.CON.7 {
    @ poly.CON.7: poly must not overlap areaid:seal
    AND polyi SEALID
}
li.CON.7 {
    @ li.CON.7: li must not overlap areaid:seal
    AND li_i SEALID
}
met1.CON.7 {
    @ met1.CON.7: met1 must not overlap areaid:seal
    AND met1i SEALID
}
met2.CON.7 {
    @ met2.CON.7: met2 must not overlap areaid:seal
    AND met2i SEALID
}
met3.CON.7 {
    @ met3.CON.7: met3 must not overlap areaid:seal
    AND met3i SEALID
}
met4.CON.7 {
    @ met4.CON.7: met4 must not overlap areaid:seal
    AND met4i SEALID
}
met5.CON.7 {
    @ met5.CON.7: met5 must not overlap areaid:seal
    AND met5i SEALID
}
diff.CON.8 {
    @ diff.CON.8: diff must not straddle areaid:seal
    CUT diffi SEALID
}
thkox.WARN.1 {
    @ thkox.WARN.1: Layer thkox doesn't interact with v5, v12 or v20
    thkox NOT INTERACT (OR v5 v12 v20)
}
mcon.CON.10 {
    @ mcon.CON.10: mcon must be enclosed by li
    mcon NOT  li
}
via1.CON.10 {
    @ via1.CON.10: via1 outside of areaid:moduleCut should be orthogonal rectangle
    NOT RECTANGLE via1 ORTHOGONAL ONLY
}
via2.CON.10 {
    @ via2.CON.10: via2 outside of areaid:moduleCut should be orthogonal rectangle
    NOT RECTANGLE via2 ORTHOGONAL ONLY
}
via3.CON.10 {
    @ via3.CON.10: via3 outside of areaid:moduleCut should be orthogonal rectangle
    NOT RECTANGLE via3 ORTHOGONAL ONLY
}
via4.CON.10 {
    @ via4.CON.10: via4 outside of areaid:moduleCut should be orthogonal rectangle
    NOT RECTANGLE via4 ORTHOGONAL ONLY
}
areaid_layers = OR COREID SEALID moduleCutAREA frameBndr
cfom.CON.12 {
    @ cfom.CON.12: cfom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT cfom areaid_layers
}
clvtnm.CON.12 {
    @ clvtnm.CON.12: clvtnm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT clvtnm areaid_layers
}
chvtpm.CON.12 {
    @ chvtpm.CON.12: chvtpm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT chvtpm areaid_layers
}
conom.CON.12 {
    @ conom.CON.12: conom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT conom areaid_layers
}
clvom.CON.12 {
    @ clvom.CON.12: clvom allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT clvom areaid_layers
}
cntm.CON.12 {
    @ cntm.CON.12: cntm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT cntm areaid_layers
}
chvntm.CON.12 {
    @ chvntm.CON.12: chvntm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT chvntm areaid_layers
}
cnpc.CON.12 {
    @ cnpc.CON.12: cnpc allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT cnpc areaid_layers
}
cnsdm.CON.12 {
    @ cnsdm.CON.12: cnsdm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT cnsdm areaid_layers
}
cpsdm.CON.12 {
    @ cpsdm.CON.12: cpsdm allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT cpsdm areaid_layers
}
cli1m.CON.12 {
    @ cli1m.CON.12: cli1m allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT cli1m areaid_layers
}
cviam3.CON.12 {
    @ cviam3.CON.12: cviam3 allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT cviam3 areaid_layers
}
cviam4.CON.12 {
    @ cviam4.CON.12: cviam4 allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT cviam4 areaid_layers
}
PMM2mk.CON.12 {
    @ PMM2mk.CON.12: PMM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT PMM2mk areaid_layers
}
CU1Mmk.CON.12 {
    @ CU1Mmk.CON.12: CU1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT CU1Mmk areaid_layers
}
RPMmk.CON.12 {
    @ RPMmk.CON.12: RPMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT RPMmk areaid_layers
}
PBOmk.CON.12 {
    @ PBOmk.CON.12: PBOmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT PBOmk areaid_layers
}
PDMmk.CON.12 {
    @ PDMmk.CON.12: PDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT PDMmk areaid_layers
}
NSMmk.CON.12 {
    @ NSMmk.CON.12: NSMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT NSMmk areaid_layers
}
MM5mk.CON.12 {
    @ MM5mk.CON.12: MM5mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT MM5mk areaid_layers
}
VIM4mk.CON.12 {
    @ VIM4mk.CON.12: VIM4mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT VIM4mk areaid_layers
}
MM4mk.CON.12 {
    @ MM4mk.CON.12: MM4mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT MM4mk areaid_layers
}
VIM3mk.CON.12 {
    @ VIM3mk.CON.12: VIM3mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT VIM3mk areaid_layers
}
MM3mk.CON.12 {
    @ MM3mk.CON.12: MM3mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT MM3mk areaid_layers
}
VIM2mk.CON.12 {
    @ VIM2mk.CON.12: VIM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT VIM2mk areaid_layers
}
MM2mk.CON.12 {
    @ MM2mk.CON.12: MM2mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT MM2mk areaid_layers
}
VIMmk.CON.12 {
    @ VIMmk.CON.12: VIMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT VIMmk areaid_layers
}
MM1mk.CON.12 {
    @ MM1mk.CON.12: MM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT MM1mk areaid_layers
}
CTM1mk.CON.12 {
    @ CTM1mk.CON.12: CTM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT CTM1mk areaid_layers
}
LI1Mmk.CON.12 {
    @ LI1Mmk.CON.12: LI1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT LI1Mmk areaid_layers
}
LICM1mk.CON.12 {
    @ LICM1mk.CON.12: LICM1mk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT LICM1mk areaid_layers
}
PSDMmk.CON.12 {
    @ PSDMmk.CON.12: PSDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT PSDMmk areaid_layers
}
NSDMmk.CON.12 {
    @ NSDMmk.CON.12: NSDMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT NSDMmk areaid_layers
}
LDNTMmk.CON.12 {
    @ LDNTMmk.CON.12: LDNTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT LDNTMmk areaid_layers
}
NPCMmk.CON.12 {
    @ NPCMmk.CON.12: NPCMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT NPCMmk areaid_layers
}
HVNTMmk.CON.12 {
    @ HVNTMmk.CON.12: HVNTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT HVNTMmk areaid_layers
}
NTMmk.CON.12 {
    @ NTMmk.CON.12: NTMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT NTMmk areaid_layers
}
P1Mmk.CON.12 {
    @ P1Mmk.CON.12: P1Mmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT P1Mmk areaid_layers
}
LVOMmk.CON.12 {
    @ LVOMmk.CON.12: LVOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT LVOMmk areaid_layers
}
ONOMmk.CON.12 {
    @ ONOMmk.CON.12: ONOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT ONOMmk areaid_layers
}
TUNMmk.CON.12 {
    @ TUNMmk.CON.12: TUNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT TUNMmk areaid_layers
}
HVTRMmk.CON.12 {
    @ HVTRMmk.CON.12: HVTRMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT HVTRMmk areaid_layers
}
HVTPMmk.CON.12 {
    @ HVTPMmk.CON.12: HVTPMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT HVTPMmk areaid_layers
}
LVTNMmk.CON.12 {
    @ LVTNMmk.CON.12: LVTNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT LVTNMmk areaid_layers
}
NWMmk.CON.12 {
    @ NWMmk.CON.12: NWMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT NWMmk areaid_layers
}
DNMmk.CON.12 {
    @ DNMmk.CON.12: DNMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT DNMmk areaid_layers
}
FOMmk.CON.12 {
    @ FOMmk.CON.12: FOMmk allowed inside areaid:mt or inside areaid.sl or inside areaid.ft only
    NOT FOMmk areaid_layers
}
localsub.CON.1 {
    @ localsub.CON.1: ptap must not straddle local sub layer
    CUT PTAP localSub
}
valid_npn = INSIDE CELL npn "npn_1x1" "npn_1x1_v5" "npn_1x2"
npn.CON.1 {
    @ npn.CON.1: Layer npn can only be used inside cell npn_1x1, npn_1x1_v5 or npn_1x2
    npn NOT valid_npn
}
valid_pnp = INSIDE CELL pnp "pnp" "pnp_5x"
pnp.CON.1 {
    @ pnp.CON.1: Layer pnp can only be used inside cell pnp2 or pnp_5x
    pnp NOT valid_pnp
}


//
// hvtp checks
//


PFETa = GATE AND PDIFF
PFET_PERI = PFETa NOT COREID
hvtp.WID.1 {
    @ hvtp.WID.1: Min width of hvtp < 0.38
    INTERNAL hvtp < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hvtp.SP.1 {
    @ hvtp.SP.1: Min spacing/notch of hvtp < 0.38
    EXTERNAL hvtp < 0.38 ABUT < 90 SINGULAR REGION
}
hvtp.ENC.1 {
    @ hvtp.ENC.1: Min enclosure of pfet not in areaid:core by hvtp < 0.18
    ENCLOSURE (PFET_PERI AND hvtp) hvtp < 0.18 MEASURE ALL ABUT < 90 SINGULAR REGION
}
hvtp.SP.2 {
    @ hvtp.SP.2: Min spacing of pfet not in areaid:core to hvtp < 0.18
    EXTERNAL PFET_PERI hvtp < 0.18 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hvtp.AR.1 {
    @ hvtp.AR.1: Min area of hvtp < 0.265
    AREA hvtp < 0.265
}
hvtp.AR.2 {
    @ hvtp.AR.2: Min area of hvtpHole < 0.265
    AREA (HOLES hvtp) < 0.265
}
hvtp.ENC.2 {
    @ hvtp.ENC.2: Min/Max enclosure of nwell by hvtp in areaid:core == 0
    (INTERACT hvtp_CORE (hvtp_CORE AND nwell)) NOT nwell
}


//
// hvtr checks
//


hvtr.WID.1 {
    @ hvtr.WID.1: Min width of hvtr < 0.38
    INTERNAL hvtr < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hvtr.SP.1 {
    @ hvtr.SP.1: Min. spacing of hvtr to hvtp < 0.38
    EXTERNAL hvtr hvtp < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hvtr.CON.1 {
    @ hvtr.CON.1: hvtr must not overlap hvtp
    hvtr AND hvtp
}
hvtr.ENC.1 {
    @ hvtr.ENC.1: Min enclosure of PFET by hvtr < 0.18
    ENCLOSURE PFETa hvtr < 0.18 MEASURE ALL ABUT < 90 SINGULAR REGION
}


//
// lvtn checks
//


lvNwell_drc = nwell NOT v5
PolyLvNwell = poly AND lvNwell_drc
lvNtap = tap AND lvNwell_drc
varChannel_drc = (PolylvNwell AND lvNtap) NOT COREID
LVnwellnovarChannel = lvNwell_drc NOT (INTERACT lvNwell_drc (lvNwell_drc AND varChannel_drc))
lvtEncPDiff = lvtn ENCLOSE PDIFF
periDiffNoLvt = diff_PERI NOT lvtn_PERI
lvtGate = lvtn AND GATE
nwellNoVarac = (nwell NOT (INTERACT nwell (nwell AND varChannel_drc))) NOT INSIDE lvtn
coreNwell = nwell INSIDE COREID
lvtnHoles = HOLES lvtn
GATE_PERI_non_v20 = gate_PERI NOT v20
lvtn.WID.1 {
    @ lvtn.WID.1: Min width of lvtn < 0.38
    INTERNAL lvtn < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lvtn.SP.1 {
    @ lvtn.SP.1: Min spacing/notch of lvtn < 0.38
    EXTERNAL lvtn < 0.38 ABUT < 90 SINGULAR REGION
}
lvtn.SP.2 {
    @ lvtn.SP.2: Min spacing of lvtn to gate. Rule exempted inside v20 and outside areaid:core < 0.18
    EXTERNAL GATE_PERI_non_v20 lvtn_PERI < 0.18 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lvtn.SP.3 {
    @ lvtn.SP.3: Min spacing of lvtn not in areaid:core to pfet along S/D direction < 0.19
    EXTERNAL (COINCIDENT OUTSIDE EDGE (NOT INTERACT pgate lvtn) psrcdrn) lvtn < 0.19 ABUT < 90 REGION
}
non_20v_gate_peri = (diffi AND polyi) NOT (COREID OR v20)
lvtn.ENC.1 {
    @ lvtn.ENC.1: Min enclosure of gate not in areaid:core or v20 by lvtn not in areaid:core < 0.18
    ENCLOSURE non_20v_gate_peri lvtn_PERI < 0.18 MEASURE ALL ABUT < 90 SINGULAR REGION
}
lvtn.SP.4 {
    @ lvtn.SP.4: Min spacing of lvtn & hvtp < 0.38
    EXTERNAL lvtn hvtp < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lvtn.OVL.1 {
    @ lvtn.OVL.1: lvtn must not overlap hvtp
    lvtn AND hvtp
}
lvtn.ENC.2 {
    @ lvtn.ENC.2: Min enclosure of lvtn by (nwell not overlapping Var_channel) (exclude coincident edges) < 0.38
    NOT TOUCH (ENCLOSURE lvtn nwellNoVarac < 0.38 REGION) nwellNoVarac
}
lvtn.SP.5 {
    @ lvtn.SP.5: Min spacing of lvtn & nwell in areaid:core < 0.38
    EXTERNAL lvtn coreNwell < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
lvtn.AR.1 {
    @ lvtn.AR.1: Min area of lvtn < 0.265
    AREA lvtn < 0.265
}
lvtn.AR.2 {
    @ lvtn.AR.2: Min area of lvtn Holes < 0.265
    AREA lvtnHoles < 0.265
}


//
// diff checks
//


tmp1Diff = INTERNAL diffi < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
tmp2Diff = INTERNAL (diffi NOT COREID) < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
diffEdge = diff OUTSIDE EDGE tap
ntapTouchNwell = ntap INSIDE nwell
nwellTouchNtap = nwell INSIDE ntap
ntapnwellInNdiff = (HOLES ndiff) INSIDE (ntapTouchNwell OR nwellTouchNtap)
ESD_nwell_tap = ESDID AND (ntapTouchNwell AND ntapnwellInNdiff)
nwell_noesd = nwell NOT ESD_nwell_tap
diff_noesd = diff NOT ESD_nwell_tap
tap_noesd = tap NOT ESD_nwell_tap
tabut_edge = TOUCH EDGE tap_noesd diff_noesd
dabut_edge = TOUCH EDGE diff_noesd tap_noesd
diff.WID.1 {
    @ diff.WID.1: Min width of diff crossing areaid:core < 0.15
    SIZE (tmp2Diff INSIDE (CUT tmp1Diff COREID)) BY 0.005 INSIDE OF tmp1Diff STEP 0.15
}
diff.WID.2 {
    @ diff.WID.2: Min width of diff inside periphery < 0.15
    tmp1Diff OUTSIDE COREID
}
diff.WID.3 {
    @ diff.WID.3: Min width of diff inside areaid:core < 0.14
    (INTERNAL (AND diffi COREID) < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE COREID
}
tmp1DiffTap = INTERNAL tap < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
diff.WID.4 {
    @ diff.WID.4: Min width of tap crossing areaid:core < 0.15
    SIZE ((INTERNAL (tap NOT COREID) < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE (CUT tmp1DiffTap COREID)) BY 0.005 INSIDE OF tmp1DiffTap STEP 0.15
}
diff.WID.5 {
    @ diff.WID.5: Min width of tap inside periphery < 0.15
    tmp1DiffTap OUTSIDE COREID
}
diff.WID.6 {
    @ diff.WID.6: Min width of tap inside areaid:core < 0.14
    (INTERNAL tap < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE COREID
}
diff.WID.7 {
    @ diff.WID.7: Min width of gate outside areaid:standardc < 0.42
    INTERNAL ((GATE_PERI NOT STDCID) COINCIDENT INSIDE EDGE diff) < 0.42 ABUT < 90 REGION OPPOSITE
}
diff.WID.8 {
    @ diff.WID.8: Min width of gate inside areaid:standardc < 0.36
    INTERNAL ((GATE_PERI AND STDCID) COINCIDENT INSIDE EDGE diff) < 0.36 ABUT < 90 REGION OPPOSITE
}
diff.SP.1 {
    @ diff.SP.1: Min spacing/notch of diff < 0.27
    EXTERNAL diffi < 0.27 ABUT < 90 SINGULAR REGION
}
diff.WID.9 {
    @ diff.WID.9: Min width of tap butting diff < 0.29
    ENCLOSURE (diff COINCIDENT OUTSIDE EDGE tap) tap < 0.29 ABUT < 90 MEASURE COINCIDENT REGION
}
diff.WID.10 {
    @ diff.WID.10: Min width of tap in periphery butting and between diff < 0.40
    INTERNAL (tap_PERI COINCIDENT OUTSIDE EDGE diff) < 0.40 ABUT < 90 REGION
}
diff.WARN.2 {
    @ diff.WARN.2: diff and tap are not allowed to extend beyond their abutting edge
    (EXPAND EDGE ((TOUCH EDGE tap diff) OUTSIDE EDGE diff) OUTSIDE BY 0.005) OR (EXPAND EDGE ((TOUCH EDGE diff tap) OUTSIDE EDGE tap) OUTSIDE BY 0.005)
}
diff.SP.2 {
    @ diff.SP.2: Min spacing of diff butting edge to non-coincident diff edge < 0.13
    (EXTERNAL nsdm (AND diffi psdm) < 0.13 OPPOSITE PARALLEL ONLY REGION) OR (EXTERNAL psdm (AND diffi nsdm) < 0.13 OPPOSITE PARALLEL ONLY REGION)
}
diff.ENC.1 {
    @ diff.ENC.1: Min enclosure of pdiff in periphery outside areaid:esd or v20 by nwell < 0.18
    ENCLOSURE ((PDIFF_PERI NOT ((ESD_nwell_tap OR ENID) OR v20)) AND nwell) nwell < 0.18 MEASURE ALL ABUT < 90 SINGULAR REGION
}
diff.SP.3 {
    @ diff.SP.3: Min spacing of ndiff outside (areaid:esd or v20) or nwell outside areaid:esd < 0.34
    EXTERNAL (NDIFF_PERI NOT (ESD_nwell_tap OR ENID)) nwell_noesd < 0.34 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff.ENC.2 {
    @ diff.ENC.2: Min enclosure of ntap outside areaid:esd or v20 by nwell < 0.18
    ENCLOSURE ((NTAP_PERI NOT (ESD_nwell_tap OR v20)) AND nwell) nwell < 0.18 MEASURE ALL ABUT < 90 SINGULAR REGION
}
diff.SP.4 {
    @ diff.SP.4: Min spacing of ptap outside v20 to nwell < 0.13
    EXTERNAL (PTAP NOT v20) nwell < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff.WID.11 {
    @ diff.WID.11: Min width of gate in areaid:core < 0.14
    INTERNAL (emosgate_CORE COINCIDENT INSIDE EDGE diff) < 0.14 ABUT < 90 REGION
}
diff.WID.12 {
    @ diff.WID.12: Min width of tap in areaid:core butting & between diff < 0.38
    INTERNAL (tap_CORE COINCIDENT OUTSIDE EDGE diff) < 0.38 ABUT < 90 REGION
}
diff.ENC.3 {
    @ diff.ENC.3: Min enclosure of pdiff in areaid:core by nwell < 0.15
    ENCLOSURE (pdiff_CORE AND nwell) nwell < 0.15 MEASURE ALL ABUT < 90 SINGULAR REGION
}
diff.ENC.4 {
    @ diff.ENC.4: Min enclosure of ntap in areaid:core by nwell < 0.15
    ENCLOSURE (NTAP_CORE AND nwell) nwell < 0.15 MEASURE ALL ABUT < 90 SINGULAR REGION
}
diff.ENC.5 {
    @ diff.ENC.5: Min enclosure of adjacent sides of pdiff in areaid:core by nwell < 0.18
    NOT RECTANGLE (EXPAND EDGE (ENCLOSURE [pdiff_CORE] nwell < 0.18 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0) INSIDE BY 0.005) ORTHOGONAL ONLY
}
diff.ENC.6 {
    @ diff.ENC.6: Min enclosure of adjacent sides of ndiff in areaid:core by pwell < 0.34
    NOT RECTANGLE (EXPAND EDGE (ENCLOSURE [ndiff_CORE] pwell < 0.34 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0) INSIDE BY 0.005) ORTHOGONAL ONLY
}
diff.SP.5 {
    @ diff.SP.5: Min spacing of ndiff in areaid:core & nwell < 0.32
    EXTERNAL ndiff_CORE nwell < 0.32 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff.SP.6 {
    @ diff.SP.6: Min spacing of pwbm and diff not in v20 < 0.5
    EXTERNAL pwbm (NOT diff v20) < 0.5 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}


//
// NSDM and PSDM checks
//


ZENERID = COPY 4002
ENIDgate = poly AND ENID
ENIDsource = INTERACT diff ENIDgate
ENIDNsource = NOT INTERACT NDIFF ENIDgate
pDiffTapNotENIDsource = pDiffTap NOT (ENIDsource OR ZENERID)
nDiffTapNotENIDsource = (ndiffTap NOT ENIDsource) NOT SEALID_6um
nDiffTapNotENIDsource_not_gated_npn = nDiffTapNotENIDsource NOT (gated_npn OR ZENERID)
nsdmFoo = nsdm NOT ZENERID
psdmFoo = psdm NOT ZENERID
nsdm_width = INTERNAL nsdm < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
nsdm.WID.1 {
    @ nsdm.WID.1: Min width of nsdm across areaid:core < 0.38
    SIZE ((INTERNAL (nsdm NOT COREID) < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE (CUT nsdm_width COREID)) BY 0.005 INSIDE OF nsdm_width STEP 0.38
}
nsdm.WID.2 {
    @ nsdm.WID.2: Min width of nsdm in PERI < 0.38
    nsdm_width OUTSIDE COREID
}
nsdm.WID.3 {
    @ nsdm.WID.3: Min width of nsdm in COREID < 0.29
    (INTERNAL nsdm < 0.29 ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE COREID
}
nsdm.SP.1 {
    @ nsdm.SP.1: Min spacing/notch of nsdm in periphery < 0.38
    EXTERNAL nsdm_PERI < 0.38 ABUT < 90 SINGULAR REGION
}
nsdm.SP.2 {
    @ nsdm.SP.2: Min spacing of nsdm across areaid:core boundary < 0.38
    EXTERNAL nsdm_CORE nsdm_PERI > 0 < 0.38 ABUT > 0 < 90 SINGULAR REGION
}
diff2chk = (nsdm AND diffi) NOT (((diffi AND v5) AND thkox) INSIDE npn)
nsdm.ENC.1 {
    @ nsdm.ENC.1: Min enclosure of n+ diff by nsdm < 0.125
    (ENC [diff2chk] nsdm < 0.125 SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE tap
}
nsdm.ENC.2 {
    @ nsdm.ENC.2: Min enclosure of n+ tap in peri by nsdm < 0.125
    (ENCLOSURE [NTAP_PERI] nsdm < 0.125 SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE diff
}
nsdm.SP.3 {
    @ nsdm.SP.3: Min spacing of nsdm & opposite implant diff or tap < 0.13
    EXTERNAL nsdm diffTap < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsdm.OVL.1 {
    @ nsdm.OVL.1: nsdm must not overlap pdiff/ptap (source of extendedDrain fet exempted)
    nsdm AND pDiffTapNotENIDsource
}
nsdm.AR.1 {
    @ nsdm.AR.1: Min area of nsdm < 0.265
    AREA nsdm < 0.265
}
nsdm.AR.2 {
    @ nsdm.AR.2: Min area of nsdmHole < 0.265
    AREA ((HOLES nsdm) NOT nsdm) < 0.265
}
nsdm.WID.4 {
    @ nsdm.WID.4: Min width of nsdm (opposite parallel) < 0.38
    (INTERNAL nsdm < 0.38 OPPOSITE PARALLEL ONLY REGION) INSIDE COREID
}
nsdm.SP.4 {
    @ nsdm.SP.4: Min spacing/notch of nsdm in areaid:core (opposite parallel) < 0.38
    EXTERNAL nsdm_CORE < 0.38 REGION PARALLEL ONLY OPPOSITE
}
nsdm.SP.5 {
    @ nsdm.SP.5: Min spacing/notch of nsdm in areaid:core < 0.29
    EXTERNAL nsdm_CORE < 0.29 ABUT < 90 SINGULAR REGION
}
nsdm.ENC.3 {
    @ nsdm.ENC.3: Min enclosure of n+ tap in areaid:core by nsdm < 0.13
    (ENCLOSURE [NTAP_CORE] nsdm < 0.13 SINGULAR MEASURE ALL ABUT > 0 < 90) OUTSIDE EDGE diff
}
psdm_width = INTERNAL psdm < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
psdm.WID.1 {
    @ psdm.WID.1: Min width of psdm across areaid:core < 0.38
    SIZE ((psdm NOT COREID) INSIDE (CUT psdm_width COREID)) BY 0.005 INSIDE OF psdm_width STEP 0.38
}
psdm.WID.2 {
    @ psdm.WID.2: Min width of psdm in PERI < 0.38
    psdm_width OUTSIDE COREID
}
psdm.WID.3 {
    @ psdm.WID.3: Min width of psdm in COREID < 0.29
    (INTERNAL psdm < 0.29 ABUT < 90 SINGULAR REGION EXCLUDE FALSE) INSIDE COREID
}
psdm.SP.1 {
    @ psdm.SP.1: Min spacing/notch of psdm in periphery < 0.38
    EXTERNAL psdm_PERI < 0.38 ABUT < 90 SINGULAR REGION
}
psdm.SP.2 {
    @ psdm.SP.2: Min spacing of psdm across areaid:core boundary < 0.38
    EXTERNAL psdm_CORE psdm_PERI > 0 < 0.38 ABUT > 0 < 90 SINGULAR REGION
}
psdm.ENC.1 {
    @ psdm.ENC.1: Min enclosure of p+ diff by psdm < 0.125
    (ENC [PDIFF] psdm < 0.125 SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE tap
}
psdm.ENC.2 {
    @ psdm.ENC.2: Min enclosure of p+ tap in peri by psdm < 0.125
    (ENCLOSURE [PTAP_PERI] psdm < 0.125 SINGULAR MEASURE ALL ABUT < 90) OUTSIDE EDGE diff
}
psdm.SP.3 {
    @ psdm.SP.3: Min spacing of psdm & opposite implant diff or tap < 0.13
    EXTERNAL psdm diffTap < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
psdm.OVL.1 {
    @ psdm.OVL.1: psdm must not overlap ndiff/ntap (source of extendedDrain fet exempted)
    psdm AND nDiffTapNotENIDsource
}
psdm.AR.1 {
    @ psdm.AR.1: Min area of psdm < 0.255
    AREA psdm < 0.255
}
psdm.AR.2 {
    @ psdm.AR.2: Min area of psdmHole < 0.265
    AREA ((HOLES psdm) NOT psdm) < 0.265
}
psdm.WID.4 {
    @ psdm.WID.4: Min width of psdm (opposite parallel) < 0.38
    (INTERNAL psdm < 0.38 OPPOSITE PARALLEL ONLY REGION) INSIDE COREID
}
psdm.SP.4 {
    @ psdm.SP.4: Min spacing/notch of psdm in areaid:core (opposite parallel) < 0.38
    EXTERNAL psdm_CORE < 0.38 REGION PARALLEL ONLY OPPOSITE
}
psdm.SP.5 {
    @ psdm.SP.5: Min spacing/notch of psdm in areaid:core < 0.29
    EXTERNAL psdm_CORE < 0.29 ABUT < 90 SINGULAR REGION
}
psdm.ENC.3 {
    @ psdm.ENC.3: Min enclosure of p+ tap in areaid:core by psdm < 0.12
    (ENCLOSURE [PTAP_CORE] psdm < 0.12 SINGULAR MEASURE ALL ABUT > 0 < 90) OUTSIDE EDGE diff
}


//
// Poly checks
//


poly.WID.1 {
    @ poly.WID.1: Min width of poly over diff inside thkox in periphery < 0.5
    INTERNAL (INTERNAL (poly COINCIDENT EDGE (gate_PERI AND thkox)) < 0.5 OPPOSITE PARALLEL ONLY REGION) < 0.5 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
poly.CON.2 {
    @ poly.CON.2: gate must not straddle thkox
    CUT GATE thkox
}
poly.WID.2 {
    @ poly.WID.2: Min width of poly < 0.15
    INTERNAL poly < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
poly.LEN.1 {
    @ poly.LEN.1: Min channel length of pfet overlapping lvtn < 0.35
    INTERNAL ((PFETa INTERACT (PFETa AND lvtn)) COINCIDENT OUTSIDE EDGE SRCDRN) < 0.35 OPPOSITE PARALLEL ONLY REGION
}
poly.SP.1 {
    @ poly.SP.1: Min spacing/notch of poly in periphery < 0.21
    EXTERNAL poly_PERI < 0.21 ABUT < 90 SINGULAR REGION
}
poly.SP.2 {
    @ poly.SP.2: Min spacing of poly not covered by cell sr_bltd_eq across areaid:core boundary < 0.21
    poly2noXmt = poly NOT (EXTENT CELL "sr_bltd_eq" ORIGINAL)
    EXTERNAL (poly2noXmt AND COREID) (poly2noXmt NOT COREID) > 0 < 0.21 ABUT > 0 < 90 SINGULAR REGION
}
polyGapLEedg = LENGTH poly_CORE <= 0.15
polyGapGoodSp = (EXPAND EDGE polyGapLEedg OUTSIDE BY (0.16/2)) INSIDE (EXTERNAL polyGapLEedg <= 0.16 OPPOSITE REGION)
poly.SP.3 {
    @ poly.SP.3: Min spacing of poly (except for poly core gap) < 0.175
    (EXTERNAL poly_CORE < 0.175 ABUT < 90 REGION SINGULAR) NOT INTERACT polyGapGoodSp
}
poly.SP.4 {
    @ poly.SP.4: Min spacing of poly for poly core gap < 0.16
    (EXTERNAL poly_CORE < 0.16 ABUT < 90 REGION SINGULAR) INTERACT polyGapGoodSp
}
poly.WID.3 {
    @ poly.WID.3: Min width of poly resistor < 0.33
    q0polyAndRes = poly COINCIDENT OUTSIDE EDGE polyres
    q1polyAndRes = LENGTH q0polyAndRes < 0.33
    q2polyAndRes = EXPAND EDGE q1polyAndRes OUTSIDE BY 0.005 CORNER FILL
    q3polyAndRes = polyres WITH EDGE (polyres COINCIDENT EDGE q2polyAndRes)
    q4polyAndRes = polyres OUTSIDE EDGE poly
    q5polyAndRes = EXPAND EDGE q4polyAndRes INSIDE BY 0.16 CORNER FILL
    q6polyAndRes = polyres NOT q5polyAndRes
    q7polyAndRes = INTERNAL q6polyAndRes < 0.005 ABUT < 90 REGION
    q8polyAndRes = q6polyAndRes NOT q7polyAndRes
    q9polyAndRes = INTERACT polyres (polyres AND q8polyAndRes) == 1
    q10polyAndRes = polyres NOT q9polyAndRes
    q3polyAndRes OR q10polyAndRes
}
poly.SP.5 {
    @ poly.SP.5: Min spacing of poly in periphery & diff < 0.075
    EXTERNAL poly_PERI diff < 0.075 ABUT == 0 REGION PARALLEL ONLY EXCLUDE FALSE
}
poly.SP.6 {
    @ poly.SP.6: Min spacing of poly in periphery & tap < 0.055
    EXTERNAL poly_PERI tap < 0.055 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
GATESIDE_PERI = GATESIDE OUTSIDE EDGE COREID
poly.ENC.1 {
    @ poly.ENC.1: Min extension of diff edge butting a tap beyond gate edge in periphery < 0.3
    ENCLOSURE GATESIDE_PERI diffTapEdge < 0.3 MEASURE COINCIDENT ABUT < 90 REGION
}
poly.ENC.2 {
    @ poly.ENC.2: Min extension of diff beyond gate edge in periphery < 0.25
    ENCLOSURE GATESIDE_PERI diff < 0.25 MEASURE COINCIDENT ABUT < 90 REGION
}
poly.ENC.3 {
    @ poly.ENC.3: Min extension of poly beyond gate end in periphery < 0.13
    ENCLOSURE (GATEEND OUTSIDE EDGE COREID) poly < 0.13 MEASURE COINCIDENT ABUT < 90 REGION
}
poly.SP.7 {
    @ poly.SP.7: Min spacing of high precision or high sheet poly resistor & diff < 0.48
    EXTERNAL (polyres INTERACT (rpm OR urpm)) diffTap < 0.48 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
poly.OVL.1 {
    @ poly.OVL.1: poly resistor must not overlap diff or tap
    polyres AND diffTap
}
poly.SP.8 {
    @ poly.SP.8: Min spacing of poly resistor & poly < 0.21
    EXTERNAL polyres poly < 0.21 ABUT > 0 < 90 SINGULAR REGION EXCLUDE FALSE
}
q1poly = NOT RECTANGLE (poly AND diff) ORTHOGONAL ONLY
poly.OVL.2 {
    @ poly.OVL.2: poly must not overlap any inner corner of diff
    (EXTERNAL q1poly <= 0.005 ABUT REGION) AND poly
}
poly.ANG.1 {
    @ poly.ANG.1: No 90 degree bends of poly on diff
    q2poly = INTERNAL q1poly <= 0.005 ABUT == 90 PERPENDICULAR ONLY REGION
    q4poly = q2poly WITH EDGE (q2poly COINCIDENT INSIDE EDGE diff)
    q6poly = q2poly NOT q4poly
    q3poly = EXTERNAL q1poly <= 0.005 ABUT == 90 PERPENDICULAR ONLY REGION
    q5poly = TOUCH q3poly diff
    q7poly = q3poly NOT q5poly
    q8poly = q6poly OR q7poly
    COPY q8poly
}
poly.OVL.3 {
    @ poly.OVL.3: poly not in nwell or v20 must not overlap a tap in the periphery
    exemptNhvnativeCell = EXTENT CELL "s8fgvr_fg2n" ORIGINAL
    PolyNotLvNwell = (poly NOT lvNwell_drc) NOT (exemptNhvnativeCell OR (gated_npn OR v20))
    PolyNotLvNwellno_v20 = PolyNotLvNwell NOT v20
    PolyNotLvNwellno_v20_not_npn_5v = (PolyNotLvNwell NOT v20) NOT (npn AND v5)
    PolyNotLvNwellno_v20_not_npn_5v AND tap_PERI
}
poly.OVL.4 {
    @ poly.OVL.4: poly must not overlap diffres
    poly AND diffres
}
poly.SP.9 {
    @ poly.SP.9: Min spacing of poly in areaid:core & diff < 0.03
    EXTERNAL poly_CORE diff < 0.03 ABUT == 0 REGION PARALLEL ONLY EXCLUDE FALSE
}
poly.SP.10 {
    @ poly.SP.10: Min spacing of poly in areaid:core & tap < 0.03
    EXTERNAL poly_CORE tap < 0.03 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}


//
// coreID checks
//


validCoreID9 = INSIDE CELL COREID s8cell_ee_bseln s8cell_ee_cellcorn_n s8cell_ee_termcella  s8cell_ee_bselp s8cell_ee_cellcorn_p s8cell_ee_termcella_int s8cell_ee_cell s8cell_ee_colend_lasta  s8cell_ee_termcellb s8cell_ee_cell_int s8cell_ee_colend_lastb s8cell_ee_termcellb_int  s8cell_ee_cell_last s8cell_ee_colenda s8cell_mcell4_last_int s8cell_ee_cell_last_int s8cell_ee_colendb  s8sram_colenda s8sram_precharge_ce_3x s8sram_colend_cent s8sram_horstrap_opt1_blx_ce s8sram_rowend_hstrap_ce  s8sram_colend s8sram_cell s8sram_hor_wlstrap_ce s8sram_cornera s8sram_precharge s8sram_precharge_ce  s8sram_precharge_end_2x s8sram_corner s8sram_precharge_end s8sram_precharge_end_3x s8sram_wlstrap_ce  s8sram_colenda_cent s8sram_precharge_2x s8sram_rowend_ce s8sram_horstrap_opt1_ce s8sram_precharge_3x  s8sram_precharge_ce_2x s8sram_precharge_ce_via1 s8sram_precharge_ce_2x_via1 s8sram_precharge_ce_3x_via1  s8sram_precharge_end_via1 s8sram_precharge_end_2x_via1 s8sram_precharge_end_3x_via1  s8cell_col_precharge s8cell_sp_colend_opt1_ce s8cell_sp_horstrap_opt1_ce  s8cell_col_precharge_ce s8cell_sp_colend_opt1a_ce s8cell_sp_horstrap_opt3_ce  s8cell_col_precharge_end s8cell_sp_colend1_ce s8cell_sp_rowend_ce s8cell_sp_cell  s8cell_sp_corner_ce s8cell_sp_rowend_hstrap_ce s8cell_sp_colend_ce s8cell_sp_hor_wlstrap_ce s8cell_sp_wlstrap_ce  s8cell_sp_colend_cent_ce s8cell_sp_horstrap_opt1_blx_ce s8cell_tc_tech_CD_top s8cell_tc_tech_CD_lcross  s8cell_tc_tech_CD_top_pcell s8nvlatch_cell1ux s8nvlatch_lvD s8nvlatch_s8cell_ee_cell s8nvlatch_cell s8nvlatch_lvC  s8nvlatch_cellg s8nvlatch_cells s8nvlatch_s8cell_ee_cell_back s8cell_nvlfp_cell s8sram16x16_wlstrap_p_ce   s8sram16x16_colend s8sram16x16_ctl_load_unit s8sram16x16_colend_p_cent s8sram16x16_colenda   s8sram16x16_wlstrapa2x s8sram16x16_cornerb s8sram16x16_rowend_ce s8sram16x16_wlstrap2x s8sram16x16_cornera  s8sram16x16_colenda_p_cent s8sram16x16_corner s8sram16x16_ctl_load s8cell_ee_colend_last s8cell_ee_colend s8cell_ee_cell  
 s8cell_ee_corner_east s8cell_ee_cell_opt0 s8cell_ee_colend_lastb_opt0 s8cell_ee_cell_last  s8cell_ee_termcellb_ref s8cell_ee_colendb s8cell_ee_cellcorn_p_ref_opt0 s8cell_ee_termcella_ref  s8cell_ee_colenda s8cell_ee_colenda_opt0 s8cell_ee_rowend_west s8cell_ee_corner_east_opt0 s8cell_ee_rowend_east_opt0  
 s8cell_ee_cellcorn_n_ref_opt0 s8cell_ee_corner_west_opt0 s8cell_ee_colend_lasta_opt0 s8cell_ee_cell_last_opt0  s8cell_ee_cellcorn_p_ref s8cell_ee_rowend_west_opt0 s8cell_ee_termcellb_ref_opt0 s8cell_ee_corner_west  s8cell_ee_colend_opt0 s8cell_ee_rowend_east s8cell_ee_cellcorn_n_ref s8cell_ee_colend_lastb  s8cell_ee_termcella_ref_opt0 s8cell_ee_colenda_d s8cell_ee_colend_lasta s8cell_ee_colendb_opt0  s8cell_ee_colend_lasta_d s8cell_ee_bseln_enda_d s8cell_ee_bseln_enda_poly_d s8cell_ee_bselp_enda_d  s8cell_ee_plus_1t_cell s8cell_ee_plus_rowtie_ref s8cell_ee_plus_sselptie_ref s8cell_ee_plus_sselp_ref  s8cell_ee_plus_sselntie_ref s8cell_ee_plus_sseln_a s8cell_ee_plus_sseln_b s8cell_ee_plus_coltie_ref  s8cell_ee_plus_corner_tie s8cell_ee_plus_sselp_a s8cell_ee_plus_sselp_b sr_blld sr_mcell_tie up_rom_tie sr_bltd_eq  sr_tcell up_rom1 sr_mcell sr_tcell_tie up_romref sr_mcell_tie_L sr_mcell_tie_R sr_tcell_tie_L sr_tcell_tie_R  s8tnvcell_mcell_tie_END_b_cell7 s8tnvcell_mcell_tie_END_t_cell7 s8tnvcell_tcell_END_t_cell7  s8tnvcell_tcell_END_b_cell7 s8tnvcell_mcell_tie_END_sub_t_cell7 s8tnvcell_mcell_tie_END_sub_b_cell7  s8tnvcell_tcell_tie_Rt_cell7 s8tnvcell_tcell_tie_Rb_cell7 s8tnvcell_mcell_tie_Rt_cell7 s8tnvcell_mcell_tie_Rb_cell7  s8tnvcell_mcell_Mt_cell7 s8tnvcell_mcell_Mb_cell7 s8tnvcell_mcell_t_cell7 s8tnvcell_mcell_b_cell7  s8tnvcell_tcell_t_cell7 s8tnvcell_tcell_b_cell7 s8tnvcell_mcell_tie_Lt_cell7 s8tnvcell_mcell_tie_Lb_cell7  s8tnvcell_tcell_tie_Lb_cell7 s8tnvcell_tcell_tie_Lt_cell7 s8tnvcell_tcell_tie_t_cell7 s8tnvcell_tcell_tie_b_cell7  s8tnvcell_mcell_tie_t_cell7 s8tnvcell_mcell_tie_b_cell7 s8tnvssr_bltd_eq s8tnvssr_bltd_tie s8tnvssr_blld_tie  s8tnvssr_blld s8ovation_atc2_pd_12_6_BiCell
validCoreID1 = INSIDE CELL COREID ram8_buildspace s8diaet_md3235_a s8diaet_md7301_a s8diaet_md7302_a  s8diaet_md7303_a s8diaet_md7304_a s8diaet_md7321_a s8diaet_md7322_a s8diaet_md7333_a s8diaet_md7334_a  s8diaet_s7333_hvpmos_cap_a s8Fab_etch_a s8Fab_etch_b s8Fab_etch_c s8Fab_etch_d s8Fab_etch_e s8Fab_etch_f s8Fab_fab_fomc  s8Fab_fab_li1mc s8Fab_fab_pimc s8Fab_fabCD_b s8Fab_fabCD_c s8Fab_fabCD_d s8Fab_fabCD_e s8Fab_plot_etch_a  s8Fab_sem_CDcross s8Fab_tech_CD_drawn_a s8te2et_2t_cell_end01 s8te2et_2t_cell_end01_NoVia s8te2et_2t_cell_end01_sonos_Diff  s8te2et_2t_cell_end01_sonos_Diff_b s8te2et_2t_cell_end01_sonos_Diff_R s8te2et_2t_cell_end02_opt1_L  s8te2et_2t_cell_end02_opt1_L_b s8te2et_2t_cell_end02_opt1_R s8te2et_2t_cell_end02_opt1_R01 s8te2et_2t_cell_end02_opt2_L  s8te2et_2t_cell_end02_opt2_L_b s8te2et_2t_cell_end02_opt2_L_c s8te2et_2t_cell_end02_opt2_R s8te2et_2t_cell_end02_opt2_R01  s8te2et_2t_cell_end02_opt3_L s8te2et_2t_cell_end02_opt3_L_b s8te2et_2t_cell_end02_opt3_L_c s8te2et_2t_cell_end02_opt3_R  s8te2et_2t_cell_end02_opt3_R01 s8te2et_2t_cell_end02_opt4_L s8te2et_2t_cell_end02_opt4_L_c s8te2et_2t_cell_end02_opt4_R  s8te2et_2t_cell_end02_opt4_R01 s8te2et_2t_cell_end02_sonos_Diff s8te2et_2t_cell_end02_sonos_Diff_b   s8te2et_2t_cell_end02_sonos_Diff_L s8te2et_2t_cell_end02_sonos_Diff_L_b s8te2et_2t_cell_end02_sonos_Diff_R   s8te2et_2t_cell_option1_swap s8te2et_2t_cell_option1_swap_b s8te2et_2t_cell_option1_swap_ncBot  
 s8te2et_2t_cell_option1_swap_ncBot_b s8te2et_2t_cell_option1_swap_ncTop s8te2et_2t_cell_option1_swap_ncTop_b  
 s8te2et_2t_cell_option2_swap s8te2et_2t_cell_option2_swap_b s8te2et_2t_cell_option2_swap_ncBot   s8te2et_2t_cell_option2_swap_ncBot_b s8te2et_2t_cell_option2_swap_ncTop s8te2et_2t_cell_option2_swap_ncTop_b  s8te2et_2t_cell_option3_swap s8te2et_2t_cell_option3_swap_b s8te2et_2t_cell_option3_swap_c  s8te2et_2t_cell_option3_swap_ncTop s8te2et_2t_cell_option3_swap_ncTop_b s8te2et_2t_cell_option3_swap_ncTop_c  
 s8te2et_2t_cell_option3_swap1_ncBot s8te2et_2t_cell_option3_swap1_ncBot_b s8te2et_2t_cell_option3_swap1_ncBot_c  
 s8te2et_2t_cell_option4_swap s8te2et_2t_cell_option4_swap_c s8te2et_2t_cell_option4_swap_ncBot  
 s8te2et_2t_cell_option4_swap_ncBot_c s8te2et_2t_cell_option4_swap_ncTop s8te2et_2t_cell_option4_swap_ncTop_c  s8te2et_2t_cell_sonos_Diff_swap s8te2et_2t_cell_sonos_Diff_swap_b s8te2et_2t_cell_sonos_Diff_swap_ncTop  s8te2et_2t_cell_sonos_Diff_swap_ncTop_b s8te2et_2t_cell_sonos_Diff_swap1_ncBot s8te2et_2t_cell_sonos_Diff_swap1_ncBot_b  s8te2et_2t_cell_sonos_Diff_swapR s8te2et_2t_cell_sonos_Diff_swapR_b s8te2et_2t_cellcrnr_L s8te2et_2t_cellcrnr_R  s8te2et_md1005_a s8te2et_md1092_a s8te2et_md1701_a
validCoreID2 = INSIDE CELL COREID s8te2et_md1702_a s8te2et_md1702_b s8te2et_md1703_a s8te2et_md1705_a  
 s8te2et_md1773_a s8te2et_md3235_a s8te2et_md3242_b s8te2et_md3244_b s8te2et_md3248_d s8te2et_md3251_b s8te2et_md3277_b  s8te2et_md3288_b s8te2et_md3288_c s8te2et_md7301_a s8te2et_md7302_a s8te2et_md7303_a s8te2et_md7304_a s8te2et_md8111_a   s8te2et_md8113_a s8te2et_PassGate_sonos_Fet_novia s8te2et_s_hv_depmos_dieler_opt1 s8te2et_s_hv_depmos_dieler_opt2  
 s8te2et_s_hv_depmos_dieler_opt3 s8te2et_s0755_rowend_1 s8te2et_s0790_cell_1 s8te2et_s0790_cell_2 s8te2et_s0790_colend_1  
 s8te2et_s0791_cell_1 s8te2et_s0791_colend_1 s8te2et_s0791_rowend_1 s8te2et_s1700_hier0_basecell_a  s8te2et_s1700_hier0_basecell_b s8te2et_s1700_hier0_bot_basecell_a s8te2et_s1700_hier0_corner_a s8te2et_s1700_hier0_elem_a  s8te2et_s1700_hier0_elem_b s8te2et_s1700_hier0_left_a s8te2et_s1700_hier0_rcorner_a s8te2et_s1700_hier0_right_a  
 s8te2et_s1700_hier0_top_basecell_a s8te2et_s1701_hier0_base_cell_a s8te2et_s1701_hier0_bot_con_a  s8te2et_s1701_hier0_corner_a s8te2et_s1701_hier0_lft_con_a s8te2et_s1701_hier0_rht_con_a s8te2et_s1701_hier0_top_con_a  s8te2et_s1702_hier0_base_cell_a s8te2et_s1702_hier0_base_cell_b s8te2et_s1702_hier0_bot_a s8te2et_s1702_hier0_corner_l_a  s8te2et_s1702_hier0_corner_r_a s8te2et_s1702_hier0_left_a s8te2et_s1702_hier0_right_a s8te2et_s1702_hier0_top_a  s8te2et_s1703_hier0_base_cell_a s8te2et_s1703_hier0_bot_con_a s8te2et_s1703_hier0_corner_a s8te2et_s1703_hier0_lft_con_a  s8te2et_s1703_hier0_rht_con_a s8te2et_s1703_hier0_top_con_a s8te2et_s1705_hier0_base_cell_a s8te2et_s1709_hier0_base_cell_a  s8te2et_s1709_hier0_lft_con_a s8te2et_s1709_hier0_rht_con_a s8te2et_s1709_hier0_top_con_a s8te2et_s1726_hier0_base_cell_a  s8te2et_s1726_hier0_base_cell_b s8te2et_s1726_hier0_lft_con_a s8te2et_s1726_hier0_rht_con_b s8te2et_s1726_hier1_array_b  s8te2et_s1726_hier1_array_c s8te2et_s1726_hier1_array_d s8te2et_s1726_hier2_array_a s8te2et_s1743_hier0_base_cell_a  s8te2et_s1743_hier0_sl_a s8te2et_s1743_hier0_sr_a s8te2et_s1743_hier1_array_a s8te2et_s1743_hier1_array_b  s8te2et_s1744_hstrap_term_a s8te2et_s1744_hstrap_term_n_a s8te2et_s1744_hstrap2_a s8te2et_s1744_npass_a  s8te2et_s1744_npass_b s8te2et_s1744_npass_cent_a s8te2et_s1744_npass_horiz_term_cent_a  s8te2et_s1744_npass_vert_a s8te2et_s1744_npd_a s8te2et_s1744_npd_b s8te2et_s1744_npd_cent_a s8te2et_s1744_npd_horiz_a  s8te2et_s1744_npd_horiz_term_a s8te2et_s1744_npd_horiz_term_cent_a s8te2et_s1744_npd_horiz_term_wl_a  s8te2et_s1744_npd_vert_a s8te2et_s1744_npd_vert_term_cent_a
validCoreID3 = INSIDE CELL COREID s8te2et_s1744_ppu_a s8te2et_s1744_ppu_b s8te2et_s1744_ppu_cent_c  s8te2et_s1744_ppu_corn_a s8te2et_s1744_ppu_cornu_a s8te2et_s1744_ppu_vert_a s8te2et_s1744_ppu_vert_hstrap2_a  s8te2et_s1744_ppu_vert_term_a s8te2et_s1744_ppu_vert_term_cent_a s8te2et_s1744_topbot_hstrap2_a  s8te2et_s1756_hier0_base_cell_1_a s8te2et_s1756_hier0_base_cell_1_b s8te2et_s1756_hier0_base_cell_2_a  s8te2et_s1756_hier0_bot_con_1_a s8te2et_s1756_hier0_bot_con_2_a s8te2et_s1756_hier0_top_con_1_a  s8te2et_s1756_hier0_top_con_2_a s8te2et_s1756_hier1_array_2_a s8te2et_s1756_npass_bot_term_a  s8te2et_s1756_npass_top_term_a s8te2et_s1756_npd_4x2_a s8te2et_s1756_npd_4x2_b s8te2et_s1756_npd_a s8te2et_s1756_npd_b  s8te2et_s1756_npd_bot_term_a s8te2et_s1756_npd_top_term_a s8te2et_s1758_ppu_4x2_a  s8te2et_s1758_ppu_4x2_c s8te2et_s1758_ppu_a s8te2et_s1758_ppu_bot_term_a s8te2et_s1758_ppu_c s8te2et_s1758_ppu_top_term_a  s8te2et_s1760_hier1_array_a s8te2et_s1760_hier1_array_b s8te2et_s1761_hier1_array_a s8te2et_s1762_hier0_cell_1  s8te2et_s1762_hier0_colend_a s8te2et_s1762_hier0_rowend_2_a s8te2et_s1762_hier1_array_b s8te2et_s1773_hier0_base_cell_a  s8te2et_s2t_cell_end02 s8te2et_s2t_cell_end02_NoVia s8te2et_s2t_cell_end03 s8te2et_s2t_cell_end03_NoVia s8te2et_s2t_cellcrnr_01_L  s8te2et_s2t_cellcrnr_01_R s8te2et_s3243_sonos_0p42_0p18 s8te2et_s3243_sonos_0p42_0p18_c s8te2et_s3243_sonos_0p42_0p22  s8te2et_s3243_sonos_0p42_0p22_c s8te2et_s3243_sonos_0p42_0p26 s8te2et_s3243_sonos_0p42_0p26_c s8te2et_s3243_sonos_25_0p22  s8te2et_s3243_sonos_25_0p22_c s8te2et_s3243_sonos_25_25 s8te2et_s3243_sonos_25_25_c s8te2et_s3248_sonos_2p0_2p0  s8te2et_s3248_sonos_2p0_2p0_d s8te2et_s3255_MiniArray_b s8te2et_s3259_2t_cell_end02_opt2_L  s8te2et_s3259_2t_cellcrnr_L s8te2et_s3262_2t_cell_a s8te2et_s3262_2t_cell_end02_L s8te2et_s3262_2t_cell_end02_R  s8te2et_s3262_2t_cell_end02_R01 s8te2et_s3262_2t_cell_ncBot s8te2et_s3262_2t_cell_ncTop s8te2et_s3263_2t_cell_a  s8te2et_s3263_2t_cell_end02_L s8te2et_s3263_2t_cell_end02_R s8te2et_s3263_2t_cell_end02_R01 s8te2et_s3263_2t_cell_ncBot  s8te2et_s3263_2t_cell_ncTop s8te2et_s3264_2t_2x2_b s8te2et_s3264_2t_2x2_NoVia_b s8te2et_s3264_2t_cell_a s8te2et_s3264_2t_cell_c  s8te2et_s3264_2t_cell_end02_L s8te2et_s3264_2t_cell_end02_L_b s8te2et_s3264_2t_cell_end02_L_c s8te2et_s3264_2t_cell_end02_R  s8te2et_s3264_2t_cell_end02_R01 s8te2et_s3264_2t_cell_ncBot s8te2et_s3264_2t_cell_ncBot_c s8te2et_s3264_2t_cell_ncTop  s8te2et_s3264_2t_cell_ncTop_c s8te2et_s3265_2t_cell_a s8te2et_s3265_2t_cell_b s8te2et_s3265_2t_cell_end01 s8te2et_s3265_2t_cell_end01_NoVia  s8te2et_s3265_2t_cell_end02_L s8te2et_s3265_2t_cell_end02_L_b s8te2et_s3265_2t_cell_end02_R s8te2et_s3265_2t_cell_end02_R01 s8te2et_s3265_2t_cell_ncBot
validCoreID4 = INSIDE CELL COREID s8te2et_s3265_2t_cell_ncBot_b s8te2et_s3265_2t_cell_ncTop s8te2et_s3265_2t_cell_ncTop_b  s8te2et_s3266_2t_cell_a s8te2et_s3266_2t_cell_b s8te2et_s3266_2t_cell_end02_L s8te2et_s3266_2t_cell_end02_L_b s8te2et_s3266_2t_cell_end02_R  s8te2et_s3266_2t_cell_end02_R01 s8te2et_s3266_2t_cell_ncBot s8te2et_s3266_2t_cell_ncBot_b s8te2et_s3266_2t_cell_ncTop s8te2et_s3266_2t_cell_ncTop_b  s8te2et_s3267_2t_2x2_a s8te2et_s3267_2t_2x2_b s8te2et_s3267_2t_2x2_c s8te2et_s3267_PassGate_sonos_2x2 s8te2et_s3267_PassGate_sonos_2x2_b  s8te2et_s3267_PassGate_sonos_2x2_novia s8te2et_s3267_PassGate_sonos_2x2_novia_b s8te2et_s3267_PassGate_sonos_2x2_novia_c s8te2et_s3268_sonos_Fet_novia  s8te2et_s3268_sonos_Fet_novia_b s8te2et_s3268_sonos_Fet_novia_c s8te2et_s3268_Sonos_soFet_2x2 s8te2et_s3268_Sonos_soFet_2x2_c s8te2et_s3269_2t_2x2_a  s8te2et_s3269_2t_2x2_b s8te2et_s3269_2t_2x2_c s8te2et_s3269_PassGate_sonos_2x2 s8te2et_s3269_PassGate_sonos_2x2_b s8te2et_s3269_PassGate_sonos_2x2_c  s8te2et_s3270_2t_2x2_opt3 s8te2et_s3270_2t_2x2_opt3_b s8te2et_s3270_2t_2x2_opt3_c s8te2et_s3270_2x2_NoVia s8te2et_s3270_2x2_NoVia_b  s8te2et_s3270_2x2_NoVia_c s8te2et_s3270_Sonos_soFet_2x2 s8te2et_s3270_Sonos_soFet_2x2_b s8te2et_s3270_Sonos_soFet_2x2_c s8te2et_s3271_32x32_Array  s8te2et_s3272_2t_2x2_a s8te2et_s3272_2t_2x2_NoVia s8te2et_s3272_2t_cell_end02_L s8te2et_s3272_2t_cell_end02_R s8te2et_s3272_32x32_Array  s8te2et_s3273_2t_end02_L s8te2et_s3273_2t_end02_L_b s8te2et_s3273_2t_end02_R s8te2et_s3274_2x2_NoVia s8te2et_s3274_2x2_NoVia_b s8te2et_s3274_32x32_Array  s8te2et_s3274_32x32_Array_b s8te2et_s3275_2t_cell s8te2et_s3275_2t_cell_a s8te2et_s3275_2t_cell_b s8te2et_s3275_2t_cell_end01 s8te2et_s3275_2t_cell_end01_NoVia  s8te2et_s3275_2t_cell_ncBot s8te2et_s3275_2t_cell_ncTop s8te2et_s3275_2x2_NoVia s8te2et_s3275_2x2_NoVia_b s8te2et_s3275_32x32_Array  s8te2et_s3275_32x32_Array_b s8te2et_s3275_cell s8te2et_s3275_cell_end01 s8te2et_s3275_cell_end01_NoVia s8te2et_s3276_W2_L2  s8te2et_s3277_W2_L2 s8te2et_s3278_clock_latch s8te2et_s3279_8T_latch s8te2et_s3280_6T_latch s8te2et_s3280_6T_latch_b s8te2et_s3282_2T_Spl_cell2x2  s8te2et_s3282_2T_Spl_cell2x2_b s8te2et_s3282_2T_Spl_cell2x2_nc s8te2et_s3282_2T_Spl_cell2x2_nosrc s8te2et_s3282_cellend  s8te2et_s3282_cellend_cntr s8te2et_s3282_celltop s8te2et_s3282_celltop_nc s8te2et_s3283_3T_Dual_cell2x2_nc s8te2et_s3283_3T_Dual_cell2x2_nc_b  s8te2et_s3283_3T_Dual_cell2x2_nosrc s8te2et_s3283_3T_Spl_Chanel_cell s8te2et_s3283_cellend s8te2et_s3283_cellend_cntr s8te2et_s3284_1T_SSL_cell2x2  s8te2et_s3284_1T_SSL_cell2x2_nc s8te2et_s3284_1T_SSL_cell2x2_nosrc s8te2et_s3284_cellend s8te2et_s3284_cellend_cntr s8te2et_s3284_celltop s8te2et_s3284_celltop_nc
validCoreID5 = INSIDE CELL COREID s8te2et_s3286_cell2x2 s8te2et_s3286_cell2x2_nc s8te2et_s3286_cell2x2_nosrc  s8te2et_s3287_2t_cell_end02_opt3_L s8te2et_s3287_2x2 s8te2et_s3287_2x2_Bot s8te2et_s3287_2x2_NoVia  s8te2et_s3287_2x2_NoViaB s8te2et_s3287_2x2_Top s8te2et_s3287_32x32_Array s8te2et_s3287_32x32_Array_b  s8te2et_s3287_cell_end01 s8te2et_s3287_cell_end01_NoVia s8te2et_s3289_14T_latch s8te2et_s3t_cell_end  s8te2et_s3t_cell_end_01 s8te2et_s3t_cell_end_01_NoVia s8te2et_s3t_cell_end_NoVia s8te2et_s3t_cellcrnr_01_L  s8te2et_s3t_cellcrnr_01_R s8te2et_s3t_cellcrnr_L s8te2et_s3t_cellcrnr_R s8te2et_s4100_2t_cell_end02_opt3_L  s8te2et_s4100_2t_cell_option3_NP1 s8te2et_s4100_2t_cell_option3_swap_ncTop s8te2et_s4100_2t_cell_option3_swap1_ncBot  s8te2et_s4100_2t_cellcrnr_01_L s8te2et_s4100_2t_cellend_R s8te2et_s4100_2t_cellend_R01 s8te2et_s4101_2t_cell_option3_IP2  s8te2et_s4102_2t_cell_option3_swap_ncTop s8te2et_s4102_2t_cell_option3_swap1_ncBot s8te2et_s4102_2t_cell_STD  s8te2et_s4102_2t_cellend_L s8te2et_s4102_2t_cellend_R s8te2et_s4102_2t_cellend_R01 s8te2et_s4103_2t_cell_Bot  s8te2et_s4103_2t_cell_NoLvtn s8te2et_s4103_2t_cell_NP1 s8te2et_s4103_2t_cell_option3_swap_ncTop  s8te2et_s4103_2t_cell_option3_swap1_ncBot s8te2et_s4103_2t_cell_Top  s8te2et_s4103_2t_cellend_L s8te2et_s4103_2t_cellend_L_NoLvtn s8te2et_s4103_2t_cellend_R  s8te2et_s4103_2t_cellend_R01 s8te2et_s4104_2t_cell_Bot s8te2et_s4104_2t_cell_NP2 s8te2et_s4104_2t_cell_Top  s8te2et_s4104_2t_cellend_L s8te2et_s4105_2t_cell_Bot s8te2et_s4105_2t_cell_NP3 s8te2et_s4105_2t_cell_Top  s8te2et_s4105_2t_cellend_L s8te2et_s4105_2t_cellend_R s8te2et_s4105_2t_cellend_R01 s8te2et_s4106_2t_cell_Bot  s8te2et_s4106_2t_cell_NP4 s8te2et_s4106_2t_cell_Top s8te2et_s4106_2t_cellend_L s8te2et_s4106_2t_cellend_R  s8te2et_s4106_2t_cellend_R01 s8te2et_s4107_2t_cell_Bot s8te2et_s4107_2t_cell_NP5 s8te2et_s4107_2t_cell_Top  s8te2et_s4107_2t_cellend_L s8te2et_s4107_2t_cellend_R s8te2et_s4107_2t_cellend_R01 s8te2et_s4108_2t_cell_Bot  s8te2et_s4108_2t_cell_STD s8te2et_s4108_2t_cell_Top s8te2et_s4108_2t_cellend_L  s8te2et_s4108_2t_cellend_R s8te2et_s4108_2t_cellend_R01 s8te2et_s4109_2t_cell_Bot s8te2et_s4109_2t_cell_NP1  s8te2et_s4109_2t_cell_Top s8te2et_s4109_2t_cellend_L s8te2et_s4109_2t_cellend_R s8te2et_s4109_2t_cellend_R01  s8te2et_s4110_2t_cell_Bot s8te2et_s4110_2t_cell_NP2 s8te2et_s4110_2t_cell_Top s8te2et_s4110_2t_cellend_L  s8te2et_s4111_2t_cell_Bot s8te2et_s4111_2t_cell_NP3 s8te2et_s4111_2t_cell_Top s8te2et_s4111_2t_cellend_L  s8te2et_s4112_2t_cell_Bot s8te2et_s4112_2t_cell_NP4 s8te2et_s4112_2t_cell_Top  s8te2et_s4112_2t_cellend_L s8te2et_s4112_2t_cellend_R s8te2et_s4112_2t_cellend_R01 s8te2et_s4113_2t_cell_Bot
validCoreID6 = INSIDE CELL COREID s8te2et_s4113_2t_cell_NP5 s8te2et_s4113_2t_cell_Top s8te2et_s4113_2t_cellend_L s8te2et_s4113_2t_cellend_R s8te2et_s4113_2t_cellend_R01 s8te2et_s4114_2t_cell_Bot s8te2et_s4114_2t_cell_STD s8te2et_s4114_2t_cell_Top s8te2et_s4114_2t_cellend_L s8te2et_s4114_2t_cellend_R s8te2et_s4114_2t_cellend_R01 s8te2et_s4115_2t_cell_Bot s8te2et_s4115_2t_cell_NP1 s8te2et_s4115_2t_cell_Top s8te2et_s4115_2t_cellend_L s8te2et_s4115_2t_cellend_R s8te2et_s4115_2t_cellend_R01 s8te2et_s4116_2t_cell_Bot s8te2et_s4116_2t_cell_NP2 s8te2et_s4116_2t_cell_Top s8te2et_s4116_2t_cellend_L s8te2et_s4117_2t_cell_Bot s8te2et_s4117_2t_cell_NP3 s8te2et_s4117_2t_cell_Top s8te2et_s4117_2t_cellend_L s8te2et_s4118_2t_cell_Bot s8te2et_s4118_2t_cell_NP4 s8te2et_s4118_2t_cell_Top s8te2et_s4118_2t_cellend_L s8te2et_s4118_2t_cellend_R s8te2et_s4118_2t_cellend_R01 s8te2et_s4119_2t_cell_Bot s8te2et_s4119_2t_cell_NP5 s8te2et_s4119_2t_cell_Top s8te2et_s4119_2t_cellend_L s8te2et_s4119_2t_cellend_R s8te2et_s4119_2t_cellend_R01 s8te2et_s4120_2t_cell_Bot s8te2et_s4120_2t_cell_STD s8te2et_s4120_2t_cell_Top s8te2et_s4120_2t_cellend_L s8te2et_s4120_2t_cellend_R s8te2et_s4120_2t_cellend_R01 s8te2et_s4121_2t_cell_Bot s8te2et_s4121_2t_cell_NP1 s8te2et_s4121_2t_cell_Top s8te2et_s4121_2t_cellend_L s8te2et_s4121_2t_cellend_R s8te2et_s4121_2t_cellend_R01 s8te2et_s4122_2t_cell_Bot s8te2et_s4122_2t_cell_NP2 s8te2et_s4122_2t_cell_Top s8te2et_s4122_2t_cellend_L s8te2et_s4123_2t_cell_Bot s8te2et_s4123_2t_cell_NP3 s8te2et_s4123_2t_cell_Top s8te2et_s4123_2t_cellend_L s8te2et_s4124_2t_cell_Bot s8te2et_s4124_2t_cell_NP4 s8te2et_s4124_2t_cell_Top s8te2et_s4124_2t_cellend_L s8te2et_s4124_2t_cellend_R s8te2et_s4124_2t_cellend_R01 s8te2et_s4125_2t_cell_Bot s8te2et_s4125_2t_cell_NP5 s8te2et_s4125_2t_cell_Top s8te2et_s4125_2t_cellend_L s8te2et_s4125_2t_cellend_R s8te2et_s4125_2t_cellend_R01 s8te2et_s4126_2t_cell_Bot s8te2et_s4126_2t_cell_STD s8te2et_s4126_2t_cell_Top s8te2et_s4126_2t_cellend_L s8te2et_s4126_2t_cellend_R s8te2et_s4126_2t_cellend_R01 s8te2et_s4127_2t_cell_Bot s8te2et_s4127_2t_cell_NP1 s8te2et_s4127_2t_cell_Top s8te2et_s4127_2t_cellend_L s8te2et_s4127_2t_cellend_R s8te2et_s4127_2t_cellend_R01 s8te2et_s4128_2t_cell_Bot s8te2et_s4128_2t_cell_NP2 s8te2et_s4128_2t_cell_Top s8te2et_s4128_2t_cellend_L s8te2et_s4128_2t_cellend_R s8te2et_s4128_2t_cellend_R01 s8te2et_s4129_2t_cell_Bot s8te2et_s4129_2t_cell_NP3 s8te2et_s4129_2t_cell_Top s8te2et_s4129_2t_cellend_L s8te2et_s4129_2t_cellend_R s8te2et_s4129_2t_cellend_R01 s8te2et_s4130_2t_cell_Bot s8te2et_s4130_2t_cell_NP4
validCoreID7 = INSIDE CELL COREID s8te2et_s4130_2t_cell_Top s8te2et_s4130_2t_cellend_L  s8te2et_s4130_2t_cellend_R s8te2et_s4130_2t_cellend_R01 s8te2et_s4131_2t_cell_Bot s8te2et_s4131_2t_cell_NP5  s8te2et_s4131_2t_cell_Top s8te2et_s4131_2t_cellend_L s8te2et_s4131_2t_cellend_R s8te2et_s4131_2t_cellend_R01  s8te2et_s4132_2t_cellend_L s8te2et_s4132_3t_cell_Bot s8te2et_s4132_3t_cell_STD s8te2et_s4132_3t_cell_Top  s8te2et_s4132_3t_cellend_R s8te2et_s4132_3t_cellend_R01 s8te2et_s4133_2t_cellend_L s8te2et_s4133_3t_cell_Bot  s8te2et_s4133_3t_cell_NP1 s8te2et_s4133_3t_cell_Top s8te2et_s4133_3t_cellend_R s8te2et_s4133_3t_cellend_R01  s8te2et_s4135_2t_cellend_L s8te2et_s4135_3t_cell_Bot s8te2et_s4135_3t_cell_NP3 s8te2et_s4135_3t_cell_Top  s8te2et_s4135_3t_cellend_R s8te2et_s4135_3t_cellend_R01 s8te2et_s4150_2t_cell s8te2et_s4150_2t_cell_Bot  s8te2et_s4150_2t_cell_Top s8te2et_s4150_2t_cellcrnr_L s8te2et_s4150_2t_cellcrnr_R s8te2et_s4150_2t_cellend_L  s8te2et_s4150_2t_cellend_R s8te2et_s4150_32x32_Array s8te2et_s4151_2t_2x2_a s8te2et_s4151_2t_cell_end01  s8te2et_s4151_2t_cell_end01_no_mcon s8te2et_s4151_2t_cell_end02_L s8te2et_s4151_2t_cell_end02_R  s8te2et_s4151_2t_cell_end02_R01 s8te2et_s4151_2t_cellcrnr_L s8te2et_s4151_2t_cellcrnr_R  s8te2et_s4151_PassGate_sonos_2x2 s8te2et_s4151_PassGate_sonos_2x2_no_mcon s8te2et_s4152_2t_2x2_a  s8te2et_s4152_PassGate_sonos_2x2 s8te2et_s4154_2t_cell_a s8te2et_s4154_2t_cell_end02_L s8te2et_s4154_2t_cell_end02_R  s8te2et_s4154_2t_cell_end02_R01 s8te2et_s4154_2t_cell_ncBot s8te2et_s4154_2t_cell_ncTop s8te2et_s4155_2t_cell_a  s8te2et_s4155_2t_cell_end02_L s8te2et_s4155_2t_cell_end02_R s8te2et_s4155_2t_cell_end02_R01 s8te2et_s4155_2t_cell_ncBot  s8te2et_s4155_2t_cell_ncTop s8te2et_s4156_2t_cell s8te2et_s4156_2t_cell_end s8te2et_s4156_2t_cell_end_no_mcon  s8te2et_s4156_2t_cell_ncBot s8te2et_s4156_2t_cell_ncTop s8te2et_s7300_DNW_Ring s8te2et_s7300_DNW_Ring_Big  s8te2et_s7300_DNW_Ring_s s8te2et_s7306_cap_padNFPASS_a s8te2et_sonos_Diff_MiniArray_opt3  s8te2et_SONOS_L0p13_Wmin s8te2et_SONOS_L0p15_Wmin s8te2et_SONOS_L0p17_Wmin s8te2et_SONOS_L0p18_Wmin  s8te2et_sonos_L0p22_W25 s8te2et_SONOS_L0p22_W25 s8te2et_SONOS_L0p22_Wmin s8te2et_SONOS_L0p26_Wmin  s8te2et_sonos_L25_W25 s8te2et_SONOS_L25_W25 s8te2et_sonos_L25_W25_cntm_ldntm  s8te2et_SONOS_L25_Wmin s8te2et_sonos_Lmin_W25 s8te2et_SONOS_Lmin_W25 s8te2et_sonos_Lmin_W25_cntm_ldntm  s8te2et_SONOS_Lmin_Wmin s8te2et_sonos_Lp5_W25 s8te2et_sonos_Lp5_Wp8 s8te2et_Sonos_soFet_2x2  s8te2et_sonos_W1_L1 s8te2et_sonos_W1_L1_NoDnw s8te2et_sonos_W1_L25 s8te2et_sonos_W1_L25_NoDnw s8tnvet_md5216_a  s8tnvet_s9xxx_cyp_cap_padNHLV40
validCoreID8 = INSIDE CELL COREID s8tnvet_s9xxx_cyp_cap_padNPD40 s8tnvet_s9xxx_cyp_cap_padPPU40  s8tnvet_s9xxx_cyp_cap_padS40 s8tnvet_s9xxx_pcm_iso_ppu_14_15 s8tnvet_s9xxx_pcm_iso_ppu_21_15  s8tnvet_s9xxx_pcm_iso_ppu_30_15 s8tnvet_s9xxx_pcm_multi_nhlv s8tnvet_s9xxx_pcm_multi_npass s8tnvet_s9xxx_pcm_multi_npd  s8tnvet_s9xxx_pcm_multi_ppu s8tnvet_s9xxx_sr_mcell s8tnvet_s9xxx_sr_mcell_nTfr_1x s8tnvet_s9xxx_sr_mcell_pLoad_1x  s8tnvet_s9xxx_sr_mcell_pLoad_1x_2 s8tnvet_s9xxx_sr_mcell_rcl s8tnvet_s9xxx_sr_mcell_rcl_2  s8tnvet_s9xxx_sr_mcell_TGvsr_1x_b s8tnvet_s9xxx_sr_mcell_TGvsr_1x_b_2 s8tnvet_s9xxx_sr_mcell_tie  s8tnvet_s9xxx_sr_mcell_tie_special_L s8tnvet_s9xxx_sr_mcell_tie_special_R s8tnvet_s9xxx_sr_tcell  s8cell_ee_vcctrk_cell s8cell_ee_vcctrk_cellcorn_p s8cell_ee_vcctrk_termcella s8cell_ee_vcctrk_cellcorn_n  s8cell_ee_vcctrk_colend s8cell_ee_vcctrk_termcellb s8cell_ee_colenda_d s8cell_ee_colend_lasta_d "s8sram_tech_CD_top*"  s8sram_tech_CD_lcross s8sram_tech_CD_top_pcell "s8cell_ee_tech_CD_top*" s8cell_ee_tech_CD_lcross  s8cell_ee_tech_CD_top_pcell
validCoreID10 = INSIDE CELL COREID "s8q_tech_CD_top*" s8q_tech_CD_lcross s8q_tech_CD_top_pcell
validCoreIDAW = INSIDE CELL COREID sr_mcell_b_cell7 sr_mcell_tie_Mt_cell7 sr_tcell_tie_b_cell7  sr_mcell_t_cell7 sr_mcell_tie_Rb_cell7 sr_tcell_tie_t_cell7 sr_mcell_tie_END_b_cell7 sr_mcell_tie_Rt_cell7  sr_tcell_END_b_cell7 sr_mcell_tie_END_t_cell7 sr_tcell_b_cell7 sr_tcell_END_t_cell7 sr_mcell_tie_Lb_cell7  sr_tcell_t_cell7 sr_tcell_tie_Rb_cell7 sr_mcell_tie_Lt_cell7 sr_tcell_tie_Lt_cell7 sr_tcell_tie_Rt_cell7  sr_mcell_tie_Mb_cell7 sr_tcell_tie_Lb_cell7 sr_blld_tie "s8sram_s8p_tech_CD_top*"
validCoreID_TDRrevCA = INSIDE CELL COREID s8tnvpsr_bltd_eq s8tnvpsr_bltd_tie s8tnvpsr_blld_tie  s8tnvpsr_blld s8tnvpsr_mcell_tie_END_sub_t_cell7 s8tnvpsr_mcell_tie_Mt_cell7 s8tnvpsr_mcell_tie_Lt_cell7  s8tnvpsr_mcell_tie_Rt_cell7 s8tnv64kssr_bltd_eq s8tnv64kssr_bltd_tie s8tnv64kssr_blld_tie s8tnv64kssr_blld
validCoreID_TDRrevCL = INSIDE CELL COREID s8fmlt64k_cell_cell s8fmlt64k_cell_cell_last  s8fmlt64k_cell_cellcorn_n s8fmlt64k_cell_cellcorn_p s8fmlt64k_cell_colend_lasta_d s8fmlt64k_cell_colend_lastb  s8fmlt64k_cell_colenda_d s8fmlt64k_cell_colendb s8fmlt64k_cell_strapn s8fmlt64k_cell_strapp
validCoreID_TDRrevCW = INSIDE CELL COREID s8rom_rom_wlvnb2 s8rom_romb0 s8rom_romb1
validCoreID_s8fmlt_cell = INSIDE CELL COREID s8fmlt_cell_cell s8fmlt_cell_cellcorn_p  s8fmlt_cell_colenda_d s8fmlt_cell_strapp s8fmlt_cell_cell_last s8fmlt_cell_colend_lasta_d  s8fmlt_cell_colendb s8fmlt_cell_cellcorn_n s8fmlt_cell_colend_lastb s8fmlt_cell_strapn
validCoreID_product_srom = INSIDE CELL COREID "*_srom*_rom*"
validCoreID_s8fs = INSIDE CELL COREID s8fs_cell_vcctrk_cell s8fs_cell_bseln_endb s8fs_cell_strapn  s8fs_cell_vcctrk_cellcorn_n s8fs_cell_bselp_enda_d s8fs_cell_strapn_colendb_d s8fs_cell_vcctrk_cellcorn_p  s8fs_cell_cellcorn_n s8fs_cell_strapp s8fs_cell_vcctrk_colend s8fs_cell_cellcorn_p s8fs_cell_strapp_colenda_d  s8fs_cell_vcctrk_termcella s8fs_cell_cellcorn_poly s8fs_cell_termcella s8fs_cell_vcctrk_termcellb  s8fs_cell_colenda_d s8fs_cell_termcellb s8fs_cell_cell s8fs_cell_colendb
validCoreID = (((validCoreID1 OR validCoreID2) OR (validCoreID3 OR validCoreID4)) OR  ((validCoreID5 OR validCoreID6) OR (validCoreID7 OR (validCoreID8 OR validCoreID10)))) OR  
 (validCoreID9 OR (validCoreIDAW OR (validCoreID_TDRrevCA OR (validCoreID_TDRrevCL OR  (validCoreID_TDRrevCW OR (validCoreID_s8fmlt_cell OR (validCoreID_product_srom OR validCoreID_s8fs)))))))
inValidCoreID = COREID NOT validCoreID
coreID.CON.1 {
    @ coreID.CON.1: Unapproved cells contain areaid:core marker layer
    COPY inValidCoreID
}


//
// denmos checks
//


deNFetDevice = ENCLOSE thkox (INTERACT nwell (NOT ENID dnwell))
deNFetNwell = INTERACT nwell deNFetDevice
deNFetDiff = INTERACT diffi deNFetNwell
deNFetGate = INTERACT (AND poly ENID) deNFetDiff
deNFetSource = INTERACT deNFetDiff deNFetGate
deNFetSourceOvlPoly = AND deNFetSource deNFetGate
deNFetSourceNotPoly = NOT deNFetSource deNFetGate
deNFetDrain = INSIDE diffi deNFetNwell
deNFetDrainBB = EXTENTS deNFetDrain
deNFetDrainEdges = TOUCH EDGE deNFetDrain deNFetDrainBB
deNFetSourceOvlNwell = AND deNFetSource deNFetNwell
deNFetSourceGood = INTERNAL deNFetSourceOvlNwell == 0.225 REGION
deNFetSourceToDrainRegion = NOT (AND ENID deNFetNwell) (OR deNFetSource deNFetDrainBB)
deNFetSourceToDrainSpacingGood = INTERNAL deNFetSourceToDrainRegion == 1.585 PARALLEL REGION
denmos.WID.1 {
    @ denmos.WID.1: Min width of de_nFet_gate < 1.055
    INTERNAL deNFetGate < 1.055 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
denmos.WID.2 {
    @ denmos.WID.2: Min width of de_nFet_source not overlapping poly < 0.28
    INTERNAL deNFetSourceNotPoly < 0.28 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
denmos.WID.3 {
    @ denmos.WID.3: Min width of de_nFet_source overlapping poly < 0.925
    INTERNAL deNFetSourceOvlPoly < 0.925 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
denmos.WID.4 {
    @ denmos.WID.4: Min width of the de_nFet_drain < 0.17
    LENGTH deNFetDrainEdges < 0.17
}
denmos.ENC.1 {
    @ denmos.ENC.1: Min/Max extension between de_nFET_source over nwell = 0.225
    NOT deNFetSourceOvlNwell deNFetSourceGood
}
denmos.SP.1 {
    @ denmos.SP.1: Min/Max spacing between de_nFET_source and de_nFET_drain = 1.585
    NOT deNFetSourceToDrainRegion deNFetSourceToDrainSpacingGood
}
denmos.WID.5 {
    @ denmos.WID.5: Min channel width for de_nFet_gate < 5.0
    LENGTH (deNFetGate INSIDE EDGE deNFetSource) < 5.0
}
denmos.CON.1 {
    @ denmos.CON.1: 90 degree angles are not permitted for nwell overlapping de_nFET_drain
    CONVEX EDGE deNFetNwell ANGLE1 == 90 ANGLE2 > 0
}
denmos.ENC.2 {
    @ denmos.ENC.2: Min enclosure of de_nFet_drain by nwell < 0.66
    ENCLOSURE deNFetDrain deNFetNwell < 0.66 MEASURE ALL ABUT < 90 SINGULAR REGION
}
denmos.SP.2 {
    @ denmos.SP.2: Min spacing between p+ tap and (nwell overlapping de_nFet_drain) < 0.86
    deNFetPtap = AND (OUTSIDE diffi deNFetNwell) deNFetDevice
    EXTERNAL deNFetPtap deNFetNwell < 0.86 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
denmos.SP.3 {
    @ denmos.SP.3: Min spacing between nwells overlapping de_nFET_drain < 2.4
    EXTERNAL deNFetNwell < 2.4 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE
}
denmos.ENC.3 {
    @ denmos.ENC.3: Min enclosure of de_nFet_source by nsdm < 0.13
    ENCLOSURE deNFetSource nsdm < 0.13 MEASURE ALL ABUT < 90 SINGULAR REGION
}
denmos.CON.2 {
    @ denmos.CON.2: de_nFet_source must be enclosed by nsdm
    NOT deNFetSource nsdm
}


//
// standard denmos 20v checks
//


ngate_v20a = (((((gate AND nsdm) AND v20) NOT dnwell) AND thkox) AND lvtn) NOT (OR v5 v12 ESDID LVID pnp npn)
ngate_v20_iso_rec = ((((((gate AND nsdm) AND v20) AND dnwell) AND thkox) NOT lvtn) NOT (OR ngate_v20a v5 v12 ESDID LVID pnp npn)) INTERACT pwbm
ngate_v20_iso_sub = ((HOLES pwbm) INTERACT ngate_v20_iso_rec) AND dnwell
ngate_v20_iso_sub_cont = (psdm AND diff) AND ngate_v20_iso_sub
ngate_v20_iso_gate = COPY ngate_v20_iso_rec
ngate_v20 = OR ngate_v20a ngate_v20_iso_rec
nsd_20v = (diff AND nsdm) NOT ngate_v20
nsd_20v_src_1 = EXPAND EDGE ((nsd_20v NOT ngate_v20) COINCIDENT EDGE ENID) OUTSIDE BY 0.05
nsd_20v_src = (nsd_20v NOT ngate_v20) TOUCH nsd_20v_src_1 == 3
ngate_v20_nat = ((lvtn ENCLOSE nsdm) AND ngate_v20) NOT pwbm
nsd_20v_nat_drn = ((ENID INTERACT ngate_v20_nat) NOT ngate_v20_nat) NOT nsd_20v_src
nsd_20v_drn = (((ENID INTERACT ngate_v20) NOT ngate_v20) NOT nsd_20v_src) NOT nsd_20v_nat_drn
ngate_v20_zvt = (((lvtn CUT nsdm) NOT (lvtn ENCLOSE nsdm)) AND ngate_v20) NOT (OR ngate_v20_iso_rec ngate_v20_nat)
ngate_v20_nom = ngate_v20 NOT (poly INTERACT (OR ngate_v20_nat ngate_v20_zvt ngate_v20_iso_rec))
denmos_20.WID.1 {
    @ denmos_20.WID.1: Min width of gate poly in standard 20v nmos drain extended device < 3.0
    INT (poly INTERACT ngate_v20_nom) < 3.0 ABUT<90 REGION
}
denmos_20.WID.2 {
    @ denmos_20.WID.2: Min width of source in standard 20v nmos drain extended device < 0.29
    INT (nsd_20v_src INTERACT ngate_v20_nom) < 0.29 ABUT<90 REGION
}
denmos_20.WID.3 {
    @ denmos_20.WID.3: Min width of gate of standard 20v nmos drain extended device < 1.5
    INT (((diffi AND poly) INTERACT ENID) INTERACT (dnwell INTERACT ngate_v20_nom)) < 1.5 ABUT<90 REGION
}
denmos_20.WID.4 {
    @ denmos_20.WID.4: Min width of drain of standard 20v nmos drain extended device < 0.75
    INT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_nom)) AND (diffi NOT polyi)) < 0.75 ABUT<90 REGION OPPOSITE PARALLEL
}
denmos_20.OVL.1 {
    @ denmos_20.OVL.1: Min extension of deep nwell over channel of standard 20v nmos drain extended device < 0.5
    INT (((dnwell INTERACT ngate_v20_nom) AND diffi) NOT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_nom)) AND (diffi NOT polyi))) < 0.5 ABUT<90 REGION
}
denmos_20.SP.1 {
    @ denmos_20.SP.1: Min space from drain_diff to gate or src_diff of standard 20v nmos drain extended device < 3.0
    EXT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_nom)) AND (diffi NOT polyi)) (diffi INTERACT ngate_v20_nom) < 3.0 ABUT<90 REGION
}
denmos_20.LEN.1 {
    @ denmos_20.LEN.1: Min channel width of standard 20v nmos drain extended device < 30.0
    EXPAND EDGE (LENGTH (ngate_v20_nom COINCIDENT EDGE nsd_20v_src) < 30.0) OUTSIDE BY 0.05
}
denmos_20.ANG.1 {
    @ denmos_20.ANG.1: 90 degree corners are not allowed on the drain_diff of the standard 20v nmos drain extended device
    diffi ENCLOSE (INT ((diffi AND (nsd_20v_drn AND (dnwell INTERACT ngate_v20_nom))) NOT INTERACT polyi) < 0.05 ABUT==90 REGION)
}
denmos_20.ENC.1 {
    @ denmos_20.ENC.1: Min enclosure of drain tap by dnwell in the direction of current flow of standard 20v nmos drain extended device < 3.5
    ENC (((diffi AND (nsd_20v_drn AND (dnwell INTERACT ngate_v20_nom))) NOT INTERACT polyi) COINCIDENT EDGE nwell) dnwell < 3.5 ABUT<90 REGION
}
denmos_20.ENC.2 {
    @ denmos_20.ENC.2: Min pwbm enclosure of dnwell of standard 20v nmos drain extended device < 0.5
    ENC (dnwell INTERACT ngate_v20_nom) pwbm < 0.5 ABUT<90 REGION
}
denmos_20.WID.5 {
    @ denmos_20.WID.5: Min channel length of standard 20v nmos drain extended device < 0.5
    INT ngate_v20_nom < 0.5 ABUT<90 REGION OPPOSITE PARALLEL
}
denmos_20.EXT.1 {
    @ denmos_20.EXT.1: Min poly field extension past diffusion of standard 20v nmos drain extended device < 1.0
    ENC (diffi INTERACT nsd_20v_drn) (polyi INTERACT ngate_v20_nom) < 1.0 ABUT<90 REGION
}
denmos_20.SP.2 {
    @ denmos_20.SP.2: Min space from P+ tap to source of standard 20v nmos drain extended device < 0.5
    EXT ptap (nsd_20v_src INTERACT (ENID INTERACT ngate_v20_nom)) < 0.5 ABUT<90 REGION
}
denmos_20.XOR.1 {
    @ denmos_20.XOR.1: lvtn must be coincident with pwbm of standard 20v nmos drain extended device
    XOR ((lvtn INTERACT ENID) INTERACT ngate_v20_nom) ((pwbm INTERACT ENID) INTERACT ngate_v20_nom)
}
denmos_20.ENC.3 {
    @ denmos_20.ENC.3: Min enclosure of drain by nwell of standard 20v nmos drain extended device < 0.05
    dnm_20_drn_not_coin_edge_nw = LENGTH (NOT COINCIDENT EDGE ((nsd_20v_drn INTERACT (ENID INTERACT ngate_v20_nom)) AND diffi) nwell) > 10
    ENC dnm_20_drn_not_coin_edge_nw nwell < 0.05 ABUT<90 REGION OPPOSITE PARALLEL
}


//
// native denmos 20v checks
//


denmos_20.WID.6 {
    @ denmos_20.WID.6: Min width of poly gate in native 20v nmos drain extended device < 3.0
    INT (poly INTERACT ngate_v20_nat) < 3.0 ABUT<90 REGION
}
denmos_20.WID.7 {
    @ denmos_20.WID.7: Min width of source in native 20v nmos drain extended device < 0.29
    INT (nsd_20v_src INTERACT ngate_v20_nat) < 0.29 ABUT<90 REGION
}
denmos_20.WID.8 {
    @ denmos_20.WID.8: Min width of gate of native 20v nmos drain extended device < 1.5
    INT (((diffi AND poly) INTERACT ENID) INTERACT (ENID INTERACT ngate_v20_nat)) < 1.5 ABUT<90 REGION
}
denmos_20.WID.9 {
    @ denmos_20.WID.9: Min width of drain of native 20v nmos drain extended device < 0.75
    INT ((ENID INTERACT nsd_20v_nat_drn) AND (diffi NOT INTERACT polyi)) < 0.75 ABUT<90 REGION OPPOSITE PARALLEL
}
denmos_20.OVL.2 {
    @ denmos_20.OVL.2: Min extension of deep nwell over channel of native 20v nmos drain extended device < 0.5
    INT (dnwell AND (diffi INTERACT ngate_v20_nat)) < 0.5 ABUT<90 REGION
}
denmos_20.SP.3 {
    @ denmos_20.SP.3: Min space from drain_diff to gate or src_diff of native 20v nmos drain extended device < 3.0
    EXT ((ENID INTERACT nsd_20v_nat_drn) AND (diffi NOT INTERACT polyi)) (diffi INTERACT ngate_v20_nat) < 3.0 ABUT<90 REGION
}
denmos_20.LEN.2 {
    @ denmos_20.LEN.2: Min channel width of native 20v nmos drain extended device < 30.0
    EXPAND EDGE (LENGTH (ngate_v20_nat COINCIDENT EDGE nsd_20v_src) < 30.0) OUTSIDE BY 0.05
}
denmos_20.ANG.2 {
    @ denmos_20.ANG.2: 90 degree corners are not allowed on the drain_diff of the native 20v nmos drain extended device
    diffi ENCLOSE (INT ((diffi AND (nsd_20v_nat_drn AND (ENID INTERACT ngate_v20_nat))) NOT INTERACT polyi) < 0.05 ABUT==90 REGION)
}
denmos_20.ENC.4 {
    @ denmos_20.ENC.4: Min enclosure of drain tap by dnwell in the direction of current flow of native 20v nmos drain extended device < 3.5
    ENC (((diffi AND (nsd_20v_nat_drn AND (ENID INTERACT ngate_v20_nat))) NOT INTERACT polyi) COINCIDENT EDGE nwell) dnwell < 4.0 ABUT<90 REGION
}
denmos_20.ENC.5 {
    @ denmos_20.ENC.5: Min pwbm enclosure of dnwell of native 20v nmos drain extended device < 0.5
    ENC (dnwell INTERACT (ENID INTERACT ngate_v20_nat)) pwbm < 0.5 ABUT<90 REGION
}
denmos_20.WID.10 {
    @ denmos_20.WID.10: Min channel length of native 20v nmos drain extended device < 0.5
    INT ngate_v20_nat < 0.5 ABUT<90 REGION OPPOSITE PARALLEL
}
denmos_20.EXT.2 {
    @ denmos_20.EXT.2: Min poly field extension past diffusion of native 20v nmos drain extended device < 1.5
    ENC (diffi INTERACT (diffi AND (nsd_20v_nat_drn AND (ENID INTERACT ngate_v20_nat)))) (polyi INTERACT ngate_v20_nat) < 1.5 ABUT<90 REGION
}
denmos_20.SP.4 {
    @ denmos_20.SP.4: Min space from P+ tap to source of native 20v nmos drain extended device < 0.5
    EXT ptap (nsd_20v_src INTERACT (ENID INTERACT ngate_v20_nat)) < 0.5 ABUT<90 REGION
}
denmos_20.OVL.3 {
    @ denmos_20.OVL.3: lvtn must cover entire device of native 20v nmos drain extended device
    ngate_v20_nat_ovlp3_a = lvtn INTERACT (EXPAND EDGE (lvtn OUTSIDE EDGE pwbm) OUTSIDE BY 0.05)
    all_p = polyi OR (HOLES polyi)
    ngate_v20_nat_ovlp3 = ((all_p OR diffi) INTERACT ngate_v20_nat_ovlp3_a) INTERACT ngate_v20
    ngate_v20_nat_ovlp3 NOT lvtn
}
denmos_20.ENC.6 {
    @ denmos_20.ENC.6: Min enclosure of drain by nwell of native 20v nmos drain extended device < 0.05
    nat_drn_diff = (ENID INTERACT nsd_20v_nat_drn) AND (diffi NOT INTERACT polyi)
    nat_dnm_20_drn_not_coin_edge_nw = LENGTH (NOT COINCIDENT EDGE nat_drn_diff nwell) > 10
    ENC nat_dnm_20_drn_not_coin_edge_nw nwell < 0.05 ABUT<90 REGION OPPOSITE PARALLEL
}


//
// zvt denmos 20v checks
//


denmos_20.WID.11 {
    @ denmos_20.WID.11: Min width of poly gate in zvt 20v nmos drain extended device < 7.0
    diff_inter_zvt = diffi INTERACT ngate_v20_zvt
    dnw_inter_zvt = dnwell INTERACT ngate_v20_zvt
    ply2chk = (polyi AND (OR diff_inter_zvt dnw_inter_zvt)) AND ENID
    INT ply2chk < 7.0 ABUT<90 REGION
}
denmos_20.WID.12 {
    @ denmos_20.WID.12: Min width of source in zvt 20v nmos drain extended device < 0.29
    INT (nsd_20v_src INTERACT ngate_v20_zvt) < 0.29 ABUT<90 REGION
}
denmos_20.WID.13 {
    @ denmos_20.WID.13: Min width of gate of zvt 20v nmos drain extended device < 6.0
    INT (((diffi AND poly) INTERACT ENID) INTERACT (ENID INTERACT ngate_v20_zvt)) < 6.0 ABUT<90 REGION
}
denmos_20.WID.14 {
    @ denmos_20.WID.14: Min width of drain of zvt 20v nmos drain extended device < 0.75
    INT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_zvt)) AND (diffi NOT polyi)) < 0.75 ABUT<90 REGION OPPOSITE PARALLEL
}
denmos_20.OVL.4 {
    @ denmos_20.OVL.4: Min extension of deep nwell over channel of zvt 20v nmos drain extended device < 0.5
    INT (((dnwell INTERACT ngate_v20_zvt) AND diffi) NOT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_zvt)) AND (diffi NOT polyi))) < 0.5 ABUT<90 REGION
}
denmos_20.SP.5 {
    @ denmos_20.SP.5: Min space from drain diffusion to gate/src diffusion of zvt 20v nmos drain extended device < 2.0
    EXT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_zvt)) AND (diffi NOT polyi)) (diffi INTERACT ngate_v20_zvt) < 2.0 ABUT<90 REGION
}
denmos_20.LEN.3 {
    @ denmos_20.LEN.3: Min channel width of zvt 20v nmos drain extended device < 30.0
    EXPAND EDGE (LENGTH (ngate_v20_zvt COINCIDENT EDGE nsd_20v_src) < 30.0) OUTSIDE BY 0.05
}
denmos_20.ANG.3 {
    @ denmos_20.ANG.3: 90 degree corners are not allowed on the drain_diff of the zvt 20v nmos drain extended device
    diffi ENCLOSE (INT ((diffi AND (nsd_20v_drn AND (dnwell INTERACT ngate_v20_zvt))) NOT INTERACT polyi) < 0.05 ABUT==90 REGION)
}
denmos_20.ENC.7 {
    @ denmos_20.ENC.7: Min enclosure of drain tap by dnwell in the direction of current flow of zvt 20v nmos drain extended device < 3.0
    ENC (((diffi AND (nsd_20v_drn AND (dnwell INTERACT ngate_v20_zvt))) NOT INTERACT polyi) COINCIDENT EDGE nwell) dnwell < 3.0 ABUT<90 REGION
}
denmos_20.WID.15 {
    @ denmos_20.WID.15: Min channel length of zvt 20v nmos drain extended device < 5.5
    INT ngate_v20_zvt < 5.5 ABUT<90 REGION OPPOSITE PARALLEL
}
denmos_20.EXT.3 {
    @ denmos_20.EXT.3: Min poly field extension past diffusion of zvt 20v nmos drain extended device < 1.0
    ENC (diffi INTERACT nsd_20v_drn) (polyi INTERACT ngate_v20_zvt) < 1.0 ABUT<90 REGION
}
denmos_20.SP.6 {
    @ denmos_20.SP.6: Min space from P+ tap to source of zvt 20v nmos drain extended device < 0.5
    EXT ptap (nsd_20v_src INTERACT (ENID INTERACT ngate_v20_zvt)) < 0.5 ABUT<90 REGION
}
denmos_20.XOR.2 {
    @ denmos_20.XOR.2: lvtn must be coincident with pwbm of zvt 20v nmos drain extended device
    XOR ((lvtn INTERACT ENID) INTERACT ngate_v20_zvt) ((pwbm INTERACT ENID) INTERACT ngate_v20_zvt)
}
denmos_20.ENC.8 {
    @ denmos_20.ENC.8: Min pwbm enclosure of dnwell of zvt 20v nmos drain extended device < 6.0
    dnw_edge = dnwell INSIDE EDGE (diffi INTERACT ngate_v20_zvt)
    ENC dnw_edge pwbm < 6.0 ABUT<90 REGION
}
denmos_20.ENC.9 {
    @ denmos_20.ENC.9: Min enclosure of drain by nwell of zvt 20v nmos drain extended device < 0.05
    dnm_20_drn_not_coin_edge_nw = LENGTH (NOT COINCIDENT EDGE ((nsd_20v_drn INTERACT (ENID INTERACT ngate_v20_zvt)) AND diffi) nwell) > 10
    ENC dnm_20_drn_not_coin_edge_nw nwell < 0.05 ABUT<90 REGION OPPOSITE PARALLEL
}


//
// iso denmos 20v checks
//


denmos_20.WID.16 {
    @ denmos_20.WID.16: Min width of gate poly in iso 20v nmos drain extended device < 2.5
    INT (poly INTERACT ngate_v20_iso_rec) < 2.5 ABUT<90 REGION
}
denmos_20.WID.17 {
    @ denmos_20.WID.17: Min width of source in iso 20v nmos drain extended device < 0.63
    INT (nsd_20v_src INTERACT ngate_v20_iso_rec) < 0.63 ABUT<90 REGION
}
denmos_20.WID.18 {
    @ denmos_20.WID.18: Min width of gate of iso 20v nmos drain extended device < 1.5
    INT (((diffi AND poly) INTERACT ENID) INTERACT (dnwell INTERACT ngate_v20_iso_rec)) < 1.5 ABUT<90 REGION
}
denmos_20.WID.19 {
    @ denmos_20.WID.19: Min width of drain of iso 20v nmos drain extended device < 1.5
    INT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_iso_rec)) AND (diffi NOT polyi)) < 1.5 ABUT<90 REGION OPPOSITE PARALLEL
}
denmos_20.OVL.5 {
    @ denmos_20.OVL.5: Min extension of pwbm over channel of iso 20v nmos drain extended device < 1.0
    INT (((pwbm INTERACT ngate_v20_iso_rec) AND diffi) NOT ((nsd_20v_drn AND (pwbm INTERACT ngate_v20_iso_rec)) AND (diffi NOT polyi))) < 1.0 ABUT<90 REGION
}
denmos_20.SP.7 {
    @ denmos_20.SP.7: Min space from drain_diff to gate or src_diff of iso 20v nmos drain extended device < 2.0
    EXT ((nsd_20v_drn AND (dnwell INTERACT ngate_v20_iso_rec)) AND (diffi NOT polyi)) (diffi INTERACT ngate_v20_iso_rec) < 2.0 ABUT<90 REGION
}
denmos_20.LEN.4 {
    @ denmos_20.LEN.4: Min channel width of iso 20v nmos drain extended device < 30.0
    EXPAND EDGE (LENGTH (ngate_v20_iso_rec COINCIDENT EDGE nsd_20v_src) < 30.0) OUTSIDE BY 0.05
}
denmos_20.ANG.4 {
    @ denmos_20.ANG.4: 90 degree corners are not allowed on the drain_diff of the iso 20v nmos drain extended device
    diffi ENCLOSE (INT ((diffi AND (nsd_20v_drn AND (dnwell INTERACT ngate_v20_iso_rec))) NOT INTERACT polyi) < 0.05 ABUT==90 REGION)
}
denmos_20.WID.20 {
    @ denmos_20.WID.20: Min channel length of iso 20v nmos drain extended device < 0.5
    INT ngate_v20_iso_rec < 0.5 ABUT<90 REGION OPPOSITE PARALLEL
}
denmos_20.EXT.4 {
    @ denmos_20.EXT.4: Min poly field extension past diffusion of iso 20v nmos drain extended device < 1.0
    ENC (diffi INTERACT nsd_20v_drn) (polyi INTERACT ngate_v20_iso_rec) < 1.0 ABUT<90 REGION
}
denmos_20.SP.8 {
    @ denmos_20.SP.8: Min space from P+ tap to source of iso 20v nmos drain extended device < 0.5
    n20_iso_ptap = (((diff AND psdm) NOT pwbm) AND dnwell) AND (HOLES pwbm) 
    EXT n20_iso_ptap (nsd_20v_src INTERACT (ENID INTERACT ngate_v20_iso_rec)) < 0.5 ABUT<90 REGION
}
denmos_20.XOR.3 {
    @ denmos_20.XOR.3: lvtn inside poly must be coincident with pwbm inside poly of isolated 20v nmos drain extended device
    poly_healed = (polyi INTERACT ngate_v20_iso_rec) OR (HOLES (polyi INTERACT ngate_v20_iso_rec))
    poly_healed_size = SIZE poly_healed BY -0.5
    XOR (((lvtn INTERACT ENID) INTERACT ngate_v20_iso_rec) AND poly_healed_size) (((pwbm INTERACT ENID) AND poly_healed_size) INTERACT ngate_v20_iso_rec)
}
denmos_20.ENC.10 {
    @ denmos_20.ENC.10: Min enclosure of drain by nwell of iso 20v nmos drain extended device < 0.05
    dnm_20_drn_not_coin_edge_nw = LENGTH (NOT COINCIDENT EDGE ((nsd_20v_drn INTERACT (ENID INTERACT ngate_v20_iso_rec)) AND diffi) nwell) > 10
    ENC dnm_20_drn_not_coin_edge_nw nwell < 0.05 ABUT<90 REGION OPPOSITE PARALLEL
}

//
// depmos checks
//


dePFetDevice = ENCLOSE thkox (INTERACT nwell (AND ENID dnwell))
dePFetNwell = INTERACT nwell dePFetDevice
dePFetNwellHole = HOLES dePFetNwell
dePFetDiff = INTERACT diffi dePFetNwellHole
dePFetGate = INTERACT (AND poly ENID) dePFetDiff
dePFetSource = INTERACT dePFetDiff dePFetGate
dePFetSourceAndPoly = AND dePFetSource dePFetGate
dePFetSourceNotPoly = NOT dePFetSource dePFetGate
dePFetDrain = INSIDE diffi dePFetNwellHole
dePFetDrainBB = EXTENTS dePFetDrain
dePFetDrainEdges = TOUCH EDGE dePFetDrain dePFetDrainBB
dePFetSourceOvlNwellHole = AND (AND dePFetNwellHole ENID) dePFetSource
dePFetSourceGood = INTERNAL dePFetSourceOvlNwellHole == 0.26 REGION
dePFetSourceToDrainRegion = NOT (AND ENID dePFetNwellHole) (OR dePFetSource dePFetDrainBB)
dePFetSourceToDrainSpacingGood = INTERNAL dePFetSourceToDrainRegion == 1.19 PARALLEL REGION
depmos.WID.1 {
    @ depmos.WID.1: Min width of de_pFet_gate < 1.05
    INTERNAL dePFetGate < 1.05 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
depmos.WID.2 {
    @ depmos.WID.2: Min width of de_pFet_source not overlapping poly < 0.28
    INTERNAL dePFetSourceNotpoly < 0.28 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
depmos.WID.3 {
    @ depmos.WID.3: Min width of de_pFet_source overlapping poly < 0.92
    INTERNAL dePFetSourceAndPoly < 0.92 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
depmos.WID.4 {
    @ depmos.WID.4: Min width of the de_pFet_drain < 0.17
    LENGTH dePFetDrainEdges < 0.17
}
depmos.EXT.1 {
    @ depmos.EXT.1: Min/Max extension of de_pFet_source beyond nwell = 0.26
    (NOT dePFetSourceOvlNwellHole dePFetSourceGood) NOT INTERACT (ENID INTERACT pgate_de_20v)
}
depmos.SP.2 {
    @ depmos.SP.2: Min/Max spacing between de_pFET_source and de_pFET_drain = 1.19
    (NOT dePFetSourceToDrainRegion dePFetSourceToDrainSpacingGood) NOT INTERACT (ENID INTERACT pgate_de_20v)
}
depmos.WID.5 {
    @ depmos.WID.5: Min channel width for de_pFet_gate < 5.0
    LENGTH (dePFetGate INSIDE EDGE dePFetSource) < 5.0
}
depmos.CON.1 {
    @ depmos.CON.1: 90-degree angles are not permitted for nwell hole overlapping de_pFET_drain
    (EXPAND EDGE (CONVEX EDGE dePFetNwellHole ANGLE1 == 90 ANGLE2 > 0) OUTSIDE by 0.05) NOT INTERACT (dnwell INTERACT pgate_de_20v)
}
depmos.ENC.1 {
    @ depmos.ENC.1: Min enclosure of de_pFet_drain by nwell hole < 0.86
    ENCLOSURE dePFetDrain dePFetNwellHole < 0.86 MEASURE ALL ABUT < 90 SINGULAR REGION
}
depmos.SP.3 {
    @ depmos.SP.3: Min spacing between n+ tap and (nwell hole enclosing de_pFET_drain) < 0.66
    dePFetNtap = AND (OUTSIDE diffi dePFetNwellHole) dePFetDevice
    EXTERNAL dePFetNtap dePFetNwellHole < 0.66 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
depmos.ENC.2 {
    @ depmos.ENC.2: de_pFet_source must be enclosed by psdm < 0.13
    ENCLOSURE dePFetSource psdm < 0.13 MEASURE ALL ABUT < 90 SINGULAR REGION
}
depmos.CON.2 {
    @ depmos.CON.2: de_pFet_source must be enclosed by psdm
    dePFetSource NOT psdm
}


//
// denpos 20v checks
//


pgate_de_20v = (((((poly AND v20) AND thkox) AND diff) AND psdm) NOT lvtn) AND (ENID INTERACT pwde)
psd_20v = ((diff AND psdm) NOT pgate_de_20v) INTERACT pgate_de_20v
psd_20v_src_1 = EXPAND EDGE ((psd_20v NOT pgate_de_20v) COINCIDENT EDGE ENID) OUTSIDE BY 0.05
psrc_de_20v = (psd_20v NOT pgate_de_20v) TOUCH psd_20v_src_1 == 3
pdrn_de_20v = (ENID INTERACT pgate_de_20v) NOT (OR pgate_de_20v psrc_de_20v)
depmos_20.WID.1 {
    @ depmos_20.WID.1: Min width of gate poly in 20v pmos drain extended device < 2.0
    INT (poly INTERACT pgate_de_20v) < 2.0 ABUT<90 REGION
}
depmos_20.WID.2 {
    @ depmos_20.WID.2: Min width of source of 20v pmos drain extended device < 0.29
    INT psrc_de_20v < 0.29 ABUT<90 REGION
}
depmos_20.WID.3 {
    @ depmos_20.WID.3: Min width of gate of 20v pmos drain extended device < 1.5
    INT (((diffi AND poly) INTERACT ENID) INTERACT (dnwell INTERACT pgate_de_20v)) < 1.5 ABUT<90 REGION
}
depmos_20.WID.4 {
    @ depmos_20.WID.4: Min width of drain of 20v pmos drain extended device < 0.75
    INT ((pdrn_de_20v AND (dnwell INTERACT pgate_de_20v)) AND (diffi NOT polyi)) < 0.75 ABUT<90 REGION OPPOSITE PARALLEL
}
depmos_20.WID.5 {
    @ depmos_20.WID.5: Min width of pwde AND diff AND poly < 0.5
    INT ((pwde INTERACT (polyi INTERACT pdrn_de_20v)) AND diffi) < 0.5 ABUT<90 REGION
}
depmos_20.SP.1 {
    @ depmos_20.SP.1: Min space from drain_diff to gate or src_diff of 20v pmos drain extended device < 1.5
    EXT ((pdrn_de_20v AND (dnwell INTERACT pgate_de_20v)) AND (diffi NOT polyi)) (diffi INTERACT pgate_de_20v) < 1.5 ABUT<90 REGION
}
depmos_20.LEN.1 {
    @ depmos_20.LEN.1: Min channel width of 20v pmos drain extended device < 30.0
    EXPAND EDGE (LENGTH (pgate_de_20v COINCIDENT EDGE psrc_de_20v) < 30.0) OUTSIDE BY 0.05
}
depmos_20.ANG.1 {
    @ depmos_20.ANG.1: 90 degree corners are not allowed on the drain_diff of the 20v pmos drain extended device
    diffi ENCLOSE (INT ((diffi AND pdrn_de_20v) NOT INTERACT polyi) < 0.05 ABUT==90 REGION)
}
depmos_20.ENC.1 {
    @ depmos_20.ENC.1: Min enclosure of drain tap by pwbm in the direction of current flow of 20v pmos drain extended device < 3.0
    ENC (((diffi AND (pdrn_de_20v AND (dnwell INTERACT pgate_de_20v))) NOT INTERACT polyi) COINCIDENT EDGE ENID) pwbm < 3.0 ABUT<90 REGION
}
depmos_20.ENC.2 {
    @ depmos_20.ENC.2: Min enclosure of drain tap by pwde in the direction of current flow of 20v pmos drain extended device < 2.5
    ENC (((diffi AND (pdrn_de_20v AND (dnwell INTERACT pgate_de_20v))) NOT INTERACT polyi) COINCIDENT EDGE ENID) pwde < 2.5 ABUT<90 REGION
}
depmos_20.ENC.3 {
    @ depmos_20.ENC.3: Min enclosure of pwde by pwdm of 20v pmos drain extended device < 0.5
    ENC (pwde INTERACT (ENID INTERACT pdrn_de_20v)) (pwbm INTERACT (ENID INTERACT pdrn_de_20v)) <  0.5 ABUT<90 REGION
}
depmos_20.WID.6 {
    @ depmos_20.WID.6: Min channel length of 20v pmos drain extended device < 0.5
    INT pgate_de_20v < 0.5 ABUT<90 REGION
}
depmos_20.EXT.1 {
    @ depmos_20.EXT.1: Min poly field extension past diffusion of 20v pmos drain extended device < 0.5
    ENC (diffi INTERACT pdrn_de_20v) (polyi INTERACT pgate_de_20v) < 0.5 ABUT<90 REGION
}
depmos_20.SP.2 {
    @ depmos_20.SP.2: Min space from ntap to source of 20v pmos drain extended device < 0.29
    EXT ntap psrc_de_20v < 0.29 ABUT<90 REGION
}


//
// pwres checks
//


DnwNoRing = dnwell NOT nwellring
PwresDnw = pwres AND DnwNoRing
PwresNwell = PwresDnw COINCIDENT OUTSIDE EDGE nwell
GoodPwresNwell = PwresDnw WITH EDGE PwresNwell == 2
BadPwresNwell = PwresDnw NOT GoodPwresNwell
PwresTap = TOUCH EDGE PwresDnw tap
GoodPwresTap = PwresDnw WITH EDGE PwresTap == 2
BadPwresTap = PwresDnw NOT GoodPwresTap
PwresTerm = tap WITH EDGE (tap COINCIDENT OUTSIDE EDGE GoodPwresTap)
GoodPwTap = EXTERNAL PwresTerm nwell == 0.22 ABUT < 90 SINGULAR REGION
PwresTermOutEdge = PwresTerm NOT COINCIDENT EDGE PwresDnw
BadPwTap = PwresTermOutEdge NOT COINCIDENT EDGE GoodPwTap
BadTapW = SIZE (SIZE PwresTerm BY -(0.53/2)) BY (0.53/2)
GoodTapLicon = INTERACT PwresTerm (PwresTerm AND Licon) == 12
GoodTapMcon = INTERACT PwresTerm (PwresTerm AND Mcon) == 12
BadTapLicon = PwresTerm NOT GoodTapLicon
BadTapMcon_tmp = PwresTerm NOT GoodTapMcon
BadTapMcon = BadTapMcon_tmp AND met1
nwellEnclosePwres = TOUCH nwell PwresDnw
tapRing = (DONUT tap) AND nwellEnclosePwres
tapRingLicon = licon AND tapRing
tapRingLi1 = INTERACT li tapRingLicon
tapRingMcon = mcon AND tapRingLi1
tapRingMet1 = INTERACT met1 tapRingMcon
tapRingMetStrap = INTERACT tapRing tapRingMet1
nonTapwell = nwellEnclosePwres NOT (INTERACT nwell tapRingMetStrap)
pwres.CON.1 {
    @ pwres.CON.1: pwres must be inside dnwell and inside an nwell hole
    pwres NOT DnwNoRing
}
pwres.CON.2 {
    @ pwres.CON.2: pwres enclosed by dnwell should be rectangular
    NOT RECTANGLE PwresDnw ORTHOGONAL ONLY
}
pwres.WID.1 {
    @ pwres.WID.1: Min/Max width of pwres = 2.65
    pwresWidth1 = INTERNAL PwresDnw < 2.65 REGION
    pwresWidth2 = INTERNAL PwresDnw == 2.65 REGION
    pwresWidth1 OR (PwresDnw NOT pwresWidth2)
}
pwres.LEN.1 {
    @ pwres.LEN.1: Min length of pwres < 26.50
    INTERNAL PwresDnw < 26.50 PROJECTING < 26.50 REGION
}
pwres.LEN.2 {
    @ pwres.LEN.2: Max length of pwres = 265.00
    PwresDnw WITH EDGE (LENGTH PwresDnw > 265.00)
}
pwres.SP.1 {
    @ pwres.SP.1: Min/Max spacing of a tap inside the pwell resistor to nwell = 0.22
    COPY BadPwTap
}
pwres.WID.2 {
    @ pwres.WID.2: Min width of pwres terminal < 0.53
    INTERNAL PwresTerm < 0.53 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
pwres.CON.3 {
    @ pwres.CON.3: pwres cannot be wider than width of pwell resistor P+ tap
    COPY BadTapW
}
pwres.CON.4 {
    @ pwres.CON.4: P+ tap of pwell resister terminal must enclose 12 licons
    BadTapLicon OR BadTapMcon
}
pwres.CON.5a {
    @ pwres.CON.5a: diff or poly is not allowed in the pwell resistor
    (OR diff poly) AND PwresDnw
}
pwres.CON.6 {
    @ pwres.CON.6: N+ tap inside nwell ring of pwres must have metal straps
    COPY nonTapwell
}
pwres.CON.7 {
    @ pwres.CON.7: pwell:res must abut pwell resistor terminals on opposite and parallel edges
    COPY BadPwresTap
}
pwres.CON.8 {
    @ pwres.CON.8: pwell res must abut nwell edges on opposite sides
    COPY BadPwresNwell
}


//
// hnwell checks
//


nw_12_20v = ((nwell INTERACT v12) OR (nwell INTERACT v20)) NOT exempt_tech_CD


//
// hpoly checks
//


gateHV_PERI = gate_PERI AND v5
gateEdgeHV_PERI = poly COINCIDENT EDGE gateHV_PERI
gateEdgeHV_PERI_err = INTERNAL gateEdgeHV_PERI < 0.5 OPPOSITE PARALLEL ONLY REGION
hpoly.WID.1 {
    @ hpoly.WID.1: Min width of poly over diff inside v5 in periphery < 0.5
    INTERNAL gateEdgeHV_PERI_err < 0.5 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hpoly.CON.1 {
    @ hpoly.CON.1: gate must not straddle v5
    CUT GATE v5
}


//
// extd checks
//


deFetPoly = INTERACT poly (poly AND ENID)
deFetGate = deFetPoly AND ENID
difftapInsideEnid = difftap INSIDE ENID
difftapEndidEdg = difftapInsideEnid COINCIDENT INSIDE EDGE ENID
difftapEndidEdgExp = EXPAND EDGE difftapEndidEdg OUTSIDE BY 0.005
goodHvdifftap = TOUCH difftapInsideEnid difftapEndidEdgExp >= 2 <= 3
badHvdifftap = difftapInsideEnid NOT goodHvdifftap
polyGap = deFetGate NOT difftapInsideEnid
extd.CON.1 {
    @ extd.CON.1: diff must not straddle areaid:extendedDrain
    CUT difftap ENID
}
extd.CON.2 {
    @ extd.CON.2: diff must have two or three coincident edges with areaid:extendedDrain if enclosed by areaid:extendedDrain
    COPY badHvdifftap
}
extd.CON.3 {
    @ extd.CON.3: poly must extend beyond overlapping diffusion inside areaid:extendedDrain
    deFetPoly OUTSIDE polyGap
}


//
// npc checks
//


ringLCON1 = DONUT licon
rectLCON1 = licon NOT ringLCON1
LCON1AndRpm = rectLCON1 AND (rpm OR urpm)
slotted_licon = (WITH WIDTH LCON1AndRpm == 0.19) WITH EDGE (LENGTH LCON1AndRpm == 2.0)
poly_with_slotlicon = polyi ENCLOSE slotted_licon
npc_no_hrpoly = NOT INTERACT npc poly_with_slotlicon
poly_edges_horiz = ANGLE poly_with_slotlicon == 0
poly_edges_vert = ANGLE poly_with_slotlicon == 90
npc.WID.1 {
    @ npc.WID.1: Min width of npc < 0.270
    INTERNAL npc < 0.270 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
npc.SP.1 {
    @ npc.SP.1: Min spacing/notch of npc < 0.270
    EXTERNAL npc < 0.270 ABUT < 90 SINGULAR REGION
}
npc.SP.2 {
    @ npc.SP.2: Min spacing of npc & gate < 0.090
    EXTERNAL npc GATE < 0.090 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
npc.CON.1 {
    @ npc.CON.1: npc must not overlap gate
    npc AND GATE
}


//
// diff dummy (formally fom/dummy)
//


diff_fill.WID.1 {
    @ diff_fill.WID.1: Min width of diff fill < 0.50
    INTERNAL diff_fill < 0.50 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff_fill.WID.2 {
    @ diff_fill.WID.2: Max width of diff fill > 25.00
    LENGTH diff_fill > 25.00
}
diff_fill.SP.1 {
    @ diff_fill.SP.1: Min spacing/notch of diff fill < 0.40
    EXTERNAL diff_fill < 0.40 ABUT < 90 SINGULAR REGION
}
diff_fill.SP.2 {
    @ diff_fill.SP.2: Min spacing of diff fill to areaid:seal < 1.00
    EXTERNAL diff_fill SEALID < 1.00 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff_fill.CON.1 {
    @ diff_fill.CON.1: diff fill must not overlap areaid:seal
    diff_fill AND SEALID
}
diff_fill.SP.4 {
    @ diff_fill.SP.4: Min spacing of diff fill to nsdm < 0.13
    EXTERNAL diff_fill nsdm < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff_fill.CON.3 {
    @ diff_fill.CON.3: diff fill must not overlap nsdm
    diff_fill AND nsdm
}
diff_fill.SP.5 {
    @ diff_fill.SP.5: Min spacing of diff fill to psdm < 0.13
    EXTERNAL diff_fill psdm < 0.13 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff_fill.CON.4 {
    @ diff_fill.CON.4: diff fill must not overlap psdm
    diff_fill AND psdm
}
diff_fill.ENC.1 {
    @ diff_fill.ENC.1: Min enclosure of diff fill by nwell < 0.18
    ENCLOSURE (diff_fill AND nwell) nwell < 0.18 MEASURE ALL ABUT < 90 SINGULAR
}
diff_fill.SP.6 {
    @ diff_fill.SP.6: Min spacing of diff fill to nwell < 0.34
    EXTERNAL diff_fill nwell < 0.34 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
five_volt_nw = (nwell INTERACT v5) NOT INTERACT (OR v12 v20)
diff_fill.ENC.2 {
    @ diff_fill.ENC.2: Min enclosure of diff fill by 5 volt nwell < 0.43
    ENCLOSURE (diff_fill AND five_volt_nw) five_volt_nw < 0.43 MEASURE ALL ABUT < 90 SINGULAR
}
diff_fill.SP.7 {
    @ diff_fill.SP.7: Min spacing of diff fill to HVnwell < 0.33
    EXTERNAL diff_fill five_volt_nw < 0.33 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff_fill.ENC.3 {
    @ diff_fill.ENC.3: Min enclosure of diff fill by areaid:frame < 0.50
    ENCLOSURE (diff_fill AND FRAMEID) FRAMEID < 0.50 MEASURE ALL ABUT < 90 SINGULAR
}
diff_fill.SP.8 {
    @ diff_fill.SP.8: Min spacing of diff fill to areaid:dieCut < 0.50
    EXTERNAL diff_fill dieCut < 0.50 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}


//
// diff_v5 checks
//


diffHV = (diffi AND v5) AND thkox
diffHV_CORE = diffHV AND COREID
diffHV_PERI = diffHV NOT COREID
diffHVpRes_PERI = diffHV_PERI AND (diffRes AND nwell)
diffHVpResNormSize = INTERACT diffHVpRes_PERI (EXPAND EDGE (LENGTH (diffHVpRes_PERI INSIDE EDGE diffHV) >= 0.29) INSIDE BY 0.005)
diffHVnopRes_PERI = (diffHV_PERI NOT diffHVpRes_PERI) OR diffHVpResNormSize
ndiffHV = (NDIFF AND v5) AND thkox
ndiffHV_PERI = ndiffHV NOT COREID
tapHV = (tap AND v5) and thkox
tapHV_PERI = tapHV NOT COREID
ptapHV = (PTAP AND v5) AND thkox
ptapHV_PERI = ptapHV NOT COREID
diffTapHV = (diffTap AND v5) INTERACT thkox
diffTapHV_PERI_nonV20 = diffTapHV NOT (COREID OR v20)
diffTapNoHv = diffTap NOT (v5 AND thkox)
diffTapNoHv_PERI = diffTapNoHv NOT COREID
NTAP_nonESD_nonv20 = NTAP_PERI NOT (ESD_nwell_tap OR v20)
nTapHV_nonESD_v20 = NTAP_nonESD_nonv20 AND ((v5 AND thkox) OR HVNID)
ptapHV_PERI_noAbut = NOT TOUCH ptapHV_PERI ndiffHV_PERI
PTAP_noPwellRes = PTAP NOT (TOUCH PTAP pwres)
ndiffHV_nonESD = (ndiffHV NOT ESDID) NOT ENID
ndiff_nonESD = (NDIFF NOT ESD_nwell_tap) NOT ENID
pdiffHV_nonESD = (((PDIFF NOT ESD_nwell_tap) AND (v5 OR HVNID)) AND thkox) NOT (ENID OR v20)
diffHV_noV20 = diffHV NOT v20
tapHV_noV20 = tapHV NOT v20
ndiff_nonESDv20 = ndiff_nonESD NOT v20
ndiffHV_nonESDv20 = ndiffHV_nonESD NOT v20
PTAP_noPwellRes_noV20 = PTAP_noPwellRes NOT v20
diff_5v.WID.1 {
    @ diff_5v.WID.1: Min width of diff (not tap) in v5 and periphery (exempt for pdiff resistor inside v5) < 0.29
    INTERNAL ((diffHVnopRes_PERI OR (diffres INTERACT diffHVnopRes_PERI)) NOT tap) < 0.29 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff_5v.WID.2 {
    @ diff_5v.WID.2: Min width of pdiff resistor inside v5 in periphery < 0.15
    INTERNAL (NOT (AND (AND (AND nwell diffi) diffRes) v5) COREID) < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff_5v.SP.1 {
    @ diff_5v.SP.1: Min spacing/notch of diff inside v5 and periphery < 0.3
    EXTERNAL (diffHV_PERI NOT tap) < 0.3 ABUT < 90 SINGULAR REGION
}
diff_5v.SP.2 {
    @ diff_5v.SP.2: Min space of n+diff to non-abutting p+tap inside v5 < 0.37
    EXTERNAL ndiffHV_PERI ptapHV_PERI_noAbut < 0.37 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
butting_edge_marker = EXPAND EDGE (diffHV_noV20 COINCIDENT EDGE tapHV) OUTSIDE BY 0.05
diff_5v.WID.3 {
    @ diff_5v.WID.3: Min width tap butting diff on one or two sides inside v5 (rule exempted inside v20) < 0.7
    INT (PTAP TOUCH butting_edge_marker == 3) < 0.7 ABUT < 90 REGION
}
diff_5v.WID.4 {
    @ diff_5v.WID.4: Min width of abutting tap abutting and between diff inside v5 < 0.7
    INT (PTAP TOUCH butting_edge_marker == 2) < 0.7 ABUT < 90 REGION
}
diff_5v.ENC.1 {
    @ diff_5v.ENC.1: nwell inside v5 min enclosure of (pdiff outside areaid:esd) < 0.33
    ENCLOSURE (pdiffHV_nonESD AND five_volt_nw) five_volt_nw < 0.33 MEASURE ALL ABUT < 90 SINGULAR
}
diff_5v.SP.3 {
    @ diff_5v.SP.3: Min spacing of ndiff (outside areaid:ESD) to nwell inside v5 < 0.43
    EXTERNAL ndiff_nonESDv20 five_volt_nw < 0.43 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff_5v.ENC.2 {
    @ diff_5v.ENC.2: nwell inside v5 min enclosure of (ntap outside areaid:esd) < 0.33
    ENCLOSURE (nTapHV_nonESD_v20 AND five_volt_nw) five_volt_nw < 0.33 MEASURE ALL ABUT < 90 SINGULAR REGION
}
diff_5v.SP.4 {
    @ diff_5v.SP.4: Min spacing of P+ tap to nwell inside v5 (Exempt for p+tap butting pwell resistor and inside v20) < 0.43
    EXTERNAL PTAP_noPwellRes_noV20 five_volt_nw < 0.43 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff_5v.CON.1 {
    @ diff_5v.CON.1: diff in periphery must not straddle v5
    CUT diffTap_PERI v5
}
diff_5v.CON.1a {
    @ diff_5v.CON.1a: diff in periphery must not straddle thkox
    CUT diffTap_PERI thkox
}
diff_5v.ENC.3 {
    @ diff_5v.ENC.3: Min enclosure of diff inside v5 by thkox (exempt inside v20) < 0.18
    ENCLOSURE (diffTapHV_PERI_nonV20 AND thkox) thkox < 0.18 MEASURE ALL ABUT < 90 SINGULAR REGION
}
diff_5v.SP.5 {
    @ diff_5v.SP.5: Min spacing between diff outside thkox to thkox < 0.18
    EXTERNAL diffTapNoHv_PERI thkox < 0.18 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
diff_5v.SP.6 {
    @ diff_5v.SP.6: Min spacing of ndiff inside v5 (outside areaid:ESD and outside v20)) to nwell < 0.43
    EXTERNAL ndiffHV_nonESDv20 nwell < 0.43 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}


//
// hv checks
//


hv_diff_n = nsd NET AREA RATIO (nsd AND (v12 OR v20)) > 0
hv_diff_p = psd NET AREA RATIO (psd AND (v12 OR v20)) > 0
hv_diff = OR hv_diff_n hv_diff_p
hv_diff_not_tap = hv_diff NOT TOUCH tap
CONNECT li hv_diff_not_tap by licon
lv_diff_not_tap = (diffi NOT tap) NOT (OR v12 v20)
hv_diff_not_butting_tap = hv_diff_not_tap NOT TOUCH tap
lv_diff_not_butting_tap = lv_diff_not_tap NOT TOUCH tap
shv_ntap = ntap AND (OR v12 v20)
shv_nw = NET AREA RATIO nwell shv_ntap > 0
hv.SP.1 {
    @ hv.SP.1: Minimum 12v or 20v source/drain spacing to diff for edges of 12v or 20v source/drain diff not butting tap < 0.3
    EXT hv_diff_not_butting_tap diffi < 0.3 ABUT<90 REGION
}
nsd_net_hv_diff_1a = NET AREA RATIO nsd hv_diff_not_tap > 0
psd_net_hv_diff_1b = NET AREA RATIO psd hv_diff_not_tap > 0
net_conn_hv_diff = OR nsd_net_hv_diff_1a psd_net_hv_diff_1b
diff_res_term_touch_net_conn_hv_diff = net_conn_hv_diff TOUCH (OR rndiff rpdiff)
diff_res_body_touch_diff_term_hv_net = (rpdiff OR rndiff) TOUCH diff_res_term_touch_net_conn_hv_diff
hv.SP.2 {
    @ hv.SP.2: Minimum spacing of n+/p+ diff resistors connected to 12v or 20v source/drain to diff < 0.3
    EXTERNAL diff_res_body_touch_diff_term_hv_net diffi < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
dio_body = diffi AND DIODEID
dio_body_conn_hv_diff = dio_body AND net_conn_hv_diff
diff_dio_conn_hv_diff = dio_body_conn_hv_diff AND diffi
hv.SP.3 {
    @ hv.SP.3: Minimum spacing of n+/p+ diff diodes connected to 12v or 20v source/drain to diff < 0.3
    EXTERNAL diff_dio_conn_hv_diff diffi < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nw_net_hv_diff = NET AREA RATIO nwell hv_diff_not_tap > 0
hv.SP.4 {
    @ hv.SP.4: Minimum spacing of nwell connected to 12v or 20v source/drain to n+ diff < 0.43
    EXTERNAL nw_net_hv_diff (diffi AND nsdm)  < 0.43 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hv.SP.5 {
    @ hv.SP.5: Minimum N+ 12v or 20v source/drain spacing to nwell < 0.55
    EXTERNAL hv_diff_not_tap nwell < 0.55 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hv.SP.6 {
    @ hv.SP.6: Minimum spacing of n+ diff resistors connected to 12v or 20v source/drain to nwell < 0.55
    EXTERNAL (diff_res_body_touch_diff_term_hv_net AND nsdm) nwell < 0.55 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hv.SP.7 {
    @ hv.SP.7: Minimum spacing of n+ diff diodes connected to 12v or 20v source/drain to nwell < 0.55
    EXTERNAL (diff_dio_conn_hv_diff AND nsdm) nwell < 0.55 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hv_gate = gate AND ((v12 OR v20) AND thkox)
sd = OR nsd psd
hv_mark = v12 OR v20
hv_sd = sd AND hv_mark
hv_poly = polyi TOUCH (sd AND (hv_mark AND thkox))
poly_touch_nsd_tied = hv_gate NET INTERACT nsd == 2
poly_touch_psd_tied = hv_gate NET INTERACT psd == 2
poly_touch_sd_tied = OR poly_touch_nsd_tied poly_touch_psd_tied
hv_poly_cross_gt_1_diff = hv_poly INTERACT sd > 2
hv.CON.1 {
    @ hv.CON.1: 12v or 20v poly must overlap only one diff unless source and drains are tied
    hv_poly_cross_gt_1_diff NOT INTERACT poly_touch_sd_tied
}
poly_x_nw_exempt = polyii INSIDE CELL "pmos_de_v12*" "pmos_de_v20*" "nmos_de_12" "nmos_de_v20"
hv.CON.2 {
    @ hv.CON.2: 12v or 20v poly cannot cross nwell boundary except for pmos drain extended devices
    (EXPAND EDGE (nwell INSIDE EDGE hv_poly) OUTSIDE BY 0.05) NOT poly_x_nw_exempt
}
hv.SP.8 {
    @ hv.SP.8: Min spacing of 12v or 20v poly to 1.8v, 3.3v or 5v diff (exempt for diff butting v12 or v20 poly) < 0.3
    diff_butt_poly = diffi TOUCH hv_poly
    EXT hv_poly (diffi NOT (OR v12 v20 diff_butt_poly)) < 0.3 ABUT<90 REGION
}
hv.SP.9 {
    @ hv.SP.9: Min spacing of 12v or 20v poly to nwell (exempt poly stradding nwell in a depmos) < 0.55
    EXTERNAL (hv_poly NOT poly_x_nw_exempt) nwell < 0.55 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hv.ENC.1 {
    @ hv.ENC.1: Min enclosure of 12v or 20v poly (including high voltage poly resistor) by nwell (exempt for poly straddling nwell in a depmos) < 0.3
    ENC ((hv_poly AND nwell) NOT poly_x_nw_exempt) nwell < 0.3 REGION MEASURE ALL ABUT < 90 SINGULAR
}
diff_exempt = diffii INSIDE CELL "pmos_de_v12*" "pmos_de_v20*" "nmos_de_v12*" "nmos_de_v20*"
hv.ENC.2 {
    @ hv.ENC.2: Min extension of poly beyond 12v or 20v gate (exempt poly extending beyond diff along the S/D direction in a denmos/depmos) < 0.16
    ENC ((diffi NOT diff_exempt) INTERACT hv_sd) polyi < 0.16 ABUT<90 REGION SINGULAR
}


//
// tunm checks
//


tunm.WID.1 {
    @ tunm.WID.1: Min width of tunm < 0.41
    INTERNAL tunm < 0.41 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
tunm.SP.1 {
    @ tunm.SP.1: Min spacing/notch of tunm to tunm < 0.5
    EXTERNAL tunm < 0.5 ABUT < 90 SINGULAR REGION
}
tunm.ENC.1 {
    @ tunm.ENC.1: Extension of tunm beyond (poly and diff) < 0.095
    ENC GATE tunm < 0.095 MEASURE COINCIDENT ABUT < 90 SINGULAR REGION
}
tunm.SP.2 {
    @ tunm.SP.2: Min spacing of tunm to (poly and diff) outside tunm < 0.095
    EXTERNAL (GATE NOT tunm) tunm < 0.095 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
tunm.CON.1 {
    @ tunm.CON.1: gate (poly and diff) may not straddle tunm
    CUT GATE tunm
}
tunm.CON.2 {
    @ tunm.CON.2: tunm outside deep n-well is not allowed
    (tunm NOT dnwell) NOT exempt_tech_CD
}
tunm.AR.1 {
    @ tunm.AR.1: Min tunm area < 0.672
    AREA tunm < 0.672
}
tunm.CON.3 {
    @ tunm.CON.3: tunm must be enclosed by areaid:core
    tunm NOT COREID
}


//
// hvntm checks
//


hvntm_peri = hvntm NOT COREID
ndiffInV5 = (NDIFF AND v5) AND thkox
ndiffInV5Peri = ndiffInV5 NOT (ndiffInV5 AND COREID)
ndiffOutsideV5 = NDIFF OUTSIDE v5
PDIFF_notENID = PDIFF NOT ENID
PTAPnoButtDiff = PTAP OUTSIDE EDGE NDIFF
diffpTapButtEdge_sz = EXPAND EDGE (NDIFF COINCIDENT OUTSIDE EDGE PTAP) OUTSIDE BY 0.005
ESD_nwell_tap_inside_v5 = ESD_nwell_tap INSIDE (v5 INTERACT thkox)
hvntm.CON.2 {
    @ hvntm.CON.2: hvntm must be drawn inside v5 and thkox
    hvntm NOT INSIDE (v5 AND thkox)
}
hvntm.WID.1 {
    @ hvntm.WID.1: Min width of hvntm not in areaid:core < 0.7
    INTERNAL hvntm_peri < 0.7 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hvntm.SP.1 {
    @ hvntm.SP.1: Min spacing/notch of hvntm not in areaid:core < 0.7
    EXTERNAL hvntm_peri < 0.7 ABUT < 90 SINGULAR REGION
}
hvntm.ENC.1 {
    @ hvntm.ENC.1: Min enclosure of (n+_diff inside v5 and thkox) but not overlapping areaid:core by hvntm < 0.185
    ENCLOSURE (ndiffInV5Peri AND hvntm_peri) hvntm_peri < 0.185 MEASURE ALL ABUT < 90 SINGULAR REGION
}
hvntm.SP.2 {
    @ hvntm.SP.2: Min spacing between n+_diff outside v5 and thkox and hvntm < 0.185
    EXTERNAL hvntm_peri ndiffOutsideV5 < 0.185 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hvntm.CON.3 {
    @ hvntm.CON.3: No overlap between n+_diff outside v5 and thkox and hvntm
    hvntm_peri AND ndiffOutsideV5
    hvntm_peri NOT thkox
}
hvntm.SP.3 {
    @ hvntm.SP.3: Min spacing between p+_diff and hvntm < 0.185
    EXTERNAL hvntm_peri PDIFF_notENID < 0.185 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
hvntm.CON.4 {
    @ hvntm.CON.4: No overlap between p+_diff and hvntm
    hvntm_peri AND PDIFF_notENID
}
hvntm.SP.4 {
    @ hvntm.SP.4: Min spacing between p+_tap and hvntm (except along the diff-butting edge) < 0.185
    EXTERNAL hvntm_peri PTAPnoButtDiff < 0.185 ABUT < 90 REGION EXCLUDE FALSE
}
hvntm.CON.5 {
    @ hvntm.CON.5: No overlap between p+_tap and hvntm (except along the diff-butting edge)
    hvntm_peri AND PTAP
}
hvntm.CON.6 {
    @ hvntm.CON.6: No overlap between p+_tap and hvntm along the diff-butting edge
    hvntm_peri AND diffpTapButtEdge_sz
}
hvntm.CON.7 {
    @ hvntm.CON.7: hvntm not in areaid:CORE must enclose ESD nwell n+ tap inside v5 and thkox
    (esd_nwell_tap_inside_v5 AND thkox) NOT hvntm_peri
}
hvntm.CON.8 {
    @ hvntm.CON.8: A 5v ESD nwell n+ tap must be enclosed by hvntm when not in areaid:core
    ESD_nwell_tap_inside_v5 NOT hvntm_peri
}
hvntm.CON.9 {
    @ hvntm.CON.9: hvntm must not overlap areaid:core
    hvntm AND COREID
}


//
// metal blockage checks
//


met1_block.SP.1 {
    @ met1_block.SP.1: Min spacing of met1 to met1_block < 0.14
    EXTERNAL met1 met1_block < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met1_block.CON.1 {
    @ met1_block.CON.1: met1 must not overlap met1_block
    met1 AND met1_block
}
met1_block.SP.2 {
    @ met1_block.SP.2: Min spacing of met1_block to met1_routing < 0.145
    EXTERNAL met1_block (SIZE met1pin BY 0.07 INSIDE OF met1 STEP 0.095) < 0.145 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met2_block.SP.1 {
    @ met2_block.SP.1: Min spacing of met2 to met2_block < 0.14
    EXTERNAL met2 met2_block < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met2_block.CON.1 {
    @ met2_block.CON.1: met2 must not overlap met2_block
    met2 AND met2_block
}
met2_block.SP.2 {
    @ met2_block.SP.2: Min spacing of met2_block to met2_routing < 0.145
    EXTERNAL met2_block (SIZE met2pin BY 0.07 INSIDE OF met2 STEP 0.095) < 0.145 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met3_block.SP.1 {
    @ met3_block.SP.1: Min spacing of met3 to met3_block < 0.3
    EXTERNAL met3 met3_block < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met3_block.CON.1 {
    @ met3_block.CON.1: met3 must not overlap met3_block
    met3 AND met3_block
}
met3_block.SP.2 {
    @ met3_block.SP.2: Min spacing of met3_block to met3_routing < 0.305
    EXTERNAL met3_block (SIZE met3pin BY 0.15 INSIDE OF met3 STEP 0.21) < 0.305 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met4_block.SP.1 {
    @ met4_block.SP.1: Min spacing of met4 to met4_block < 0.3
    EXTERNAL met4 met4_block < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met4_block.CON.1 {
    @ met4_block.CON.1: met4 must not overlap met4_block
    met4 AND met4_block
}
met4_block.SP.2 {
    @ met4_block.SP.2: Min spacing of met4_block to met4_routing < 0.305
    EXTERNAL met4_block (SIZE met4pin BY 0.15 INSIDE OF met4 STEP 0.21) < 0.305 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met5_block.SP.1 {
    @ met5_block.SP.1: Min spacing of met5 to met5_block < 1.6
    EXTERNAL met5 met5_block < 1.6 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met5_block.CON.1 {
    @ met5_block.CON.1: met5 must not overlap met5_block
    met5 AND met5_block
}
met5_block.SP.2 {
    @ met5_block.SP.2: Min spacing of met5_block to met5_routing < 1.605
    EXTERNAL met5_block (SIZE met5pin BY 0.8 INSIDE OF met5 STEP 1.13) < 1.605 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
li_block.SP.1 {
    @ li_block.SP.1: Min spacing of li to li_block < 0.17
    EXTERNAL li li_block < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
li_block.CON.1 {
    @ li_block.CON.1: li must not overlap li_block
    li AND li_block
}
li_block.SP.2 {
    @ li_block.SP.2: Min spacing of li_block to li_routing < 0.17
    EXTERNAL li_block (SIZE lipin BY 0.085 INSIDE OF li STEP 0.12) < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
SEALnoHoles_ORIGIN = (DONUT SEALID) OR (HOLES SEALID)
pr_chip_check_REQUIRED = prBndry AND SEALnoHoles_ORIGIN
pr_ip_check_REQUIRED = prBndry NOT SEALnoHoles_ORIGIN
prBndry.CON.1 {
    @ prBndry.CON.1: prBoundary.boundary not allowed in IP layout
    COPY pr_ip_check_REQUIRED
}
// 
// PAD rules
// 
sealid_hole = HOLES SEALID
dieEdgeHoriz = ANGLE SEALID == 0
dieEdgePerp = ANGLE SEALID == 90
dieEdgeHorizSz = EXPAND EDGE dieEdgeHoriz OUTSIDE BY 0.005
dieEdgePerpSz = EXPAND EDGE dieEdgePerp OUTSIDE BY 0.005
dieEdgeH = dieEdgeHorizSz COINCIDENT EDGE sealid_hole
dieEdgeP = dieEdgePerpSz COINCIDENT EDGE sealid_hole
hoizXaxis = COPY 4006
perpXaxis = COPY 4007
padNoSEAL = pad NOT SEALID
dieEdgStepH41 = EXPAND EDGE dieEdgeH INSIDE by 41
dieEdgStepHpad41 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH41)) NOT perpXaxis
allHorizX41 = hoizXaxis OR dieEdgStepHpad41
dieEdgStepP41 = EXPAND EDGE dieEdgeP INSIDE by 41
dieEdgStepPpad41 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP41)) NOT dieEdgStepHpad41
allPerpX41 = perpXaxis OR dieEdgStepPpad41
newSetPad41 = padNoSEAL NOT (dieEdgStepHpad41 OR dieEdgStepPpad41)
cornerPads41 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH41)) AND (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP41))
horzAndCornPad = dieEdgStepH41 AND cornerPads41
vertAndCornPad = dieEdgStepP41 AND cornerPads41
padEdgeHorzErr =  EXTERNAL padCenter horzAndCornPad < 60.0 ABUT < 90 PARALLEL OPPOSITE
padEdgeVertErr =  EXTERNAL padCenter vertAndCornPad < 60.0 ABUT < 90 PARALLEL OPPOSITE
pad_length_ang_0 = ANGLE (cornerPads41 AND pad_length) == 0
pad_length_ang_90 = ANGLE (cornerPads41 AND pad_length) == 90
dfmVertXedge = cornerPads41 ENCLOSE (EXPAND EDGE pad_length_ang_90 OUTSIDE by 0.2)
dfmHorzXedge = cornerPads41 ENCLOSE (EXPAND EDGE pad_length_ang_0 OUTSIDE by 0.2)
dieEdgStepH82 = EXPAND EDGE dieEdgeH INSIDE by 82
dieEdgStepHpad82 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH82)) NOT allPerpX41
allHorizX82 = allHorizX41 OR dieEdgStepHpad82
dieEdgStepP82 = EXPAND EDGE dieEdgeP INSIDE by 82
dieEdgStepPpad82 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP82)) NOT dieEdgStepHpad82
allPerpX82 = allPerpX41 OR dieEdgStepPpad82
newSetPad82 = padNoSEAL NOT (dieEdgStepHpad82 OR dieEdgStepPpad82)
dieEdgStepH123 = EXPAND EDGE dieEdgeH INSIDE by 123
dieEdgStepHpad123 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH123)) NOT allPerpX82
allHorizX123 = allHorizX82 OR dieEdgStepHpad123
dieEdgStepP123 = EXPAND EDGE dieEdgeP INSIDE by 123
dieEdgStepPpad123 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP123)) NOT dieEdgStepHpad123
allPerpX123 = allPerpX82 OR dieEdgStepPpad123
newSetPad123 = padNoSEAL NOT (dieEdgStepHpad123 OR dieEdgStepPpad123)
dieEdgStepH164 = EXPAND EDGE dieEdgeH INSIDE by 164
dieEdgStepHpad164 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH164)) NOT allPerpX123
allHorizX164 = allHorizX123 OR dieEdgStepHpad164
dieEdgStepP164 = EXPAND EDGE dieEdgeP INSIDE by 164
dieEdgStepPpad164 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP164)) NOT dieEdgStepHpad164
allPerpX164 = allPerpX123 OR dieEdgStepPpad164
newSetPad164 = padNoSEAL NOT (dieEdgStepHpad164 OR dieEdgStepPpad164)
dieEdgStepH205 = EXPAND EDGE dieEdgeH INSIDE by 205
dieEdgStepHpad205 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH205)) NOT allPerpX164
allHorizX205 = allHorizX164 OR dieEdgStepHpad205
dieEdgStepP205 = EXPAND EDGE dieEdgeP INSIDE by 205
dieEdgStepPpad205 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP205)) NOT dieEdgStepHpad205
allPerpX205 = allPerpX164 OR dieEdgStepPpad205
newSetPad205 = padNoSEAL NOT (dieEdgStepHpad205 OR dieEdgStepPpad205)
dieEdgStepH246 = EXPAND EDGE dieEdgeH INSIDE by 246
dieEdgStepHpad246 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH246)) NOT allPerpX205
allHorizX246 = allHorizX205 OR dieEdgStepHpad246
dieEdgStepP246 = EXPAND EDGE dieEdgeP INSIDE by 246
dieEdgStepPpad246 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP246)) NOT dieEdgStepHpad246
allPerpX246 = allPerpX205 OR dieEdgStepPpad246
newSetPad246 = padNoSEAL NOT (dieEdgStepHpad246 OR dieEdgStepPpad246)
dieEdgStepH287 = EXPAND EDGE dieEdgeH INSIDE by 287
dieEdgStepHpad287 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH287)) NOT allPerpX246
allHorizX287 = allHorizX246 OR dieEdgStepHpad287
dieEdgStepP287 = EXPAND EDGE dieEdgeP INSIDE by 287
dieEdgStepPpad287 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP287)) NOT dieEdgStepHpad287
allPerpX287 = allPerpX246 OR dieEdgStepPpad287
newSetPad287 = padNoSEAL NOT (dieEdgStepHpad287 OR dieEdgStepPpad287)
dieEdgStepH328 = EXPAND EDGE dieEdgeH INSIDE by 328
dieEdgStepHpad328 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH328)) NOT allPerpX287
allHorizX328 = allHorizX287 OR dieEdgStepHpad328
dieEdgStepP328 = EXPAND EDGE dieEdgeP INSIDE by 328
dieEdgStepPpad328 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP328)) NOT dieEdgStepHpad328
allPerpX328 = allPerpX287 OR dieEdgStepPpad328
newSetPad328 = padNoSEAL NOT (dieEdgStepHpad328 OR dieEdgStepPpad328)
dieEdgStepH369 = EXPAND EDGE dieEdgeH INSIDE by 369
dieEdgStepHpad369 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH369)) NOT allPerpX328
allHorizX369 = allHorizX328 OR dieEdgStepHpad369
dieEdgStepP369 = EXPAND EDGE dieEdgeP INSIDE by 369
dieEdgStepPpad369 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP369)) NOT dieEdgStepHpad369
allPerpX369 = allPerpX328 OR dieEdgStepPpad369
newSetPad369 = padNoSEAL NOT (dieEdgStepHpad369 OR dieEdgStepPpad369)
dieEdgStepH410 = EXPAND EDGE dieEdgeH INSIDE by 410
dieEdgStepHpad410 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH410)) NOT allPerpX369
allHorizX410 = allHorizX369 OR dieEdgStepHpad410
dieEdgStepP410 = EXPAND EDGE dieEdgeP INSIDE by 410
dieEdgStepPpad410 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP410)) NOT dieEdgStepHpad410
allPerpX410 = allPerpX369 OR dieEdgStepPpad410
newSetPad410 = padNoSEAL NOT (dieEdgStepHpad410 OR dieEdgStepPpad410)
dieEdgStepH451 = EXPAND EDGE dieEdgeH INSIDE by 451
dieEdgStepHpad451 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH451)) NOT allPerpX410
allHorizX451 = allHorizX410 OR dieEdgStepHpad451
dieEdgStepP451 = EXPAND EDGE dieEdgeP INSIDE by 451
dieEdgStepPpad451 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP451)) NOT dieEdgStepHpad451
allPerpX451 = allPerpX410 OR dieEdgStepPpad451
newSetPad451 = padNoSEAL NOT (dieEdgStepHpad451 OR dieEdgStepPpad451)
dieEdgStepH492 = EXPAND EDGE dieEdgeH INSIDE by 492
dieEdgStepHpad492 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH492)) NOT allPerpX451
allHorizX492 = allHorizX451 OR dieEdgStepHpad492
dieEdgStepP492 = EXPAND EDGE dieEdgeP INSIDE by 492
dieEdgStepPpad492 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP492)) NOT dieEdgStepHpad492
allPerpX492 = allPerpX451 OR dieEdgStepPpad492
newSetPad492 = padNoSEAL NOT (dieEdgStepHpad492 OR dieEdgStepPpad492)
dieEdgStepH533 = EXPAND EDGE dieEdgeH INSIDE by 533
dieEdgStepHpad533 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepH533)) NOT allPerpX492
allHorizX533 = allHorizX492 OR dieEdgStepHpad533
dieEdgStepP533 = EXPAND EDGE dieEdgeP INSIDE by 533
dieEdgStepPpad533 = (INTERACT padNoSEAL (padNoSEAL AND dieEdgStepP533)) NOT dieEdgStepHpad533
allPerpX533 = allPerpX492 OR dieEdgStepPpad533
newSetPad533 = padNoSEAL NOT (dieEdgStepHpad533 OR dieEdgStepPpad533)
padXorg = COPY allHorizX533
padYorg = COPY allPerpX533
padCornerXtmp = COPY dfmHorzXedge
padCornerYtmp = COPY dfmVertXedge
padCornXpitchPadX = EXPAND EDGE (ANGLE padCornerXtmp == 90) OUTSIDE BY 7
padCornXpitchPadY = EXPAND EDGE (ANGLE padCornerXtmp == 0) OUTSIDE BY 7
padCornXtouchPitchInY = TOUCH padCornXpitchPadY pad == 2
padCornXtouchPitchInX = TOUCH padCornXpitchPadX pad == 2
padCornerSwapxtoY = NOT TOUCH (TOUCH padCornerXtmp padCornXtouchPitchInY) padCornXtouchPitchInX
padCornerX = (padCornerXtmp OR padCornerSwapYtoX) NOT padCornerSwapXtoY
padCornYpitchPadY = EXPAND EDGE (ANGLE padCornerYtmp == 90) OUTSIDE BY 7
padCornYpitchPadX = EXPAND EDGE (ANGLE padCornerYtmp == 0) OUTSIDE BY 7
padCornYtouchPitchInY = TOUCH padCornYpitchPadY pad == 2
padCornYtouchPitchInX = TOUCH padCornYpitchPadX pad == 2
padCornerSwapYtoX = NOT TOUCH (TOUCH padCornerYtmp padCornYtouchPitchInY) padCornYtouchPitchInX
padCornerY = (padCornerYtmp OR padCornerSwapXtoY) NOT padCornerSwapYtoX
padX = (padXorg OR padCornerX) NOT padCornerY
padY = (padYorg OR padCornerY) NOT padCornerX
minSpacepadYedges = EXPAND EDGE (ANGLE padY == 0) INSIDE BY 0.005
minSpacepadYyEdge = EXPAND EDGE (ANGLE padY == 90) INSIDE BY 0.005
minSpacepadXedges = EXPAND EDGE (ANGLE padX == 90) INSIDE BY 0.005
minSpacepadXyEdge = EXPAND EDGE (ANGLE padX == 0) INSIDE BY 0.005
laser_targetCells = EXTENT CELL "lazX_*" "lazY_*" ORIGINAL
BONDPAD = pad OUTSIDE (OR SEALID fuse FRAMEID laser_targetCells)
padInInd = pad AND inductor
bondpadPcell_0 = (EXTENT CELL "padPL*" ORIGINAL) OR bondpadCuPillar
bondpadPcell_1 = EXTENT CELL "pad_bond*" ORIGINAL
bondpadPcell_2 = EXTENT CELL "pad_microprobe*" ORIGINAL
bondpadPcell_3 = EXTENT CELL "pad_probe*" ORIGINAL
bondpadPcell = OR bondpadPcell_0 bondpadPcell_1 bondpadPcell_2 bondpadPcell_3
plasticPackPad = WITH TEXT bondpadPcell "plastic" textdraw
hermeticPackPad = WITH TEXT bondpadPcell "hermetic" textdraw
PadPLhp = WITH TEXT BONDPAD "HP" textdraw
PadPLfp = WITH TEXT BONDPAD "FP" textdraw
PadPLstg = WITH TEXT BONDPAD "STG" textdraw
PadPLwlbi = WITH TEXT BONDPAD "WLBI" textdraw
bondpadCuPillar = EXTENT CELL "s8fpafeg1_io_amkor_pad*" "fpg1_amkor_39x39_pad*" ORIGINAL
notValidbondPad = BONDPAD NOT (padInInd OR (bondpadPcell OR bondpadCuPillar))
bondpadPcellNoText = bondpadPcell NOT plasticPackPad
anyPadPlastic = pad AND plasticPackPad
pad.CON.1 {
    @ pad.CON.1: pad pcells should be used for bondpad
    COPY notValidbondPad
}
pad.CON.3 {
    @ pad.CON.3: Hermetic package pads are not supported in this flow
    COPY hermeticPackPad
}
bondpadNormal = BONDPAD AND bondpadPcell
bondpadNormalPlastic = BONDPAD AND plasticPackPad
bondpadHP = BONDPAD AND PadPLhp
bondpadFP = BONDPAD AND PadPLfp
bondpadSTG = BONDPAD AND PadPLstg
bondpadWLBI = BONDPAD AND PadPLwlbi
pad_in_bond = pad AND ((met5 ENCLOSE pad) INTERACT met4)
probe_pad = WITH TEXT pad "e-test"
uprobe_pad = WITH TEXT pad "u-test"
pad.ENC.1 {
    @ pad.ENC.1: Min. enclosure of normal bond pad by met5 < 0.27
    ENC (pad_in_bond NOT (OR probe_pad uprobe_pad)) met5 < 2.7 MEASURE ALL ABUT < 90 SINGULAR REGION
}
met4_ring = DONUT (met4 INTERACT pad_in_bond)
pad.SP.1 {
    @ pad.SP.1: Metal4 ring in bond pad must be coincident and outside pad layer of pad cell
    met4_ring INTERACT (met4_ring AND pad_in_bond)
}
bondpadEdges = BONDPAD COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)
bondpadEdgesSz = EXPAND EDGE bondpadEdges INSIDE BY 30
bondpadEdgesSide = EXPAND EDGE (LENGTH (bondpadEdgesSz INSIDE EDGE BONDPAD) <= 60.0 > (60.0 / 2.0)) INSIDE BY 0.005
SmallBondPad = BONDPAD INTERACT bondpadEdgesSide
LargeBondPad = BONDPAD NOT SmallBondPad
padGroupingY = (BONDPAD INTERACT (BONDPAD AND (padCenter AND padCenterDieY))) OR padCenterDieY
smallGroupingY = (INTERACT padGroupingY (padGroupingY AND (padCenter AND SmallBondPad))) AND BONDPAD
largeGroupingY = (padGroupingY NOT smallGroupingY) AND BONDPAD
padGroupingX = (INTERACT BONDPAD (BONDPAD AND (padCenter AND padCenterDieX))) OR padCenterDieX
smallGroupingX = (INTERACT padGroupingX (padGroupingX AND (padCenter AND SmallBondPad))) AND BONDPAD
largeGroupingX = (padGroupingX NOT smallGroupingX) AND BONDPAD
met4OutsidePad = met4 OUTSIDE bondPadPcell
met5OutsidePad = met5 OUTSIDE bondPadPcell
pad.SP.2 {
    @ pad.SP.2: Min. spacing of pad opening inside a group of small bondpads in the Y direction to met4/5 outside the bond pad < 5.0
    @ if at least one pad opening across the chip in x-direction is <= 60um
    EXT smallGroupingY met5OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT smallGroupingY met4OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
pad.SP.3 {
    @ pad.SP.3: Min. spacing of pad opening of inside a group of large bondpads in the Y direction met4/5 outside the bond pad < 10.0
    @ if at least one pad opening across the chip in x-direction is > 60um
    EXT largeGroupingY met5OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT largeGroupingY met4OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
pad.SP.4 {
    @ pad.SP.4: Min. spacing of pad opening of small bondpads in the X direction to met4/5 outside the bond pad < 5.0
    @ if at least one pad opening across the chip in x-direction is <= 60um
    EXT smallGroupingX met5OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT smallGroupingX met4OutsidePad < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
pad.SP.5 {
    @ pad.SP.5: Min. spacing of pad opening inside a group of large bondpads in the X direction to met4/5 outside the bond pad < 10.0
    @ if at least one pad opening across the chip in x-direction is > 60um
    EXT largeGroupingX met5OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT largeGroupingX met4OutsidePad < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
bondpadNormalprobe = WITH TEXT bondpadNormalPlastic "probe-only" textdraw
bondpadNormalNoprobe = bondpadNormalPlastic NOT (cuPillarPadText OR bondpadNormalprobe)
pad.OVL.1 {
    @ pad.OVL.1: Normal pad opening (not probe) must not overlap met4
    bondpadNormalNoprobe AND met4
}
bp_outl1 = EXPAND EDGE (pad NOT INTERACT (OR uprobe_pad probe_pad)) OUTSIDE BY 0.05
bp_outl = (pad NOT INTERACT (uprobe_pad OR probe_pad)) COINCIDENT OUTSIDE EDGE bp_outl1
bondpad_45_edges = ANGLE bp_outl == 45
bondpad_90_edges = NOT ANGLE bp_outl == 45
bondpad_corner = INT pad_squared_off < 10 ABUT==90 REGION
pad.CON.4 {
    @ pad.CON.4: Bondpad should not have 90 degree corner
    SIZE (INT bondpadNormalPlastic < 0.005 ABUT == 90 INTERSECTING REGION) BY 0.5 INSIDE OF pad
}
pad.CON.5 {
    @ pad.CON.5: Bondpad missing 45 degree corner
    bondpad_corner NOT INTERACT (EXPAND EDGE bondpad_45_edges OUTSIDE BY 0.05)
}
pad.CON.6 {
    @ pad.CON.6: Bondpad does not have 4 chamferred 45 degree corners
    (pad NOT (OR uprobe_pad probe_pad)) NOT TOUCH (EXPAND EDGE bondpad_45_edges OUTSIDE BY 0.05) == 4
}
pad.CON.7 {
    @ pad.CON.7: Bondpad should have only 4 orthogonal edges
    (pad NOT (OR uprobe_pad probe_pad)) NOT TOUCH (EXPAND EDGE bondpad_90_edges OUTSIDE BY 0.05) == 4
}
pad.LEN.1 {
    @ pad.LEN.1: Min length of 45 degree bevel on Bond pad < 7.0
    LENGTH bondpad_45_edges < 7
}
pad.LEN.2 {
    @ pad.LEN.2: Max length of 45 degree bevel on Bond pad > 8.8
    LENGTH bondpad_45_edges > 8.8
}
solid_seal = (HOLES SEALID) OR (DONUT SEALID)
solid_seal_shrink = SIZE solid_seal BY -500.0
maxSpcPadSeal = bondpadNormalPlastic WITH EDGE (bondpadNormalPlastic COINCIDENT INSIDE EDGE solid_seal_shrink)
lessMaxSpcPadSeal = CUT bondpadNormalPlastic solid_seal_shrink
cuPillarPadText = INTERACT pad (WITH TEXT pad "CU-PILLAR-PAD" textdraw)
aupDummyPadText = bondpadCuPillar INTERACT (WITH TEXT pad "AUP-DUMMY-OK" textdraw)
cadXmpt = COPY cuPillarPadText
err_pad_15 = (bondpadNormalPlastic NOT (maxSpcPadSeal OR (lessMaxSpcPadSeal OR cadXmpt))) AND solid_seal_shrink
pad.ENC.2 {
    @ pad.ENC.2: Min. enclosure of any plastic pad by solid_seal < 16.99
    q0anyPadPlasticand = anyPadPlastic AND solid_seal
    ENCLOSURE q0anyPadPlasticand solid_seal < 16.99 MEASURE ALL ABUT < 90 SINGULAR REGION
}
pad.SP.10 {
    @ pad.SP.10: Max spacing between bondpad opening and edge of scribe line (outer end of seal ring) > 500.0
    COPY err_pad_15
}
padMetal = pad AND (bondPadPcell AND met5)
met1Shield = COPY 4008
met1UndPadMet = met1i INTERACT (met1i AND padMetal)
met1UndPadMetOnly = met1UndPadMet AND (BONDPAD NOT aupDummyPadText)
met1UndPadMetMinW = INTERNAL met1UndPadMetOnly < 0.14 PARALLEL OPPOSITE REGION
pad.SP.11 {
    @ pad.SP.11: Min. spacing/notch of met1 under pad metal < 1.5
    EXTERNAL met1UndPadMetOnly < 1.5 ABUT < 90 SINGULAR REGION OPPOSITE
}
pad.WID.1 {
    @ pad.WID.1: Min width of met1 under pad metal < 0.14
    COPY met1UndPadMetMinW
}
met2UndPadMet = INTERACT met2 (met2 AND padMetal)
met2UndPadMetOnly = met2UndPadMet AND (BONDPAD NOT aupDummyPadText)
met2UndPadMetMinW = INTERNAL met2UndPadMetOnly < 0.14 PARALLEL OPPOSITE REGION
pad.SP.12 {
    @ pad.SP.12: Min. spacing/notch of met2 under pad metal < 1.5
    EXTERNAL met2UndPadMetOnly < 1.5 ABUT < 90 SINGULAR REGION OPPOSITE
}
pad.WID.2 {
    @ pad.WID.2: Min width of met2 under pad metal < 0.14
    COPY met2UndPadMetMinW
}
met3UndPadMet = INTERACT met3 (met3 AND padMetal)
met3UndPadMetOnly = met3UndPadMet AND (BONDPAD NOT aupDummyPadText)
met3UndPadMetMinW = INTERNAL met3UndPadMetOnly < 0.3 PARALLEL OPPOSITE REGION
pad.SP.13 {
    @ pad.SP.13: Min. spacing/notch of met3 under pad metal < 1.5
    EXTERNAL met3UndPadMetOnly < 1.5 ABUT < 90 SINGULAR REGION OPPOSITE
}
pad.WID.3 {
    @ pad.WID.3: Min width of met3 under pad metal < 0.3
    COPY met3UndPadMetMinW
}
pad.WID.4 {
    @ pad.WID.4: Max width of met1 under pad metal > 25.0
    WITH WIDTH ((met1 AND padMetal) NOT met1Shield) > 25.0
}
pad.WID.5 {
    @ pad.WID.5: Max width of met2 under pad metal > 25.0
    WITH WIDTH ((met2 AND padMetal) NOT met1Shield) > 25.0
}
pad.SP.6 {
    @ pad.SP.6: Min pad spacing < 1.27
    EXT pad < 1.27 ABUT<90 REGION
}
hpb_exemptions = EXTENT CELL "hpb_esdTriggerULB_b*"  ORIGINAL
qspi_exemptions = EXTENT CELL "s8tnvsio18_io_top" "s8tnviso18_io_top_hv" "quadspinvsram_top*" ORIGINAL
pad_19_exemptions = OR hpb_exemptions qspi_exemptions
pad.WID.6 {
    @ pad.WID.6: Max width of met3 under pad metal > 6.0
    (WITH WIDTH (met3 AND padMetal) > 6.0) NOT pad_19_exemptions
}
padFPedgX = bondpadFP COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)
padFPedgXsz = EXPAND EDGE padFPedgX INSIDE BY 30
badFPwEdg = LENGTH (padFPedgXsz NOT COINCIDENT EDGE padFPedgX) > 30.0 < 60.0
badFPwEdgSz = EXPAND EDGE badFPwEdg INSIDE BY 0.005
badFPwidth = INTERACT (bondpadFP NOT bondpadCuPillar) ((bondpadFP NOT bondpadCuPillar) AND (INTERACT (EXPAND EDGE padFPedgX INSIDE BY 0.005) ((EXPAND EDGE padFPedgX INSIDE BY 0.005) AND badFPwEdgSz) == 2))
padFPedgY = bondpadFP COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge)
padFPedgYsz = EXPAND EDGE padFPedgY INSIDE BY 30
badFPlEdg = LENGTH (padFPedgYsz NOT COINCIDENT EDGE padFPedgY) > 30.0 < 60.0
badFPlEdgSz = EXPAND EDGE badFPlEdg INSIDE BY 0.005
badFPlength = INTERACT (bondpadFP NOT bondpadCuPillar) ((bondpadFP NOT bondpadCuPillar) AND (INTERACT (EXPAND EDGE padFPedgY INSIDE BY 0.005) ((EXPAND EDGE padFPedgY INSIDE BY 0.005) AND badFPlEdgSz) == 2))
padSTGedgX = bondpadSTG COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)
padSTGedgXsz = EXPAND EDGE padSTGedgX INSIDE BY 30
badSTGwEdg = LENGTH (padSTGedgXsz NOT COINCIDENT EDGE padSTGedgX) > 30.0 < 60.0
badSTGwEdgSz = EXPAND EDGE badSTGwEdg INSIDE BY 0.005
badSTGwidth = INTERACT bondpadSTG (bondpadSTG AND (INTERACT (EXPAND EDGE padSTGedgX INSIDE BY 0.005) ((EXPAND EDGE padSTGedgX INSIDE BY 0.005) AND badSTGwEdgSz) == 2))
padSTGedgY = bondpadSTG COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge)
padSTGedgYsz = EXPAND EDGE padSTGedgY INSIDE BY 30
badSTGlEdg = LENGTH (padSTGedgYsz NOT COINCIDENT EDGE padSTGedgY) > 30.0 < 60.0
badSTGlEdgSz = EXPAND EDGE badSTGlEdg INSIDE BY 0.005
badSTGlength = INTERACT bondpadSTG (bondpadSTG AND (INTERACT (EXPAND EDGE padSTGedgY INSIDE BY 0.005) ((EXPAND EDGE padSTGedgY INSIDE BY 0.005) AND badSTGlEdgSz) == 2))
psoc4cuCells = EXTENT CELL "psoc4*_top*"
bondpadHPcu = bondpadHP AND psoc4cuCells
bondpadHPorg = bondpadHP NOT bondpadHPcu
padHPedgX = bondpadHPorg COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)
padHPedgXsz = EXPAND EDGE padHPedgX INSIDE BY 30
badHPwEdg = LENGTH (padHPedgXsz NOT COINCIDENT EDGE padHPedgX) > 30.0 < 60.0
badHPwEdgSz = EXPAND EDGE badHPwEdg INSIDE BY 0.005
badHPwidth = INTERACT bondpadHP (bondpadHP AND (INTERACT (EXPAND EDGE padHPedgX INSIDE BY 0.005) ((EXPAND EDGE padHPedgX INSIDE BY 0.005) AND badHPwEdgSz) == 2))
padHPedgY = bondpadHPorg COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge)
padHPedgYsz = EXPAND EDGE padHPedgY INSIDE BY 30
badHPlEdg = LENGTH (padHPedgYsz NOT COINCIDENT EDGE padHPedgY) > 30.0 < 60.0
badHPlEdgSz = EXPAND EDGE badHPlEdg INSIDE BY 0.005
badHPlength = INTERACT bondpadHP (bondpadHP AND (INTERACT (EXPAND EDGE padHPedgY INSIDE BY 0.005) ((EXPAND EDGE padHPedgY INSIDE BY 0.005) AND badHPlEdgSz) == 2))
padHPcuedgX = bondpadHPcu COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)
padHPcuedgXsz = EXPAND EDGE padHPcuedgX INSIDE BY 29
badHPcuwEdg = LENGTH (padHPcuedgXsz NOT COINCIDENT EDGE padHPcuedgX) > 29.0 < 58.0
badHPcuwEdgSz = EXPAND EDGE badHPcuwEdg INSIDE BY 0.005
badHPcuwidth = INTERACT (bondpadHPcu NOT bondpadHPcuSolo) ((bondpadHPcu NOT bondpadHPcuSolo) AND (INTERACT (EXPAND EDGE padHPcuedgX INSIDE BY 0.005) ((EXPAND EDGE padHPcuedgX INSIDE BY 0.005) AND badHPcuwEdgSz) == 2))
padHPcuedgY = bondpadHPcu COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge)
padHPcuedgYsz = EXPAND EDGE padHPcuedgY INSIDE BY 30
badHPculEdg = LENGTH (padHPcuedgYsz NOT COINCIDENT EDGE padHPcuedgY) > 30.0 < 60.0
badHPculEdgSz = EXPAND EDGE badHPculEdg INSIDE BY 0.005
badHPculength = INTERACT (bondpadHPcu NOT bondpadHPcuSolo) ((bondpadHPcu NOT bondpadHPcuSolo) AND (INTERACT (EXPAND EDGE padHPcuedgY INSIDE BY 0.005) ((EXPAND EDGE padHPcuedgY INSIDE BY 0.005) AND badHPculEdgSz) == 2))
bondpadHPcuSz = SIZE bondPadHPcu BY (50.0 / 2)
bondpadHPcuSolo = bondpadHPcu AND (INTERACT bondpadHPcuSz bondpadHPcu == 1)
bondpadHPcuSoloSz = SIZE bondPadHPcuSolo BY 10 UNDEROVER
badHPcuSoloWL = NOT RECTANGLE bondpadHPcuSoloSz >= 58.0 BY >= 60.0
padWLBIedgX = bondpadWLBI COINCIDENT EDGE (minSpacepadXedges OR minSpacepadYedges)
padWLBIedgXsz = EXPAND EDGE padWLBIedgX INSIDE BY 25
badWLBIwEdg = LENGTH (padWLBIedgXsz NOT COINCIDENT EDGE padWLBIedgX) > 25.0 < 50.0
badWLBIwEdgSz = EXPAND EDGE badWLBIwEdg INSIDE BY 0.005
badWLBIwidth = INTERACT bondpadWLBI (bondpadWLBI AND (INTERACT (EXPAND EDGE padWLBIedgX INSIDE BY 0.005) ((EXPAND EDGE padWLBIedgX INSIDE BY 0.005) AND badWLBIwEdgSz) == 2))
padWLBIedgY = bondpadWLBI COINCIDENT EDGE (minSpacepadXyEdge OR minSpacepadYyedge)
padWLBIedgYsz = EXPAND EDGE padWLBIedgY INSIDE BY 30
badWLBIlEdg = LENGTH (padWLBIedgYsz NOT COINCIDENT EDGE padWLBIedgY) > 30.0 < 60.0
badWLBIlEdgSz = EXPAND EDGE badWLBIlEdg INSIDE BY 0.005
badWLBIlength = INTERACT bondpadWLBI (bondpadWLBI AND (INTERACT (EXPAND EDGE padWLBIedgY INSIDE BY 0.005) ((EXPAND EDGE padWLBIedgY INSIDE BY 0.005) AND badWLBIlEdgSz) == 2))
pad_squared_off = SIZE (BONDPAD NOT INTERACT (OR uprobe_pad probe_pad)) BY 10 UNDEROVER
pad_ctr_cross = INT pad_squared_off < 150 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 1
pad_ctr_box = pad_ctr_cross NOT (INT pad_ctr_cross < 1.005 ABUT<90 OPPOSITE PARALLEL REGION)
padCenter = EXTENTS pad CENTERS 0.2
pad_cross_not_ctr = pad_ctr_cross NOT pad_ctr_box
pad_cross_len = (pad_cross_not_ctr INTERACT pad_length) OR pad_ctr_box
pad_cross_wid = (pad_cross_not_ctr NOT INTERACT pad_length) OR pad_ctr_box
pad_cross_len_x = ANGLE (LENGTH pad_cross_len > 2) == 0
pad_cross_len_y = ANGLE (LENGTH pad_cross_len > 2) == 90
pad_cross_wid_x = ANGLE (LENGTH pad_cross_wid > 2) == 0
pad_cross_wid_y = ANGLE (LENGTH pad_cross_wid > 2) == 90
pad.WID.7 {
    @ pad.WID.7: Min width of fine pitch pad in x direction < 60.0
    LENGTH (pad_cross_len_x INSIDE EDGE bondpadFP) < 60
}
pad.LEN.3 {
    @ pad.LEN.3: Min length of fine pitch pad in y direction < 60.0
    LENGTH (pad_cross_len_y INSIDE EDGE bondpadFP) < 60
}
pad.WID.8 {
    @ pad.WID.8: Min width of staggered pad in x direction < 60.0
    LENGTH (pad_cross_len_x INSIDE EDGE bondpadSTG) < 60
}
pad.LEN.4 {
    @ pad.LEN.4: Min length of staggered pad in y direction < 60.0
    LENGTH (pad_cross_len_y INSIDE EDGE bondpadSTG) < 60
}
pad.WID.9 {
    @ pad.WID.9: Min width of high parallel pad in x direction < 60.0
    LENGTH (pad_cross_len_x INSIDE EDGE bondpadHP) < 60
}
pad.LEN.5 {
    @ pad.LEN.5: Min length of high parallel pad in y direction < 60.0
    LENGTH (pad_cross_len_y INSIDE EDGE bondpadHP) < 60
}
isolated_pad_1 = EXT pad < 50 ABUT<90 REGION
isolated_pad = pad NOT INTERACT isolated_pad_1
non_iso_pad = pad NOT isolated_pad
isolated_pad_x = EXPAND EDGE (pad_cross_len_x INSIDE EDGE non_iso_pad) OUTSIDE BY 0.05
isolated_pad_y = EXPAND EDGE (pad_cross_len_y INSIDE EDGE non_iso_pad) OUTSIDE BY 0.05
pad.WID.12 {
    @ pad.WID.12: Min width of wafer level burn-in pad in x direction < 50.0
    LENGTH (pad_cross_len_x INSIDE EDGE bondpadWLBI) < 50
}
pad.LEN.7 {
    @ pad.LEN.7: Min length of wafer level burn-in pad in y direction < 60.0
    LENGTH (pad_cross_len_y INSIDE EDGE bondpadWLBI) < 60
}
pad.SP.14 {
    @ pad.SP.14: Min space of fine pitch pad in x direction to fine pitch, high pitch, staggered or wafer level burn_in in pad < 8.0
    (EXT bondpadFP (OR bondpadFP bondpadHP bondpadSTG bondpadWLBI) < 8 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_wid_x BY 0.1)
}
pad.SP.15 {
    @ pad.SP.15: Min space of high pitch pad in x direction to high pitch, staggered and wafer level burn in pad < 15.0
    (EXT bondpadHP (OR bondpadHP bondpadSTG bondpadWLBI) < 15 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_wid_x BY 0.1)
}
pad.SP.17 {
    @ pad.SP.17: Min space of wafer level burn in pad in x direction to staggered or wafer level burn in pad < 50.0
    (EXT bondpadWLBI (OR bondpadSTG bondpadWLBI) < 50 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_wid_x BY 0.1)
}
pad.SP.18 {
    @ pad.SP.18: Min space of staggered pad in x direction < 30.0
    (EXT bondpadSTG < 30 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_wid_x BY 0.1)
}
pad.LEN.9 {
    @ pad.LEN.9: Max width/length of bond pad > 150.0
    LENGTH pad_squared_off > 150
}
padCenterAllX = padCenter AND (BONDPAD AND padX)
padCenterAllY = padCenter AND (BONDPAD AND padY)
padCenterAllxSz = EXPAND EDGE (ANGLE padCenterAllX == 90) OUTSIDE BY 200000
padCenterAllySz = EXPAND EDGE (ANGLE padCenterAllY == 0) OUTSIDE BY 200000
padCenterDieX = (padCenterAllX OR padCenterAllxSz) AND solid_seal
padCenterDieY = (padCenterAllY OR padCenterAllySz) AND solid_seal
padCenterinDieXw = INTERNAL padCenterDieX == 0.2 ABUT < 90 OPPOSITE PARALLEL REGION
padCenterinDieYw = INTERNAL padCenterDieY == 0.2 ABUT < 90 OPPOSITE PARALLEL REGION
padCenterinDieXsp = EXTERNAL padCenterDieX < 9.0 ABUT < 90 SINGULAR REGION
padCenterinDieYsp = EXTERNAL padCenterDieY < 9.0 ABUT < 90 SINGULAR REGION
padCenterinDieXwBad = padCenterDieX NOT padCenterinDieXw
padCenterinDieYwBad = padCenterDieY NOT padCenterinDieYw
padCenterinDieXspBad = padCenterinDieXsp OR (INTERACT BONDPAD (BONDPAD AND (INTERACT padCenterAllX padCenterinDieXsp)))
padCenterinDieYspBad = padCenterinDieYsp OR (INTERACT BONDPAD (BONDPAD AND (INTERACT padCenterAllY padCenterinDieYsp)))
padCenterSTGxySz = EXPAND EDGE (ANGLE (bondpadSTG AND padCenterAllX) == 0) OUTSIDE BY 5000
padCenterSTGyySz = EXPAND EDGE (ANGLE (bondpadSTG AND padCenterAllY) == 90) OUTSIDE BY 5000
padCenterSTGinDieXy = (padCenterAllX OR padCenterSTGxySz) AND solid_seal
padCenterSTGinDieYy = (padCenterAllY OR padCenterSTGyySz) AND solid_seal
pad.SP.19 {
    @ pad.SP.19: Min. pitch spacing of staggered pad (adjacent row) in X-direction < 40.0
    (EXT (pad_ctr_box AND bondPadSTG) < 39 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_len_x BY 0.1)
}
pad.SP.20 {
    @ pad.SP.20: Min. pitch spacing of staggered pad (adjacent row) in Y-direction < 40.0
    (EXT (pad_ctr_box AND bondPadSTG) < 39 ABUT<90 REGION OPPOSITE PARALLEL) INTERACT (EXPAND EDGE pad_cross_len_y BY 0.1)
}
padCenterSTGxxSz = EXPAND EDGE (ANGLE (bondpadSTG AND padCenterAllX) == 90) OUTSIDE BY 5000
padCenterSTGinDieXx = (padCenterAllX OR padCenterSTGxxSz) AND solid_seal
padCenterinDieXspSTG = EXTERNAL padCenterSTGinDieXx < 9.0 ABUT < 90 SINGULAR REGION
padCenterinDieXspSTGGood = padCenterSTGinDieXx NOT padCenterinDieXspSTG
padSTGinDieXsp = bondPadSTG INTERACT (bondPadSTG AND ((padCenterAllX AND bondPadSTG) INTERACT padCenterinDieXspSTGGood))
pad.SP.21 {
    @ pad.SP.21: Min. spacing of staggered pad in adjacent rows in y direction < 9.0
    EXTERNAL padSTGinDieXsp bondPadSTG < 9.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
bondpadSTGscribe = EXPAND EDGE padSTGedgX OUTSIDE BY 284
bondpadFPscribe = EXPAND EDGE padFPedgX OUTSIDE BY 200
bondpadHPscribe = EXPAND EDGE padHPedgX OUTSIDE BY 200
bondpadWLBIscribe = EXPAND EDGE padWLBIedgX OUTSIDE BY 200
outsideSEALedge = EXPAND EDGE (solid_seal COINCIDENT EDGE SEALID) OUTSIDE BY 0.005
bondpadSTGscribeBad = bondpadSTGscribe INTERACT (bondpadSTGscribe AND outsideSEALedge)
bondpadFPscribeBad = bondpadFPscribe INTERACT (bondpadFPscribe AND outsideSEALedge)
bondpadHPscribeBad = bondpadHPscribe INTERACT (bondpadHPscribe AND outsideSEALedge)
bondpadWLBIscribeBad = bondpadWLBIscribe INTERACT (bondpadWLBIscribe AND outsideSEALedge)
pad.SP.22 {
    @ pad.SP.22: Min space staggered pad opening to adj. scribe (outer edge of seal) in x direction < 200.0
    COPY bondpadSTGscribeBad
}
pad.SP.23 {
    @ pad.SP.23: Min space fine pitch pad opening to adj. scribe (outer edge of seal) < 200.0
    COPY bondpadFPscribeBad
}
pad.SP.24 {
    @ pad.SP.24: Min space of wafer level burn in pad opening in x direction to adj. scribe in x direction < 200.0
    COPY bondpadWLBIscribeBad
}
pmmInInd = pmm AND inductor
pad.WID.14 {
    @ pad.WID.14: Min. width of pad opening inside inductor < 5.0
    INT padInInd < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
pad.ENC.3 {
    @ pad.ENC.3: Min. enclosure of pad opening inside inductor by pmm is 0
    q0padInIndand = padInInd AND pmm
    padInInd NOT pmm
}
pad.CON.10 {
    @ pad.CON.10: pad opening inside inductor must be enclosed by pmm
    padInInd NOT pmm
}
pad.ENC.4 {
    @ pad.ENC.4: Min. enclosure of pad opening inside inductor by met5 < 2.7
    q1padInIndand = padInInd AND met5
    ENC q1padInIndand met5 < 2.7 MEASURE ALL ABUT < 90 SINGULAR REGION
}
pad.CON.11 {
    @ pad.CON.11: pad opening inside inductor must be enclosed by met5
    padInInd NOT met5
}
pad.ENC.5 {
    @ pad.ENC.5: Min. enclosure of pmm inside inductor by rdl < 10.75
    q0pmmInIndand = pmmInInd AND rdl
    ENCLOSURE q0pmmInIndand rdl < 10.75 MEASURE ALL ABUT < 90 SINGULAR
}
pad.ENC.6 {
    @ pad.ENC.6: pmm inside inductor must be enclosed by rdl
    pmmInInd NOT rdl
}
pad_power = pad INTERACT pad_pwr
pad_ground = pad INTERACT pad_gnd
pad_signal = pad INTERACT pad_io
pad.CON.12 {
    @ pad.CON.12: Only one layer areaid/pad_pwr, areaid/pad_io and/or areaid/pad_gnd can be used on a single pad
    (pad AND pad_power) AND pad_ground
    (pad AND pad_power) AND pad_signal
    (pad AND pad_ground) AND pad_signal
    (pad AND pad_signal) AND pad_power
    (pad AND pad_signal) AND pad_ground
}
pad.CON.13 {
    @ pad.CON.13: Layers areaid/pad_pwr, areaid/pad_io and/or areaid/pad_gnd must be inside layer pad
    pad_gnd NOT pad
    pad_pwr NOT pad
    pad_io NOT pad
}
pad.CON.14 {
    @ pad.con.14: Met4 is prohibited inside pad
    pad AND met4i
}


//
// LVS Exclude Rules
//


LVS_exclude.WARN.1 {
    @ LVS_exclude.WARN.1: LVS_exclude does not enclose any device
    LVS_exclude NOT ENCLOSE (OR diffi polyi capm cap2m npn pnp diffres polyres lires m1res m2res m3res m4res m5res pwres DIODEID PHdiodeID fuse pad)
}
LVS_exclude.CON.1 {
    @ LVS_exclude.CON.1: LVS_exclude must not straddle gate
    LVS_exclude INSIDE EDGE gate
}
LVS_exclude.CON.2 {
    @ LVS_exclude.CON.2: LVS_exclude must not straddle N+ source/drain
    LVS_exclude INSIDE EDGE nsd
}
LVS_exclude.CON.3 {
    @ LVS_exclude.CON.3: LVS_exclude must not straddle P+ source/drain
    LVS_exclude INSIDE EDGE psd
}
LVS_exclude.CON.4 {
    @ LVS_exclude.CON.4: LVS_exclude must not straddle capm
    LVS_exclude INSIDE EDGE capm
}
LVS_exclude.CON.5 {
    @ LVS_exclude.CON.5: LVS_exclude must not straddle cap2m
    LVS_exclude INSIDE EDGE cap2m
}
LVS_exclude.CON.6 {
    @ LVS_exclude.CON.6: LVS_exclude must not straddle pwell:res
    LVS_exclude INSIDE EDGE pwres
}
LVS_exclude.CON.7 {
    @ LVS_exclude.CON.7: LVS_exclude must not straddle diff:res
    LVS_exclude INSIDE EDGE diffres
}
LVS_exclude.CON.8 {
    @ LVS_exclude.CON.8: LVS_exclude must not straddle poly:res
    LVS_exclude INSIDE EDGE polyres
}
LVS_exclude.CON.9 {
    @ LVS_exclude.CON.9: LVS_exclude must not straddle li:res
    LVS_exclude INSIDE EDGE lires
}
LVS_exclude.CON.10 {
    @ LVS_exclude.CON.10: LVS_exclude must not straddle met1:res
    LVS_exclude INSIDE EDGE m1res
}
LVS_exclude.CON.11 {
    @ LVS_exclude.CON.11: LVS_exclude must not straddle met2:res
    LVS_exclude INSIDE EDGE m2res
}
LVS_exclude.CON.12 {
    @ LVS_exclude.CON.12: LVS_exclude must not straddle met3:res
    LVS_exclude INSIDE EDGE m3res
}
LVS_exclude.CON.13 {
    @ LVS_exclude.CON.13: LVS_exclude must not straddle met4:res
    LVS_exclude INSIDE EDGE m4res
}
LVS_exclude.CON.14 {
    @ LVS_exclude.CON.14: LVS_exclude must not straddle met5:res
    LVS_exclude INSIDE EDGE m5res
}
LVS_exclude.CON.15 {
    @ LVS_exclude.CON.15: LVS_exclude must not straddle areaid:diode
    LVS_exclude INSIDE EDGE DiodeID
}
LVS_exclude.CON.16 {
    @ LVS_exclude.CON.16: LVS_exclude must not straddle pnp
    LVS_exclude INSIDE EDGE pnp
}
LVS_exclude.CON.17 {
    @ LVS_exclude.CON.17: LVS_exclude must not straddle npn
    LVS_exclude INSIDE EDGE npn
}
LVS_exclude.CON.18 {
    @ LVS_exclude.CON.18: LVS_exclude must not straddle areaid:photo
    LVS_exclude INSIDE EDGE PHdiodeID
}
LVS_exclude.CON.19 {
    @ LVS_exclude.CON.19: LVS_exclude must not straddle pad
    LVS_exclude INSIDE EDGE pad
}
LVS_exclude.OVL.1 {
    @ LVS_exclude.OVL.1: LVS_exclude must be inside areaid:moduleCut
    LVS_exclude NOT moduleCutArea 
}

//
// RECOMMENDED RULES
//

#IFNDEF SKIP_RECOMMENDED_CHECKS


pr_chip_check_RECOMMENDED = prBndry AND SEALnoHoles_ORIGIN
pr_ip_check_RECOMMENDED = prBndry NOT SEALnoHoles_ORIGIN
prBndry.CON.2 {
    @ prBndry.CON.2: prBoundary.boundary not allowed in chip layout
    COPY pr_chip_check_RECOMMENDED
}


#ENDIF


//
// photo checks
//


photoDiode = dnwell INTERACT (dnwell AND (ntap AND PHdiodeID))
photo.WID.1 {
    @ photo.WID.1: Min/Max width of areaid:photo = 3.0
    NOT LENGTH photoDiode == 3.0
}
photo.SP.1 {
    @ photo.SP.1: Min spacing/notch of areaid:photo < 5.0
    EXTERNAL photoDiode < 5.0 ABUT < 90 SINGULAR REGION
}
photo.SP.2 {
    @ photo.SP.2: Min spacing between areaid:photo and deep nwell < 5.3
    EXTERNAL photoDiode (dnwell NOT photoDiode) < 5.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
photo.CON.1 {
    @ photo.CON.1: Photo diode edges must be coincident with areaid:photo
    photoDiode NOT COINCIDENT INSIDE EDGE PHdiodeID
}
photo.CON.2 {
    @ photo.CON.2: areaid:photo must be enclosed by dnwell ring
    photoDiode NOT (HOLES dnwell INNER)
}
photo.CON.3 {
    @ photo.CON.3: areaid:photo must be enclosed by p+tap ring
    photoDiode NOT (HOLES PTAP INNER)
}
photo.WID.2 {
    @ photo.WID.2: Min/Max width of nwell inside areaid:photo = 0.84
    NOT LENGTH (photoDiode AND nwell) == 0.84
}
photo.ENC.1 {
    @ photo.ENC.1: Min/Max enclosure of nwell by areaid:photo = 1.08
    photoOutsideNwell = photoDiode NOT nwell
    photoOutsideNwell NOT (INTERNAL photoOutsideNwell == 1.08 OPPOSITE EXTENDED 1.08 PARALLEL ONLY REGION)
}
photo.WID.3 {
    @ photo.WID.3: Min/Max width of tap inside areaid:photo = 0.41
    NOT LENGTH (photoDiode AND tap) == 0.41
}
photo.ENC.2 {
    @ photo.ENC.2: Min/Max enclosure of tap by nwell inside areaid:photo = 0.215
    photoNwellBeyondTap = (photoDiode AND nwell) NOT tap
    photoNwellBeyondTap NOT (INTERNAL photoNwellBeyondTap == 0.215 OPPOSITE EXTENDED 0.215 PARALLEL ONLY REGION)
}


//
// Metal checks
//


met1.AR.1 {
    @ met1.AR.1: Min area of met1 < 0.083
    AREA met1i < 0.083
}
met1_hole = HOLES met1i
met1_hole_empty = HOLES met1i INNER
met1.AR.2 {
    @ met1.AR.2: Min area of met1 hole < 0.14
    AREA met1_hole < 0.14
    AREA met1_hole_empty < 0.14
}
met1.WID.1 {
    @ met1.WID.1: Min width of met1 < 0.14
    INT met1i < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met1.SP.1 {
    @ met1.SP.1: Min space & notch of met1 < 0.14
    EXT met1i < 0.14 ABUT < 90 SINGULAR REGION
}
wide_met1a = WITH WIDTH met1i > 3.0
wide_met1 = SIZE wide_met1a BY 0.28 INSIDE OF met1i STEP 0.07
met1.SP.2 {
    @ met1.SP.2: Wide met1 (including wide metal extending 0.28 into narrow metal) min spacing to met1 < 0.28
    EXT wide_met1 met1i < 0.28 ABUT<90 REGION
}
#IFDEF SAVE_CONSTRUCTION_LAYERS
keep_wide_met1 {
    @ keep_wide_met1: Derived wide met1 for reference
    COPY wide_met1
}
#ENDIF
met2.AR.1 {
    @ met2.AR.1: Min area of met2 < 0.0676
    AREA met2i < 0.0676
}
met2_hole = HOLES met2i
met2_hole_empty = HOLES met2i INNER
met2.AR.2 {
    @ met2.AR.2: Min area of met2 hole < 0.14
    AREA met2_hole < 0.14
    AREA met2_hole_empty < 0.14
}
met2.WID.1 {
    @ met2.WID.1: Min width of met2 < 0.14
    INT met2i < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met2.SP.1 {
    @ met2.SP.1: Min space & notch of met2 < 0.14
    EXT met2i < 0.14 ABUT < 90 SINGULAR REGION
}
wide_met2a = WITH WIDTH met2i > 3.0
wide_met2 = SIZE wide_met2a BY 0.28 INSIDE OF met2i STEP 0.07
met2.SP.2 {
    @ met2.SP.2: Wide met2 (including wide metal extending 0.28 into narrow metal) min spacing to met2 < 0.28
    EXT wide_met2 met2i < 0.28 ABUT<90 REGION
}
#IFDEF SAVE_CONSTRUCTION_LAYERS
keep_wide_met2 {
    @ keep_wide_met2: Derived wide met2 for reference
    COPY wide_met2
}
#ENDIF
met3.AR.1 {
    @ met3.AR.1: Min area of met3 < 0.24
    AREA met3i < 0.24
}
met3_hole = HOLES met3i
met3_hole_empty = HOLES met3i INNER
met3.AR.2 {
    @ met3.AR.2: Min area of met3 hole < 0.2
    AREA met3_hole < 0.2
    AREA met3_hole_empty < 0.2
}
met3.WID.1 {
    @ met3.WID.1: Min width of met3 < 0.3
    INT met3i < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met3.SP.1 {
    @ met3.SP.1: Min space & notch of met3 < 0.3
    EXT met3i < 0.3 ABUT < 90 SINGULAR REGION
}
wide_met3a = WITH WIDTH met3i > 3.0
wide_met3 = SIZE wide_met3a BY 0.28 INSIDE OF met3i STEP 0.07
met3.SP.2 {
    @ met3.SP.2: Wide met3 (including wide metal extending 0.28 into narrow metal) min spacing to met3 < 0.4
    EXT wide_met3 met3i < 0.4 ABUT<90 REGION
}
#IFDEF SAVE_CONSTRUCTION_LAYERS
keep_wide_met3 {
    @ keep_wide_met3: Derived wide met3 for reference
    COPY wide_met3
}
#ENDIF
met4.AR.1 {
    @ met4.AR.1: Min area of met4 < 0.24
    AREA met4i < 0.24
}
met4_hole = HOLES met4i
met4_hole_empty = HOLES met4i INNER
met4.AR.2 {
    @ met4.AR.2: Min area of met4 hole < 0.2
    AREA met4_hole < 0.2
    AREA met4_hole_empty < 0.2
}
met4.WID.1 {
    @ met4.WID.1: Min width of met4 < 0.3
    INT met4i < 0.3 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met4.SP.1 {
    @ met4.SP.1: Min space & notch of met4 < 0.3
    EXT met4i < 0.3 ABUT < 90 SINGULAR REGION
}
wide_met4a = WITH WIDTH met4i > 3.0
wide_met4 = SIZE wide_met4a BY 0.28 INSIDE OF met4i STEP 0.07
met4.SP.2 {
    @ met4.SP.2: Wide met4 (including wide metal extending 0.28 into narrow metal) min spacing to met4 < 0.4
    EXT wide_met4 met4i < 0.4 ABUT<90 REGION
}
#IFDEF SAVE_CONSTRUCTION_LAYERS
keep_wide_met4 {
    @ keep_wide_met4: Derived wide met4 for reference
    COPY wide_met4
}
#ENDIF
met5.AR.1 {
    @ met5.AR.1: Min area of met5 < 4.0
    AREA met5i < 4.0
}
met5_hole = HOLES met5i
met5_hole_empty = HOLES met5i INNER
met5.AR.2 {
    @ met5.AR.2: Min area of met5 hole < 0.14
    AREA met5_hole < 0.14
    AREA met5_hole_empty < 0.14
}
met5.WID.1 {
    @ met5.WID.1: Min width of met5 < 1.6
    INT met5i < 1.6 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met5.SP.1 {
    @ met5.SP.1: Min space & notch of met5 < 1.6
    EXT met5i < 1.6 ABUT < 90 SINGULAR REGION
}
wide_met5a = WITH WIDTH met5i > 3.0
wide_met5 = SIZE wide_met5a BY 0.28 INSIDE OF met5i STEP 0.07
m1_enc_mc_exempt = EXTENT CELL "s8cell_ee_plus_sseln_a" "s8cell_ee_plus_sseln_b" "s8cell_ee_plus_sselp_a" "s8cell_ee_plus_sselp_b" "s8fpls_pl8" "s8fs_cmux4_fm"
met1.ENC.1 {
    @ met1.ENC.1: Min enclosure of mcon by met1 (except inside areaid:core) < 0.03
    ENC (mcon NOT COREID) met1i < 0.03 MEASURE ALL ABUT<90 SINGULAR REGION
}
met1.ENC.1a {
    @ met1.ENC.1a: Min enclosure of mcon by met1 (for exempt cells) < 0.005
    ENC ((mcon AND m1_enc_mc_exempt) NOT COREID) met1i < 0.005 MEASURE ALL ABUT<90 SINGULAR REGION
}
met1.ENC.2 {
    @ met1.ENC.2: Min enclosure of adj. sides of mcon in periphery by met1 < 0.06
    m1_enc_1 = ENC [mcon_PERI] met1i < 0.06 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0
    NOT RECTANGLE (EXPAND EDGE m1_enc_1 INSIDE BY 0.005) ORTHOGONAL ONLY
}
met2.ENC.1 {
    @ met2.ENC.1: Min enclosure of via1 by met2 outside areaid:core < 0.055
    ENC (via1 NOT COREID) met2 < 0.055 ABUT<90 REGION SINGULAR
}
met2.ENC.3 {
    @ met2.ENC.3: Min enclosure of via1 by met2 inside areaid:core < 0.045
    ENC (via1 AND COREID) met2 < 0.045 ABUT<90 REGION SINGULAR
}
met2.ENC.2 {
    @ met2.ENC.2: Min enclosure of adj. sides of via1 in periphery by met2 < 0.085
    m2_enc_1 = ENC [via1] met2i < 0.085 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0
    NOT RECTANGLE (EXPAND EDGE m2_enc_1 INSIDE BY 0.005) ORTHOGONAL ONLY
}
met3.ENC.1 {
    @ met3.ENC.1: Min enclosure of via2 by met3 < 0.065
    ENC via2 met3i < 0.065 ABUT<90 REGION SINGULAR
}
met4.ENC.1 {
    @ met4.ENC.1: Min enclosure of via3 by met4 < 0.065
    ENC via3 met4i < 0.065 ABUT<90 REGION SINGULAR
}
met5.ENC.1 {
    @ met5.ENC.1: Min enclosure of via4 by met5 < 0.31
    ENC via4 met5i < 0.31 ABUT<90 REGION SINGULAR
}


//
// Local interconnect checks
//


vpp_hd5 = EXTENT CELL "vpp*"
li_in_vpp = li_i AND vpp_hd5
li_not_vpp = li_i NOT li_in_vpp
li_not_vpp_cut_or_outside_core = (li_not_vpp NOT INTERACT COREID) OR (li_not_vpp CUT COREID)
li_in_vpp_or_inside_core = li_in_vpp  OR (li_not_vpp INSIDE COREID)
li_inside_core = li INSIDE COREID
li.WID.1 {
    @ li.WID.1: Min width of local interconnect (not vpp) crossing or outside areaid:core < 0.17
    INT (((li_i NOT COREID) NOT vpp_hd5) OR ((li_i CUT COREID) NOT vpp_hd5))  < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
li.WID.2 {
    @ li.WID.2: Min width of local interconnect in vppcap < 0.14
    INT (li_i AND vpp_hd5)  < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
li.WID.3 {
    @ li.WID.3: Min width of local interconnect in areaid:core < 0.14
    INT (li_i AND COREID)  < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
li.SP.1 {
    @ li.SP.1: Min space of local interconnect (not vpp) crossing or outside areaid:core < 0.17
    EXT (li_i NOT COREID) li_i < 0.17 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
li.SP.2 {
    @ li.SP.2: Min space of local interconnect in vppcap < 0.14
    EXT li_in_vpp li < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
li.SP.3 {
    @ li.SP.3: Min space of local interconnect inside areaid:core < 0.165
    EXT li_inside_core li < 0.165 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
licon_nocore = licon NOT COREID
li.ENC.1 {
    @ li.ENC.1: Enclosure of licon by one of two adjacent local interconnect sides < 0.08
    li_en_1 = ENC [licon_nocore] li < 0.08 ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0
    NOT RECTANGLE (EXPAND EDGE li_en_1 INSIDE BY 0.005) ORTHOGONAL ONLY
}
li.AR.1 {
    @ li.AR.1: Min area of local interconnect < 0.0561
    AREA li < 0.0561
}
li.WID.4 {
    @ li.WID.3: Min local interconnect resistor width < 0.29
    li_and_res = lires AND li_i
    li_and_res_not_esd = li_and_res NOT ESDID
    li_and_res_not_esd_not_li_edge = EXPAND EDGE (li_and_res_not_esd NOT COIN EDGE li) OUTSIDE by 0.005
    (EXT li_and_res_not_esd_not_li_edge < 0.29 ABUT<90 REGION EXCLUDE FALSE) AND li_and_res_not_esd
}


//
// Via/contact checks
//


licon_no_prec_res = (licon NOT INTERACT (OR rpm urpm)) NOT SEALID
licon_prec_res = licon INTERACT (OR rpm urpm)
licon.WID.1 {
    @ licon.WID.1: Min licon width (non-bar) < 0.17
    INT licon_no_prec_res < 0.17 ABUT<90 REGION
}
licon.LEN.1 {
    @ licon.LEN.1: Max licon length (non-bar) > 0.17
    LENGTH licon_no_prec_res > 0.17
}
licon.WID.2 {
    @ licon.WID.2: Exact size of bar licon = 0.19 X 2.0
    NOT RECTANGLE licon_prec_res == 0.19 BY == 2.0 ORTHOGONAL ONLY
}
licon.SP.1 {
    @ licon.SP.1: Min licon space (non-bar) outside areaid:core < 0.17
    EXT (licon_no_prec_res NOT COREID) < 0.17 ABUT<90 SINGULAR REGION
}
licon.SP.2 {
    @ licon.SP.2: Min end-to-end space of bar licon < 0.35
    bar_licon_end = LENGTH licon_prec_res < 2.0
    EXT bar_licon_end < 0.35 ABUT<90 REGION
}
licon.SP.3 {
    @ licon.SP.3: Min side-to-side spacing of bar licon < 0.510
    bar_licon_side = LENGTH licon_prec_res > 0.19
    EXT bar_licon_side < 0.510 ABUT<90 REGION
}
licon.SP.4 {
    @ licon.SP.4: Min space from bar licon to square licon < 0.510
    EXT licon_no_prec_res licon_prec_res < 0.510 ABUT<90 REGION SINGULAR
}
licon.WID.3 {
    @ licon.WID.3: Min width licon in areaid:seal < 0.17
    INT (licon AND SEALID) < 0.17 ABUT<90 REGION
}
licon.WID.4 {
    @ licon.WID.4: Max width of licon in areaid:seal > 0.17+0.005
    WITH WIDTH (licon AND SEALID) > 0.17+0.005
}
licon.ENC.1 {
    @ licon.ENC.1: Min enclosure of licon by diff (not tap) < 0.04
    ENC (licon_nocore NOT tap) diffi < 0.04 MEASURE ALL ABUT<90 REGION SINGULAR
}
licon.SP.5 {
    @ licon.SP.5: Min space from tap licon to diff-abutting tap edge > 0.06
    EXT (licon_nocore and tap) (diff COINCIDENT OUTSIDE EDGE tap) < 0.06 ABUT<90 REGION
}
licon.ENC.2 {
    @ licon.ENC.2: Min enclosure of licon by diff on one of two adjacent sides < 0.06
    li_enc_2 = ENC [licon_nocore] diff < 0.06 ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0
    NOT RECTANGLE (EXPAND EDGE li_enc_2 INSIDE BY 0.005) ORTHOGONAL ONLY
}
licon.CON.7 {
    @ licon.CON.7: Layer licon cannot straddle tap
    licon_nocore cut tap
}
licon.ENC.4 {
    @ licon.ENC.4: Min enclosure of licon by isolated tap on one of two adjacent sides < 0.12
    non_isolated_tap = tap WITH EDGE (tap COINCIDENT OUTSIDE EDGE diff)
    isolated_tap = tap NOT non_isolated_tap
    li_enc_4 = ENC [licon_nocore] isolated_tap < 0.12 ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0
    NOT RECTANGLE (EXPAND EDGE li_enc_4 INSIDE BY 0.005) ORTHOGONAL ONLY
}
licon.ENC.5 {
    @ licon.ENC.5: Min enclosure of licon by poly < 0.05
    ENC licon_nocore polyi < 0.05 ABUT<90 REGION SINGULAR
}
licon.ENC.6 {
    @ licon.ENC.6: Min enclosure of licon by poly on one of two adjacent sides < 0.08
    li_enc_6 = ENC [licon_nocore] polyi < 0.08 ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0
    NOT RECTANGLE (EXPAND EDGE li_enc_6 INSIDE BY 0.005) ORTHOGONAL ONLY
}
licon.SP.6 {
    @ licon.SP.6: Min space from poly licon to psdm (no overlap alowed) < 0.110
    EXT ((licon_nocore AND poly) OUTSIDE (rpm OR urpm)) psdm < 0.110 ABUT<90 SINGULAR REGION
    ((poly AND licon_nocore) OUTSIDE (rpm OR urpm)) AND psdm
}
licon.SP.7 {
    @ licon.SP.7: Min space from licon on (tap in low voltage nwell) to varactor channel < 0.25
    poly_in_lv_nw = poly AND (nwell NOT INTERACT (OR v5 v12 v20))
    var_ch = poly_in_lv_nw AND (tap AND (nwell NOT INTERACT (OR v5 v12 v20)))
    var_licon = (licon_nocore AND (nwell NOT INTERACT (OR v5 v12 v20))) AND tap
    EXT var_licon var_ch < 0.25 ABUT<90 REGION SINGULAR
}
MOSDIFFandPOLY = diffi AND polyi
userGate = MOSDIFFandPOLY AND polyGate
derivedGate = MOSDIFFandPOLY OUTSIDE polyGate
allGatetmp = (derivedGate OR userGate) NOT ENID
remGate = allGatetmp TOUCH drainGate == 1
allGate = allGatetmp NOT remGate
drainGate = EXPAND EDGE (MOSDIFFandPOLY COINCIDENT INSIDE EDGE poly) OUTSIDE BY 0.005
licon.SP.8 {
    @ licon.SP.8: Min space and no overlap from licon on diff to poly on diff (except standard cells) < 0.055
    esdGate = allGate AND ESDID
    pesd = esdGate AND nwell
    phvesd = pesd INTERACT v5
    allENIDgate = ENID AND (poly AND v5)
    nwellENID = INTERACT nwell ENID
    pfetExtDrTmp = allENIDgate AND dnwell
    pfetExtDr = pfetExtDrTmp AND nwellENID
    pvhv = COPY pfetExtDr
    fetGate = allGate NOT esdGate
    pfet_dev = fetGate AND nwell
    phv = (pfet_dev INTERACT v5) NOT (pvhv OR phvesd)
    gate_not_std_cell = gate NOT STDCID
    xfom = diff NOT poly
    licon1ToXfom = licon INTERACT (licon AND xfom)
    licon1ToXfom_PERI = licon1ToXfom NOT COREID
    EXT licon1ToXfom_PERI gate_not_std_cell < 0.055 ABUT<90 REGION SINGULAR
    licon1ToXfom_PERI AND gate_not_std_cell
}
phvt_15_gate = INT (((poly AND diff) AND psdm) AND hvtp) == 0.15 REGION ABUT<90
licon.SP.9 {
    @ licon.SP.9: Min space from licon on diff to poly on diff in standard cells (except 0.15um p+ high vt) < 0.05
    EXT ((licon_nocore AND diff) AND STDCID) ((poly AND diff) NOT phvt_15_gate) < 0.05 ABUT<90 REGION SINGULAR
}
licon.SP.10 {
    @ licon.SP.10: Min space from licon on diff to poly on diff in standard cells for p+ high vt < 0.055
    EXT (phvt_15_gate AND STDCID) ((licon_nocore AND diff) AND STDCID) < 0.055 ABUT<90 REGION SINGULAR
}
licon.SP.11 {
    @ licon.SP.11: Min space (no overlap) from licon on diff to npc < 0.09
    EXT ((diffi and licon_nocore) NOT COREID) npc < 0.09 ABUT<90 SINGULAR REGION
    (diffi and licon_nocore) AND npc
}
licon.SP.12 {
    @ licon.SP.12: Min space from poly licon to diff < 0.19
    EXT ((polyi AND licon) NOT COREID) diffi < 0.19 ABUT<90 REGION SINGULAR
}
licon.SP.13 {
    @ licon.SP.13: Min space from poly licon to diff in core < 0.13
    EXT ((polyi AND licon) AND COREID) diffi < 0.13 ABUT<90 REGION SINGULAR
}
licon.SP.14 {
    @ licon.SP.14: Min licon space (non-bar) inside areaid:core < 0.165
    EXT (licon_no_prec_res AND COREID) < 0.165 ABUT<90 SINGULAR REGION
}
licon.ENC.7 {
    @ licon.ENC.7: Min enclosure of poly licon by npc outside areaid:core < 0.1
    ENC ((polyi AND licon) NOT COREID) npc < 0.1 ABUT<90 REGION SINGULAR
}
licon.ENC.8 {
    @ licon.ENC.8: Min enclosure of poly licon by npc inside areaid:core >= 0.045
    ENC ((polyi AND licon) AND COREID) npc < 0.045 ABUT<90 REGION SINGULAR
}
licon.CON.8 {
    @ licon.CON.8: Every source or drain diff must enclose at least 1 licon (except in v20)
    nsrcdrn = (diff NOT poly) and nsdm
    psrcdrn = (diff NOT poly) and psdm
    source_diffusion = (nsrcdrn WITH EDGE (nsrcdrn COINCIDENT OUTSIDE EDGE ptap)) OR (psrcdrn WITH EDGE (psrcdrn COINCIDENT OUTSIDE EDGE ntap))
    source_diffusion_peri = source_diffusion NOT COREID
    licon_in_source = licon INSIDE source_diffusion_peri
    (source_diffusion_peri OUTSIDE licon_in_source) NOT V20
}
licon.CON.9 {
    @ licon.CON.9: Every tap must enclose at least 1 licon (except in v20)
    tap_PERI = tap NOT COREID
    npcon_tap = tap_PERI OR (tap CUT COREID)
    (npcon_tap NOT ENCLOSE licon) NOT v20
}
licon.CON.10 {
    @ licon.CON.10: Layer licon must not overlap both poly and diff
    (poly and licon) AND diff
}
licon.CON.11 {
    @ licon.CON.11: Poly licon must be inside npc
    (poly AND licon) NOT npc
}
licon.CON.12 {
    @ licon.CON.12: psdm overlapping poly and licon is prohibited inside areaid:core
    ((poly AND licon) AND psdm) AND COREID
}
mcon_donut = DONUT mcon
non_ring_mcon = mcon NOT mcon_donut
mcon.WID.1 {
    @ mcon.WID.1: Min width of mcon < 0.17
    INT mcon < 0.17 REGION
}
mcon.LEN.1 {
    @ mcon.LEN.1: Max width of mcon > 0.17
    non_ring_mcon WITH EDGE (LENGTH non_ring_mcon > 0.17)
}
mcon.SP.1 {
    @ mcon.SP.1: Min spacing of mcon < 0.19
    EXT mcon < 0.19 ABUT < 90 SINGULAR REGION
}
via1.WID.1 {
    @ via1.WID.1: Min width of via1 outside areaid:moduleCut < 0.15
    INT (via1 NOT moduleCutAREA) < 0.15 ABUT<90 REGION
}
via1.LEN.1 {
    @ via1.LEN.1: Max length of via1 outside areaid:moduleCut > 0.15
    LENGTH (via1 NOT moduleCutAREA) > 0.15
}
via_in_mc_good_1 = RECTANGLE (via1 AND moduleCutAREA) == 0.15 BY == 0.15 ORTHOGONAL ONLY
via_in_mc_good_2 = RECTANGLE (via1 AND moduleCutAREA) == 0.23 BY == 0.23 ORTHOGONAL ONLY
via_in_mc_good_3 = RECTANGLE (via1 AND moduleCutAREA) == 0.28 BY == 0.28 ORTHOGONAL ONLY
via1.WID.2 {
    @ via1.WID.2: Only three size of square via1s allowed inside areaid:moduleCut: 0.15, 0.23 or 0.28
    (via1 AND moduleCutAREA) NOT (OR via_in_mc_good_1 via_in_mc_good_2 via_in_mc_good_3)
}
via1.SP.1 {
    @ via1.SP.1: Min space of via1 < 0.17
    EXT via1 < 0.17 ABUT<90 REGION SINGULAR EXCLUDE FALSE
}
via1.ENC.1 {
    @ via1.ENC.1: Min enclosure of via1 by metal 1 outside module cut area < 0.055
    ENC (via1 NOT moduleCutAREA) met1i < 0.055 MEASURE ALL ABUT<90 SINGULAR REGION
}
via1.ENC.2 {
    @ via1.ENC.2: Min enclosure of 0.23um via1 by met1 inside module cut area < 0.03
    ENC via_in_mc_good_2 met1i < 0.03 MEASURE ALL ABUT<90 SINGULAR REGION
}
via1.ENC.3 {
    @ via1.ENC.3: Min enclosure of 0.28 um via by met1 inside module cut area < 0
    via_in_mc_good_3 NOT met1i
}
via1.ENC.4 {
    @ via1.ENC.4: Min enclosure of 0.15um via by met1 on one of two adjacent sides < 0.085
    via_15 = RECTANGLE via1 == 0.15 BY == 0.15 ORTHOGONAL ONLY
    via_enc_5 = ENC [via_15] met1i < 0.085 ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0
    NOT RECTANGLE (EXPAND EDGE via_enc_5 INSIDE BY 0.005) ORTHOGONAL ONLY
}
via1.ENC.5 {
    @ via1.ENC.5: Min enclosure of 0.23um via by met1 on one of two adjacent sides < 0.085
    via_23 = RECTANGLE via1 == 0.23 BY == 0.23 ORTHOGONAL ONLY
    via_enc_5 = ENC [via_23] met1i < 0.06 ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0
    NOT RECTANGLE (EXPAND EDGE via_enc_5 INSIDE BY 0.005) ORTHOGONAL ONLY
}
via2.WID.1 {
    @ via2.WID.1: Min via2 width outside areaid:moduleCut < 0.2
    INT (via2 NOT moduleCutAREA) < 0.2 ABUT<90 REGION
}
via2.LEN.1 {
    @ via2.LEN.1: Max length via2 outside areaid:moduleCut > 0.2
    LENGTH (via2 NOT moduleCutAREA) > 0.2
}
via2_in_mc_good_1 = RECTANGLE (via2 AND moduleCutAREA) == 0.2 BY == 0.2 ORTHOGONAL ONLY
via2_in_mc_good_2 = RECTANGLE (via2 AND moduleCutAREA) == 0.28 BY == 0.28 ORTHOGONAL ONLY
via2_in_mc_good_3 = RECTANGLE (via2 AND moduleCutAREA) == 1.2 BY == 1.2 ORTHOGONAL ONLY
via2_in_mc_good_4 = RECTANGLE (via2 AND moduleCutAREA) == 1.5 BY == 1.5 ORTHOGONAL ONLY
via2.WID.2 {
    @ via2.WID.2: Only four sizes of square via2s allowed inside areaid:moduleCut: 0.2, 0.28, 1.2 or 1.5
    (via2 AND moduleCutAREA) NOT (OR via2_in_mc_good_1 via2_in_mc_good_2 via2_in_mc_good_3 via2_in_mc_good_4)
}
via2.SP.1 {
    @ via2.SP.1: Min space of via2 < 0.2
    EXT via2 < 0.2 ABUT<90 REGION SINGULAR EXCLUDE FALSE
}
via2.ENC.1 {
    @ via2.ENC.1: Min enclosure of via2 by met2 < 0.04
    ENC via2 met2 < 0.04 ABUT<90 MEASURE ALL SINGULAR REGION
}
via2.ENC.2 {
    @ via2.ENC.2: Min enclosure of 1.5um via2 by met2 inside module cut area < 0.14
    ENC via2_in_mc_good_4 met2i < 0.14 ABUT<90 MEASURE ALL SINGULAR REGION
}
via2.ENC.3 {
    @ via2.ENC.3: Min enclosure of via2 by met2 on one of two adjacent sides < 0.085
    via2_enc_5 = ENC [via2] met2i < 0.085 ABUT<90 PARALLEL MEASURE ALL PROJECTING > 0
    NOT RECTANGLE (EXPAND EDGE via2_enc_5 INSIDE BY 0.005) ORTHOGONAL ONLY
}
ring_via3 = DONUT via3
non_ring_via3 = via3 NOT ring_via3
via3_not_modulecut = via3 NOT moduleCutAREA
via3_and_modulecut = via3 AND moduleCutAREA
via3.WID.1 {
    @ via3.WID.1: Min width of via3 outside areaid:moduleCut < 0.20
    INT via3_not_modulecut < 0.20 REGION
}
via3.LEN.1 {
    @ via3.LEN.1: Max length via3 outside areaid:moduleCut > 0.20
    via3_not_modulecut WITH EDGE (LENGTH via3_not_modulecut > 0.20)
}
via3.WID.2 {
    @ via3.WID.2: via3 size inside areaid:moduleCut must be 0.20 or 0.80
    good_a_v3 = RECTANGLE via3_and_modulecut == 0.20 BY == 0.20 ORTHOGONAL ONLY
    good_b_v3 = RECTANGLE via3_and_modulecut == 0.80 BY == 0.80 ORTHOGONAL ONLY
    all_good_v3 = good_a_v3 OR good_b_v3
    via3_and_modulecut NOT all_good_v3
}
via3.SP.1 {
    @ via3.SP.1: Min space of via3 < 0.20
    EXT via3 < 0.20 ABUT < 90 SINGULAR REGION
}
via3.ENC.1 {
    @ via3.ENC.1: Min enclosure of via3 by met3 < 0.06
    ENC via3 met3i < 0.06 MEASURE ALL ABUT<90 SINGULAR
}
via3.ENC.2 {
    @ via3.ENC.2: Min enclosure of adjacent sides of via3 by met3 < 0.09
    via3_enc_2 = ENC [via3] met3i < 0.09 ABUT < 90 PARALLEL MEASURE ALL PROJECTING > 0
    NOT RECTANGLE (EXPAND EDGE via3_enc_2 INSIDE BY 0.005) ORTHOGONAL ONLY
}
ring_via4 = DONUT via4
non_ring_via4 = via4 NOT ring_via4
via4_not_modulecut = non_ring_via4 NOT moduleCutAREA
via4_and_modulecut = non_ring_via4 AND moduleCutAREA
via4.WID.1 {
    @ via4.WID.1: Min width via4 outside areaid:moduleCut < 0.80
    INT non_ring_via4 < 0.80 REGION
}
via4.LEN.1 {
    @ via4.LEN.1: Max length via4 outside areaid:moduleCut > 0.80
    non_ring_via4 WITH EDGE (LENGTH non_ring_via4 > 0.80)
}
via4.SP.1 {
    @ via4.SP.1: Min space of via4 < 0.80
    EXT via4 < 0.80 ABUT < 90 SINGULAR REGION
}
via4.ENC.1 {
    @ via4.ENC.1: Min enclosure of via4 by met4 < 0.06
    ENC via4 met4i < 0.06 ABUT<90 MEASURE ALL REGION SINGULAR
}


//
// NSM checks
//


nsm.WID.1 {
    @ nsm.WID.1: Min width nsm < 3.0
    INT nsm < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.SP.1 {
    @ nsm.SP.1: Min space nsm < 4.0
    EXT nsm < 4.0 ABUT < 90 SINGULAR REGION
}
nsm_or_nsm_mask = nsm OR NSMmk
exempt_NSM3_Cells = (SEALID AND (DONUT diff)) OR ((EXTENT CELL "nikon*") OR nikon_cross)
exempt_NSM3a_Cells = (EXTENT CELL "s8Fab_crntic*") OR dieCut
diffi_not_exempt = diffi NOT exempt_NSM3_Cells
nsm.SP.2 {
    @ nsm.SP.2: nsm or nsm mask space to non-exempt diff < 1.0
    EXT diffi_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT diffi_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.2 {
    @ nsm.OVL.2: diff cannot overlap nsm or nsm mask
    diffi_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.2 {
    @ nsm.ENC.2: diff enclosure by frame boundary < 3.0
    diffi_not_exempt2 = diffi NOT exempt_NSM3a_Cells
    ENC diffi_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
diff_fill_not_exempt = diff_fill NOT exempt_NSM3_Cells
nsm.SP.3 {
    @ nsm.SP.3: nsm or nsm mask space to non-exempt diff fill < 1.0
    EXT diff_fill_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT diff_fill_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.3 {
    @ nsm.OVL.3: diff fill cannot overlap nsm or nsm mask
    diff_fill_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.3 {
    @ nsm.ENC.3: diff fill enclosure by frame boundary < 3.0
    diff_fill_not_exempt2 = diff_fill NOT exempt_NSM3a_Cells
    ENC diff_fill_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
FOMmk_not_exempt = FOMmk NOT exempt_NSM3_Cells
nsm.SP.4 {
    @ nsm.SP.4: nsm or nsm mask space to non-exempt cfom mask < 1.0
    EXT FOMmk_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT FOMmk_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.4 {
    @ nsm.OVL.4: cfom mask cannot overlap nsm or nsm mask
    FOMmk_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.4 {
    @ nsm.ENC.4: cfom mask enclosure by frame boundary < 3.0
    FOMmk_not_exempt2 = FOMmk NOT exempt_NSM3a_Cells
    ENC FOMmk_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
polyi_not_exempt = polyi NOT exempt_NSM3_Cells
nsm.SP.5 {
    @ nsm.SP.5: nsm or nsm mask space to non-exempt poly < 1.0
    EXT polyi_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT polyi_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.5 {
    @ nsm.OVL.5: poly cannot overlap nsm or nsm mask
    polyi_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.5 {
    @ nsm.ENC.5: poly enclosure by frame boundary < 3.0
    polyi_not_exempt2 = polyi NOT exempt_NSM3a_Cells
    ENC polyi_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
P1Mmk_not_exempt = P1Mmk NOT exempt_NSM3_Cells
nsm.SP.6 {
    @ nsm.SP.6: nsm or nsm mask space to non-exempt poly mask < 1.0
    EXT P1Mmk_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT P1Mmk_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.6 {
    @ nsm.OVL.6: poly mask cannot overlap nsm or nsm mask
    P1Mmk_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.6 {
    @ nsm.ENC.6: poly mask enclosure by frame boundary < 3.0
    P1Mmk_not_exempt2 = P1Mmk NOT exempt_NSM3a_Cells
    ENC P1Mmk_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
li_i_not_exempt = li_i NOT exempt_NSM3_Cells
nsm.SP.7 {
    @ nsm.SP.7: nsm or nsm mask space to non-exempt li < 1.0
    EXT li_i_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT li_i_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.7 {
    @ nsm.OVL.7: li cannot overlap nsm or nsm mask
    li_i_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.7 {
    @ nsm.ENC.7: li enclosure by frame boundary < 3.0
    li_i_not_exempt2 = li_i NOT exempt_NSM3a_Cells
    ENC li_i_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
LI1Mmk_not_exempt = LI1Mmk NOT exempt_NSM3_Cells
nsm.SP.8 {
    @ nsm.SP.8: nsm or nsm mask space to non-exempt li mask < 1.0
    EXT LI1Mmk_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT LI1Mmk_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.8 {
    @ nsm.OVL.8: li mask cannot overlap nsm or nsm mask
    LI1Mmk_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.8 {
    @ nsm.ENC.8: li mask enclosure by frame boundary < 3.0
    LI1Mmk_not_exempt2 = LI1Mmk NOT exempt_NSM3a_Cells
    ENC LI1Mmk_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
met1i_not_exempt = met1i NOT exempt_NSM3_Cells
nsm.SP.9 {
    @ nsm.SP.9: nsm or nsm mask space to non-exempt met1 < 1.0
    EXT met1i_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT met1i_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.9 {
    @ nsm.OVL.9: met1 cannot overlap nsm or nsm mask
    met1i_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.9 {
    @ nsm.ENC.9: met1 enclosure by frame boundary < 3.0
    met1i_not_exempt2 = met1i NOT exempt_NSM3a_Cells
    ENC met1i_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
MM1mk_not_exempt = MM1mk NOT exempt_NSM3_Cells
nsm.SP.10 {
    @ nsm.SP.10: nsm or nsm mask space to non-exempt met1 mask < 1.0
    EXT MM1mk_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT MM1mk_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.10 {
    @ nsm.OVL.10: met1 mask cannot overlap nsm or nsm mask
    MM1mk_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.10 {
    @ nsm.ENC.10: met1 mask enclosure by frame boundary < 3.0
    MM1mk_not_exempt2 = MM1mk NOT exempt_NSM3a_Cells
    ENC MM1mk_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
met2i_not_exempt = met2i NOT exempt_NSM3_Cells
nsm.SP.11 {
    @ nsm.SP.11: nsm or nsm mask space to non-exempt met2 < 1.0
    EXT met2i_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT met2i_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.11 {
    @ nsm.OVL.11: met2 cannot overlap nsm or nsm mask
    met2i_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.11 {
    @ nsm.ENC.11: met2 enclosure by frame boundary < 3.0
    met2i_not_exempt2 = met2i NOT exempt_NSM3a_Cells
    ENC met2i_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
MM2mk_not_exempt = MM2mk NOT exempt_NSM3_Cells
nsm.SP.12 {
    @ nsm.SP.12: nsm or nsm mask space to non-exempt met2 mask < 1.0
    EXT MM2mk_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT MM2mk_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.12 {
    @ nsm.OVL.12: met2 mask cannot overlap nsm or nsm mask
    MM2mk_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.12 {
    @ nsm.ENC.12: met2 mask enclosure by frame boundary < 3.0
    MM2mk_not_exempt2 = MM2mk NOT exempt_NSM3a_Cells
    ENC MM2mk_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
met3i_not_exempt = met3i NOT exempt_NSM3_Cells
nsm.SP.13 {
    @ nsm.SP.13: nsm or nsm mask space to non-exempt met3 < 1.0
    EXT met3i_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT met3i_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.13 {
    @ nsm.OVL.13: met3 cannot overlap nsm or nsm mask
    met3i_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.13 {
    @ nsm.ENC.13: met3 enclosure by frame boundary < 3.0
    met3i_not_exempt2 = met3i NOT exempt_NSM3a_Cells
    ENC met3i_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
MM3mk_not_exempt = MM3mk NOT exempt_NSM3_Cells
nsm.SP.14 {
    @ nsm.SP.14: nsm or nsm mask space to non-exempt met3 mask < 1.0
    EXT MM3mk_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT MM3mk_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.14 {
    @ nsm.OVL.14: met3 mask cannot overlap nsm or nsm mask
    MM3mk_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.14 {
    @ nsm.ENC.14: met3 mask enclosure by frame boundary < 3.0
    MM3mk_not_exempt2 = MM3mk NOT exempt_NSM3a_Cells
    ENC MM3mk_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
met4i_not_exempt = met4i NOT exempt_NSM3_Cells
nsm.SP.15 {
    @ nsm.SP.15: nsm or nsm mask space to non-exempt met4 < 1.0
    EXT met4i_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT met4i_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.15 {
    @ nsm.OVL.15: met4 cannot overlap nsm or nsm mask
    met4i_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.15 {
    @ nsm.ENC.15: met4 enclosure by frame boundary < 3.0
    met4i_not_exempt2 = met4i NOT exempt_NSM3a_Cells
    ENC met4i_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
MM4mk_not_exempt = MM4mk NOT exempt_NSM3_Cells
nsm.SP.16 {
    @ nsm.SP.16: nsm or nsm mask space to non-exempt met4 mask < 1.0
    EXT MM4mk_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT MM4mk_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.16 {
    @ nsm.OVL.16: met4 mask cannot overlap nsm or nsm mask
    MM4mk_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.16 {
    @ nsm.ENC.16: met4 mask enclosure by frame boundary < 3.0
    MM4mk_not_exempt2 = MM4mk NOT exempt_NSM3a_Cells
    ENC MM4mk_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
met5i_not_exempt = met5i NOT exempt_NSM3_Cells
nsm.SP.17 {
    @ nsm.SP.17: nsm or nsm mask space to non-exempt met5 < 1.0
    EXT met5i_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT met5i_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.17 {
    @ nsm.OVL.17: met5 cannot overlap nsm or nsm mask
    met5i_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.17 {
    @ nsm.ENC.17: met5 enclosure by frame boundary < 3.0
    met5i_not_exempt2 = met5i NOT exempt_NSM3a_Cells
    ENC met5i_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}
MM5mk_not_exempt = MM5mk NOT exempt_NSM3_Cells
nsm.SP.18 {
    @ nsm.SP.18: nsm or nsm mask space to non-exempt met5 mask < 1.0
    EXT MM5mk_not_exempt nsm < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
    EXT MM5mk_not_exempt NSMmk < 1.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nsm.OVL.18 {
    @ nsm.OVL.18: met5 mask cannot overlap nsm or nsm mask
    MM5mk_not_exempt AND nsm_or_nsm_mask
}
nsm.ENC.18 {
    @ nsm.ENC.18: met5 mask enclosure by frame boundary < 3.0
    MM5mk_not_exempt2 = MM5mk NOT exempt_NSM3a_Cells
    ENC MM5mk_not_exempt2 frameBndr < 3.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}


//
// NCM checks
//


ncmCore_drc = (ncm AND COREID) NOT exempt_tech_CD
ncmPeri_drc = ncm NOT ncmCore_drc
ncm_holes = HOLES ncm
ncm.OVL.1 {
    @ ncm.OVL.1: ncm in CORE (not exempt) must not overlap ndiff in periphery
    ncmCore_drc AND ndiff_PERI
}
ncm.WID.1 {
    @ ncm.WID.1: Min ncm width in periphery < 0.38
    INT ncmPeri_drc < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
ncm.SP.1 {
    @ ncm.SP.1: Min ncm spacing/notch < 0.38
    EXT ncmPeri_drc < 0.38 ABUT < 90 SINGULAR REGION
}
ncm.AR.1 {
    @ ncm.AR.1: Min ncm area < 0.265
    AREA ncm < 0.265
}
ncm.AR.2 {
    @ ncm.AR.2: Min area of ncm holes < 0.265
    AREA ncm_holes < 0.265
}
ncm.ENC.1 {
    @ ncm.ENC.1: Min enclosure of P+ diff by ncm in areaid:core (not exempt) < 0.235
    pdiff_in_ncm_core = (diffi AND psdm) AND ncmCore_drc
    ENC pdiff_in_ncm_core ncmCore_drc < 0.235 MEASURE ALL ABUT < 90 SINGULAR REGION
}
ncm.SP.2 {
    @ ncm.SP.2: Min spacing of ncm in areaid:core (not exempt) to ndiff < 0.235
    EXT ncmCore_drc (nsdm AND diffi) < 0.235 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
ncm.OVL.2 {
    @ ncm.OVL.2: ncm in areaid:core (not exempt) must not overlap ndiff
    ncmCore_drc AND (nsdm AND diffi)
}
nwellOutCore = (nwell OUTSIDE COREID) NOT TOUCH COREID
ncm.SP.3 {
    @ ncm.SP.3: Min space of ncm in areaid:core (not exempt) to nwell outside areaid:core < 0.38
    EXT nwellOutCore ncmCore_drc < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}


//
// RPM/URPM checks
//


precResistor = polyi AND (polyres AND ((rpm OR urpm) AND psdm))
rpm.WID.1 {
    @ rpm.WID.1: Min width rpm < 1.27
    INT rpm < 1.27 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
rpm.SP.1 {
    @ rpm.SP.1: Min space/notch rpm < 0.84
    EXT rpm < 0.84 ABUT < 90 SINGULAR REGION
}
rpm.ENC.1 {
    @ rpm.ENC.1: Min enclosure or precision resistor by rpm < 0.2
    ENC (precResistor AND rpm) rpm < 0.2 MEASURE ALL ABUT < 90 SINGULAR REGION
}
rpm.SP.2 {
    @ rpm.SP.2: Min spacing of rpm and nsdm < 0.2
    EXT rpm nsdm < 0.2 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
rpm.OVL.1 {
    @ rpm.OVL.1: rpm cannot overlap nsdm
    rpm AND nsdm
}
rpm.OVL.2 {
    @ rpm.OVL.2: poly must not straddle rpm
    poly CUT rpm
}
urpm.WID.1 {
    @ urpm.WID.1: Min width urpm < 1.27
    INT urpm < 1.27 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
urpm.SP.1 {
    @ urpm.SP.1: Min space/notch urpm < 0.84
    EXT urpm < 0.84 ABUT < 90 SINGULAR REGION
}
urpm.ENC.1 {
    @ urpm.ENC.1: Min enclosure or precision resistor by rpm < 0.2
    ENC (precResistor AND urpm) urpm < 0.2 MEASURE ALL ABUT < 90 SINGULAR REGION
}
urpm.SP.2 {
    @ urpm.SP.2: Min spacing of urpm and nsdm < 0.2
    EXT urpm nsdm < 0.2 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
urpm.OVL.1 {
    @ urpm.OVL.1: urpm cannot overlap nsdm
    urpm AND nsdm
}
urpm.OVL.2 {
    @ urpm.OVL.2: poly must not straddle urpm
    poly CUT urpm
}
rpm.SP.3 {
    @ rpm.SP.3: Min spacing of rpm and poly < 0.2
    EXT rpm poly < 0.2 ABUT<90 SINGULAR REGION EXCLUDE FALSE
}
rpmNotXmt = COPY rpm
rpm.SP.4 {
    @ rpm.SP.4: Min spacing of rpm and pwell block mask (pwbm) < 2.0
    EXT rpmNotXmt pwbm < 2.0 SINGULAR REGION EXCLUDE FALSE
}
urpm.SP.3 {
    @ urpm.SP.3: Min spacing of urpm and poly < 0.2
    EXT urpm poly < 0.2 ABUT<90 SINGULAR REGION EXCLUDE FALSE
}
rpm.OVL.3 {
    @ rpm.OVL.3: rpm must not overlap pwell block mask (pwbm)
    rpm AND pwbm
}
rpm.OVL.4 {
    @ rpm.OVL.4: rpm layer must overlap poly
    rpm NOT INTERACT polyi
}
urpm.OVL.3 {
    @ urpm.OVL.3: urpm layer must overlap poly
    urpm NOT INTERACT polyi
}


//
// PRECISION RESISTOR checks
//


prec_res.ENC.1 {
    @ prec_res.ENC.1: Enclosure of precision resistor by psdm < 0.11
    ENC (precResistor AND psdm) psdm < 0.11 MEASURE ALL ABUT < 90 SINGULAR REGION
}
precResis = polyi AND (polyres AND (rpm OR urpm))
prec_res.CON.1 {
    @ prec_res.CON.1: Precision resistor must be enclosed by psdm
    precResis NOT psdm
}
prec_res.ENC.2 {
    @ prec_res.ENC.2: Enclosure of precision resitor by npc < 0.095
    ENC (precResistor AND npc) npc < 0.095 MEASURE ALL ABUT < 90 SINGULAR REGION
}
prec_res.CON.2 {
    @ prec_res.CON.2: Precision resistor must be enclosed by npc
    precResistor NOT npc
}
prec_res.SP.1 {
    @ prec_res.SP.1: Space of precision resistor to hvntm < 0.185
    EXT precResistor hvntm < 0.185 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
prec_res.OVL.1 {
    @ prec_res.OVL.1: Precision resistor must not overlap hvntm
    precResistor AND hvntm
}


//
// LDNTM checks
//


ldntm_and_core = ldntm AND COREID
ldntm_and_core_exempt = ldntm_and_core AND exempt_tech_CD
ldntm.WID.1 {
    @ ldntm.WID.1: Min width ldntm in areaid:core < 0.7
    INT ldntm_and_core < 0.7 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
ldntm.SP.1 {
    @ ldntm.SP.1: Min space/notch of ldntm in areaid:core < 0.7
    EXT ldntm_and_core < 0.7 ABUT < 90 SINGULAR REGION
}
ldntm.ENC.1 {
    @ ldntm.ENC.1: Min enclosure of ndiff by ldntm must be < 0.18
    ENC [ndiff] ldntm_and_core < 0.18 SINGULAR MEASURE ALL ABUT < 90
}
ldntm.ENC.2 {
    @ ldntm.ENC.2: Min enclosure of N+ FET by ldntm in areaid:core < 0.125
    ENC (ngate AND ldntm_and_core) ldntm_and_core < 0.125 MEASURE ALL ABUT < 90 SINGULAR REGION
}
ldntm.OVL.1 {
    @ ldntm.OVL.1: ldntm not allowed outside of areaid:core
    (ldntm NOT ldntm_and_core) NOT exempt_tech_CD
}
ldntm.SP.2 {
    @ ldntm.SP.2: Min space between ldntm in areaid:core (exempt) and pdiff < 0.18
    EXT ldntm_and_core_exempt (diffi AND psdm) < 0.18 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}


//
// Module Cut checks
//


build_space = EXTENT CELL "*_buildspace" ORIGINAL
m1_lrg = met1 WITH WIDTH >= 3.0
m2_lrg = met2 WITH WIDTH >= 3.0
m3_lrg = met3 WITH WIDTH >= 3.0
m4_lrg = met4 WITH WIDTH >= 3.0
moduleCut.SP.1 {
    @ moduleCut.SP.1: Min spacing of areaid:moduleCut and (nwell NOT build space) < 0.635
    EXT moduleCutAREA (nwell NOT build_space) < 0.635 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.1 {
    @ moduleCut.ENC.1: Min enclosure of (nwell NOT build space) BY areaid:moduleCut < 0.635
    ENC (nwell NOT build_space) moduleCutArea < 0.635 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.2 {
    @ moduleCut.SP.2: Min spacing of areaid:moduleCut and (diff NOT build space) < 0.135
    EXT moduleCutAREA (diff NOT build_space) < 0.135 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.2 {
    @ moduleCut.ENC.2: Min enclosure of (diff NOT build space) BY areaid:moduleCut < 0.135
    ENC (diff NOT build_space) moduleCutArea < 0.135 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.3 {
    @ moduleCut.SP.3: Min spacing of areaid:moduleCut and (dnwell NOT build space) < 3.15
    EXT moduleCutAREA (dnwell NOT build_space) < 3.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.3 {
    @ moduleCut.ENC.3: Min enclosure of (dnwell NOT build space) BY areaid:moduleCut < 3.15
    ENC (dnwell NOT build_space) moduleCutArea < 3.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.4 {
    @ moduleCut.SP.4: Min spacing of areaid:moduleCut and (lvtn NOT build space) < 0.19
    EXT moduleCutAREA (lvtn NOT build_space) < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.4 {
    @ moduleCut.ENC.4: Min enclosure of (lvtn NOT build space) BY areaid:moduleCut < 0.19
    ENC (lvtn NOT build_space) moduleCutArea < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.5 {
    @ moduleCut.SP.5: Min spacing of areaid:moduleCut and (hvtp NOT build space) < 0.19
    EXT moduleCutAREA (hvtp NOT build_space) < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.5 {
    @ moduleCut.ENC.5: Min enclosure of (hvtp NOT build space) BY areaid:moduleCut < 0.19
    ENC (hvtp NOT build_space) moduleCutArea < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.6 {
    @ moduleCut.SP.6: Min spacing of areaid:moduleCut and (v5 NOT build space) < 0.35
    EXT moduleCutAREA (v5 NOT build_space) < 0.35 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.6 {
    @ moduleCut.ENC.6: Min enclosure of (v5 NOT build space) BY areaid:moduleCut < 0.35
    ENC (v5 NOT build_space) moduleCutArea < 0.35 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.7 {
    @ moduleCut.SP.7: Min spacing of areaid:moduleCut and (tunm NOT build space) < 0.25
    EXT moduleCutAREA (tunm NOT build_space) < 0.25 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.7 {
    @ moduleCut.ENC.7: Min enclosure of (tunm NOT build space) BY areaid:moduleCut < 0.25
    ENC (tunm NOT build_space) moduleCutArea < 0.25 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.8 {
    @ moduleCut.SP.8: Min spacing of areaid:moduleCut and (poly NOT build space) < 0.105
    EXT moduleCutAREA (poly NOT build_space) < 0.105 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.8 {
    @ moduleCut.ENC.8: Min enclosure of (poly NOT build space) BY areaid:moduleCut < 0.105
    ENC (poly NOT build_space) moduleCutArea < 0.105 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.9 {
    @ moduleCut.SP.9: Min spacing of areaid:moduleCut and (npc NOT build space) < 0.135
    EXT moduleCutAREA (npc NOT build_space) < 0.135 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.9 {
    @ moduleCut.ENC.9: Min enclosure of (npc NOT build space) BY areaid:moduleCut < 0.135
    ENC (npc NOT build_space) moduleCutArea < 0.135 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.10 {
    @ moduleCut.SP.10: Min spacing of areaid:moduleCut and (nsdm NOT build space) < 0.19
    EXT moduleCutAREA (nsdm NOT build_space) < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.10 {
    @ moduleCut.ENC.10: Min enclosure of (nsdm NOT build space) BY areaid:moduleCut < 0.19
    ENC (nsdm NOT build_space) moduleCutArea < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.11 {
    @ moduleCut.SP.11: Min spacing of areaid:moduleCut and (psdm NOT build space) < 0.19
    EXT moduleCutAREA (psdm NOT build_space) < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.11 {
    @ moduleCut.ENC.11: Min enclosure of (psdm NOT build space) BY areaid:moduleCut < 0.19
    ENC (psdm NOT build_space) moduleCutArea < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.12 {
    @ moduleCut.SP.12: Min spacing of areaid:moduleCut and (licon NOT build space) < 0.085
    EXT moduleCutAREA (licon NOT build_space) < 0.085 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.12 {
    @ moduleCut.ENC.12: Min enclosure of (licon NOT build space) BY areaid:moduleCut < 0.085
    ENC (licon NOT build_space) moduleCutArea < 0.085 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.13 {
    @ moduleCut.SP.13: Min spacing of areaid:moduleCut and (li NOT build space) < 0.085
    EXT moduleCutAREA (li NOT build_space) < 0.085 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.13 {
    @ moduleCut.ENC.13: Min enclosure of (li NOT build space) BY areaid:moduleCut < 0.085
    ENC (li NOT build_space) moduleCutArea < 0.085 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.14 {
    @ moduleCut.SP.14: Min spacing of areaid:moduleCut and (mcon NOT build space) < 0.095
    EXT moduleCutAREA (mcon NOT build_space) < 0.095 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.14 {
    @ moduleCut.ENC.14: Min enclosure of (mcon NOT build space) BY areaid:moduleCut < 0.095
    ENC (mcon NOT build_space) moduleCutArea < 0.095 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.15 {
    @ moduleCut.SP.15: Min spacing of areaid:moduleCut and (met1 NOT build space) < 0.07
    EXT moduleCutAREA (met1 NOT build_space) < 0.07 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.15 {
    @ moduleCut.ENC.15: Min enclosure of (met1 NOT build space) BY areaid:moduleCut < 0.07
    ENC (met1 NOT build_space) moduleCutArea < 0.07 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.16 {
    @ moduleCut.SP.16: Min spacing of areaid:moduleCut and (via1 NOT build space) < 0.085
    EXT moduleCutAREA (via1 NOT build_space) < 0.085 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.16 {
    @ moduleCut.ENC.16: Min enclosure of (via1 NOT build space) BY areaid:moduleCut < 0.085
    ENC (via1 NOT build_space) moduleCutArea < 0.085 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.17 {
    @ moduleCut.SP.17: Min spacing of areaid:moduleCut and (met2 NOT build space) < 0.07
    EXT moduleCutAREA (met2 NOT build_space) < 0.07 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.17 {
    @ moduleCut.ENC.17: Min enclosure of (met2 NOT build space) BY areaid:moduleCut < 0.07
    ENC (met2 NOT build_space) moduleCutArea < 0.07 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.18 {
    @ moduleCut.SP.18: Min spacing of areaid:moduleCut and (via2 NOT build space) < 0.1
    EXT moduleCutAREA (via2 NOT build_space) < 0.1 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.18 {
    @ moduleCut.ENC.18: Min enclosure of (via2 NOT build space) BY areaid:moduleCut < 0.1
    ENC (via2 NOT build_space) moduleCutArea < 0.1 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.19 {
    @ moduleCut.SP.19: Min spacing of areaid:moduleCut and (met3 NOT build space) < 0.15
    EXT moduleCutAREA (met3 NOT build_space) < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.19 {
    @ moduleCut.ENC.19: Min enclosure of (met3 NOT build space) BY areaid:moduleCut < 0.15
    ENC (met3 NOT build_space) moduleCutArea < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.20 {
    @ moduleCut.SP.20: Min spacing of areaid:moduleCut and (via3 NOT build space) < 0.1
    EXT moduleCutAREA (via3 NOT build_space) < 0.1 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.20 {
    @ moduleCut.ENC.20: Min enclosure of (via3 NOT build space) BY areaid:moduleCut < 0.1
    ENC (via3 NOT build_space) moduleCutArea < 0.1 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.21 {
    @ moduleCut.SP.21: Min spacing of areaid:moduleCut and (met4 NOT build space) < 0.15
    EXT moduleCutAREA (met4 NOT build_space) < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.21 {
    @ moduleCut.ENC.21: Min enclosure of (met4 NOT build space) BY areaid:moduleCut < 0.15
    ENC (met4 NOT build_space) moduleCutArea < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.22 {
    @ moduleCut.SP.22: Min spacing of areaid:moduleCut and (via4 NOT build space) < 0.4
    EXT moduleCutAREA (via4 NOT build_space) < 0.4 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.22 {
    @ moduleCut.ENC.22: Min enclosure of (via4 NOT build space) BY areaid:moduleCut < 0.4
    ENC (via4 NOT build_space) moduleCutArea < 0.4 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.23 {
    @ moduleCut.SP.23: Min spacing of areaid:moduleCut and (met5 NOT build space) < 0.8
    EXT moduleCutAREA (met5 NOT build_space) < 0.8 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.23 {
    @ moduleCut.ENC.23: Min enclosure of (met5 NOT build space) BY areaid:moduleCut < 0.8
    ENC (met5 NOT build_space) moduleCutArea < 0.8 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.24 {
    @ moduleCut.SP.24: Min spacing of areaid:moduleCut and (nsm NOT build space) < 2.0
    EXT moduleCutAREA (nsm NOT build_space) < 2.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.24 {
    @ moduleCut.ENC.24: Min enclosure of (nsm NOT build space) BY areaid:moduleCut < 2.0
    ENC (nsm NOT build_space) moduleCutArea < 2.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.25 {
    @ moduleCut.SP.25: Min spacing of areaid:moduleCut and (pad NOT build space) < 0.635
    EXT moduleCutAREA (pad NOT build_space) < 0.635 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.25 {
    @ moduleCut.ENC.25: Min enclosure of (pad NOT build space) BY areaid:moduleCut < 0.635
    ENC (pad NOT build_space) moduleCutArea < 0.635 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.26 {
    @ moduleCut.SP.26: Min spacing of areaid:moduleCut and (ldntm NOT build space) < 0.35
    EXT moduleCutAREA (ldntm NOT build_space) < 0.35 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.26 {
    @ moduleCut.ENC.26: Min enclosure of (ldntm NOT build space) BY areaid:moduleCut < 0.35
    ENC (ldntm NOT build_space) moduleCutArea < 0.35 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.27 {
    @ moduleCut.SP.27: Min spacing of areaid:moduleCut and (hvntm NOT build space) < 0.19
    EXT moduleCutAREA (hvntm NOT build_space) < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.27 {
    @ moduleCut.ENC.27: Min enclosure of (hvntm NOT build space) BY areaid:moduleCut < 0.19
    ENC (hvntm NOT build_space) moduleCutArea < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.28 {
    @ moduleCut.SP.28: Min spacing of areaid:moduleCut and (ncm NOT build space) < 0.19
    EXT moduleCutAREA (ncm NOT build_space) < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.28 {
    @ moduleCut.ENC.28: Min enclosure of (ncm NOT build space) BY areaid:moduleCut < 0.19
    ENC (ncm NOT build_space) moduleCutArea < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.29 {
    @ moduleCut.SP.29: Min spacing of areaid:moduleCut and (rdl NOT build space) < 5.0
    EXT moduleCutAREA (rdl NOT build_space) < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.29 {
    @ moduleCut.ENC.29: Min enclosure of (rdl NOT build space) BY areaid:moduleCut < 5.0
    ENC (rdl NOT build_space) moduleCutArea < 5.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.30 {
    @ moduleCut.SP.30: Min spacing of areaid:moduleCut and (hvtr NOT build space) < 0.19
    EXT moduleCutAREA (hvtr NOT build_space) < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.30 {
    @ moduleCut.ENC.30: Min enclosure of (hvtr NOT build space) BY areaid:moduleCut < 0.19
    ENC (hvtr NOT build_space) moduleCutArea < 0.19 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.31 {
    @ moduleCut.SP.31: Min spacing of areaid:moduleCut and (large met1 NOT build space) < 0.14
    EXT moduleCutAREA (m1_lrg NOT build_space) < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.31 {
    @ moduleCut.ENC.31: Min enclosure of (large met1 NOT build space) BY areaid:moduleCut < 0.14
    ENC (m1_lrg NOT build_space) moduleCutArea < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.32 {
    @ moduleCut.SP.32: Min spacing of areaid:moduleCut and (large met2 NOT build space) < 0.14
    EXT moduleCutAREA (m2_lrg NOT build_space) < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.32 {
    @ moduleCut.ENC.32: Min enclosure of (large met2 NOT build space) BY areaid:moduleCut < 0.14
    ENC (m2_lrg NOT build_space) moduleCutArea < 0.14 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.33 {
    @ moduleCut.SP.33: Min spacing of areaid:moduleCut and (large met3 NOT build space) < 0.20
    EXT moduleCutAREA (m3_lrg NOT build_space) < 0.20 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.33 {
    @ moduleCut.ENC.33: Min enclosure of (large met3 NOT build space) BY areaid:moduleCut < 0.20
    ENC (m3_lrg NOT build_space) moduleCutArea < 0.20 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.34 {
    @ moduleCut.SP.34: Min spacing of areaid:moduleCut and (large met4 NOT build space) < 0.20
    EXT moduleCutAREA (m4_lrg NOT build_space) < 0.20 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.34 {
    @ moduleCut.ENC.34: Min enclosure of (large met4 NOT build space) BY areaid:moduleCut < 0.20
    ENC (m4_lrg NOT build_space) moduleCutArea < 0.20 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.35 {
    @ moduleCut.SP.35: Min space of capm BY areaid:moduleCut < 0.42
    EXT capm moduleCutArea < 0.42 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.35 {
    @ moduleCut.ENC.35: Min enclosure of capm BY areaid:moduleCut < 0.42
    ENC capm moduleCutArea < 0.42 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.36 {
    @ moduleCut.SP.36: Min space of cap2m BY areaid:moduleCut < 0.42
    EXT cap2m moduleCutArea < 0.42 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.36 {
    @ moduleCut.ENC.36: Min enclosure of cap2m BY areaid:moduleCut < 0.42
    ENC cap2m moduleCutArea < 0.42 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.SP.37 {
    @ moduleCut.SP.37: Min spacing of areaid:moduleCut and (thkox NOT build space) < 0.35
    EXT moduleCutAREA (thkox NOT build_space) < 0.35 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
moduleCut.ENC.37 {
    @ moduleCut.ENC.37: Min enclosure of (thkox NOT build space) BY areaid:moduleCut < 0.35
    ENC (thkox NOT build_space) moduleCutArea < 0.35 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}


//
// SEALID checks
//


sealid.WID.1 {
    @ sealid.WID.1: Min width areaid:seal < 6.0
    INT SEALID < 6.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}

LAYER quad1_shape 9999
POLYGON  0.000 0.000 0.001 0.001  quad1_shape // create a dummy shape whose south and west edges abut to the x-y axis in quadrant 1
LAYER quad2_shape 9998
POLYGON -0.001 0.000 0.000 0.001  quad2_shape // create a dummy shape whose south and east edges abut to the x-y axis in quadrant 2
LAYER quad3_shape 9997
POLYGON -0.001 -0.001 0.000 0.000 quad3_shape // create a dummy shape whose north and east edges abut to the x-y axis in quadrant 3
LAYER quad4_shape 9996
POLYGON  0.000 -0.001 0.001 0.000 quad4_shape // create a dummy shape whose north and west edges abut to the x-y axis in quadrant 4
SEALIDextent = EXTENT SEALID
SEALIDextentAtOrigin = ( ( (SEALIDextent ENCLOSE quad1_shape) AND (SEALIDextent TOUCH quad2_shape) ) AND (SEALIDextent TOUCH quad4_shape) ) AND (SEALIDextent OUTSIDE quad3_shape)

seal.CON.1 {
    @ seal.CON.1: SEAL ring is not at origin (0,0)
    SEALIDextent NOT SEALIDextentAtOrigin
}


//
// SCRIBE checks
//


FRAMEPAD = pad AND (FRAMEID OR moduleCutAREA)
ETESTPAD = WITH TEXT FRAMEPAD "e-test" padText
UTESTPAD = WITH TEXT FRAMEPAD "u-test" padText
RFTESTPAD = WITH TEXT FRAMEPAD "RF" padText
EUTESTPAD = OR ETESTPAD UTESTPAD RFTESTPAD
FRAMEPADnoTXT = FRAMEPAD NOT (EUTESTPAD OR laser_targetCells)
mconOrVia = mcon OR via1
ModulecutAndEtest = moduleCutAREA AND ETESTID
dieCut150 = CONVEX EDGE dieCut == 2 WITH LENGTH >= 150.0
dieCutCorner = INTERNAL [dieCut150] <= 150.0 INTERSECTING ONLY ABUT == 90
dieCutCornerSz = EXPAND EDGE dieCutCorner INSIDE BY 0.005 CORNER FILL
dieCutCornerSzOut = EXPAND EDGE dieCutCorner OUTSIDE BY 150 CORNER FILL
scribeJunc150 = frameBndr AND (dieCutCornerSzOut NOT (INTERACT dieCut dieCutCornerSz))
realScribeLine = frameBndr NOT (INTERACT dieCut dieCutCornerSz)
scribe.CON.1 {
    @ scribe.CON.1: Wide diff within 150 um of scribe junction
    wide_diffi = WITH WIDTH diffi >= 10.0
    wide_diffi AND scribeJunc150
}
scribe.CON.2 {
    @ scribe.CON.2: Wide poly within 150 um of scribe junction
    wide_polyi = WITH WIDTH polyi >= 10.0
    wide_polyi AND scribeJunc150
}
scribe.CON.3 {
    @ scribe.CON.3: Wide li within 150 um of scribe junction
    wide_li_i = WITH WIDTH li_i >= 10.0
    wide_li_i AND scribeJunc150
}
scribe.CON.4 {
    @ scribe.CON.4: Wide met1 within 150 um of scribe junction
    wide_met1i = WITH WIDTH met1i >= 10.0
    wide_met1i AND scribeJunc150
}
scribe.CON.5 {
    @ scribe.CON.5: Wide met2 within 150 um of scribe junction
    wide_met2i = WITH WIDTH met2i >= 10.0
    wide_met2i AND scribeJunc150
}
scribe.CON.6 {
    @ scribe.CON.6: Wide met3 within 150 um of scribe junction
    wide_met3i = WITH WIDTH met3i >= 10.0
    wide_met3i AND scribeJunc150
}
scribe.CON.7 {
    @ scribe.CON.7: Wide met4 within 150 um of scribe junction
    wide_met4i = WITH WIDTH met4i >= 10.0
    wide_met4i AND scribeJunc150
}
scribe.CON.8 {
    @ scribe.CON.8: Wide met5 within 150 um of scribe junction
    wide_met5i = WITH WIDTH met5i >= 10.0
    wide_met5i AND scribeJunc150
}
scribe.CON.9 {
    @ scribe.CON.9: Wide mcon within 150 um of scribe junction
    wide_mcon = WITH WIDTH mcon >= 10.0
    wide_mcon AND scribeJunc150
}
scribe.CON.10 {
    @ scribe.CON.10: Wide licon within 150 um of scribe junction
    wide_licon = WITH WIDTH licon >= 10.0
    wide_licon AND scribeJunc150
}
scribe.CON.11 {
    @ scribe.CON.11: Wide via1 within 150 um of scribe junction
    wide_via1 = WITH WIDTH via1 >= 10.0
    wide_via1 AND scribeJunc150
}
scribe.CON.12 {
    @ scribe.CON.12: Wide via2 within 150 um of scribe junction
    wide_via2 = WITH WIDTH via2 >= 10.0
    wide_via2 AND scribeJunc150
}
scribe.CON.13 {
    @ scribe.CON.13: Wide via3 within 150 um of scribe junction
    wide_via3 = WITH WIDTH via3 >= 10.0
    wide_via3 AND scribeJunc150
}
scribe.CON.14 {
    @ scribe.CON.14: Wide via4 within 150 um of scribe junction
    wide_via4 = WITH WIDTH via4 >= 10.0
    wide_via4 AND scribeJunc150
}
scribe.CON.15 {
    @ scribe.CON.15: Wide mm1mk within 150 um of scribe junction
    wide_mm1mk = WITH WIDTH mm1mk >= 10.0
    wide_mm1mk AND scribeJunc150
}
scribe.CON.16 {
    @ scribe.CON.16: Wide mm2mk within 150 um of scribe junction
    wide_mm2mk = WITH WIDTH mm2mk >= 10.0
    wide_mm2mk AND scribeJunc150
}
scribe.CON.17 {
    @ scribe.CON.17: Wide mm3mk within 150 um of scribe junction
    wide_mm3mk = WITH WIDTH mm3mk >= 10.0
    wide_mm3mk AND scribeJunc150
}
scribe.CON.18 {
    @ scribe.CON.18: Wide p1mmk within 150 um of scribe junction
    wide_p1mmk = WITH WIDTH p1mmk >= 10.0
    wide_p1mmk AND scribeJunc150
}
scribe.CON.19 {
    @ scribe.CON.19: Wide fommk within 150 um of scribe junction
    wide_fommk = WITH WIDTH fommk >= 10.0
    wide_fommk AND scribeJunc150
}
scribe.CON.20 {
    @ scribe.CON.20: Wide ctm1mk within 150 um of scribe junction
    wide_ctm1mk = WITH WIDTH ctm1mk >= 10.0
    wide_ctm1mk AND scribeJunc150
}
scribe.CON.21 {
    @ scribe.CON.21: Wide licm1mk within 150 um of scribe junction
    wide_licm1mk = WITH WIDTH licm1mk >= 10.0
    wide_licm1mk AND scribeJunc150
}
scribe.CON.22 {
    @ scribe.CON.22: Wide li1mmk within 150 um of scribe junction
    wide_li1mmk = WITH WIDTH li1mmk >= 10.0
    wide_li1mmk AND scribeJunc150
}
scribe.CON.23 {
    @ scribe.CON.23: Wide vimmk within 150 um of scribe junction
    wide_vimmk = WITH WIDTH vimmk >= 10.0
    wide_vimmk AND scribeJunc150
}
scribe.CON.24 {
    @ scribe.CON.24: Wide vim2mk within 150 um of scribe junction
    wide_vim2mk = WITH WIDTH vim2mk >= 10.0
    wide_vim2mk AND scribeJunc150
}
scribe.CON.25 {
    @ scribe.CON.25: Wide mm4mk within 150 um of scribe junction
    wide_mm4mk = WITH WIDTH mm4mk >= 10.0
    wide_mm4mk AND scribeJunc150
}
scribe.CON.26 {
    @ scribe.CON.26: Wide mm5mk within 150 um of scribe junction
    wide_mm5mk = WITH WIDTH mm5mk >= 10.0
    wide_mm5mk AND scribeJunc150
}
scribe.CON.27 {
    @ scribe.CON.27: Wide vim3mk within 150 um of scribe junction
    wide_vim3mk = WITH WIDTH vim3mk >= 10.0
    wide_vim3mk AND scribeJunc150
}
scribe.CON.28 {
    @ scribe.CON.28: Wide vim4mk within 150 um of scribe junction
    wide_vim4mk = WITH WIDTH vim4mk >= 10.0
    wide_vim4mk AND scribeJunc150
}
scribe.WID.1 {
    @ scribe.WID.1: Min width of scribe line < 76.0
    INT realScribeLine < 76.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
padInScribe = (pad OR PDMmk) AND realScribeLine
padRing = padAreaToCheck AND pad
scribe20_xmpt = EXTENT CELL "s8Fab_*" "cys8_*"
dieCutSizeLarge = (SIZE dieCut BY 13) NOT dieCut
dieCutSizeSmall = (SIZE dieCut BY 3) NOT dieCut
padAreaToCheck = dieCutSizeLarge NOT (dieCutSizeSmall OR scribe20_xmpt)
scribe.CON.29 {
    @ scribe.CON.29: Scribe must not enclose pad scribe protect (drawing nor mask) except for etest pads, die pad rings
    padInScribe NOT (padRing OR moduleCutArea)
}


//
// CAPM checks
//


capm.CON.1 {
    @ capm.CON.1: ccapm mask should not be used
    COPY ccapm
}
capm.CON.2 {
    @ capm.CON.2: capm without met3 or met4 is prohibited
    capm NOT met3
    capm NOT met4
}
capm.CON.3 {
    @ capm.CON.3: capm without via3 is prohibited
    capm NOT INTERACT via3
}
capm.WID.1 {
    @ capm.WID.1: Min capm width < 1.0
    INT capm < 1.0 ABUT < 90 SINGULAR REGION
}
capm.SP.1 {
    @ capm.SP.1: Min capm space < 0.84
    EXT capm < 0.84 ABUT < 90 SINGULAR REGION
}
capm.SP.2 {
    @ capm.SP.2: Min space between capm bottom plates < 1.2
    a = EXTERNAL m3_bot_plate < 1.2 REGION
    b = EXTERNAL m3_bot_plate met3 < 1.2 REGION
    (a or b) INTERACT met3 > 1
    EXT m3_bot_plate < 1.2 ABUT < 90 SINGULAR REGION NOT CONNECTED
}
capm.ENC.1 {
    @ capm.ENC.1: Min enclosure of capm by met3 < 0.14
    ENC (capm AND met3) met3 < 0.14 MEASURE ALL ABUT < 90 SINGULAR REGION
}
capm.ENC.2 {
    @ capm.ENC.2: Min enclosure of via3 by capm < 0.14
    ENC (via3 AND capm) capm < 0.14 MEASURE ALL ABUT < 90 SINGULAR REGION
}
capm.SP.3 {
    @ capm.SP.3: Min spacing of capm and via3 < 0.14
    EXT capm via3 < 0.14 ABUT < 90 SINGULAR REGION
}
capm.CON.4 {
    @ capm.CON.4: Max capm aspect ratio (L/W) > 20.00
    RECTANGLE capm ASPECT > 20.00
}
capm.CON.5 {
    @ capm.CON.5: Only rectangular capm is permitted
    NOT RECTANGLE capm
}
capm.SP.4 {
    @ capm.SP.4: Min space of capm to via2 < 0.14
    EXT capm via2 < 0.14 ABUT < 90 SINGULAR REGION
}
capm.SP.5 {
    @ capm.SP.5: Min space of capm and met3 not overlapping capm < 0.5
    EXT capm (met3 NOT INTERACT capm) < 0.5 ABUT < 90 REGION MEASURE ALL
}
capm.CON.6 {
    @ capm.CON.6: capm cannot overlap via2
    capm AND via2
}
capm.AR.1 {
    @ capm.AR.1: Max area of capm > 10000000.0
    AREA capm > 10000000.0
}


//
// CAP2M checks
//


cap2m.CON.1 {
    @ cap2m.CON.1: cap2m without met4 or met5 is prohibited
    cap2m NOT met4
    cap2m NOT met5
}
cap2m.CON.2 {
    @ cap2m.CON.2: cap2m without via4 is prohibited
    cap2m NOT INTERACT via4
}
cap2m.WID.1 {
    @ cap2m.WID.1: Min cap2m width < 1.0
    INT cap2m < 1.0 ABUT < 90 SINGULAR REGION
}
cap2m.SP.1 {
    @ cap2m.SP.1: Min cap2m space < 0.84
    EXT cap2m < 0.84 ABUT < 90 SINGULAR REGION
}
cap2m.SP.2 {
    @ cap2m.SP.2: Min space between cap2m bottom plates < 1.2
    EXT m4_bot_plate < 1.2 ABUT < 90 SINGULAR REGION NOT CONNECTED
}
cap2m.ENC.1 {
    @ cap2m.ENC.1: Min enclosure of cap2m by met4 < 0.14
    ENC (cap2m AND met4) met4 < 0.14 MEASURE ALL ABUT < 90 SINGULAR REGION
}
cap2m.ENC.2 {
    @ cap2m.ENC.2: Min enclosure of via4 by ca2m < 0.20
    ENC (via4 AND cap2m) cap2m < 0.20 MEASURE ALL ABUT < 90 SINGULAR REGION
}
cap2m.SP.3 {
    @ cap2m.SP.3: Min spacing of cap2m and via4 < 0.20
    EXT cap2m via4 < 0.20 ABUT < 90 SINGULAR REGION
}
cap2m.CON.3 {
    @ cap2m.CON.3: Max cap2m aspect ratio (L/W) > 20.00
    RECTANGLE cap2m ASPECT > 20.00
}
cap2m.CON.4 {
    @ cap2m.CON.4: Only rectangular cap2m is permitted
    NOT RECTANGLE cap2m
}
cap2m.SP.4 {
    @ cap2m.SP.4: Min space of cap2m to via3 < 0.14
    EXT cap2m via3 < 0.14 ABUT < 90 SINGULAR REGION
}
cap2m.SP.5 {
    @ cap2m.SP.5: Min space of cap2m and met4 not overlapping cap2m < 0.5
    EXT cap2m (met4 NOT INTERACT cap2m) < 0.5 ABUT < 90 REGION MEASURE ALL
}
cap2m.CON.5 {
    @ cap2m.CON.5: cap2m cannot overlap via3
    cap2m AND via3
}
cap2m.AR.1 {
    @ cap2m.AR.1: Max area of cap2m is 10000000.0
    AREA cap2m > 10000000.0
}


//
// HVTPM checks
//


nw_lv = nwell NOT INTERACT (OR v5 v12 v20)
lv_nwell_peri = nw_lv NOT COREID
varac_channel = (NTAP AND poly) AND nw_lv
varac_nwell = INTERACT nwell varac_channel
lv_nwell_not_varac = nw_lv NOT varac_nwell
lv_nwell_not_varac_not_lvtn = nw_lv NOT lvtn
lv_nwell_over_varac = INTERACT nw_lv (nw_lv AND varac_channel)
lv_nwell_over_varac_and_hvtp = nw_lv AND hvtp
clhvtpm_tmp = lv_nwell_not_varac_not_lvtn OR lv_nwell_over_varac_and_hvtp
clhvtpm = clhvtpm_tmp OR chvtpm
chvtpm.WID.1 {
    @ chvtpm.WID.1: Min width of CLHVTPM < 0.38
    INT clhvtpm < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
chvtpm.SP.1 {
    @ chvtpm.SP.1: Min space/notch of CLHVTPM < 0.38
    EXT clhvtpm < 0.38 ABUT < 90 SINGULAR REGION
}
chvtpm.OVL.1 {
    @ chvtpm.OVL.1: Min enclosure of low voltage nwell not overlapping varactor channel not lvtn by CLHVTPM is 0
    lv_nwell_not_varac_not_lvtn NOT clhvtpm
}
chvtpm.OVL.2 {
    @ chvtpm.OVL.2: Min enclosure of low voltage nwell not overlapping varactor channel and hvtp by CLHVTPM is 0
    lv_nwell_over_varac_and_hvtp NOT clhvtpm
}


//
// LVTNM checks
//


nw_hvtp_core = nwell AND (hvtp OR COREID)
clvtnm_all = OR lvtn nw_hvtp_core lv_nwell_over_varac clvtnm
lvtnm_merge = EXTERNAL clvtnm_all < 0.38 PARALLEL ONLY OPPOSITE REGION
lvtnm_tmp = clvtnm_all OR lvtnm_merge
lvtnm_all = lvtnm_tmp OR clvtnm
lvtnm_peri = lvtnm_all OUTSIDE COREID
clvtnm.WID.1 {
    @ clvtnm.WID.1: Min width of clvtnm in periphery < 0.38
    INT lvtnm_peri < 0.38 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
clvtnm.SP.1 {
    @ clvtnm.SP.1: Min space/notch of clvtnm < 0.38
    EXT lvtnm_peri < 0.38 ABUT < 90 SINGULAR REGION PARALLEL OPPOSITE
}


//
// NTM checks
//


nwellTmp = COPY nwell
// jag changed as thkox is the mask layer not v5 which is only a marker:
v5_tmp = thkox NOT COREID
ldntm_tmp = COPY ldntm
ntm_tmp = NTMdg OR (nwelltmp OR (ldntm_tmp OR (v5_tmp OR (rpm OR urpm))))
ntm_merged_tmp = ntm_tmp OR (EXTERNAL ntm_tmp < 0.7 SPACE OPPOSITE PARALLEL ONLY REGION)
ntm_merged_tmp2 = ntm_merged_tmp OR (EXTERNAL ntm_merged_tmp < 0.7 NOTCH OPPOSITE PARALLEL ONLY REGION)
ntm_merged = ntm_merged_tmp2 OR (EXTERNAL ntm_merged_tmp2 < 0.7 NOTCH OPPOSITE PARALLEL ONLY REGION)
ntm_all = COPY ntm_merged
ntm_all_0 = INTERNAL ntm_all (LENGTH ntm_all <= 0.0) < 0.84 REGION OPPOSITE PARALLEL ONLY
ntm_all_1 = ntm_all NOT (ntm_all_0 OUTSIDE ntm_tmp)
ntm_all_2 = COPY ntm_all_1
ntm_all_3 = INTERNAL ntm_all_2 (LENGTH ntm_all_2 <= 0.0) < 0.84 REGION OPPOSITE PARALLEL ONLY
ntm_all_4 = ntm_all_2 NOT (ntm_all_3 OUTSIDE ntm_tmp)
ntm_all_5 = COPY ntm_all_4
clntm_tmp = COPY ntm_all_5
CLNTM = clntm_tmp OR NTMdg
cntm.WID.1 {
    @ cntm.WID.1: Min width CLNTM < 0.84
    INT CLNTM < 0.84 ABUT<90 SINGULAR REGION EXCLUDE FALSE
}
cntm.SP.1 {
    @ cntm.SP.1: Min space/notch CLNTM < 0.7
    EXT CLNTM < 0.7 ABUT<90 SINGULAR REGION
}
cntm.ENC.1 {
    @ cntm.ENC.1: Layer Nwell must be enclosed by CLNTM
    nwell NOT CLNTM
}
cntm.ENC.2 {
    @ cntm.ENC.2: thkox outside core must be enclosed by CLNTM
    (thkox NOT COREID) NOT CLNTM
}
cntm.ENC.3 {
    @ cntm.ENC.3: ldntm must be enclosed by CLNTM
    ldntm NOT CLNTM
}


//
// RDL checks
//


rdl.WID.1 {
    @ rdl.WID.1: Min width of rdl < 10.0
    INT rdl < 10.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
rdl.SP.1 {
    @ rdl.SP.1: Min space of rdl < 10.0
    EXT rdl < 10.0 REGION CORNER TO EDGE
    EXT rdl < 10.0 ABUT < 90 REGION OPPOSITE PARALLEL ONLY
}
rdl.ENC.1 {
    @ rdl.ENC.1: Min enclosure of pad by rdl (outside bump) < 10.75
    ENC (pad AND (rdl NOT INTERACT bump)) (rdl NOT INTERACT bump) < 10.75 MEASURE ALL ABUT < 90 SINGULAR REGION
}
rdl.SP.2 {
    @ rdl.SP.2: Min space of rdl to outer edge of scribe line < 15.0
    ENC rdl (OR sealRing sealHoles) < 15.0 MEASURE ALL ABUT<90 SINGULAR REGION
}
rdl.CON.1 {
    @ rdl.CON.1: rdl or ccu1m.mk must not overlap areaid.ft (frame boundary)
    ((rdl OR CU1Mmk) AND frameBndr) NOT dieCut
}
rdl.SP.3 {
    @ rdl.SP.3: Min space of rdl (outside bump) and pad < 19.66
    EXT (rdl NOT INTERACT bump) pad < 19.66 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}


//
// BUMP checks
//


bump_ctr = EXTENTS bump CENTERS 1.0
bump_pitch_400_rect = EXT bump_ctr == 399 ABUT < 90 OPPOSITE PARALLEL ONLY REGION
bump_pitch_500_rect = EXT bump_ctr == 499 ABUT < 90 OPPOSITE PARALLEL ONLY REGION
bump_small_pitch = bump INTERACT bump_pitch_400_rect
bump_large_pitch = (bump INTERACT bump_pitch_500_rect) OR (bump NOT INTERACT bump_pitch_400_rect)
ETESTPAD_x = pad WITH TEXT "etest" padText
bump.CON.1 {
    @ bump.CON.1: Bump cannot straddle areaid:ModuleCut
    bump CUT (moduleCutAREA INTERACT ETESTPAD)
}
bump.WID.1 {
    @ bump.WID.1: Min width of bump ball < 261
    INT bump < 260.5 ABUT < 90 SINGULAR PARALLEL ONLY OPPOSITE REGION
}
bump.WID.2 {
    @ bump.WID.2: Min width of bump ball for pitch > 400um is < 310
    INT bump_large_pitch < 309.5 ABUT < 90 SINGULAR PARALLEL ONLY OPPOSITE REGION
}
bump.SP.1 {
    @ bump.SP.1: Min/Max pitch spacing for bump is not 400 or 500
    bump NOT INTERACT (OR bump_pitch_400_rect bump_pitch_500_rect)
}
bump.ENC.1 {
    @ bump.ENC.1: Min enclosure of bump by scribe_line < 25.0
    ENC bump (OR SEALID sealHoles) < 25.0 ABUT < 90 REGION SINGULAR
}
bump.CON.2 {
    @ bump.CON.2: Min size of chip extent with 500um pitch bumps < 1000
    INT (sealHoles INTERACT bump_large_pitch) < 1000 ABUT < 90 REGION
}
bump.CON.3 {
    @ bump.CON.3: Max size of chip extent with 500um pitch bumps > 6800
    RECTANGLE (sealHoles INTERACT bump_large_pitch) > 6800
}
bump.CON.4 {
    @ bump.CON.4: Min size of chip extent with 400um pitch bumps < 750 BY 1000
    RECTANGLE (sealHoles INTERACT bump_small_pitch) < 750 BY < 1000
}
bump.CON.5 {
    @ bump.CON.5: Max size of chip extent with 400um pitch bumps > 6800
    RECTANGLE sealHoles > 6800
}
bump.CON.6 {
    @ bump.CON.6: Chip can contain only 400 pitch or 500 pitch bumps but not both
    (sealHoles INTERACT bump_small_pitch) AND (sealHoles INTERACT bump_large_pitch)
}


//
// UBM checks
//


ubm.CON.1 {
    @ ubm.CON.1: ubm drawn layer cannot straddle areaid:ModuleCut layer
    ubm CUT (moduleCutAREA INTERACT ETESTPAD)
}
ubm.WID.1 {
    @ ubm.WID.1: Min width of ubm on 400 pitch balls (parallel opposite edges) < 215.0
    INT (ubm AND bump_small_pitch) < 215.0 PARALLEL ONLY OPPOSITE
}
ubm.WID.2 {
    @ ubm.WID.2: Min width of ubm on 500 pitch balls (parallel opposite edges) < 250.0
    INT (ubm AND bump_large_pitch) < 250.0 PARALLEL ONLY OPPOSITE
}
ubm.ENC.1 {
    @ ubm.ENC.1: Min enclosure ubm by rdl < 10.0
    ENC ubm rdl < 9.95 ABUT < 90 REGION SINGULAR
}
ubm.CON.2 {
    @ ubm.CON.2: ubm must be inside RDL
    ubm NOT rdl
}
ubm_ctr = EXTENTS UBM CENTERS 1
ubm.SP.1 {
    @ ubm.SP.1: Min space between center of 400 pitch UBM to scribe_line < 155.0
    ENC (ubm_ctr AND bump_small_pitch) (sealHoles OR SEALID) <  154.5 ABUT < 90 REGION SINGULAR
}
ubm.SP.2 {
    @ ubm.SP.2: Min space between center of 500 pitch UBM to scribe_line < 195.0
    ENC (ubm_ctr AND bump_large_pitch) (sealHoles OR SEALID) <  194.5 ABUT < 90 REGION SINGULAR
}


//
// pwbm checks
//


pwbm_v20 = pwbm AND v20
pwbm_holes = HOLES pwbm_v20
pwbm_or_pwbm_holes = pwbm_v20 OR pwbm_holes
pwbm.WID.1 {
    @ pwbm.WID.1: Min width of pwbm < 0.84
    INT pwbm < 0.84 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
pwbm.SP.1 {
    @ pwbm.SP.1: Min space/notch of pwbm inside v20 < 1.27
    EXT pwbm_v20 < 1.27 ABUT < 90 SINGULAR REGION
}
pwbm.ENC.1 {
    @ pwbm.ENC.1: (dnwell inside v20) must be enclosed by pwbm (exempt for pwbm holes inside dnwell)
    (dnwell and v20) NOT pwbm_or_pwbm_holes
}
pwbm.SP.2 {
    @ pwbm.SP.2: Min spacing of pwbm holes inside v20 < 0.84
    EXT (pwbm_holes AND v20) < 0.84 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
pwbm.ENC.2 {
    @ pwbm.ENC.2: Min enclosure of dnwell inside v20 by pwbm (exempt for pwbm holes inside dnwell) >= 0
    (dnwell AND v20) NOT pwbm_or_pwbm_holes
}


//
// pwde checks
//


pwde_v20 = pwde AND v20
pwde_uhvi_samenet = EXTERNAL pwde_v20 < 1.27 ABUT < 90 SINGULAR REGION CONNECTED
pwde.WID.1 {
    @ pwde.WID.1: Min width of pwde < 0.84
    INT pwde < 0.84 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
pwde.SP.1 {
    @ pwde.SP.1: Min space of 20v pwde < 1.27
    EXT pwde_v20 < 1.27 ABUT < 90 SINGULAR REGION CONNECTED EXCLUDE FALSE
}
pwde.ENC.1 {
    @ pwde.ENC.1: Layer pwde must be enclosed by v20
    pwde NOT v20
}
pwde.ENC.2 {
    @ pwde.ENC.2: Layer pwde must be enclosed by pwbm >= 0
    pwde NOT pwbm
}
pwde.ENC.3 {
    @ pwde.ENC.3: Layer pwde must be enclosed by dnwell
    pwde NOT dnwell
}
pwde.ENC.4 {
    @ pwde.ENC.4: Layer pwde enclosure by dnwell in v20 < 1.0
    ENC pwde_v20 dnwell_v20 < 1.0 MEASURE ALL ABUT < 90 SINGULAR REGION
}


//
// nikon checks
//


nikon.cfom.CON.1 {
    @ nikon.cfom.CON.1: FOMmk in the nikon cross has the wrong polarity
    FOMmk_and_seal = FOMmk AND SEALID
    DONUT FOMmk_and_seal
}
nikon.cfom.CON.2 {
    @ nikon.cfom.CON.2: FOMmk is missing from the nikon cross in the layout
    INTERACT SEALID FOMmk != 4
}
nikon.cdnm.CON.1 {
    @ nikon.cdnm.CON.1: DNMmk in the nikon cross has the wrong polarity
    DNMmk_and_seal = DNMmk AND SEALID
    DNMmk_and_seal NOT (DONUT DNMmk_and_seal)
}
nikon.cdnm.CON.2 {
    @ nikon.cdnm.CON.2: DNMmk is missing from the nikon cross in the layout
    INTERACT SEALID DNMmk != 4
}
nikon.cnwm.CON.1 {
    @ nikon.cnwm.CON.1: NWMmk in the nikon cross has the wrong polarity
    NWMmk_and_seal = NWMmk AND SEALID
    DONUT NWMmk_and_seal
}
nikon.cnwm.CON.2 {
    @ nikon.cnwm.CON.2: NWMmk is missing from the nikon cross in the layout
    INTERACT SEALID NWMmk != 4
}
nikon.chvtpm.CON.1 {
    @ nikon.chvtpm.CON.1: HVTPMmk in the nikon cross has the wrong polarity
    HVTPMmk_and_seal = HVTPMmk AND SEALID
    DONUT HVTPMmk_and_seal
}
nikon.chvtpm.CON.2 {
    @ nikon.chvtpm.CON.2: HVTPMmk is missing from the nikon cross in the layout
    INTERACT SEALID HVTPMmk != 4
}
nikon.clvtnm.CON.1 {
    @ nikon.clvtnm.CON.1: LVTNMmk in the nikon cross has the wrong polarity
    LVTNMmk_and_seal = LVTNMmk AND SEALID
    LVTNMmk_and_seal NOT (DONUT LVTNMmk_and_seal)
}
nikon.clvtnm.CON.2 {
    @ nikon.clvtnm.CON.2: LVTNMmk is missing from the nikon cross in the layout
    INTERACT SEALID LVTNMmk != 4
}
nikon.clvom.CON.1 {
    @ nikon.clvom.CON.1: LVOMmk in the nikon cross has the wrong polarity
    LVOMmk_and_seal = LVOMmk AND SEALID
    DONUT LVOMmk_and_seal
}
nikon.clvom.CON.2 {
    @ nikon.clvom.CON.2: LVOMmk is missing from the nikon cross in the layout
    INTERACT SEALID LVOMmk != 4
}
nikon.cp1m.CON.1 {
    @ nikon.cp1m.CON.1: P1Mmk in the nikon cross has the wrong polarity
    P1Mmk_and_seal = P1Mmk AND SEALID
    DONUT P1Mmk_and_seal
}
nikon.cp1m.CON.2 {
    @ nikon.cp1m.CON.2: P1Mmk is missing from the nikon cross in the layout
    INTERACT SEALID P1Mmk != 4
}
nikon.cntm.CON.1 {
    @ nikon.cntm.CON.1: NTMmk in the nikon cross has the wrong polarity
    NTMmk_and_seal = NTMmk AND SEALID
    DONUT NTMmk_and_seal
}
nikon.cntm.CON.2 {
    @ nikon.cntm.CON.2: NTMmk is missing from the nikon cross in the layout
    INTERACT SEALID NTMmk != 4
}
nikon.chvntm.CON.1 {
    @ nikon.chvntm.CON.1: HVNTMmk in the nikon cross has the wrong polarity
    HVNTMmk_and_seal = HVNTMmk AND SEALID
    HVNTMmk_and_seal NOT (DONUT HVNTMmk_and_seal)
}
nikon.chvntm.CON.2 {
    @ nikon.chvntm.CON.2: HVNTMmk is missing from the nikon cross in the layout
    INTERACT SEALID HVNTMmk != 4
}
nikon.cldntm.CON.1 {
    @ nikon.cldntm.CON.1: LDNTMmk in the nikon cross has the wrong polarity
    LDNTMmk_and_seal = LDNTMmk AND SEALID
    LDNTMmk_and_seal NOT (DONUT LDNTMmk_and_seal)
}
nikon.cldntm.CON.2 {
    @ nikon.cldntm.CON.2: LDNTMmk is missing from the nikon cross in the layout
    INTERACT SEALID LDNTMmk != 4
}
nikon.cnpc.CON.1 {
    @ nikon.cnpc.CON.1: NPCMmk in the nikon cross has the wrong polarity
    NPCMmk_and_seal = NPCMmk AND SEALID
    NPCMmk_and_seal NOT (DONUT NPCMmk_and_seal)
}
nikon.cnpc.CON.2 {
    @ nikon.cnpc.CON.2: NPCMmk is missing from the nikon cross in the layout
    INTERACT SEALID NPCMmk != 4
}
nikon.cnsdm.CON.1 {
    @ nikon.cnsdm.CON.1: NSDMmk in the nikon cross has the wrong polarity
    NSDMmk_and_seal = NSDMmk AND SEALID
    DONUT NSDMmk_and_seal
}
nikon.cnsdm.CON.2 {
    @ nikon.cnsdm.CON.2: NSDMmk is missing from the nikon cross in the layout
    INTERACT SEALID NSDMmk != 4
}
nikon.cpsdm.CON.1 {
    @ nikon.cpsdm.CON.1: PSDMmk in the nikon cross has the wrong polarity
    PSDMmk_and_seal = PSDMmk AND SEALID
    DONUT PSDMmk_and_seal
}
nikon.cpsdm.CON.2 {
    @ nikon.cpsdm.CON.2: PSDMmk is missing from the nikon cross in the layout
    INTERACT SEALID PSDMmk != 4
}
nikon.clicm1.CON.1 {
    @ nikon.clicm1.CON.1: LICM1mk in the nikon cross has the wrong polarity
    LICM1mk_and_seal = LICM1mk AND SEALID
    DONUT LICM1mk_and_seal
}
nikon.clicm1.CON.2 {
    @ nikon.clicm1.CON.2: LICM1mk is missing from the nikon cross in the layout
    INTERACT SEALID LICM1mk != 4
}
nikon.cli1m.CON.1 {
    @ nikon.cli1m.CON.1: LI1Mmk in the nikon cross has the wrong polarity
    LI1Mmk_and_seal = LI1Mmk AND SEALID
    DONUT LI1Mmk_and_seal
}
nikon.cli1m.CON.2 {
    @ nikon.cli1m.CON.2: LI1Mmk is missing from the nikon cross in the layout
    INTERACT SEALID LI1Mmk != 4
}
nikon.cctm1.CON.1 {
    @ nikon.cctm1.CON.1: CTM1mk in the nikon cross has the wrong polarity
    CTM1mk_and_seal = CTM1mk AND SEALID
    DONUT CTM1mk_and_seal
}
nikon.cctm1.CON.2 {
    @ nikon.cctm1.CON.2: CTM1mk is missing from the nikon cross in the layout
    INTERACT SEALID CTM1mk != 4
}
nikon.cmm1.CON.1 {
    @ nikon.cmm1.CON.1: MM1mk in the nikon cross has the wrong polarity
    MM1mk_and_seal = MM1mk AND SEALID
    DONUT MM1mk_and_seal
}
nikon.cmm1.CON.2 {
    @ nikon.cmm1.CON.2: MM1mk is missing from the nikon cross in the layout
    INTERACT SEALID MM1mk != 4
}
nikon.cviam.CON.1 {
    @ nikon.cviam.CON.1: VIMmk in the nikon cross has the wrong polarity
    VIMmk_and_seal = VIMmk AND SEALID
    DONUT VIMmk_and_seal
}
nikon.cviam.CON.2 {
    @ nikon.cviam.CON.2: VIMmk is missing from the nikon cross in the layout
    INTERACT SEALID VIMmk != 4
}
nikon.cmm2.CON.1 {
    @ nikon.cmm2.CON.1: MM2mk in the nikon cross has the wrong polarity
    MM2mk_and_seal = MM2mk AND SEALID
    DONUT MM2mk_and_seal
}
nikon.cmm2.CON.2 {
    @ nikon.cmm2.CON.2: MM2mk is missing from the nikon cross in the layout
    INTERACT SEALID MM2mk != 4
}
nikon.cnsm.CON.1 {
    @ nikon.cnsm.CON.1: NSMmk in the nikon cross has the wrong polarity
    NSMmk_and_seal = NSMmk AND SEALID
    DONUT NSMmk_and_seal
}
nikon.cnsm.CON.2 {
    @ nikon.cnsm.CON.2: NSMmk is missing from the nikon cross in the layout
    INTERACT SEALID NSMmk != 4
}
nikon.cpdm.CON.1 {
    @ nikon.cpdm.CON.1: PDMmk in the nikon cross has the wrong polarity
    PDMmk_and_seal = PDMmk AND SEALID
    PDMmk_and_seal NOT (DONUT PDMmk_and_seal)
}
nikon.cpdm.CON.2 {
    @ nikon.cpdm.CON.2: PDMmk is missing from the nikon cross in the layout
    INTERACT SEALID PDMmk != 4
}
nikon.cviam2.CON.1 {
    @ nikon.cviam2.CON.1: VIM2mk in the nikon cross has the wrong polarity
    VIM2mk_and_seal = VIM2mk AND SEALID
    DONUT VIM2mk_and_seal
}
nikon.cviam2.CON.2 {
    @ nikon.cviam2.CON.2: VIM2mk is missing from the nikon cross in the layout
    INTERACT SEALID VIM2mk != 4
}
nikon.cmm3.CON.1 {
    @ nikon.cmm3.CON.1: MM3mk in the nikon cross has the wrong polarity
    MM3mk_and_seal = MM3mk AND SEALID
    DONUT MM3mk_and_seal
}
nikon.cmm3.CON.2 {
    @ nikon.cmm3.CON.2: MM3mk is missing from the nikon cross in the layout
    INTERACT SEALID MM3mk != 4
}
nikon.cviam3.CON.1 {
    @ nikon.cviam3.CON.1: VIM3mk in the nikon cross has the wrong polarity
    VIM3mk_and_seal = VIM3mk AND SEALID
    DONUT VIM3mk_and_seal
}
nikon.cviam3.CON.2 {
    @ nikon.cviam3.CON.2: VIM3mk is missing from the nikon cross in the layout
    INTERACT SEALID VIM3mk != 4
}
nikon.cmm4.CON.1 {
    @ nikon.cmm4.CON.1: MM4mk in the nikon cross has the wrong polarity
    MM4mk_and_seal = MM4mk AND SEALID
    DONUT MM4mk_and_seal
}
nikon.cmm4.CON.2 {
    @ nikon.cmm4.CON.2: MM4mk is missing from the nikon cross in the layout
    INTERACT SEALID MM4mk != 4
}
nikon.cviam4.CON.1 {
    @ nikon.cviam4.CON.1: VIM4mk in the nikon cross has the wrong polarity
    VIM4mk_and_seal = VIM4mk AND SEALID
    DONUT VIM4mk_and_seal
}
nikon.cviam4.CON.2 {
    @ nikon.cviam4.CON.2: VIM4mk is missing from the nikon cross in the layout
    INTERACT SEALID VIM4mk != 4
}
nikon.cmm5.CON.1 {
    @ nikon.cmm5.CON.1: MM5mk in the nikon cross has the wrong polarity
    MM5mk_and_seal = MM5mk AND SEALID
    DONUT MM5mk_and_seal
}
nikon.cmm5.CON.2 {
    @ nikon.cmm5.CON.2: MM5mk is missing from the nikon cross in the layout
    INTERACT SEALID MM5mk != 4
}
nikon.crpm.CON.1 {
    @ nikon.crpm.CON.1: RPMmk in the nikon cross has the wrong polarity
    RPMmk_and_seal = RPMmk AND SEALID
    DONUT RPMmk_and_seal
}
nikon.crpm.CON.2 {
    @ nikon.crpm.CON.2: RPMmk is missing from the nikon cross in the layout
    INTERACT SEALID RPMmk != 4
}
nikon.CON.3 {
    @ nikon.CON.3: Nikon cross cannot be placed outside areaid:seal
    nikon_cross NOT SEALID
}


//
// fuse checks
//


fuse.CON.1 {
    @ fuse.CON.1: Use of the met4/fuse layer is prohibited - contact SkyWater Technology for additional information
    COPY fuse
}
target.CON.1 {
    @ target.CON.1: Use of the fuse target layer is prohibited - contact SkyWater Technology for additional information
    COPY target
}


//
// thkox checks
//


thkox.WID.1 {
    @ thkox.WID.1: Min width of thkox outside areaid:core < 0.6
    INT (thkox NOT COREID) < 0.6 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
thkox.WID.2 {
    @ thkox.WID.2: Min width of diff inside thkox in areaid:CORE < 0.15
    INTERNAL ((diffi AND thkox) AND COREID) < 0.15 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
thkox.SP.1 {
    @ thkox.SP.1: Min space/notch of thkox in periphery < 0.7
    EXT (thkox NOT COREID) < 0.7 ABUT < 90 SINGULAR REGION
}
thkox.OVL.1 {
    @ thkox.OVL.1: Layer thkox must not overlap layer tunm
    thkox AND tunm
}
thkox.SP.2 {
    @ thkox.SP.2: Min spacing of non-butting thkox and nwell < 0.7
    non_coin_thkox_nwell_edges = thkox NOT COINCIDENT EDGE nwell
    EXT non_coin_thkox_nwell_edges nwell < 0.7 ABUT < 90 REGION EXCLUDE FALSE
}
nw_v20 = nwell INTERACT (nwell AND v20)
nw_not_v20 = nwell NOT nw_v20
nw_v12 = nw_not_v20 INTERACT (nw_not_v20 AND v12)
nw_not_v12_or_v12 = nwell NOT (OR nw_v20 nw_v12)
nw_v5 = nwell INTERACT (nw_not_v12_or_v12 and v5)
nw_nom = nwell NOT (OR nw_v20 nw_v12 nw_v5)

// build the 5 volt network starting with v5 markers which can be over nw, diff, ptub, or poly,

   nsd_v5 = nsd AND v5
   psd_v5 = psd AND v5
   poly_v5 = poly AND v5
   ptub_v5 = ptub AND v5

// nets connect to v5 nwell
   v5_net_1a = NET AREA RATIO nwell nw_v5 > 0
   v5_net_1b = NET AREA RATIO pwell nw_v5 > 0
   v5_net_1c = NET AREA RATIO ptub nw_v5 > 0
   v5_net_1d = NET AREA RATIO nsd nw_v5 > 0
   v5_net_1e = NET AREA RATIO psd nw_v5 > 0
   v5_net_1f = NET AREA RATIO poly nw_v5 > 0
   v5_net_1g = NET AREA RATIO li nw_v5 > 0
   v5_net_1h = NET AREA RATIO met1 nw_v5 > 0
   v5_net_1i = NET AREA RATIO met2 nw_v5 > 0
   v5_net_1j = NET AREA RATIO met3 nw_v5 > 0
   v5_net_1k = NET AREA RATIO met4 nw_v5 > 0
   v5_net_1l = NET AREA RATIO met5 nw_v5 > 0
   v5_net_1 = OR v5_net_1a v5_net_1b v5_net_1c v5_net_1d v5_net_1e v5_net_1f v5_net_1g v5_net_1h v5_net_1i v5_net_1j v5_net_1k v5_net_1l

// nets connect to v5 nsd
   v5_net_2a = NET AREA RATIO nwell nsd_v5 > 0
   v5_net_2b = NET AREA RATIO pwell nsd_v5 > 0
   v5_net_2c = NET AREA RATIO ptub nsd_v5 > 0
   v5_net_2d = NET AREA RATIO nsd nsd_v5 > 0
   v5_net_2e = NET AREA RATIO psd nsd_v5 > 0
   v5_net_2f = NET AREA RATIO poly nsd_v5 > 0
   v5_net_2g = NET AREA RATIO li nsd_v5 > 0
   v5_net_2h = NET AREA RATIO met1 nsd_v5 > 0
   v5_net_2i = NET AREA RATIO met2 nsd_v5 > 0
   v5_net_2j = NET AREA RATIO met3 nsd_v5 > 0
   v5_net_2k = NET AREA RATIO met4 nsd_v5 > 0
   v5_net_2l = NET AREA RATIO met5 nsd_v5 > 0
   v5_net_2 = OR v5_net_2a v5_net_2b v5_net_2c v5_net_2d v5_net_2e v5_net_2f v5_net_2g v5_net_2h v5_net_2i v5_net_2j v5_net_2k v5_net_2l

// nets connect to v5 psd
   v5_net_3a = NET AREA RATIO nwell psd_v5 > 0
   v5_net_3b = NET AREA RATIO pwell psd_v5 > 0
   v5_net_3c = NET AREA RATIO ptub psd_v5 > 0
   v5_net_3d = NET AREA RATIO nsd psd_v5 > 0
   v5_net_3e = NET AREA RATIO psd psd_v5 > 0
   v5_net_3f = NET AREA RATIO poly psd_v5 > 0
   v5_net_3g = NET AREA RATIO li psd_v5 > 0
   v5_net_3h = NET AREA RATIO met1 psd_v5 > 0
   v5_net_3i = NET AREA RATIO met2 psd_v5 > 0
   v5_net_3j = NET AREA RATIO met3 psd_v5 > 0
   v5_net_3k = NET AREA RATIO met4 psd_v5 > 0
   v5_net_3l = NET AREA RATIO met5 psd_v5 > 0
   v5_net_3 = OR v5_net_3a v5_net_3b v5_net_3c v5_net_3d v5_net_3e v5_net_3f v5_net_3g v5_net_3h v5_net_3i v5_net_3j v5_net_3k v5_net_3l

// nets connect to v5 poly
   v5_net_4a = NET AREA RATIO nwell poly_v5 > 0
   v5_net_4b = NET AREA RATIO pwell poly_v5 > 0
   v5_net_4c = NET AREA RATIO ptub poly_v5 > 0
   v5_net_4d = NET AREA RATIO nsd poly_v5 > 0
   v5_net_4e = NET AREA RATIO psd poly_v5 > 0
   v5_net_4f = NET AREA RATIO poly poly_v5 > 0
   v5_net_4g = NET AREA RATIO li poly_v5 > 0
   v5_net_4h = NET AREA RATIO met1 poly_v5 > 0
   v5_net_4i = NET AREA RATIO met2 poly_v5 > 0
   v5_net_4j = NET AREA RATIO met3 poly_v5 > 0
   v5_net_4k = NET AREA RATIO met4 poly_v5 > 0
   v5_net_4l = NET AREA RATIO met5 poly_v5 > 0
   v5_net_4 = OR v5_net_4a v5_net_4b v5_net_4c v5_net_4d v5_net_4e v5_net_4f v5_net_4g v5_net_4h v5_net_4i v5_net_4j v5_net_4k v5_net_4l

// nets connect to v5 ptub
   v5_net_5a = NET AREA RATIO nwell ptub_v5 > 0
   v5_net_5b = NET AREA RATIO pwell ptub_v5 > 0
   v5_net_5c = NET AREA RATIO ptub ptub_v5 > 0
   v5_net_5d = NET AREA RATIO nsd ptub_v5 > 0
   v5_net_5e = NET AREA RATIO psd ptub_v5 > 0
   v5_net_5f = NET AREA RATIO poly ptub_v5 > 0
   v5_net_5g = NET AREA RATIO li ptub_v5 > 0
   v5_net_5h = NET AREA RATIO met1 ptub_v5 > 0
   v5_net_5i = NET AREA RATIO met2 ptub_v5 > 0
   v5_net_5j = NET AREA RATIO met3 ptub_v5 > 0
   v5_net_5k = NET AREA RATIO met4 ptub_v5 > 0
   v5_net_5l = NET AREA RATIO met5 ptub_v5 > 0
   v5_net_5 = OR v5_net_5a v5_net_5b v5_net_5c v5_net_5d v5_net_5e v5_net_5f v5_net_5g v5_net_5h v5_net_5i v5_net_5j v5_net_5k v5_net_5l

v5_net = OR v5_net_1 v5_net_2 v5_net_3 v5_net_4 v5_net_5
   

sd_not_de = ((nsd OR psd) NOT ENID) NOT v5
sd_v5 = v5_net_2 OR v5_net_3
v5.WID.1 {
    @ v5.WID.1: Min width of v5 < 0.02
    INT v5 < 0.02 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
v5.OVL.1 {
    @ v5.OVL.1: Layer v5 must not overlap areaid:core
    v5 INTERACT (v5 AND COREID)
}
v5.OVL.2 {
    @ v5.OVL.2: Gate inside v5 must overlap thkox
    (((poly and diff) NOT (npn and v5)) INTERACT v5) NOT thkox
}
v5.OVL.4 {
    @ v5.OVL.4: Layer v5 must not straddle v5 src/drn
    (sd_v5 AND diff) CUT v5
}
v5.OVL.5 {
    @ v5.OVL.5: Layer v5 must not straddle v5 gate
    ((poly AND diff) INTERACT v5) CUT v5
}
v5.OVL.6 {
    @ v5.OVL.6: V5 must not straddle nwell
    v5 INSIDE EDGE nwell
}
v5.CON.9 {
    @ v5.CON.9: v5 over diff must overlap thkox
    (v5 AND diffi) NOT thkox
}


//
// V12 checks
//


// build the 12 v network starting with v12 markers which can be over nw, diff, ptub, or poly
   nsd_v12 = nsd AND v12
   psd_v12 = psd AND v12
   poly_v12 = poly AND v12
   ptub_v12 = ptub AND v12

   v12_net_1a = NET AREA RATIO nwell nw_v12 > 0
   v12_net_1b = NET AREA RATIO pwell nw_v12 > 0
   v12_net_1c = NET AREA RATIO ptub nw_v12 > 0
   v12_net_1d = NET AREA RATIO nsd nw_v12 > 0
   v12_net_1e = NET AREA RATIO psd nw_v12 > 0
   v12_net_1f = NET AREA RATIO poly nw_v12 > 0
   v12_net_1g = NET AREA RATIO li nw_v12 > 0
   v12_net_1h = NET AREA RATIO met1 nw_v12 > 0
   v12_net_1i = NET AREA RATIO met2 nw_v12 > 0
   v12_net_1j = NET AREA RATIO met3 nw_v12 > 0
   v12_net_1k = NET AREA RATIO met4 nw_v12 > 0
   v12_net_1l = NET AREA RATIO met5 nw_v12 > 0
   v12_net_1 = OR v12_net_1a v12_net_1b v12_net_1c v12_net_1d v12_net_1e v12_net_1f v12_net_1g v12_net_1h v12_net_1i v12_net_1j v12_net_1k v12_net_1l

   v12_net_2a = NET AREA RATIO nwell nsd_v12 > 0
   v12_net_2b = NET AREA RATIO pwell nsd_v12 > 0
   v12_net_2c = NET AREA RATIO ptub nsd_v12 > 0
   v12_net_2d = NET AREA RATIO nsd nsd_v12 > 0
   v12_net_2e = NET AREA RATIO psd nsd_v12 > 0
   v12_net_2f = NET AREA RATIO poly nsd_v12 > 0
   v12_net_2g = NET AREA RATIO li nsd_v12 > 0
   v12_net_2h = NET AREA RATIO met1 nsd_v12 > 0
   v12_net_2i = NET AREA RATIO met2 nsd_v12 > 0
   v12_net_2j = NET AREA RATIO met3 nsd_v12 > 0
   v12_net_2k = NET AREA RATIO met4 nsd_v12 > 0
   v12_net_2l = NET AREA RATIO met5 nsd_v12 > 0
   v12_net_2 = OR v12_net_2a v12_net_2b v12_net_2c v12_net_2d v12_net_2e v12_net_2f v12_net_2g v12_net_2h v12_net_2i v12_net_2j v12_net_2k v12_net_2l

   v12_net_3a = NET AREA RATIO nwell psd_v12 > 0
   v12_net_3b = NET AREA RATIO pwell psd_v12 > 0
   v12_net_3c = NET AREA RATIO ptub psd_v12 > 0
   v12_net_3d = NET AREA RATIO nsd psd_v12 > 0
   v12_net_3e = NET AREA RATIO psd psd_v12 > 0
   v12_net_3f = NET AREA RATIO poly psd_v12 > 0
   v12_net_3g = NET AREA RATIO li psd_v12 > 0
   v12_net_3h = NET AREA RATIO met1 psd_v12 > 0
   v12_net_3i = NET AREA RATIO met2 psd_v12 > 0
   v12_net_3j = NET AREA RATIO met3 psd_v12 > 0
   v12_net_3k = NET AREA RATIO met4 psd_v12 > 0
   v12_net_3l = NET AREA RATIO met5 psd_v12 > 0
   v12_net_3 = OR v12_net_3a v12_net_3b v12_net_3c v12_net_3d v12_net_3e v12_net_3f v12_net_3g v12_net_3h v12_net_3i v12_net_3j v12_net_3k v12_net_3l

   v12_net_4a = NET AREA RATIO nwell poly_v12 > 0
   v12_net_4b = NET AREA RATIO pwell poly_v12 > 0
   v12_net_4c = NET AREA RATIO ptub poly_v12 > 0
   v12_net_4d = NET AREA RATIO nsd poly_v12 > 0
   v12_net_4e = NET AREA RATIO psd poly_v12 > 0
   v12_net_4f = NET AREA RATIO poly poly_v12 > 0
   v12_net_4g = NET AREA RATIO li poly_v12 > 0
   v12_net_4h = NET AREA RATIO met1 poly_v12 > 0
   v12_net_4i = NET AREA RATIO met2 poly_v12 > 0
   v12_net_4j = NET AREA RATIO met3 poly_v12 > 0
   v12_net_4k = NET AREA RATIO met4 poly_v12 > 0
   v12_net_4l = NET AREA RATIO met5 poly_v12 > 0
   v12_net_4 = OR v12_net_4a v12_net_4b v12_net_4c v12_net_4d v12_net_4e v12_net_4f v12_net_4g v12_net_4h v12_net_4i v12_net_4j v12_net_4k v12_net_4l

   v12_net_5a = NET AREA RATIO nwell ptub_v12 > 0
   v12_net_5b = NET AREA RATIO pwell ptub_v12 > 0
   v12_net_5c = NET AREA RATIO ptub ptub_v12 > 0
   v12_net_5d = NET AREA RATIO nsd ptub_v12 > 0
   v12_net_5e = NET AREA RATIO psd ptub_v12 > 0
   v12_net_5f = NET AREA RATIO poly ptub_v12 > 0
   v12_net_5g = NET AREA RATIO li ptub_v12 > 0
   v12_net_5h = NET AREA RATIO met1 ptub_v12 > 0
   v12_net_5i = NET AREA RATIO met2 ptub_v12 > 0
   v12_net_5j = NET AREA RATIO met3 ptub_v12 > 0
   v12_net_5k = NET AREA RATIO met4 ptub_v12 > 0
   v12_net_5l = NET AREA RATIO met5 ptub_v12 > 0
   v12_net_5 = OR v12_net_5a v12_net_5b v12_net_5c v12_net_5d v12_net_5e v12_net_5f v12_net_5g v12_net_5h v12_net_5i v12_net_5j v12_net_5k v12_net_5l


sd_v12 = v12_net_2 OR v12_net_3
v12.CON.1 {
    @ v12.CON.1: diff outside areaid:extendedDrain must not be connected to src/drn inside v12
    sd_not_de AND ((sd_v12 AND li) AND licon)
}
v12.WID.1 {
    @ v12.WID.1: Min width of v12 < 0.02
    INT v12 < 0.02 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
v12.OVL.1 {
    @ v12.OVL.1: Layer v12 must not overlap areaid:core
    v12 INTERACT (v12 AND COREID)
}
v12.OVL.2 {
    @ v12.OVL.2: A v12 gate must overlap thkox
    ((poly and diff) INTERACT v12) NOT thkox
}
v12.OVL.3 {
    @ v12.OVL.3: Poly connected to same net as a v12 source/drain must be overlapped by v12
    ((v12_net_3f OR v12_net_2f) AND (poly NOT INTERACT polyres)) NOT INTERACT v12
}
v12.OVL.4 {
    @ v12.OVL.5: Layer v12 must not straddle v12 src/drn (except in V12 extended drain devices)
    (v12 NOT ENID) CUT (sd_v12 AND (nsd OR psd))
}
v12.OVL.5 {
    @ v12.OVL.6: Layer v12 overlapping v12 src/drn must not overlap poly (except in V12 extended drain devices)
    ((v12 NOT ENID) INTERACT sd_v12) AND poly
}
v12.OVL.6 {
    @ v12.OVL.7: Layer v12 must not straddle v12 poly (except in V12 extended drain devices)
    (v12 NOT INTERACT ENID) CUT ((polyi NOT INSIDE v12) INTERACT v12)
}
v12.CON.6 {
    @ v12.CON.6: v12 must not overlap v20
    v12 AND v20
}
v12.CON.9 {
    @ v12.CON.9: v12 over diff must overlap thkox
    (v12 AND diffi) NOT thkox
}


//
// v20 checks
//


// build the 20 v network starting with v20 markers which can be over nw, diff, ptub or poly
   nsd_v20 = nsd AND v20
   psd_v20 = psd AND v20
   poly_v20 = poly AND v20
   ptub_v20 = ptub AND v20

   v20_net_1a = NET AREA RATIO nwell nw_v20 > 0
   v20_net_1b = NET AREA RATIO pwell nw_v20 > 0
   v20_net_1c = NET AREA RATIO ptub nw_v20 > 0
   v20_net_1d = NET AREA RATIO nsd nw_v20 > 0
   v20_net_1e = NET AREA RATIO psd nw_v20 > 0
   v20_net_1f = NET AREA RATIO poly nw_v20 > 0
   v20_net_1g = NET AREA RATIO li nw_v20 > 0
   v20_net_1h = NET AREA RATIO met1 nw_v20 > 0
   v20_net_1i = NET AREA RATIO met2 nw_v20 > 0
   v20_net_1j = NET AREA RATIO met3 nw_v20 > 0
   v20_net_1k = NET AREA RATIO met4 nw_v20 > 0
   v20_net_1l = NET AREA RATIO met5 nw_v20 > 0
   v20_net_1 = OR v20_net_1a v20_net_1b v20_net_1c v20_net_1d v20_net_1e v20_net_1f v20_net_1g v20_net_1h v20_net_1i v20_net_1j v20_net_1k v20_net_1l

   v20_net_2a = NET AREA RATIO nwell nsd_v20 > 0
   v20_net_2b = NET AREA RATIO pwell nsd_v20 > 0
   v20_net_2c = NET AREA RATIO ptub nsd_v20 > 0
   v20_net_2d = NET AREA RATIO nsd nsd_v20 > 0
   v20_net_2e = NET AREA RATIO psd nsd_v20 > 0
   v20_net_2f = NET AREA RATIO poly nsd_v20 > 0
   v20_net_2g = NET AREA RATIO li nsd_v20 > 0
   v20_net_2h = NET AREA RATIO met1 nsd_v20 > 0
   v20_net_2i = NET AREA RATIO met2 nsd_v20 > 0
   v20_net_2j = NET AREA RATIO met3 nsd_v20 > 0
   v20_net_2k = NET AREA RATIO met4 nsd_v20 > 0
   v20_net_2l = NET AREA RATIO met5 nsd_v20 > 0
   v20_net_2 = OR v20_net_2a v20_net_2b v20_net_2c v20_net_2d v20_net_2e v20_net_2f v20_net_2g v20_net_2h v20_net_2i v20_net_2j v20_net_2k v20_net_2l

   v20_net_3a = NET AREA RATIO nwell psd_v20 > 0
   v20_net_3b = NET AREA RATIO pwell psd_v20 > 0
   v20_net_3c = NET AREA RATIO ptub psd_v20 > 0
   v20_net_3d = NET AREA RATIO nsd psd_v20 > 0
   v20_net_3e = NET AREA RATIO psd psd_v20 > 0
   v20_net_3f = NET AREA RATIO poly psd_v20 > 0
   v20_net_3g = NET AREA RATIO li psd_v20 > 0
   v20_net_3h = NET AREA RATIO met1 psd_v20 > 0
   v20_net_3i = NET AREA RATIO met2 psd_v20 > 0
   v20_net_3j = NET AREA RATIO met3 psd_v20 > 0
   v20_net_3k = NET AREA RATIO met4 psd_v20 > 0
   v20_net_3l = NET AREA RATIO met5 psd_v20 > 0
   v20_net_3 = OR v20_net_3a v20_net_3b v20_net_3c v20_net_3d v20_net_3e v20_net_3f v20_net_3g v20_net_3h v20_net_3i v20_net_3j v20_net_3k v20_net_3l

   v20_net_4a = NET AREA RATIO nwell poly_v20 > 0
   v20_net_4b = NET AREA RATIO pwell poly_v20 > 0
   v20_net_4c = NET AREA RATIO ptub poly_v20 > 0
   v20_net_4d = NET AREA RATIO nsd poly_v20 > 0
   v20_net_4e = NET AREA RATIO psd poly_v20 > 0
   v20_net_4f = NET AREA RATIO poly poly_v20 > 0
   v20_net_4g = NET AREA RATIO li poly_v20 > 0
   v20_net_4h = NET AREA RATIO met1 poly_v20 > 0
   v20_net_4i = NET AREA RATIO met2 poly_v20 > 0
   v20_net_4j = NET AREA RATIO met3 poly_v20 > 0
   v20_net_4k = NET AREA RATIO met4 poly_v20 > 0
   v20_net_4l = NET AREA RATIO met5 poly_v20 > 0
   v20_net_4 = OR v20_net_4a v20_net_4b v20_net_4c v20_net_4d v20_net_4e v20_net_4f v20_net_4g v20_net_4h v20_net_4i v20_net_4j v20_net_4k v20_net_4l

   v20_net_5a = NET AREA RATIO nwell ptub_v20 > 0
   v20_net_5b = NET AREA RATIO pwell ptub_v20 > 0
   v20_net_5c = NET AREA RATIO ptub ptub_v20 > 0
   v20_net_5d = NET AREA RATIO nsd ptub_v20 > 0
   v20_net_5e = NET AREA RATIO psd ptub_v20 > 0
   v20_net_5f = NET AREA RATIO poly ptub_v20 > 0
   v20_net_5g = NET AREA RATIO li ptub_v20 > 0
   v20_net_5h = NET AREA RATIO met1 ptub_v20 > 0
   v20_net_5i = NET AREA RATIO met2 ptub_v20 > 0
   v20_net_5j = NET AREA RATIO met3 ptub_v20 > 0
   v20_net_5k = NET AREA RATIO met4 ptub_v20 > 0
   v20_net_5l = NET AREA RATIO met5 ptub_v20 > 0
   v20_net_5 = OR v20_net_5a v20_net_5b v20_net_5c v20_net_5d v20_net_5e v20_net_5f v20_net_5g v20_net_5h v20_net_5i v20_net_5j v20_net_5k v20_net_5l

 v20_net = OR v20_net_1 v20_net_2 v20_net_3 v20_net_4 v20_net_5 


v20.CON.1 {
    @ v20.CON.1: diff must not straddle v20
    CUT difftap v20
}
v20.CON.2 {
    @ v20.CON.2: poly must not straddle v20
    polyi CUT v20
}
v20.ENC.1 {
    @ v20.ENC.1: pwbm not in areaid:low_vt must be enclosed by v20
    (NOT pwbm LOWVTID) NOT v20
}
v20.CON.3 {
    @ v20.CON.3: dnwell must not straddle v20
    CUT dnwell v20
}
v20.ENC.2 {
    @ v20.ENC.2: v20 interacting with dnwell must fully enclose dnwell
    (dnwell INTERACT v20) NOT v20
}
v20.CON.4 {
    @ v20.CON.4: areaid:low_vt must not straddle v20
    CUT LOWVTID v20
}
v20.OVL.1 {
    @ v20.OVL.1: v20 gate must overlap thkox
    ((diff AND poly) INTERACT v20) NOT thkox
}
v20.CON.9 {
    @ v20.CON.9: v20 over diff must overlap thkox
    (v20 AND diffi) NOT thkox
}


//
// Stress Checks
//

stress.CON.8 {
    @ stress.CON.8: Layer areaid:notCritSide is an unsupported layer. Contact SkyWater Technologies for more information
    COPY notCritSideID
}


#IFNDEF SKIP_STRESS_CHECKS


chip_area = (DONUT SEALID) OR (HOLES SEALID)
chipExtNotNcs = (EXTENT) NOT notCritSideID
q0chip_area = COPY 4000
critsideNoSl = TVF CALtvfLay2OrEmpty chip_area chipExtNotNcs q0chip_area
critsideSl = AND chip_area critside
ccornerStree = AND chip_area ccorner
deadzone = AND chip_area deadzoneID


critsideStress = critsideNoSl OR critsideSl
critAreaStress = ((INTERACT (critsideStress OR ccornerStree) SEALID) AND chip_area) OR critSideNoSl
exemptCells = bondpadCuPillar OR (EXTENT CELL "*_logo*" "*_partnum*" "partnum*" "*_trademark*" "*_copy*" "*datecode*" "lazX_*" "lazY_*" "*tech_CD*" "padPLadv*" "padPL*" "*_visid*" "pad_bond*" ORIGINAL)
exemptStressCells = EXTENT CELL "*_logo*" "*_partnum*" "partnum*" "*_trademark*" "*_copy*" "*datecode*" "lazX_*" "lazY_*" "*tech_CD*" "*_visid*" ORIGINAL
padPcells = (EXTENT CELL "padPLadv*" "padPL*" "pad_bond*" ORIGINAL) OR bondpadCuPillar
laser_target = EXTENT CELL "lazX_*" "lazY_*" ORIGINAL
deadzoneChk = (deadzone NOT exemptCells) AND critAreaStress
BONDPAD2 = pad OUTSIDE (OR SEALID moduleCutAREA fuse FRAMEID laser_target)
critAreaNoExCells = critAreaStress NOT exemptStressCells
ccornerNoExCells = ccornerStree NOT exemptStressCells
critsideNoExCells = critsideStress NOT exemptStressCells
deviceLayers = diff OR (tap OR polyres)
exemptLayers = deviceLayers OR exemptStressCells
anchLayersStress = INTERACT ((poly AND critAreaStress) AND ((li AND critAreaStress) AND ((met1 AND critAreaStress) AND ((met2 AND critAreaStress) AND ((met3 AND critAreaStress) AND (met4 AND critAreaStress)))))) (((poly AND critAreaStress) AND ((li AND critAreaStress) AND ((met1 AND critAreaStress) AND ((met2 AND critAreaStress) AND ((met3 AND critAreaStress) AND (met4 AND critAreaStress)))))) AND critAreaStress)
alicon1Stress = licon AND anchLayersStress
amconStress = mcon AND anchLayersStress
aviaStress = via1 AND anchLayersStress
avia2Stress = via2 AND anchLayersStress
avia3Stress = via3 AND anchLayersStress
anchlicon1Stress = alicon1 OUTSIDE (OR avia3 avia2 avia amcon)
anchmconStress = amcon OUTSIDE (OR avia3 avia2 avia alicon1)
anchviaStress = avia OUTSIDE (OR avia3 avia2 amcon alicon1)
anchvia2Stress = avia2 OUTSIDE (OR avia3 avia amcon alicon1)
anchvia3Stress = avia3 OUTSIDE (OR avia2 avia amcon alicon1)
acontactsStress = OR alicon1 amcon avia avia2 avia3
anchcontactsStress = OR anchlicon1 anchmcon anchvia anchvia2 anchvia3
overlapConStress = acontactsStress NOT anchcontactsStress
anchorTmpStress = ((((anchLayersStress ENCLOSE licon) ENCLOSE mcon) ENCLOSE via1) ENCLOSE via2) ENCLOSE via3
falseAnchStress = poly CUT anchLayersStress
anchorStress = anchorTmpStress OUTSIDE (OR overlapCon falseAnchStress exemptLayers)
met1OverCA = (INTERACT met1 (AND met1 critAreaStress)) NOT (OR anchorStress (INSIDE CELL met1ii exemptStressCells))
met1Holes = ((HOLES met1OverCA INNER EMPTY) INTERACT ((HOLES met1OverCA INNER EMPTY) AND critAreaStress)) AREA < 5000
filled_met1 = met1Holes OR met1OverCA
filled_widemet1 = WITH WIDTH filled_met1 >= 25.0
met1slotAll = ((met1Holes WITH WIDTH < 20) NOT (met1Holes INTERACT (met1Holes AND met1))) AND filled_widemet1
met1slotCutPad = CUT met1slotAll padPcells
met1slot = (met1slotAll NOT padPcells) OR met1slotCutPad
#IFDEF SAVE_CONSTRUCTION_LAYERS
keep_met1slotCutPad {
    @ keep: met1slotCutPad
    COPY met1slotCutPad
}
keep_met1slot {
    @ keep: met1slot
    COPY met1slot
}
keep_met1OverCA {
    @ keep: met1OverCA
    COPY met1OverCA
}
#ENDIF
met2OverCA = (INTERACT met2 (AND met2 critAreaStress)) NOT (OR anchorStress (INSIDE CELL met2ii exemptStressCells))
met2Holes = ((HOLES met2OverCA INNER EMPTY) INTERACT ((HOLES met2OverCA INNER EMPTY) AND critAreaStress)) AREA < 5000
filled_met2 = met2Holes OR met2OverCA
filled_widemet2 = WITH WIDTH filled_met2 >= 25.0
met2slotAll = ((met2Holes WITH WIDTH < 20) NOT (met2Holes INTERACT (met2Holes AND met2))) AND filled_widemet2
met2slotCutPad = CUT met2slotAll padPcells
met2slot = (met2slotAll NOT padPcells) OR met2slotCutPad
#IFDEF SAVE_CONSTRUCTION_LAYERS
keep_met2slotCutPad {
    @ keep: met2slotCutPad
    COPY met2slotCutPad
}
keep_met2slot {
    @ keep: met2slot
    COPY met2slot
}
keep_met2OverCA {
    @ keep: met2OverCA
    COPY met2OverCA
}
#ENDIF
met3OverCA = (INTERACT met3 (AND met3 critAreaStress)) NOT (OR anchorStress (INSIDE CELL met3ii exemptStressCells))
met3Holes = ((HOLES met3OverCA INNER EMPTY) INTERACT ((HOLES met3OverCA INNER EMPTY) AND critAreaStress)) AREA < 5000
filled_met3 = met3Holes OR met3OverCA
filled_widemet3 = WITH WIDTH filled_met3 >= 25.0
met3slotAll = ((met3Holes WITH WIDTH < 20) NOT (met3Holes INTERACT (met3Holes AND met3))) AND filled_widemet3
met3slotCutPad = CUT met3slotAll padPcells
met3slot = (met3slotAll NOT padPcells) OR met3slotCutPad
#IFDEF SAVE_CONSTRUCTION_LAYERS
keep_met3slotCutPad {
    @ keep: met3slotCutPad
    COPY met3slotCutPad
}
keep_met3slot {
    @ keep: met3slot
    COPY met3slot
}
keep_met3OverCA {
    @ keep: met3OverCA
    COPY met3OverCA
}
#ENDIF
met4OverCA = (INTERACT met4 (AND met4 critAreaStress)) NOT (OR anchorStress (INSIDE CELL met4ii exemptStressCells))
met4Holes = ((HOLES met4OverCA INNER EMPTY) INTERACT ((HOLES met4OverCA INNER EMPTY) AND critAreaStress)) AREA < 5000
filled_met4 = met4Holes OR met4OverCA
filled_widemet4 = WITH WIDTH filled_met4 >= 25.0
met4slotAll = ((met4Holes WITH WIDTH < 20) NOT (met4Holes INTERACT (met4Holes AND met4))) AND filled_widemet4
met4slotCutPad = CUT met4slotAll padPcells
met4slot = (met4slotAll NOT padPcells) OR met4slotCutPad
#IFDEF SAVE_CONSTRUCTION_LAYERS
keep_met4slotCutPad {
    @ keep: met4slotCutPad
    COPY met4slotCutPad
}
keep_met4slot {
    @ keep: met4slot
    COPY met4slot
}
keep_met4OverCA {
    @ keep: met4OverCA
    COPY met4OverCA
}
#ENDIF
met5OverCA = (INTERACT met5 (AND met5 critAreaStress)) NOT (OR anchorStress padPcells (INSIDE CELL met5ii exemptStressCells))
met5Holes = ((HOLES met5OverCA INNER EMPTY) INTERACT ((HOLES met5OverCA INNER EMPTY) AND critAreaStress)) AREA < 5000
filled_met5 = met5Holes OR met5OverCA
filled_widemet5 = WITH WIDTH filled_met5 >= 25.0
met5slotAll = ((met5Holes WITH WIDTH < 20) NOT (met5Holes INTERACT (met5Holes AND met5))) AND filled_widemet5
met5slotCutPad = CUT met5slotAll padPcells
met5slot = (met5slotAll NOT padPcells) OR met5slotCutPad
#IFDEF SAVE_CONSTRUCTION_LAYERS
keep_met5slotCutPad {
    @ keep: met5slotCutPad
    COPY met5slotCutPad
}
keep_met5slot {
    @ keep: met5slot
    COPY met5slot
}
keep_met5OverCA {
    @ keep: met5OverCA
    COPY met5OverCA
}
#ENDIF
deadmetInit = INTERACT met1 deadzoneChk
q0met2 = INTERACT met2 deadzoneChk
q0deadmet = COPY q0met2
q0met3 = INTERACT met3 deadzoneChk
q1deadmet = q0deadmet OR q0met3
q0met4 = INTERACT met4 deadzoneChk
q2deadmet = q1deadmet OR q0met4
q0met5 = INTERACT met5 deadzoneChk
q3deadmet = q2deadmet OR q0met5
deadmet_new = COPY q3deadmet
deadmet_all = deadmetInit OR deadmet_new
deadmetCheck = deadmet_all NOT exemptCells
deadpoly = (poly AND deadzoneChk) NOT (exemptCells OR anchorStress)
deadmetWidthErr = (WITH WIDTH (SNAP (deadmetCheck NOT anchorStress) 5) < 8.0) AND deadzoneChk
SEALID_6um_stress = SEALID AND ((EXTENT CELL "advSeal_6um*" ORIGINAL) OR (EXTENT CELL "cuPillarAdvSeal_6um*" ORIGINAL))
diffNotSEALID_6um_stress = diff NOT SEALID_6um_stress
diff.stress.1 {
    @ diff.stress.1: diff outside areaid:seal must not overlap areaid:deadZon
    AND diffNotSEALID_6um_stress deadzoneChk
}
poly.stress.1 {
    @ poly.stress.1: poly not allowed in areaid:deadZon unless poly is within Anchor region
    COPY deadpoly
}
met1.stress.WID.1 {
    @ met1.stress.WID.1: Min width of met1 in Dead Zone < 8.00
    COPY (deadmetWidthErr AND met1i)
}
met2.stress.WID.1 {
    @ met2.stress.WID.1: Min width of met2 in Dead Zone < 8.00
    COPY (deadmetWidthErr AND met2i)
}
met3.stress.WID.1 {
    @ met3.stress.WID.1: Min width of met3 in Dead Zone < 8.00
    COPY (deadmetWidthErr AND met3i)
}
met4.stress.WID.1 {
    @ met4.stress.WID.1: Min width of met4 in Dead Zone < 8.00
    COPY (deadmetWidthErr AND met4i)
}
met5.stress.WID.1 {
    @ met5.stress.WID.1: Min width of met5 in Dead Zone < 8.00
    COPY (deadmetWidthErr AND met5i)
}
met1GrabEdge = met1OverCA WITH EDGE (LENGTH met1OverCA >= 10.0)
met1SelectEdgeShapes = ((WITH WIDTH met1GrabEdge >= 5.0) AND critAreaNoExCells) AND met1OverCA
met1BusReal = LENGTH met1SelectEdgeShapes >= 10.0
met1Line = ((LENGTH (critAreaStress AND met1OverCA) > 0) NOT COINCIDENT EDGE met1BusReal) NOT COINCIDENT EDGE (LENGTH exemptStressCells > 0)
met1.stress.SP.1 {
    @ met1.stress.SP.1: Min spacing of met1 bus (width >= 5.0 & length >= 10.0) & non-bus met1 < 0.54
    EXTERNAL met1BusReal met1Line < 0.54 ABUT == 0 REGION parallel opposite EXCLUDE FALSE
}
met1.stress.SP.2 {
    @ met1.stress.SP.2: Min spacing of met1 bus (width >= 5.0 & length >= 10.0) < 0.54
    EXTERNAL met1BusReal < 0.54 REGION parallel opposite
}
met2GrabEdge = met2OverCA WITH EDGE (LENGTH met2OverCA >= 10.0)
met2SelectEdgeShapes = ((WITH WIDTH met2GrabEdge >= 5.0) AND critAreaNoExCells) AND met2OverCA
met2BusReal = LENGTH met2SelectEdgeShapes >= 10.0
met2Line = ((LENGTH (critAreaStress AND met2OverCA) > 0) NOT COINCIDENT EDGE met2BusReal) NOT COINCIDENT EDGE (LENGTH exemptStressCells > 0)
met2.stress.SP.1 {
    @ met2.stress.SP.1: Min spacing of met2 bus (width >= 5.0 & length >= 10.0) & non-bus met2 < 0.54
    EXTERNAL met2BusReal met2Line < 0.54 ABUT == 0 REGION parallel opposite EXCLUDE FALSE
}
met2.stress.SP.2 {
    @ met2.stress.SP.2: Min spacing of met2 bus (width >= 5.0 & length >= 10.0) < 0.54
    EXTERNAL met2BusReal < 0.54 REGION parallel opposite
}
met3GrabEdge = met3OverCA WITH EDGE (LENGTH met3OverCA >= 10.0)
met3SelectEdgeShapes = ((WITH WIDTH met3GrabEdge >= 5.0) AND critAreaNoExCells) AND met3OverCA
met3BusReal = LENGTH met3SelectEdgeShapes >= 10.0
met3Line = ((LENGTH (critAreaStress AND met3OverCA) > 0) NOT COINCIDENT EDGE met3BusReal) NOT COINCIDENT EDGE (LENGTH exemptStressCells > 0)
met3.stress.SP.1 {
    @ met3.stress.SP.1: Min spacing of met3 bus (width >= 5.0 & length >= 10.0) & non-bus met3 < 0.54
    EXTERNAL met3BusReal met3Line < 0.54 ABUT == 0 REGION parallel opposite EXCLUDE FALSE
}
met3.stress.SP.2 {
    @ met3.stress.SP.2: Min spacing of met3 bus (width >= 5.0 & length >= 10.0) < 0.54
    EXTERNAL met3BusReal < 0.54 REGION parallel opposite
}
met4GrabEdge = met4OverCA WITH EDGE (LENGTH met4OverCA >= 10.0)
met4SelectEdgeShapes = ((WITH WIDTH met4GrabEdge >= 5.0) AND critAreaNoExCells) AND met4OverCA
met4BusReal = LENGTH met4SelectEdgeShapes >= 10.0
met4Line = ((LENGTH (critAreaStress AND met4OverCA) > 0) NOT COINCIDENT EDGE met4BusReal) NOT COINCIDENT EDGE (LENGTH exemptStressCells > 0)
met4.stress.SP.1 {
    @ met4.stress.SP.1: Min spacing of met4 bus (width >= 5.0 & length >= 10.0) & non-bus met4 < 0.54
    EXTERNAL met4BusReal met4Line < 0.54 ABUT == 0 REGION parallel opposite EXCLUDE FALSE
}
met4.stress.SP.2 {
    @ met4.stress.SP.2: Min spacing of met4 bus (width >= 5.0 & length >= 10.0) < 0.54
    EXTERNAL met4BusReal < 0.54 REGION parallel opposite
}
met5GrabEdge = met5OverCA WITH EDGE (LENGTH met5OverCA >= 10.0)
met5SelectEdgeShapes = ((WITH WIDTH met5GrabEdge >= 5.0) AND critAreaNoExCells) AND met5OverCA
met5BusReal = LENGTH met5SelectEdgeShapes >= 10.0
met5Line = ((LENGTH (critAreaStress AND met5OverCA) > 0) NOT COINCIDENT EDGE met5BusReal) NOT COINCIDENT EDGE (LENGTH exemptStressCells > 0)
met5.stress.SP.1 {
    @ met5.stress.SP.1: Min spacing of met5 bus (width >= 5.0 & length >= 10.0) & non-bus met5 < 0.54
    EXTERNAL met5BusReal met5Line < 0.54 ABUT == 0 REGION parallel opposite EXCLUDE FALSE
}
met5.stress.SP.2 {
    @ met5.stress.SP.2: Min spacing of met5 bus (width >= 5.0 & length >= 10.0) < 0.54
    EXTERNAL met5BusReal < 0.54 REGION parallel opposite
}
via0 = COPY mcon
met0 = COPY met1
via1x = COPY via1
stress9Reg = (INTERACT (OR critside ccorner) SEALID) AND (OR SEALID (HOLES SEALID))
met1lowerLevelContact = AND via0 met0
met1upperLevelContact = AND via1x met2
met1OverCA_9 = (stress9Reg AND met1OverCA) NOT exemptStressCells
met1_LinesStandAlone = met1OverCA_9 AND (NOT INTERACT met1 (OR met1lowerLevelContact met1upperLevelContact))
met1_LinesSA_group = (EXTERNAL met1_LinesStandAlone <= 10.0 REGION) OR met1_LinesStandAlone
met1OverCAnotSA = met1OverCA_9 NOT met1_LinesStandAlone
met1_err_stress_9 = SIZE met1OverCAnotSA BY 10 INSIDE OF stress9Reg STEP 0.1
met1_err_stress_9final = (NOT INTERACT met1_LinesSA_group met1_err_stress_9) AND critAreaNoExCells
met1.stress.SP.3 {
    @ met1.stress.SP.3: Max spacing between standalone and non-standalone met1 in critical corner/side area = 10.0 um
    COPY met1_err_stress_9final
}
met2lowerLevelContact = AND via1x met1
met2upperLevelContact = AND via2 met3
met2OverCA_9 = (stress9Reg AND met2OverCA) NOT exemptStressCells
met2_LinesStandAlone = met2OverCA_9 AND (NOT INTERACT met2 (OR met2lowerLevelContact met2upperLevelContact))
met2_LinesSA_group = (EXTERNAL met2_LinesStandAlone <= 10.0 REGION) OR met2_LinesStandAlone
met2OverCAnotSA = met2OverCA_9 NOT met2_LinesStandAlone
met2_err_stress_9 = SIZE met2OverCAnotSA BY 10 INSIDE OF stress9Reg STEP 0.1
met2_err_stress_9final = (NOT INTERACT met2_LinesSA_group met2_err_stress_9) AND critAreaNoExCells
met2.stress.SP.3 {
    @ met2.stress.SP.3: Max spacing between standalone and non-standalone met2 in critical corner/side area = 10.0 um
    COPY met2_err_stress_9final
}
met3lowerLevelContact = AND via2 met2
met3upperLevelContact = AND via3 met4
met3OverCA_9 = (stress9Reg AND met3OverCA) NOT exemptStressCells
met3_LinesStandAlone = met3OverCA_9 AND (NOT INTERACT met3 (OR met3lowerLevelContact met3upperLevelContact))
met3_LinesSA_group = (EXTERNAL met3_LinesStandAlone <= 10.0 REGION) OR met3_LinesStandAlone
met3OverCAnotSA = met3OverCA_9 NOT met3_LinesStandAlone
met3_err_stress_9 = SIZE met3OverCAnotSA BY 10 INSIDE OF stress9Reg STEP 0.1
met3_err_stress_9final = (NOT INTERACT met3_LinesSA_group met3_err_stress_9) AND critAreaNoExCells
met3.stress.SP.3 {
    @ met3.stress.SP.3: Max spacing between standalone and non-standalone met3 in critical corner/side area = 10.0 um
    COPY met3_err_stress_9final
}
met4lowerLevelContact = AND via3 met3
met4upperLevelContact = AND via4 met5
met4OverCA_9 = (stress9Reg AND met4OverCA) NOT exemptStressCells
met4_LinesStandAlone = met4OverCA_9 AND (NOT INTERACT met4 (OR met4lowerLevelContact met4upperLevelContact))
met4_LinesSA_group = (EXTERNAL met4_LinesStandAlone <= 10.0 REGION) OR met4_LinesStandAlone
met4OverCAnotSA = met4OverCA_9 NOT met4_LinesStandAlone
met4_err_stress_9 = SIZE met4OverCAnotSA BY 10 INSIDE OF stress9Reg STEP 0.1
met4_err_stress_9final = (NOT INTERACT met4_LinesSA_group met4_err_stress_9) AND critAreaNoExCells
met4.stress.SP.3 {
    @ met4.stress.SP.3: Max spacing between standalone and non-standalone met4 in critical corner/side area = 10.0 um
    COPY met4_err_stress_9final
}
met5lowerLevelContact = AND via4 met4
met5upperLevelContact = AND via4 met5
met5OverCA_9 = (stress9Reg AND met5OverCA) NOT exemptStressCells
met5_LinesStandAlone = met5OverCA_9 AND (NOT INTERACT met5 (OR met5lowerLevelContact met5upperLevelContact))
met5_LinesSA_group = (EXTERNAL met5_LinesStandAlone <= 10.0 REGION) OR met5_LinesStandAlone
met5OverCAnotSA = met5OverCA_9 NOT met5_LinesStandAlone
met5_err_stress_9 = SIZE met5OverCAnotSA BY 10 INSIDE OF stress9Reg STEP 0.1
met5_err_stress_9final = (NOT INTERACT met5_LinesSA_group met5_err_stress_9) AND critAreaNoExCells
met5.stress.SP.3 {
    @ met5.stress.SP.3: Max spacing between standalone and non-standalone met5 in critical corner/side area = 10.0 um
    COPY met5_err_stress_9final
}
met1Inner90DegCornerTmp = met1OverCA OR (met1 AND padPcells)
met1Inner90DegCorner = EXTERNAL met1Inner90DegCornerTmp < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION
met1Inner90DegCorNoSlot = NOT INTERACT met1Inner90DegCorner met1slot
met1Bus = WITH WIDTH met1OverCA >= 5.0
met1BusInner90Deg_errCS = SIZE ((TOUCH met1Inner90DegCorNoSlot met1Bus) AND critsideNoExCells) BY (10 * 0.005)
met1Inner90Deg_errCC = SIZE (met1Inner90DegCorNoSlot AND ccornerNoExCells) BY (10 * 0.005)
met1.stress.CON.1 {
    @ met1.stress.CON.1: 90-degree bend of inner side of 5um wide met1 in areaid:critSid are prohibited
    COPY met1BusInner90Deg_errCS
}
met1.stress.CON.2 {
    @ met1.stress.CON.2: 90-degree bends of inner side of met1 in areaid:critCorner are probited
    COPY met1Inner90Deg_errCC
}
met2Inner90DegCornerTmp = met2OverCA OR (met2 AND padPcells)
met2Inner90DegCorner = EXTERNAL met2Inner90DegCornerTmp < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION
met2Inner90DegCorNoSlot = NOT INTERACT met2Inner90DegCorner met2slot
met2Bus = WITH WIDTH met2OverCA >= 5.0
met2BusInner90Deg_errCS = SIZE ((TOUCH met2Inner90DegCorNoSlot met2Bus) AND critsideNoExCells) BY (10 * 0.005)
met2Inner90Deg_errCC = SIZE (met2Inner90DegCorNoSlot AND ccornerNoExCells) BY (10 * 0.005)
met2.stress.CON.1 {
    @ met2.stress.CON.1: 90-degree bend of inner side of 5um wide met2 in areaid:critSid are prohibited
    COPY met2BusInner90Deg_errCS
}
met2.stress.CON.2 {
    @ met2.stress.CON.2: 90-degree bends of inner side of met2 in areaid:critCorner are probited
    COPY met2Inner90Deg_errCC
}
met3Inner90DegCornerTmp = met3OverCA OR (met3 AND padPcells)
met3Inner90DegCorner = EXTERNAL met3Inner90DegCornerTmp < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION
met3Inner90DegCorNoSlot = NOT INTERACT met3Inner90DegCorner met3slot
met3Bus = WITH WIDTH met3OverCA >= 5.0
met3BusInner90Deg_errCS = SIZE ((TOUCH met3Inner90DegCorNoSlot met3Bus) AND critsideNoExCells) BY (10 * 0.005)
met3Inner90Deg_errCC = SIZE (met3Inner90DegCorNoSlot AND ccornerNoExCells) BY (10 * 0.005)
met3.stress.CON.1 {
    @ met3.stress.CON.1: 90-degree bend of inner side of 5um wide met3 in areaid:critSid are prohibited
    COPY met3BusInner90Deg_errCS
}
met3.stress.CON.2 {
    @ met3.stress.CON.2: 90-degree bends of inner side of met3 in areaid:critCorner are probited
    COPY met3Inner90Deg_errCC
}
met4Inner90DegCornerTmp = met4OverCA OR (met4 AND padPcells)
met4Inner90DegCorner = EXTERNAL met4Inner90DegCornerTmp < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION
met4Inner90DegCorNoSlot = NOT INTERACT met4Inner90DegCorner met4slot
met4Bus = WITH WIDTH met4OverCA >= 5.0
met4BusInner90Deg_errCS = SIZE ((TOUCH met4Inner90DegCorNoSlot met4Bus) AND critsideNoExCells) BY (10 * 0.005)
met4Inner90Deg_errCC = SIZE (met4Inner90DegCorNoSlot AND ccornerNoExCells) BY (10 * 0.005)
met4.stress.CON.1 {
    @ met4.stress.CON.1: 90-degree bend of inner side of 5um wide met4 in areaid:critSid are prohibited
    COPY met4BusInner90Deg_errCS
}
met4.stress.CON.2 {
    @ met4.stress.CON.2: 90-degree bends of inner side of met4 in areaid:critCorner are probited
    COPY met4Inner90Deg_errCC
}
met5Inner90DegCornerTmp = met5OverCA OR (met5 AND padPcells)
met5Inner90DegCorner = EXTERNAL met5Inner90DegCornerTmp < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION
met5Inner90DegCorNoSlot = NOT INTERACT met5Inner90DegCorner met5slot
met5Bus = WITH WIDTH met5OverCA >= 5.0
met5BusInner90Deg_errCS = SIZE ((TOUCH met5Inner90DegCorNoSlot met5Bus) AND critsideNoExCells) BY (10 * 0.005)
met5Inner90Deg_errCC = SIZE (met5Inner90DegCorNoSlot AND ccornerNoExCells) BY (10 * 0.005)
met5.stress.CON.1 {
    @ met5.stress.CON.1: 90-degree bend of inner side of 5um wide met5 in areaid:critSid are prohibited
    COPY met5BusInner90Deg_errCS
}
met5.stress.CON.2 {
    @ met5.stress.CON.2: 90-degree bends of inner side of met5 in areaid:critCorner are probited
    COPY met5Inner90Deg_errCC
}
met1Bus5_tmp = met1OverCA NOT (INTERNAL met1OverCA > 0 < 5.0 OPPOSITE OBTUSE ALSO REGION)
met1Bus5 = met1Bus5_tmp NOT (WITH WIDTH met1Bus5_tmp < 5.0)
met1Bus1_5_tmp = INTERNAL met1OverCA >= 1.0 < 5.0 OPPOSITE OBTUSE ALSO REGION
met1Bus1_5_tmp1 = WITH WIDTH (met1Bus1_5_tmp AND met1OverCA) >= 1.0 < 5.0
met1Bus1_5 = COPY met1Bus1_5_tmp1
met1Busless1 = WITH WIDTH met1OverCA < 1.0
met1_Turn225_225_Edge_tmp1 = (CONVEX EDGE met1OverCA ANGLE1 == 225 ANGLE2 == 225) OUTSIDE EDGE met1Holes
met1_Turn225_225_EdgeSz_tmp1 = EXPAND EDGE met1_Turn225_225_Edge_tmp1 INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met1_Turn225_225_EdgeSz_tmp2 = met1_Turn225_225_EdgeSz_tmp1 INSIDE met1OverCA
met1_Turn225_225_Edge = met1_Turn225_225_Edge_tmp1 COINCIDENT EDGE met1_Turn225_225_EdgeSz_tmp2
met1_Turn225_225_Edgeless5 = EXPAND EDGE (LENGTH met1_Turn225_225_Edge < 5.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met1_Turn225_225_Edgeless1 = EXPAND EDGE (LENGTH met1_Turn225_225_Edge < 1.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met1_Turn225_225_Edgeless05 = EXPAND EDGE (LENGTH met1_Turn225_225_Edge < 0.17) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met1_TurnLen_bus5Err = ((INTERACT met1_Turn225_225_Edgeless5 (met1_Turn225_225_Edgeless5 AND met1Bus5)) NOT (INTERACT met1_Turn225_225_Edgeless5 (met1_Turn225_225_Edgeless5 AND (met1Bus1_5 OR met1Busless1)))) AND critAreaNoExCells
met1_TurnLen_bus1_5Err = ((INTERACT met1_Turn225_225_Edgeless1 (met1_Turn225_225_Edgeless1 AND met1Bus1_5)) NOT (INTERACT met1_Turn225_225_Edgeless1 (met1_Turn225_225_Edgeless1 AND met1Busless1))) AND ccornerNoExCells
met1_TurnLen_busless1Err = (INTERACT met1_Turn225_225_Edgeless05 (met1_Turn225_225_Edgeless05 AND met1Busless1)) AND ccornerNoExCells
met1.stress.CON.3 {
    @ met1.stress.CON.3: Min inner 45-degree edge length for met1 >= 5.00um wide inside areaid:critCorner area < 5.0
    COPY met1_TurnLen_bus5Err
}
met1.stress.CON.4 {
    @ met1.stress.CON.4: Min inner 45-degree edge length for met1 > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0
    COPY met1_TurnLen_bus1_5Err
}
met1.stress.CON.5 {
    @ met1.stress.CON.5: Min inner 45-degree edge length for met1 < 1.00um wide inside areaid:critCorner < 0.17
    COPY met1_TurnLen_busless1Err
}
met2Bus5_tmp = met2OverCA NOT (INTERNAL met2OverCA > 0 < 5.0 OPPOSITE OBTUSE ALSO REGION)
met2Bus5 = met2Bus5_tmp NOT (WITH WIDTH met2Bus5_tmp < 5.0)
met2Bus1_5_tmp = INTERNAL met2OverCA >= 1.0 < 5.0 OPPOSITE OBTUSE ALSO REGION
met2Bus1_5_tmp1 = WITH WIDTH (met2Bus1_5_tmp AND met2OverCA) >= 1.0 < 5.0
met2Bus1_5 = COPY met2Bus1_5_tmp1
met2Busless1 = WITH WIDTH met2OverCA < 1.0
met2_Turn225_225_Edge_tmp1 = (CONVEX EDGE met2OverCA ANGLE1 == 225 ANGLE2 == 225) OUTSIDE EDGE met2Holes
met2_Turn225_225_EdgeSz_tmp1 = EXPAND EDGE met2_Turn225_225_Edge_tmp1 INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met2_Turn225_225_EdgeSz_tmp2 = met2_Turn225_225_EdgeSz_tmp1 INSIDE met2OverCA
met2_Turn225_225_Edge = met2_Turn225_225_Edge_tmp1 COINCIDENT EDGE met2_Turn225_225_EdgeSz_tmp2
met2_Turn225_225_Edgeless5 = EXPAND EDGE (LENGTH met2_Turn225_225_Edge < 5.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met2_Turn225_225_Edgeless1 = EXPAND EDGE (LENGTH met2_Turn225_225_Edge < 1.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met2_Turn225_225_Edgeless05 = EXPAND EDGE (LENGTH met2_Turn225_225_Edge < 0.17) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met2_TurnLen_bus5Err = ((INTERACT met2_Turn225_225_Edgeless5 (met2_Turn225_225_Edgeless5 AND met2Bus5)) NOT (INTERACT met2_Turn225_225_Edgeless5 (met2_Turn225_225_Edgeless5 AND (met2Bus1_5 OR met2Busless1)))) AND critAreaNoExCells
met2_TurnLen_bus1_5Err = ((INTERACT met2_Turn225_225_Edgeless1 (met2_Turn225_225_Edgeless1 AND met2Bus1_5)) NOT (INTERACT met2_Turn225_225_Edgeless1 (met2_Turn225_225_Edgeless1 AND met2Busless1))) AND ccornerNoExCells
met2_TurnLen_busless1Err = (INTERACT met2_Turn225_225_Edgeless05 (met2_Turn225_225_Edgeless05 AND met2Busless1)) AND ccornerNoExCells
met2.stress.CON.3 {
    @ met2.stress.CON.3: Min inner 45-degree edge length for met2 >= 5.00um wide inside areaid:critCorner area < 5.0
    COPY met2_TurnLen_bus5Err
}
met2.stress.CON.4 {
    @ met2.stress.CON.4: Min inner 45-degree edge length for met2 > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0
    COPY met2_TurnLen_bus1_5Err
}
met2.stress.CON.5 {
    @ met2.stress.CON.5: Min inner 45-degree edge length for met2 < 1.00um wide inside areaid:critCorner < 0.17
    COPY met2_TurnLen_busless1Err
}
met3Bus5_tmp = met3OverCA NOT (INTERNAL met3OverCA > 0 < 5.0 OPPOSITE OBTUSE ALSO REGION)
met3Bus5 = met3Bus5_tmp NOT (WITH WIDTH met3Bus5_tmp < 5.0)
met3Bus1_5_tmp = INTERNAL met3OverCA >= 1.0 < 5.0 OPPOSITE OBTUSE ALSO REGION
met3Bus1_5_tmp1 = WITH WIDTH (met3Bus1_5_tmp AND met3OverCA) >= 1.0 < 5.0
met3Bus1_5 = COPY met3Bus1_5_tmp1
met3Busless1 = WITH WIDTH met3OverCA < 1.0
met3_Turn225_225_Edge_tmp1 = (CONVEX EDGE met3OverCA ANGLE1 == 225 ANGLE2 == 225) OUTSIDE EDGE met3Holes
met3_Turn225_225_EdgeSz_tmp1 = EXPAND EDGE met3_Turn225_225_Edge_tmp1 INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met3_Turn225_225_EdgeSz_tmp2 = met3_Turn225_225_EdgeSz_tmp1 INSIDE met3OverCA
met3_Turn225_225_Edge = met3_Turn225_225_Edge_tmp1 COINCIDENT EDGE met3_Turn225_225_EdgeSz_tmp2
met3_Turn225_225_Edgeless5 = EXPAND EDGE (LENGTH met3_Turn225_225_Edge < 5.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met3_Turn225_225_Edgeless1 = EXPAND EDGE (LENGTH met3_Turn225_225_Edge < 1.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met3_Turn225_225_Edgeless05 = EXPAND EDGE (LENGTH met3_Turn225_225_Edge < 0.17) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met3_TurnLen_bus5Err = ((INTERACT met3_Turn225_225_Edgeless5 (met3_Turn225_225_Edgeless5 AND met3Bus5)) NOT (INTERACT met3_Turn225_225_Edgeless5 (met3_Turn225_225_Edgeless5 AND (met3Bus1_5 OR met3Busless1)))) AND critAreaNoExCells
met3_TurnLen_bus1_5Err = ((INTERACT met3_Turn225_225_Edgeless1 (met3_Turn225_225_Edgeless1 AND met3Bus1_5)) NOT (INTERACT met3_Turn225_225_Edgeless1 (met3_Turn225_225_Edgeless1 AND met3Busless1))) AND ccornerNoExCells
met3_TurnLen_busless1Err = (INTERACT met3_Turn225_225_Edgeless05 (met3_Turn225_225_Edgeless05 AND met3Busless1)) AND ccornerNoExCells
met3.stress.CON.3 {
    @ met3.stress.CON.3: Min inner 45-degree edge length for met3 >= 5.00um wide inside areaid:critCorner area < 5.0
    COPY met3_TurnLen_bus5Err
}
met3.stress.CON.4 {
    @ met3.stress.CON.4: Min inner 45-degree edge length for met3 > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0
    COPY met3_TurnLen_bus1_5Err
}
met3.stress.CON.5 {
    @ met3.stress.CON.5: Min inner 45-degree edge length for met3 < 1.00um wide inside areaid:critCorner < 0.17
    COPY met3_TurnLen_busless1Err
}
met4Bus5_tmp = met4OverCA NOT (INTERNAL met4OverCA > 0 < 5.0 OPPOSITE OBTUSE ALSO REGION)
met4Bus5 = met4Bus5_tmp NOT (WITH WIDTH met4Bus5_tmp < 5.0)
met4Bus1_5_tmp = INTERNAL met4OverCA >= 1.0 < 5.0 OPPOSITE OBTUSE ALSO REGION
met4Bus1_5_tmp1 = WITH WIDTH (met4Bus1_5_tmp AND met4OverCA) >= 1.0 < 5.0
met4Bus1_5 = COPY met4Bus1_5_tmp1
met4Busless1 = WITH WIDTH met4OverCA < 1.0
met4_Turn225_225_Edge_tmp1 = (CONVEX EDGE met4OverCA ANGLE1 == 225 ANGLE2 == 225) OUTSIDE EDGE met4Holes
met4_Turn225_225_EdgeSz_tmp1 = EXPAND EDGE met4_Turn225_225_Edge_tmp1 INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met4_Turn225_225_EdgeSz_tmp2 = met4_Turn225_225_EdgeSz_tmp1 INSIDE met4OverCA
met4_Turn225_225_Edge = met4_Turn225_225_Edge_tmp1 COINCIDENT EDGE met4_Turn225_225_EdgeSz_tmp2
met4_Turn225_225_Edgeless5 = EXPAND EDGE (LENGTH met4_Turn225_225_Edge < 5.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met4_Turn225_225_Edgeless1 = EXPAND EDGE (LENGTH met4_Turn225_225_Edge < 1.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met4_Turn225_225_Edgeless05 = EXPAND EDGE (LENGTH met4_Turn225_225_Edge < 0.17) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met4_TurnLen_bus5Err = ((INTERACT met4_Turn225_225_Edgeless5 (met4_Turn225_225_Edgeless5 AND met4Bus5)) NOT (INTERACT met4_Turn225_225_Edgeless5 (met4_Turn225_225_Edgeless5 AND (met4Bus1_5 OR met4Busless1)))) AND critAreaNoExCells
met4_TurnLen_bus1_5Err = ((INTERACT met4_Turn225_225_Edgeless1 (met4_Turn225_225_Edgeless1 AND met4Bus1_5)) NOT (INTERACT met4_Turn225_225_Edgeless1 (met4_Turn225_225_Edgeless1 AND met4Busless1))) AND ccornerNoExCells
met4_TurnLen_busless1Err = (INTERACT met4_Turn225_225_Edgeless05 (met4_Turn225_225_Edgeless05 AND met4Busless1)) AND ccornerNoExCells
met4.stress.CON.3 {
    @ met4.stress.CON.3: Min inner 45-degree edge length for met4 >= 5.00um wide inside areaid:critCorner area < 5.0
    COPY met4_TurnLen_bus5Err
}
met4.stress.CON.4 {
    @ met4.stress.CON.4: Min inner 45-degree edge length for met4 > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0
    COPY met4_TurnLen_bus1_5Err
}
met4.stress.CON.5 {
    @ met4.stress.CON.5: Min inner 45-degree edge length for met4 < 1.00um wide inside areaid:critCorner < 0.17
    COPY met4_TurnLen_busless1Err
}
met5Bus5_tmp = met5OverCA NOT (INTERNAL met5OverCA > 0 < 5.0 OPPOSITE OBTUSE ALSO REGION)
met5Bus5 = met5Bus5_tmp NOT (WITH WIDTH met5Bus5_tmp < 5.0)
met5Bus1_5_tmp = INTERNAL met5OverCA >= 1.0 < 5.0 OPPOSITE OBTUSE ALSO REGION
met5Bus1_5_tmp1 = WITH WIDTH (met5Bus1_5_tmp AND met5OverCA) >= 1.0 < 5.0
met5Bus1_5 = COPY met5Bus1_5_tmp1
met5Busless1 = WITH WIDTH met5OverCA < 1.0
met5_Turn225_225_Edge_tmp1 = (CONVEX EDGE met5OverCA ANGLE1 == 225 ANGLE2 == 225) OUTSIDE EDGE met5Holes
met5_Turn225_225_EdgeSz_tmp1 = EXPAND EDGE met5_Turn225_225_Edge_tmp1 INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met5_Turn225_225_EdgeSz_tmp2 = met5_Turn225_225_EdgeSz_tmp1 INSIDE met5OverCA
met5_Turn225_225_Edge = met5_Turn225_225_Edge_tmp1 COINCIDENT EDGE met5_Turn225_225_EdgeSz_tmp2
met5_Turn225_225_Edgeless5 = EXPAND EDGE (LENGTH met5_Turn225_225_Edge < 5.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met5_Turn225_225_Edgeless1 = EXPAND EDGE (LENGTH met5_Turn225_225_Edge < 1.0) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met5_Turn225_225_Edgeless05 = EXPAND EDGE (LENGTH met5_Turn225_225_Edge < 0.17) INSIDE BY 0.005 EXTEND BY (10.0 * 0.005)
met5_TurnLen_bus5Err = ((INTERACT met5_Turn225_225_Edgeless5 (met5_Turn225_225_Edgeless5 AND met5Bus5)) NOT (INTERACT met5_Turn225_225_Edgeless5 (met5_Turn225_225_Edgeless5 AND (met5Bus1_5 OR met5Busless1)))) AND critAreaNoExCells
met5_TurnLen_bus1_5Err = ((INTERACT met5_Turn225_225_Edgeless1 (met5_Turn225_225_Edgeless1 AND met5Bus1_5)) NOT (INTERACT met5_Turn225_225_Edgeless1 (met5_Turn225_225_Edgeless1 AND met5Busless1))) AND ccornerNoExCells
met5_TurnLen_busless1Err = (INTERACT met5_Turn225_225_Edgeless05 (met5_Turn225_225_Edgeless05 AND met5Busless1)) AND ccornerNoExCells
met5.stress.CON.3 {
    @ met5.stress.CON.3: Min inner 45-degree edge length for met5 >= 5.00um wide inside areaid:critCorner area < 5.0
    COPY met5_TurnLen_bus5Err
}
met5.stress.CON.4 {
    @ met5.stress.CON.4: Min inner 45-degree edge length for met5 > 1.00um & < 5.00um wide inside areaid:critCorner area < 1.0
    COPY met5_TurnLen_bus1_5Err
}
met5.stress.CON.5 {
    @ met5.stress.CON.5: Min inner 45-degree edge length for met5 < 1.00um wide inside areaid:critCorner < 0.17
    COPY met5_TurnLen_busless1Err
}
bondpadPcelltmp_1 = (EXTENT CELL "padPL*" ORIGINAL) OR bondpadCuPillar
bondpadPcelltmp_2 = EXTENT CELL "pad_bond*" ORIGINAL
bondpadPcelltmp = OR bondpadPcelltmp_1 bondpadPcelltmp_2
bondpadPcellAdv = EXTENT CELL "padPLadv*" ORIGINAL
bondpadPcell2 = bondpadPcelltmp NOT bondpadPcellAdv
bondpadNormal2 = BONDPAD2 AND bondpadPcell2
bondpadAdvan = BONDPAD2 AND bondpadPcellAdv
bondPadNormSz = SIZE bondpadNormal2 BY 5
bondPadAdvSz = SIZE bondpadAdvan BY 2.7
allbondPadSzTmp = bondPadNormSz OR bondPadAdvSz
degree45edge = EXPAND EDGE (ANGLE allbondPadSzTmp == 45) OUTSIDE BY 0.005
allbondPadSz = allbondPadSzTmp OR degree45edge
allbondPadSz_met5 = allbondPadSz AND met5
bondPadCon_met5 = met5 AND (WITH WIDTH (met5 NOT allbondPadSz_met5) >= 5.0)
met5Bus_PadCor90 = (EXTERNAL bondPadCon_met5 allbondPadSz_met5 < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION) OR (EXTERNAL allbondPadSz_met5 < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION)
met5Bus_PadCor90Sz = SIZE ((TOUCH met5Bus_PadCor90 met5) AND critAreaNoExCells) BY (10 * 0.025)
met5.stress.CON.6 {
    @ met5.stress.CON.6: 90-degree turns for met5 bus connecting pad at the point of connection is prohibited
    COPY met5Bus_PadCor90Sz
}
allbondPadSz_met4 = allbondPadSz AND met4
bondPadCon_met4 = met4 AND (WITH WIDTH (met4 NOT allbondPadSz_met4) >= 5.0)
met4Bus_PadCor90 = (EXTERNAL bondPadCon_met4 allbondPadSz_met4 < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION) OR (EXTERNAL allbondPadSz_met4 < 0.005 ABUT > 89.9 < 90.1 SINGULAR REGION)
met4Bus_PadCor90Sz = SIZE ((TOUCH met4Bus_PadCor90 met4) AND critAreaNoExCells) BY (10 * 0.025)
met4.stress.CON.6 {
    @ met4.stress.CON.6: 90-degree turns for met4 bus connecting pad at the point of connection is prohibited
    COPY met4Bus_PadCor90Sz
}
convexedges_90 = CONVEX EDGE met5 ANGLE1 == 90 ANGLE2 == 270
convexedges_135 = CONVEX EDGE met5 ANGLE1 == 135 ANGLE2 == 270
convexedges_45 = CONVEX EDGE met5 ANGLE1 > 0 ANGLE2 == 225
met_edge_45_225 = LENGTH convexedges_135 <= 6.4
met_edge_135_225 = LENGTH convexedges_45 <= 6.4
met_edge_90_270 = LENGTH convexedges_90 <= 6.4
convexedges_45Sz = EXPAND EDGE met_edge_45_225 INSIDE BY 0.005
convexedges_135Sz = EXPAND EDGE met_edge_135_225 INSIDE BY 0.005
met_edge_90_270Sz = EXPAND EDGE met_edge_90_270 INSIDE BY 0.005
all_met_edgesSz = EXPAND EDGE (LENGTH met5 >= 1.6 <= 3.2) INSIDE BY 0.005
all_met_edgesNot90_270 = all_met_edgesSz NOT (OR convexedges_45Sz convexedges_135Sz met_edge_90_270Sz)
topmet45Sz = EXPAND EDGE (ANGLE met5 == 45) INSIDE BY 0.005
convexedges = (OR convexedges_45Sz convexedges_135Sz met_edge_90_270Sz) NOT topmet45Sz
met_edge_90_270Real = NOT INTERACT convexedges all_met_edgesNot90_270
met_edge_90_270Regtmp = (EXTERNAL met_edge_90_270Real <= 3.19 PARALLEL OPPOSITE REGION) AND met5
met_edge_90_270Reg = NOT WITH WIDTH met_edge_90_270Regtmp == 0.005
met_edge_90_270RegChk = met_edge_90_270Real WITH EDGE (met_edge_90_270Real COINCIDENT OUTSIDE EDGE met_edge_90_270Reg)
met_turn_90_270 = INTERACT met5 (met5 AND met_edge_90_270Reg)
met_LineEnd = EXPAND EDGE (LENGTH (met5 NOT met_turn_90_270) <= 1.0) INSIDE BY 0.005
met_edge_90_270Sz1 = EXPAND EDGE met_edge_90_270RegChk OUTSIDE BY 1
met_Line_Good = NOT CUT met_LineEnd met_edge_90_270Sz1
topMet45 = ANGLE (met5 AND (critsideNoExCells OR ccornerNoExCells)) > 44.9 < 45.1
topMet45szOut = (EXPAND EDGE topMet45 OUTSIDE BY 0.005) NOT met5slot
topMetInt45 = INTERACT met5 topMet45szOut
topMet90sz = EXPAND EDGE (ANGLE topMetInt45 == 90) OUTSIDE BY 0.005
topMet0sz = EXPAND EDGE (ANGLE topMetInt45 == 0) OUTSIDE BY 0.005
topMet45_both = (INTERACT topMet45szOut topMet90sz) AND (INTERACT topMet45szOut topMet0sz)
topMet0_45_2x = INTERACT topMet0sz topMet45szOut == 2
topMet90_45_2x = INTERACT topMet90sz topMet45szOut == 2
topMet45_3x = (INTERACT topmet45szOut topMet0_45_2x) AND (INTERACT topmet45szout topMet90_45_2x)
stress18_err90 = EXPAND EDGE (LENGTH (topMetInt45 COINCIDENT EDGE (INTERACT topMet90sz topMet45_3x)) < 2.3) OUTSIDE BY 0.005
stress18_err0 = EXPAND EDGE (LENGTH (topMetInt45 COINCIDENT EDGE (INTERACT topMet0sz topMet45_3x)) < 2.3) OUTSIDE BY 0.005
err1 = INTERACT stress18_err90 (INTERACT topMet45_3x stress18_err0)
err2 = INTERACT stress18_err0 (INTERACT topMet45_3x stress18_err90)
stress.CON.7 {
    @ stress.CON.7: Min length of non-touching angled edges for shape containing 3 consecutive 45-degree edges in areaid:cristSid or areaid:critCorner < 2.3
    COPY err1
    COPY err2
}
met1.slot.WID.1 {
    @ met1.slot.WID.1: Min width of met1 slot < 2.3
    (INTERNAL met1slotAll < 2.3 PARALLEL OPPOSITE REGION) AND critAreaStress
}
met1.slot.WID.2 {
    @ met1.slot.WID.2: Max width of met1 slot > 10.0
    WITH WIDTH met1slot > 10.0
}
met1.slot.LEN.1 {
    @ met1.slot.LEN.1: Max length of met1 slot = 600.0
    LENGTH (INTERACT met1slotAll (met1slotAll AND critAreaStress)) > 600.0
}
met2.slot.WID.1 {
    @ met2.slot.WID.1: Min width of met2 slot < 2.3
    (INTERNAL met2slotAll < 2.3 PARALLEL OPPOSITE REGION) AND critAreaStress
}
met2.slot.WID.2 {
    @ met2.slot.WID.2: Max width of met2 slot > 10.0
    WITH WIDTH met2slot > 10.0
}
met2.slot.LEN.1 {
    @ met2.slot.LEN.1: Max length of met2 slot = 600.0
    LENGTH (INTERACT met2slotAll (met2slotAll AND critAreaStress)) > 600.0
}
met3.slot.WID.1 {
    @ met3.slot.WID.1: Min width of met3 slot < 2.3
    (INTERNAL met3slotAll < 2.3 PARALLEL OPPOSITE REGION) AND critAreaStress
}
met3.slot.WID.2 {
    @ met3.slot.WID.2: Max width of met3 slot > 10.0
    WITH WIDTH met3slot > 10.0
}
met3.slot.LEN.1 {
    @ met3.slot.LEN.1: Max length of met3 slot = 600.0
    LENGTH (INTERACT met3slotAll (met3slotAll AND critAreaStress)) > 600.0
}
met4.slot.WID.1 {
    @ met4.slot.WID.1: Min width of met4 slot < 2.3
    (INTERNAL met4slotAll < 2.3 PARALLEL OPPOSITE REGION) AND critAreaStress
}
met4.slot.WID.2 {
    @ met4.slot.WID.2: Max width of met4 slot > 10.0
    WITH WIDTH met4slot > 10.0
}
met4.slot.LEN.1 {
    @ met4.slot.LEN.1: Max length of met4 slot = 600.0
    LENGTH (INTERACT met4slotAll (met4slotAll AND critAreaStress)) > 600.0
}
met5.slot.WID.1 {
    @ met5.slot.WID.1: Min width of met5 slot < 2.3
    (INTERNAL met5slotAll < 2.3 PARALLEL OPPOSITE REGION) AND critAreaStress
}
met5.slot.WID.2 {
    @ met5.slot.WID.2: Max width of met5 slot > 10.0
    WITH WIDTH met5slot > 10.0
}
met5.slot.LEN.1 {
    @ met5.slot.LEN.1: Max length of met5 slot = 600.0
    LENGTH (INTERACT met5slotAll (met5slotAll AND critAreaStress)) > 600.0
}
rivetvia1 = via1 NOT (SEALID OR (exemptStressCells OR padPcells))
met1stack = (met1OverCA AND met2) INTERACT rivetvia1
met1stackBus = WITH WIDTH met1stack >= 25.0
met1stackBusCA = met1stackBus AND critAreaStress
met1UppBus = (WITH WIDTH met2 >= 25.0) NOT exemptStressCells
met1stack_uppBus = met1stackBus AND met1UppBus
met1stack_encErr_tmp = ((ENCLOSURE met1stack met2 < 1.0 ABUT < 89.5 SINGULAR REGION) NOT SEALID) AND critAreaStress
met1stack_encErr = met1stack_encErr_tmp INTERACT (met1stack_encErr_tmp AND met1stack_uppBus)
met1stackStrUpp = (met1OverCA NOT met1stack) COINCIDENT OUTSIDE EDGE met1stack
met1stackStrUppSz05 = (EXPAND EDGE met1stackStrUpp INSIDE BY 0.5) NOT CUT met1OverCA
met1stackStrUppExempt = met1stackStrUppSz05 COINCIDENT OUTSIDE EDGE met1stack
met1stack_encErrFinal = met1stack_encErr NOT (EXPAND EDGE met1stackStrUppExempt OUTSIDE BY 0.005)
CONNECT met1stackBusCA via1
met1stackNoSlots = ((met1OverCA OR met1slot) AND (met2 OR met2slot)) INTERACT rivetvia1
met1stackBusNoSlots = WITH WIDTH met1stackNoSlots >= 25.0
met1stackBusCA_NoSlots = met1stackBusNoSlots AND critAreaStress
met1Low_slot_stack = met1slot AND met1stackBusCA_NoSlots
met2Upp_slot_stack = met2slot AND met1stackBusCA_NoSlots
err_coin_slots_met1 = ((met1Low_slot_stack NOT ENCLOSE met2Upp_slot_stack) INTERACT ((met1Low_slot_stack NOT ENCLOSE met2Upp_slot_stack) AND critAreaStress)) NOT (EXTENT CELL "pad_bond*" ORIGINAL)
met1.stress.CON.9 {
    @ met1.slot.CON.9: met1 in lower slotted stack should enclose met2 in the upper slotted stack.
    COPY err_coin_slots_met1
}
met1.stress.ENC.1 {
    @ met1.stress.ENC.1: Min enclosure of met2 in a slotted stack by met1 in slotted stack < 1.0
    ENCLOSURE (met2Upp_slot_stack AND met1Low_slot_stack) met1Low_slot_stack < 1.0 MEASURE ALL ABUT < 90 SINGULAR
}
met1.stress.ENC.2 {
    @ met1.stress.ENC.2: Min enclosure of a met1 stack bus by met2 bus < 1.0
    COPY met1stack_encErrFinal
}
met1.stress.DEN.1 {
    @ met1.stress.DEN.1: Min via1 density on wide met1 and met2 bus stack is 3.00 percent
    NET AREA RATIO met1stackBusCA via1 < 0.03 [AREA(via1)/AREA(met1stackBusCA)] RDB met1.stress.DEN.1.db met1stackBusCA via1
}
rivetvia2 = via2 NOT (SEALID OR (exemptStressCells OR padPcells))
met2stack = (met2OverCA AND met3) INTERACT rivetvia2
met2stackBus = WITH WIDTH met2stack >= 25.0
met2stackBusCA = met2stackBus AND critAreaStress
met2UppBus = (WITH WIDTH met3 >= 25.0) NOT exemptStressCells
met2stack_uppBus = met2stackBus AND met2UppBus
met2stack_encErr_tmp = ((ENCLOSURE met2stack met3 < 1.0 ABUT < 89.5 SINGULAR REGION) NOT SEALID) AND critAreaStress
met2stack_encErr = met2stack_encErr_tmp INTERACT (met2stack_encErr_tmp AND met2stack_uppBus)
met2stackStrUpp = (met2OverCA NOT met2stack) COINCIDENT OUTSIDE EDGE met2stack
met2stackStrUppSz05 = (EXPAND EDGE met2stackStrUpp INSIDE BY 0.5) NOT CUT met2OverCA
met2stackStrUppExempt = met2stackStrUppSz05 COINCIDENT OUTSIDE EDGE met2stack
met2stack_encErrFinal = met2stack_encErr NOT (EXPAND EDGE met2stackStrUppExempt OUTSIDE BY 0.005)
CONNECT met2stackBusCA via2
met2stackNoSlots = ((met2OverCA OR met2slot) AND (met3 OR met3slot)) INTERACT rivetvia2
met2stackBusNoSlots = WITH WIDTH met2stackNoSlots >= 25.0
met2stackBusCA_NoSlots = met2stackBusNoSlots AND critAreaStress
met2Low_slot_stack = met2slot AND met2stackBusCA_NoSlots
met3Upp_slot_stack = met3slot AND met2stackBusCA_NoSlots
err_coin_slots_met2 = ((met2Low_slot_stack NOT ENCLOSE met3Upp_slot_stack) INTERACT ((met2Low_slot_stack NOT ENCLOSE met3Upp_slot_stack) AND critAreaStress)) NOT (EXTENT CELL "pad_bond*" ORIGINAL)
met2.stress.CON.9 {
    @ met2.slot.CON.9: met2 in lower slotted stack should enclose met3 in the upper slotted stack.
    COPY err_coin_slots_met2
}
met2.stress.ENC.1 {
    @ met2.stress.ENC.1: Min enclosure of met3 in a slotted stack by met2 in slotted stack < 1.0
    ENCLOSURE (met3Upp_slot_stack AND met2Low_slot_stack) met2Low_slot_stack < 1.0 MEASURE ALL ABUT < 90 SINGULAR
}
met2.stress.ENC.2 {
    @ met2.stress.ENC.2: Min enclosure of a met2 stack bus by met3 bus < 1.0
    COPY met2stack_encErrFinal
}
met2.stress.DEN.1 {
    @ met2.stress.DEN.1: Min via2 density on wide met2 and met3 bus stack is 3.00 percent
    NET AREA RATIO met2stackBusCA via2 < 0.03 [AREA(via2)/AREA(met2stackBusCA)] RDB met2.stress.DEN.1.db met2stackBusCA via2
}
rivetvia3 = via3 NOT (SEALID OR (exemptStressCells OR padPcells))
met3stack = (met3OverCA AND met4) INTERACT rivetvia3
met3stackBus = WITH WIDTH met3stack >= 25.0
met3stackBusCA = met3stackBus AND critAreaStress
met3UppBus = (WITH WIDTH met4 >= 25.0) NOT exemptStressCells
met3stack_uppBus = met3stackBus AND met3UppBus
met3stack_encErr_tmp = ((ENCLOSURE met3stack met4 < 1.0 ABUT < 89.5 SINGULAR REGION) NOT SEALID) AND critAreaStress
met3stack_encErr = met3stack_encErr_tmp INTERACT (met3stack_encErr_tmp AND met3stack_uppBus)
met3stackStrUpp = (met3OverCA NOT met3stack) COINCIDENT OUTSIDE EDGE met3stack
met3stackStrUppSz05 = (EXPAND EDGE met3stackStrUpp INSIDE BY 0.5) NOT CUT met3OverCA
met3stackStrUppExempt = met3stackStrUppSz05 COINCIDENT OUTSIDE EDGE met3stack
met3stack_encErrFinal = met3stack_encErr NOT (EXPAND EDGE met3stackStrUppExempt OUTSIDE BY 0.005)
CONNECT met3stackBusCA via3
met3stackNoSlots = ((met3OverCA OR met3slot) AND (met4 OR met4slot)) INTERACT rivetvia3
met3stackBusNoSlots = WITH WIDTH met3stackNoSlots >= 25.0
met3stackBusCA_NoSlots = met3stackBusNoSlots AND critAreaStress
met3Low_slot_stack = met3slot AND met3stackBusCA_NoSlots
met4Upp_slot_stack = met4slot AND met3stackBusCA_NoSlots
err_coin_slots_met3 = ((met3Low_slot_stack NOT ENCLOSE met4Upp_slot_stack) INTERACT ((met3Low_slot_stack NOT ENCLOSE met4Upp_slot_stack) AND critAreaStress)) NOT (EXTENT CELL "pad_bond*" ORIGINAL)
met3.stress.CON.9 {
    @ met3.slot.CON.9: met3 in lower slotted stack should enclose met4 in the upper slotted stack.
    COPY err_coin_slots_met3
}
met3.stress.ENC.1 {
    @ met3.stress.ENC.1: Min enclosure of met4 in a slotted stack by met3 in slotted stack < 1.0
    ENCLOSURE (met4Upp_slot_stack AND met3Low_slot_stack) met3Low_slot_stack < 1.0 MEASURE ALL ABUT < 90 SINGULAR
}
met3.stress.ENC.2 {
    @ met3.stress.ENC.2: Min enclosure of a met3 stack bus by met4 bus < 1.0
    COPY met3stack_encErrFinal
}
met3.stress.DEN.1 {
    @ met3.stress.DEN.1: Min via3 density on wide met3 and met4 bus stack is 3.00 percent
    NET AREA RATIO met3stackBusCA via3 < 0.03 [AREA(via3)/AREA(met3stackBusCA)] RDB met3.stress.DEN.1.db met3stackBusCA via3
}
rivetvia4 = via4 NOT (SEALID OR (exemptStressCells OR padPcells))
met4stack = (met4OverCA AND met5) INTERACT rivetvia4
met4stackBus = WITH WIDTH met4stack >= 25.0
met4stackBusCA = met4stackBus AND critAreaStress
met4UppBus = (WITH WIDTH met5 >= 25.0) NOT exemptStressCells
met4stack_uppBus = met4stackBus AND met4UppBus
met4stack_encErr_tmp = ((ENCLOSURE met4stack met5 < 1.0 ABUT < 89.5 SINGULAR REGION) NOT SEALID) AND critAreaStress
met4stack_encErr = met4stack_encErr_tmp INTERACT (met4stack_encErr_tmp AND met4stack_uppBus)
met4stackStrUpp = (met4OverCA NOT met4stack) COINCIDENT OUTSIDE EDGE met4stack
met4stackStrUppSz05 = (EXPAND EDGE met4stackStrUpp INSIDE BY 0.5) NOT CUT met4OverCA
met4stackStrUppExempt = met4stackStrUppSz05 COINCIDENT OUTSIDE EDGE met4stack
met4stack_encErrFinal = met4stack_encErr NOT (EXPAND EDGE met4stackStrUppExempt OUTSIDE BY 0.005)
CONNECT met4stackBusCA via4
met4stackNoSlots = ((met4OverCA OR met4slot) AND (met5 OR met5slot)) INTERACT rivetvia4
met4stackBusNoSlots = WITH WIDTH met4stackNoSlots >= 25.0
met4stackBusCA_NoSlots = met4stackBusNoSlots AND critAreaStress
met4Low_slot_stack = met4slot AND met4stackBusCA_NoSlots
met5Upp_slot_stack = met5slot AND met4stackBusCA_NoSlots
err_coin_slots_met4 = ((met4Low_slot_stack NOT ENCLOSE met5Upp_slot_stack) INTERACT ((met4Low_slot_stack NOT ENCLOSE met5Upp_slot_stack) AND critAreaStress)) NOT (EXTENT CELL "pad_bond*" ORIGINAL)
met4.stress.CON.9 {
    @ met4.slot.CON.9: met4 in lower slotted stack should enclose met5 in the upper slotted stack.
    COPY err_coin_slots_met4
}
met4.stress.ENC.1 {
    @ met4.stress.ENC.1: Min enclosure of met5 in a slotted stack by met4 in slotted stack < 1.0
    ENCLOSURE (met5Upp_slot_stack AND met4Low_slot_stack) met4Low_slot_stack < 1.0 MEASURE ALL ABUT < 90 SINGULAR
}
met4.stress.ENC.2 {
    @ met4.stress.ENC.2: Min enclosure of a met4 stack bus by met5 bus < 1.0
    COPY met4stack_encErrFinal
}
met4.stress.DEN.1 {
    @ met4.stress.DEN.1: Min via4 density on wide met4 and met5 bus stack is 3.00 percent
    NET AREA RATIO met4stackBusCA via4 < 0.03 [AREA(via4)/AREA(met4stackBusCA)] RDB met4.stress.DEN.1.db met4stackBusCA via4
}
met1Shielda = COPY 4004
met1_over_crit_area = WITH WIDTH ((INTERACT (filled_met1 NOT met1Shielda) ((filled_met1 NOT met1Shielda) AND met1slotAll)) AND critAreaStress) > 25.0
CONNECT met1_over_crit_area met1slotAll
met1.slot.DEN.1 {
    @ met1.slot.DEN.1: Min slot density on wide met1 bus < 7.50%
    NET AREA RATIO met1_over_crit_area met1slotAll < 0.075 [AREA(met1slotAll)/AREA(met1_over_crit_area)] RDB met1.slot.DEN.1.db met1_over_crit_area met1slotAll
}
met2_over_crit_area = WITH WIDTH ((INTERACT filled_met2 (filled_met2 AND met2slotAll)) AND critAreaStress) > 25.0
CONNECT met2_over_crit_area met2slotAll
met2.slot.DEN.1 {
    @ met2.slot.DEN.1: Min slot density on wide met2 bus < 7.50%
    NET AREA RATIO met2_over_crit_area met2slotAll < 0.075 [AREA(met2slotAll)/AREA(met2_over_crit_area)] RDB met2.slot.DEN.1.db met2_over_crit_area met2slotAll
}
met3_over_crit_area = WITH WIDTH ((INTERACT filled_met3 (filled_met3 AND met3slotAll)) AND critAreaStress) > 25.0
CONNECT met3_over_crit_area met3slotAll
met3.slot.DEN.1 {
    @ met3.slot.DEN.1: Min slot density on wide met3 bus < 7.50%
    NET AREA RATIO met3_over_crit_area met3slotAll < 0.075 [AREA(met3slotAll)/AREA(met3_over_crit_area)] RDB met3.slot.DEN.1.db met3_over_crit_area met3slotAll
}
met4_over_crit_area = WITH WIDTH ((INTERACT filled_met4 (filled_met4 AND met4slotAll)) AND critAreaStress) > 25.0
CONNECT met4_over_crit_area met4slotAll
met4.slot.DEN.1 {
    @ met4.slot.DEN.1: Min slot density on wide met4 bus < 7.50%
    NET AREA RATIO met4_over_crit_area met4slotAll < 0.075 [AREA(met4slotAll)/AREA(met4_over_crit_area)] RDB met4.slot.DEN.1.db met4_over_crit_area met4slotAll
}
met5_over_crit_area = WITH WIDTH ((INTERACT filled_met5 (filled_met5 AND met5slotAll)) AND critAreaStress) > 25.0
CONNECT met5_over_crit_area met5slotAll
met5.slot.DEN.1 {
    @ met5.slot.DEN.1: Min slot density on wide met5 bus < 7.50%
    NET AREA RATIO met5_over_crit_area met5slotAll < 0.075 [AREA(met5slotAll)/AREA(met5_over_crit_area)] RDB met5.slot.DEN.1.db met5_over_crit_area met5slotAll
}
met1OverCAnoSlot = INTERACT (WITH WIDTH (met1OverCA NOT met1Shielda) > 25.0) ((WITH WIDTH (met1OverCA NOT met1Shielda) > 25.0) AND critAreaStress)
met1.slot.CON.1 {
    @ met1.slot.CON.1: met1 wider than 25um inside areaid:critCorner or areaid:critSid must contain slot
    COPY met1OverCAnoSlot
}
met1.slot.SP.1 {
    @ met1.slot.SP.1: Min spacing of met1 slot < 2.3
    EXTERNAL met1slot < 2.3 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE
}
met2OverCAnoSlot = INTERACT (WITH WIDTH met2OverCA > 25.0) ((WITH WIDTH met2OverCA > 25.0) AND critAreaStress)
met2.slot.CON.1 {
    @ met2.slot.CON.1: met2 wider than 25um inside areaid:critCorner or areaid:critSid must contain slot
    COPY met2OverCAnoSlot
}
met2.slot.SP.1 {
    @ met2.slot.SP.1: Min spacing of met2 slot < 2.3
    EXTERNAL met2slot < 2.3 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE
}
met3OverCAnoSlot = INTERACT (WITH WIDTH met3OverCA > 25.0) ((WITH WIDTH met3OverCA > 25.0) AND critAreaStress)
met3.slot.CON.1 {
    @ met3.slot.CON.1: met3 wider than 25um inside areaid:critCorner or areaid:critSid must contain slot
    COPY met3OverCAnoSlot
}
met3.slot.SP.1 {
    @ met3.slot.SP.1: Min spacing of met3 slot < 2.3
    EXTERNAL met3slot < 2.3 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE
}
met4OverCAnoSlot = INTERACT (WITH WIDTH met4OverCA > 25.0) ((WITH WIDTH met4OverCA > 25.0) AND critAreaStress)
met4.slot.CON.1 {
    @ met4.slot.CON.1: met4 wider than 25um inside areaid:critCorner or areaid:critSid must contain slot
    COPY met4OverCAnoSlot
}
met4.slot.SP.1 {
    @ met4.slot.SP.1: Min spacing of met4 slot < 2.3
    EXTERNAL met4slot < 2.3 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE
}
slotMetXmt = met5 AND padPcells
met5OverCAnoSlot = INTERACT (WITH WIDTH (met5OverCA NOT slotMetXmt) > 25.0) ((WITH WIDTH (met5OverCA NOT slotMetXmt) > 25.0) AND critAreaStress)
met5.slot.CON.1 {
    @ met5.slot.CON.1: met5 wider than 25um inside areaid:critCorner or areaid:critSid must contain slot
    COPY met5OverCAnoSlot
}
met5.slot.SP.1 {
    @ met5.slot.SP.1: Min spacing of met5 slot < 2.3
    EXTERNAL met5slot < 2.3 ABUT < 90 SINGULAR REGION SPACE EXCLUDE FALSE
}
met1_slotShortLen = LENGTH met1slot >= 2.3 <= 10.0
met1_slotShortLenSz = EXPAND EDGE met1_slotShortLen OUTSIDE BY 0.005
met1_slotShortLen1 = EXPAND EDGE (LENGTH met1_slotShortLenSz == 0.005) INSIDE BY 0.005
met1_slotShortLenSpc25 = EXTERNAL met1_slotShortLen1 <= 25.0 PARALLEL OPPOSITE REGION
met1_slotShortLen15err1 = INTERACT (met1_slotShortLenSpc25 NOT (INTERACT met1_slotShortLenSpc25 (met1_slotShortLenSpc25 AND met1slot))) (EXPAND EDGE ((met1_slotShortLenSpc25 NOT (INTERACT met1_slotShortLenSpc25 (met1_slotShortLenSpc25 AND met1slot))) COINCIDENT OUTSIDE EDGE met1slot) BY 0.005 EXTEND BY 0.005) >= 2
met1_slotShortLen15err = INTERACT (INTERACT met1_slotShortLen15err1 (met1_slotShortLen15err1 AND met1_slotShortLenSz) >= 2) ((INTERACT met1_slotShortLen15err1 (met1_slotShortLen15err1 AND met1_slotShortLenSz) >= 2) AND critAreaStress)
met1.slot.CON.2 {
    @ met1.slot.CON.2: Start and end points of met1 slots spaced <= 25.00um apart in adjacent rows must be offset
    COPY met1_slotShortLen15err
}
met2_slotShortLen = LENGTH met2slot >= 2.3 <= 10.0
met2_slotShortLenSz = EXPAND EDGE met2_slotShortLen OUTSIDE BY 0.005
met2_slotShortLen1 = EXPAND EDGE (LENGTH met2_slotShortLenSz == 0.005) INSIDE BY 0.005
met2_slotShortLenSpc25 = EXTERNAL met2_slotShortLen1 <= 25.0 PARALLEL OPPOSITE REGION
met2_slotShortLen15err1 = INTERACT (met2_slotShortLenSpc25 NOT (INTERACT met2_slotShortLenSpc25 (met2_slotShortLenSpc25 AND met2slot))) (EXPAND EDGE ((met2_slotShortLenSpc25 NOT (INTERACT met2_slotShortLenSpc25 (met2_slotShortLenSpc25 AND met2slot))) COINCIDENT OUTSIDE EDGE met2slot) BY 0.005 EXTEND BY 0.005) >= 2
met2_slotShortLen15err = INTERACT (INTERACT met2_slotShortLen15err1 (met2_slotShortLen15err1 AND met2_slotShortLenSz) >= 2) ((INTERACT met2_slotShortLen15err1 (met2_slotShortLen15err1 AND met2_slotShortLenSz) >= 2) AND critAreaStress)
met2.slot.CON.2 {
    @ met2.slot.CON.2: Start and end points of met2 slots spaced <= 25.00um apart in adjacent rows must be offset
    COPY met2_slotShortLen15err
}
met3_slotShortLen = LENGTH met3slot >= 2.3 <= 10.0
met3_slotShortLenSz = EXPAND EDGE met3_slotShortLen OUTSIDE BY 0.005
met3_slotShortLen1 = EXPAND EDGE (LENGTH met3_slotShortLenSz == 0.005) INSIDE BY 0.005
met3_slotShortLenSpc25 = EXTERNAL met3_slotShortLen1 <= 25.0 PARALLEL OPPOSITE REGION
met3_slotShortLen15err1 = INTERACT (met3_slotShortLenSpc25 NOT (INTERACT met3_slotShortLenSpc25 (met3_slotShortLenSpc25 AND met3slot))) (EXPAND EDGE ((met3_slotShortLenSpc25 NOT (INTERACT met3_slotShortLenSpc25 (met3_slotShortLenSpc25 AND met3slot))) COINCIDENT OUTSIDE EDGE met3slot) BY 0.005 EXTEND BY 0.005) >= 2
met3_slotShortLen15err = INTERACT (INTERACT met3_slotShortLen15err1 (met3_slotShortLen15err1 AND met3_slotShortLenSz) >= 2) ((INTERACT met3_slotShortLen15err1 (met3_slotShortLen15err1 AND met3_slotShortLenSz) >= 2) AND critAreaStress)
met3.slot.CON.2 {
    @ met3.slot.CON.2: Start and end points of met3 slots spaced <= 25.00um apart in adjacent rows must be offset
    COPY met3_slotShortLen15err
}
met4_slotShortLen = LENGTH met4slot >= 2.3 <= 10.0
met4_slotShortLenSz = EXPAND EDGE met4_slotShortLen OUTSIDE BY 0.005
met4_slotShortLen1 = EXPAND EDGE (LENGTH met4_slotShortLenSz == 0.005) INSIDE BY 0.005
met4_slotShortLenSpc25 = EXTERNAL met4_slotShortLen1 <= 25.0 PARALLEL OPPOSITE REGION
met4_slotShortLen15err1 = INTERACT (met4_slotShortLenSpc25 NOT (INTERACT met4_slotShortLenSpc25 (met4_slotShortLenSpc25 AND met4slot))) (EXPAND EDGE ((met4_slotShortLenSpc25 NOT (INTERACT met4_slotShortLenSpc25 (met4_slotShortLenSpc25 AND met4slot))) COINCIDENT OUTSIDE EDGE met4slot) BY 0.005 EXTEND BY 0.005) >= 2
met4_slotShortLen15err = INTERACT (INTERACT met4_slotShortLen15err1 (met4_slotShortLen15err1 AND met4_slotShortLenSz) >= 2) ((INTERACT met4_slotShortLen15err1 (met4_slotShortLen15err1 AND met4_slotShortLenSz) >= 2) AND critAreaStress)
met4.slot.CON.2 {
    @ met4.slot.CON.2: Start and end points of met4 slots spaced <= 25.00um apart in adjacent rows must be offset
    COPY met4_slotShortLen15err
}
met5_slotShortLen = LENGTH met5slot >= 2.3 <= 10.0
met5_slotShortLenSz = EXPAND EDGE met5_slotShortLen OUTSIDE BY 0.005
met5_slotShortLen1 = EXPAND EDGE (LENGTH met5_slotShortLenSz == 0.005) INSIDE BY 0.005
met5_slotShortLenSpc25 = EXTERNAL met5_slotShortLen1 <= 25.0 PARALLEL OPPOSITE REGION
met5_slotShortLen15err1 = INTERACT (met5_slotShortLenSpc25 NOT (INTERACT met5_slotShortLenSpc25 (met5_slotShortLenSpc25 AND met5slot))) (EXPAND EDGE ((met5_slotShortLenSpc25 NOT (INTERACT met5_slotShortLenSpc25 (met5_slotShortLenSpc25 AND met5slot))) COINCIDENT OUTSIDE EDGE met5slot) BY 0.005 EXTEND BY 0.005) >= 2
met5_slotShortLen15err = INTERACT (INTERACT met5_slotShortLen15err1 (met5_slotShortLen15err1 AND met5_slotShortLenSz) >= 2) ((INTERACT met5_slotShortLen15err1 (met5_slotShortLen15err1 AND met5_slotShortLenSz) >= 2) AND critAreaStress)
met5.slot.CON.2 {
    @ met5.slot.CON.2: Start and end points of met5 slots spaced <= 25.00um apart in adjacent rows must be offset
    COPY met5_slotShortLen15err
}
allay_first = chip_area NOT critAreaStress
q0lay = (dnwell AND critAreaStress) OR allay_first
q1lay = (nwell AND critAreaStress) OR q0lay
q2lay = (diff AND critAreaStress) OR q1lay
q3lay = (tap AND critAreaStress) OR q2lay
q4lay = (lvtn AND critAreaStress) OR q3lay
q5lay = (hvtp AND critAreaStress) OR q4lay
q6lay = (v5 AND critAreaStress) OR q5lay
q7lay = (poly AND critAreaStress) OR q6lay
q8lay = (npc AND critAreaStress) OR q7lay
q9lay = (nsdm AND critAreaStress) OR q8lay
q10lay = (psdm AND critAreaStress) OR q9lay
q11lay = (tunm AND critAreaStress) OR q10lay
q12lay = (licon AND critAreaStress) OR q11lay
q13lay = (li AND critAreaStress) OR q12lay
q14lay = (mcon AND critAreaStress) OR q13lay
q15lay = (met1 AND critAreaStress) OR q14lay
q16lay = (via1 AND critAreaStress) OR q15lay
q17lay = (met2 AND critAreaStress) OR q16lay
q18lay = (via2 AND critAreaStress) OR q17lay
q19lay = (met3 AND critAreaStress) OR q18lay
q20lay = (via3 AND critAreaStress) OR q19lay
q21lay = (met4 AND critAreaStress) OR q20lay
q22lay = (via4 AND critAreaStress) OR q21lay
q23lay = (met5 AND critAreaStress) OR q22lay
q24lay = (v12 AND critAreaStress) OR q23lay
q25lay = (pad AND critAreaStress) OR q24lay
q26lay = (pnp AND critAreaStress) OR q25lay
allay = COPY q26lay
openArea = DENSITY allay <= 0 WINDOW 50 STEP 25 RDB anchor.1_density.db
openAreaAnc = WITH WIDTH (openArea AND (INTERACT critAreaStress (critAreaStress AND SEALID))) >= 50.0
anchor.CON.1 {
    @ anchor.CON.1: Open area anchors needed in any open window of 50umx50um in areaid:critCorner or areaid:critSid area
    COPY openAreaAnc
}
poly.anchor.WID.1 {
    @ poly.anchor.WID.1: Min width of poly overlapping anchor < 3.0
    INTERNAL (poly AND anchorStress) < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
li.anchor.WID.1 {
    @ li.anchor.WID.1: Min width of li overlapping anchor < 3.0
    INTERNAL (li AND anchorStress) < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met1.anchor.WID.1 {
    @ met1.anchor.WID.1: Min width of met1 overlapping anchor < 3.0
    INTERNAL (met1 AND anchorStress) < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met2.anchor.WID.1 {
    @ met2.anchor.WID.1: Min width of met2 overlapping anchor < 3.0
    INTERNAL (met2 AND anchorStress) < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met3.anchor.WID.1 {
    @ met3.anchor.WID.1: Min width of met3 overlapping anchor < 3.0
    INTERNAL (met3 AND anchorStress) < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met4.anchor.WID.1 {
    @ met4.anchor.WID.1: Min width of met4 overlapping anchor < 3.0
    INTERNAL (met4 AND anchorStress) < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
met5.anchor.WID.1 {
    @ met5.anchor.WID.1: Min width of met5 overlapping anchor < 3.0
    INTERNAL (met5 AND anchorStress) < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
anchor.SP.1 {
    @ anchor.SP.1: Min spacing/notch of anchor < 5.0
    EXTERNAL anchorStress < 5.0 ABUT < 90 SINGULAR REGION
}
licon_anc = licon AND anchorStress
via1_anc = via1 AND anchorStress
via2_anc = via2 AND anchorStress
via3_anc = via3 AND anchorStress
via4_anc = via4 AND anchorStress
mcon_anc = mcon AND anchorStress
licon.mcon.anchor.CON.2 {
    @ licon.mcon.anchor.CON.2: licon in anchor must not overlap mcon in anchor
    AND licon_anc mcon_anc
}
licon.via1.anchor.CON.2 {
    @ licon.via1.anchor.CON.2: licon in anchor must not overlap via1 in anchor
    AND licon_anc via1_anc
}
licon.via2.anchor.CON.2 {
    @ licon.via2.anchor.CON.2: licon in anchor must not overlap via2 in anchor
    AND licon_anc via2_anc
}
licon.via3.anchor.CON.2 {
    @ licon.via3.anchor.CON.2: licon in anchor must not overlap via3 in anchor
    AND licon_anc via3_anc
}
licon.via4.anchor.CON.2 {
    @ licon.via4.anchor.CON.2: licon in anchor must not overlap via4 in anchor
    AND licon_anc via4_anc
}
via1.via2.anchor.CON.2 {
    @ via1.via2.anchor.CON.2: via1 in anchor must not overlap via2 in anchor
    AND via1_anc via2_anc
}
via1.via3.anchor.CON.2 {
    @ via1.via3.anchor.CON.2: via1 in anchor must not overlap via3 in anchor
    AND via1_anc via3_anc
}
via1.via4.anchor.CON.2 {
    @ via1.via4.anchor.CON.2: via1 in anchor must not overlap via4 in anchor
    AND via1_anc via4_anc
}
via1.mcon.anchor.CON.2 {
    @ via1.mcon.anchor.CON.2: via1 in anchor must not overlap mcon in anchor
    AND via1_anc mcon_anc
}
via2.via3.anchor.CON.2 {
    @ via2.via3.anchor.CON.2: via2 in anchor must not overlap via3 in anchor
    AND via2_anc via3_anc
}
via2.via4.anchor.CON.2 {
    @ via2.via4.anchor.CON.2: via2 in anchor must not overlap via4 in anchor
    AND via2_anc via4_anc
}
via2.mcon.anchor.CON.2 {
    @ via2.mcon.anchor.CON.2: via2 in anchor must not overlap mcon in anchor
    AND via2_anc mcon_anc
}
via3.via4.anchor.CON.2 {
    @ via3.via4.anchor.CON.2: via3 in anchor must not overlap via4 in anchor
    AND via3_anc via4_anc
}
via3.mcon.anchor.CON.2 {
    @ via3.mcon.anchor.CON.2: via3 in anchor must not overlap mcon in anchor
    AND via3_anc mcon_anc
}
via4.mcon.anchor.CON.2 {
    @ via4.mcon.anchor.CON.2: via4 in anchor must not overlap mcon in anchor
    AND via4_anc mcon_anc
}
licon.anchor.SP.1 {
    @ licon.anchor.SP.1: Min spacing of licon overlapping anchor < 2.93
    EXTERNAL licon_anc < 2.93 ABUT < 90 SINGULAR REGION
}
mcon.anchor.SP.1 {
    @ mcon.anchor.SP.1: Min spacing of mcon overlapping anchor < 2.93
    EXTERNAL mcon_anc < 2.93 ABUT < 90 SINGULAR REGION
}
via1.anchor.SP.1 {
    @ via1.anchor.SP.1: Min spacing of via1 overlapping anchor < 2.95
    EXTERNAL via1_anc < 2.95 ABUT < 90 SINGULAR REGION
}
via2.anchor.SP.1 {
    @ via2.anchor.SP.1: Min spacing of via2 overlapping anchor < 2.9
    EXTERNAL via2_anc < 2.9 ABUT < 90 SINGULAR REGION
}
via3.anchor.SP.1 {
    @ via3.anchor.SP.1: Min spacing of via3 overlapping anchor < 2.9
    EXTERNAL via3_anc < 2.9 ABUT < 90 SINGULAR REGION
}
via4.anchor.SP.1 {
    @ via4.anchor.SP.1: Min spacing of via4 overlapping anchor < 2.3
    EXTERNAL via4_anc < 2.3 ABUT < 90 SINGULAR REGION
}
met1CrossAnc = CUT met1 anchorStress
via1LowOutsideAnc = via0 OUTSIDE anchorStress
via1UppOutsideAnc = via1 OUTSIDE anchorStress
met1CrossAncCon = (INTERACT met1CrossAnc (met1CrossAnc AND via1LowOutsideAnc)) OR (INTERACT met1CrossAnc (met1CrossAnc AND via1UppOutsideAnc))
met1.anchor.connect.CON.1 {
    @ met1.anchor.connect.CON.1: met1 inside ANCHOR region cannot connect to any other metal bus
    COPY met1CrossAncCon
}
met2CrossAnc = CUT met2 anchorStress
via2LowOutsideAnc = via1 OUTSIDE anchorStress
via2UppOutsideAnc = via2 OUTSIDE anchorStress
met2CrossAncCon = (INTERACT met2CrossAnc (met2CrossAnc AND via2LowOutsideAnc)) OR (INTERACT met2CrossAnc (met2CrossAnc AND via2UppOutsideAnc))
met2.anchor.connect.CON.1 {
    @ met2.anchor.connect.CON.1: met2 inside ANCHOR region cannot connect to any other metal bus
    COPY met2CrossAncCon
}
met3CrossAnc = CUT met3 anchorStress
via3LowOutsideAnc = via2 OUTSIDE anchorStress
via3UppOutsideAnc = via3 OUTSIDE anchorStress
met3CrossAncCon = (INTERACT met3CrossAnc (met3CrossAnc AND via3LowOutsideAnc)) OR (INTERACT met3CrossAnc (met3CrossAnc AND via3UppOutsideAnc))
met3.anchor.connect.CON.1 {
    @ met3.anchor.connect.CON.1: met3 inside ANCHOR region cannot connect to any other metal bus
    COPY met3CrossAncCon
}
met4CrossAnc = CUT met4 anchorStress
via4LowOutsideAnc = via3 OUTSIDE anchorStress
via4UppOutsideAnc = via4 OUTSIDE anchorStress
met4CrossAncCon = (INTERACT met4CrossAnc (met4CrossAnc AND via4LowOutsideAnc)) OR (INTERACT met4CrossAnc (met4CrossAnc AND via4UppOutsideAnc))
met4.anchor.connect.CON.1 {
    @ met4.anchor.connect.CON.1: met4 inside ANCHOR region cannot connect to any other metal bus
    COPY met4CrossAncCon
}
met5CrossAnc = CUT met5 anchorStress
BONDPADLowOutsideAnc = via4 OUTSIDE anchorStress
met5CrossAncCon = INTERACT met5CrossAnc (met5CrossAnc AND BONDPADLowOutsideAnc)
met5.anchor.connect.CON.1 {
    @ met5.anchor.connect.CON.1: met5 of ANCHOR cannot connect to any other metal bus
    COPY met5CrossAncCon
}
poly.licon.anchor.WARN.1 {
    @ poly.licon.anchor.WARN.1: This poly anchor region must contain additional licon
    center_anchor = (INT (poly INTERACT licon_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (licon INTERACT (poly INTERACT licon_anc))
    center_anchor_edge_len_a = NOT COINCIDENT EDGE center_anchor poly
    center_anchor_edge_len = NOT COINCIDENT EDGE center_anchor_edge_len_a licon
    error_anchor = LENGTH center_anchor_edge_len > 10
    exp_err_anc1 = (EXPAND EDGE error_anchor OUTSIDE BY 3) AND poly
    exp_err_anc2 = (EXPAND EDGE error_anchor INSIDE BY 3) AND poly
    OR exp_err_anc1 exp_err_anc2
}
li.licon.anchor.WARN.1 {
    @ li.licon.anchor.WARN.1: This li anchor region must contain additional licon
    center_anchor = (INT (li INTERACT licon_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (licon INTERACT (li INTERACT licon_anc))
    center_anchor_edge_len_a = NOT COINCIDENT EDGE center_anchor li
    center_anchor_edge_len = NOT COINCIDENT EDGE center_anchor_edge_len_a licon
    error_anchor = LENGTH center_anchor_edge_len > 10
    exp_err_anc1 = (EXPAND EDGE error_anchor OUTSIDE BY 3) AND li
    exp_err_anc2 = (EXPAND EDGE error_anchor INSIDE BY 3) AND li
    OR exp_err_anc1 exp_err_anc2
}
li.mcon.anchor.WARN.1 {
    @ li.mcon.anchor.WARN.1: This li anchor region must contain additional mcon
    center_anchor = (INT (li INTERACT mcon_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (mcon INTERACT (li INTERACT mcon_anc))
    center_anchor_edge_len_a = NOT COINCIDENT EDGE center_anchor li
    center_anchor_edge_len = NOT COINCIDENT EDGE center_anchor_edge_len_a mcon
    error_anchor = LENGTH center_anchor_edge_len > 10
    exp_err_anc1 = (EXPAND EDGE error_anchor OUTSIDE BY 3) AND li
    exp_err_anc2 = (EXPAND EDGE error_anchor INSIDE BY 3) AND li
    OR exp_err_anc1 exp_err_anc2
}
met1.mcon.anchor.WARN.1 {
    @ met1.mcon.anchor.WARN.1: This met1 anchor region must contain additional mcon
    center_anchor = (INT (met1 INTERACT mcon_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (mcon INTERACT (met1 INTERACT mcon_anc))
    center_anchor_edge_len_a = NOT COINCIDENT EDGE center_anchor met1
    center_anchor_edge_len = NOT COINCIDENT EDGE center_anchor_edge_len_a mcon
    error_anchor = LENGTH center_anchor_edge_len > 10
    exp_err_anc1 = (EXPAND EDGE error_anchor OUTSIDE BY 3) AND met1
    exp_err_anc2 = (EXPAND EDGE error_anchor INSIDE BY 3) AND met1
    OR exp_err_anc1 exp_err_anc2
}
met1.via1.anchor.WARN.1 {
    @ met1.via1.anchor.WARN.1: This met1 anchor region must contain additional via1
    center_anchor = (INT (met1 INTERACT via1_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (via1 INTERACT (met1 INTERACT via1_anc))
    center_anchor_edge_len_a = NOT COINCIDENT EDGE center_anchor met1
    center_anchor_edge_len = NOT COINCIDENT EDGE center_anchor_edge_len_a via1
    error_anchor = LENGTH center_anchor_edge_len > 10
    exp_err_anc1 = (EXPAND EDGE error_anchor OUTSIDE BY 3) AND met1
    exp_err_anc2 = (EXPAND EDGE error_anchor INSIDE BY 3) AND met1
    OR exp_err_anc1 exp_err_anc2
}
met2.via1.anchor.WARN.1 {
    @ met2.via1.anchor.WARN.1: This met2 anchor region must contain additional via1
    center_anchor = (INT (met2 INTERACT via1_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (via1 INTERACT (met2 INTERACT via1_anc))
    center_anchor_edge_len_a = NOT COINCIDENT EDGE center_anchor met2
    center_anchor_edge_len = NOT COINCIDENT EDGE center_anchor_edge_len_a via1
    error_anchor = LENGTH center_anchor_edge_len > 10
    exp_err_anc1 = (EXPAND EDGE error_anchor OUTSIDE BY 3) AND met2
    exp_err_anc2 = (EXPAND EDGE error_anchor INSIDE BY 3) AND met2
    OR exp_err_anc1 exp_err_anc2
}
met2.via2.anchor.WARN.1 {
    @ met2.via2.anchor.WARN.1: This met2 anchor region must contain additional via2
    center_anchor = (INT (met2 INTERACT via2_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (via2 INTERACT (met2 INTERACT via2_anc))
    center_anchor_edge_len_a = NOT COINCIDENT EDGE center_anchor met2
    center_anchor_edge_len = NOT COINCIDENT EDGE center_anchor_edge_len_a via2
    error_anchor = LENGTH center_anchor_edge_len > 10
    exp_err_anc1 = (EXPAND EDGE error_anchor OUTSIDE BY 3) AND met2
    exp_err_anc2 = (EXPAND EDGE error_anchor INSIDE BY 3) AND met2
    OR exp_err_anc1 exp_err_anc2
}
met3.via2.anchor.WARN.1 {
    @ met3.via2.anchor.WARN.1: This met3 anchor region must contain additional via2
    center_anchor = (INT (met3 INTERACT via2_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (via2 INTERACT (met3 INTERACT via2_anc))
    center_anchor_edge_len_a = NOT COINCIDENT EDGE center_anchor met3
    center_anchor_edge_len = NOT COINCIDENT EDGE center_anchor_edge_len_a via2
    error_anchor = LENGTH center_anchor_edge_len > 10
    exp_err_anc1 = (EXPAND EDGE error_anchor OUTSIDE BY 3) AND met3
    exp_err_anc2 = (EXPAND EDGE error_anchor INSIDE BY 3) AND met3
    OR exp_err_anc1 exp_err_anc2
}
met3.via3.anchor.WARN.1 {
    @ met3.via3.anchor.WARN.1: This met3 anchor region must contain additional via3
    center_anchor = (INT (met3 INTERACT via3_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (via3 INTERACT (met3 INTERACT via3_anc))
    center_anchor_edge_len_a = NOT COINCIDENT EDGE center_anchor met3
    center_anchor_edge_len = NOT COINCIDENT EDGE center_anchor_edge_len_a via3
    error_anchor = LENGTH center_anchor_edge_len > 10
    exp_err_anc1 = (EXPAND EDGE error_anchor OUTSIDE BY 3) AND met3
    exp_err_anc2 = (EXPAND EDGE error_anchor INSIDE BY 3) AND met3
    OR exp_err_anc1 exp_err_anc2
}
met4.via3.anchor.WARN.1 {
    @ met4.via3.anchor.WARN.1: This met4 anchor region must contain additional via3
    center_anchor = (INT (met4 INTERACT via3_anc) < 3.5 ABUT<90 OPPOSITE PARALLEL REGION CENTERLINE 0.10) NOT (via3 INTERACT (met4 INTERACT via3_anc))
    center_anchor_edge_len_a = NOT COINCIDENT EDGE center_anchor met4
    center_anchor_edge_len = NOT COINCIDENT EDGE center_anchor_edge_len_a via3
    error_anchor = LENGTH center_anchor_edge_len > 10
    exp_err_anc1 = (EXPAND EDGE error_anchor OUTSIDE BY 3) AND met4
    exp_err_anc2 = (EXPAND EDGE error_anchor INSIDE BY 3) AND met4
    OR exp_err_anc1 exp_err_anc2
}

#ENDIF


//
// DEEP NWELL (DNWELL) checks
//

////DISCONNECT
//////npccon = npc AND licon
////CONNECT dnwell nwell
////CONNECT nwell tap BY NTAP
////CONNECT tap li BY licon
////CONNECT poly li BY npccon
////CONNECT li met1 BY mcon
////CONNECT met1 met2 BY via1
////CONNECT met3 met2 BY via2
////CONNECT met3 met4 BY via3_c
////CONNECT met4 met5 BY via4_c
////CONNECT met5 pad
////CONNECT rdl pad


dnwell_in_v20 = dnwell AND v20
dnwell.WID.1 {
    @ dnwell.WID.1: Min width of deep nwell < 3.0
    INTERNAL dnwell < 3.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
dnwell.SP.1 {
    @ dnwell.SP.1: Min spacing/notch of deep nwell (exempt inside v20) < 6.3
    EXTERNAL (OUTSIDE dnwell v20) < 6.3 ABUT < 90 SINGULAR REGION
}
dnwell.CON.1 {
    @ dnwell.CON.1: deep nwell cannot overlap pnp drawing layer
    dnwell AND pnp
}
dnwell.CON.2 {
    @ dnwell.CON.2: pdiff cannot straddle deep nwell
    (diffi AND psdm) CUT dnwell
}
dnwell.CON.3 {
    @ dnwell.CON.3: deep nwell cannot straddle areaid:substratecut layer
    (dnwell CUT localSub) AND localSub
}
dnwell.CON.4 {
    @ dnwell.CON.4: dnwell must interact with nwell
    dnwell NOT INTERACT nwell
}
dnwell.SP.2 {
    @ dnwell.SP.2: Min spacing of dnwell in v20 on same net < 2.5
    EXTERNAL dnwell_in_v20 < 2.5 ABUT < 90 SINGULAR REGION CONNECTED
}
dnwell.SP.3 {
    @ dnwell.SP.3: Min spacing of dwnell in v20 not on same net < 12.0
    EXTERNAL dnwell_in_v20 < 12.0 ABUT < 90 SINGULAR REGION NOT CONNECTED
}
dnwell.SP.4 {
    @ dnwell.SP.4: Min spacing of dnwell in v20 to dnwell outside v20 < 12.0
    EXTERNAL dnwell_in_v20 (NOT dnwell v20)  < 12.0 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
dnwell.SP.5 {
    @ dnwell.SP.5: Min spacing of dnwell in v20 to nwell outside v20 < 9.5
    EXTERNAL dnwell_in_v20 (NOT nwell v20) < 9.5 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}


//
// Nwell checks
//


tech_CD_top_cells = EXTENT CELL "*_tech_CD_top*"
dnwellNotTechCD = dnwell NOT tech_CD_top_cells
nwellNotTechCD = nwell NOT tech_CD_top_cells
nwell_exempted_regions = OR v20 tech_CD_top_cells
nw_20v_1 = nwell INTERACT v20
nw_20v = STAMP nw_20v_1 BY nwell
nw_not_20v = nwell NOT nw_20v
nw_12v_1 = nw_not_20v INTERACT v12
nw_12v = STAMP nw_12v_1 BY nwell
nw_not_20v_or_12v = nwell NOT (OR nw_20v nw_12v)
nw_5v_1 = nw_not_20v_or_12v INTERACT v5
nw_5v = STAMP nw_5v_1 BY nwell
nw_1p8v_1 = nwell NOT INTERACT (OR v5 v12 v20)
nw_1p8v = STAMP nw_1p8v_1 BY nwell
nwell_outside_v20 = nwell NOT INTERACT v20
nwell.WID.1 {
    @ nwell.WID.1: Min width of nwell < 0.84
    INT nwell < 0.84 ABUT < 90 SINGULAR REGION EXCLUDE FALSE
}
nwell.SP.1 {
    @ nwell.SP.1: Min spacing/notch of 1.8v nwell < 1.27
    EXTERNAL nw_1p8v < 1.27 ABUT < 90 SINGULAR REGION
}
nwell.SP.2 {
    @ nwell.SP.2: Min spacing of 1.8v nwell to 5v nwell < 1.27
    EXTERNAL nw_1p8v nw_5v < 1.27 ABUT < 90 SINGULAR REGION
}
nwell.SP.3 {
    @ nwell.SP.3: Min spacing of 1.8v nwell to 12v nwell < 2.0
    EXTERNAL nw_1p8v nw_12v < 2.0 ABUT < 90 SINGULAR REGION
}
nwell.SP.4 {
    @ nwell.SP.4: Min spacing of 1.8v nwell to 20v nwell < 2.5
    EXTERNAL nw_1p8v nw_20v < 2.5 ABUT < 90 SINGULAR REGION
}
nwell.SP.5 {
    @ nwell.SP.5: Min spacing/notch of 5v nwell to 5v nwell < 1.27
    EXTERNAL nw_5v < 1.27 ABUT < 90 SINGULAR REGION
}
nwell.SP.6 {
    @ nwell.SP.6: Min spacing of 5v nwell to 12v nwell < 2.0
    EXTERNAL nw_5v nw_12v < 2.0 ABUT < 90 SINGULAR REGION
}
nwell.SP.7 {
    @ nwell.SP.7: Min spacing of 5v nwell to 20v nwell < 2.5
    EXTERNAL nw_5v nw_20v < 2.5 ABUT < 90 SINGULAR REGION
}
nwell.SP.8 {
    @ nwell.SP.8: Min spacing/notch of 12v nwell to 12v nwell < 2.0
    EXTERNAL nw_12v < 2.0 ABUT < 90 SINGULAR REGION
}
nwell.SP.9 {
    @ nwell.SP.9: Min spacing of 12v nwell to 20v nwell < 2.5
    EXTERNAL nw_12v nw_20v < 2.5 ABUT < 90 SINGULAR REGION
}
nwell.SP.10 {
    @ nwell.SP.10: Min spacing/notch of 20v nwell < 2.5
    EXTERNAL nw_20v < 2.5 ABUT < 90 SINGULAR REGION
}
nwell.OVL.1 {
    @ nwell.OVL.1: nwell must connect by ntap at least once
    nwell NOT ENCLOSE ntap
}
nwell.ENC.1 {
    @ nwell.ENC.1: Min enclosure of deep nwell by nwell < 0.4 (Rule exempted inside v20 and in cell names with "*_tech_CD_top*")
    ENC (NOT dnwell nwell_exempted_regions) (NOT nwell nwell_exempted_regions) < 0.4 MEASURE ALL ABUT < 90 SINGULAR REGION
}
nwell.ENC.2 {
    @ nwell.ENC.2: Min enclosure of nwell hole by dnwell outside v20 and in cell names with "*_tech_CD_top*" < 1.03
    ENC (OUTSIDE nwellHoles nwell_exempted_regions) (OUTSIDE dnwell nwell_exempted_regions) < 1.03 MEASURE ALL ABUT < 90 SINGULAR REGION
}
nwell.SP.11 {
    @ nwell.SP.11: Min spacing between (nwell AND deep nwell) on separate nets outside of cell names with "*_tech_CD_top*" < 4.5
    EXTERNAL dnwellNotTechCD nwellNotTechCD < 4.5 MEASURE ALL NOT CONNECTED REGION
}
nwell.ENC.3 {
    @ nwell.ENC.3: dnwell must completely enclose nwell inside v20
    nw_v20 NOT dnwell_v20
}
nwell.CON.1 {
    @ nwell.CON.1: different voltage nwell should not be on the same net
    NET AREA RATIO nw_1p8v nw_5v > 0
    NET AREA RATIO nw_1p8v nw_12v > 0
    NET AREA RATIO nw_1p8v nw_20v > 0
    NET AREA RATIO nw_5v nw_1p8v > 0
    NET AREA RATIO nw_5v nw_12v > 0
    NET AREA RATIO nw_5v nw_20v > 0
    NET AREA RATIO nw_12v nw_1p8v > 0
    NET AREA RATIO nw_12v nw_5v > 0
    NET AREA RATIO nw_12v nw_20v > 0
    NET AREA RATIO nw_20v nw_1p8v > 0
    NET AREA RATIO nw_20v nw_5v > 0
    NET AREA RATIO nw_20v nw_12v > 0
}
nwell.CON.2 {
    @ hnwell.CON.2: N-well marked with v5, v12 or v20 must be enclosed by thkox
    (OR nw_5v nw_12_20v) NOT thkox
}
nwell.CON.3 {
    @ hnwell.CON.3: N-well connected to 5v source or drain must have v5 marker
    psd_v5 = psd AND v5
    nsd_v5 = nsd AND v5
    (NET AREA RATIO nwell psd_v5 > 0) NOT INTERACT v5
    (NET AREA RATIO nwell nsd_v5 > 0) NOT INTERACT v5
}
nwell.CON.4 {
    @ nwell.CON.4: N-well connected to 12v source or drain must have v12 marker
    psd_v12 = psd AND v12
    nsd_v12 = nsd AND v12
    (NET AREA RATIO nwell psd_v12 > 0) NOT INTERACT v12
    (NET AREA RATIO nwell nsd_v12 > 0) NOT INTERACT v12
}
nwell.CON.5 {
    @ nwell.CON.5: N-well connected to 20v source or drain must have v20 marker
    psd_v20 = psd AND v20
    nsd_v20 = nsd AND v20
    (NET AREA RATIO nwell psd_v20 > 0) NOT INTERACT v20
    (NET AREA RATIO nwell nsd_v20 > 0) NOT INTERACT v20
}


//
// Antenna checks
//

#IFNDEF SKIP_ANTENNA_CHECKS

DISCONNECT 


Ant_short = (tap NOT poly) NOT nwell
SRCDRNTAP = diffTap NOT poly
Ant_diode = SRCDRNTAP NOT Ant_short
Gate_ant = poly AND diffTap


CONNECT poly Gate_ant


ar_poly = NET AREA RATIO poly Gate_ant > 50 [PERIMETER(poly) * 0.180000 / AREA(Gate_ant)] RDB ar_poly.db poly Gate_ant BY LAYER
poly.ANT.1 {
    @ poly.ANT.1: Max ratio poly perimter area/gate area > 50
    INTERACT Gate_ant ar_poly
}


CONNECT poly Licon


ar_licon = NET AREA RATIO Licon Gate_ant > 3  RDB ar_licon.db Licon Gate_ant BY LAYER
licon.ANT.1 {
    @ licon.ANT.1: Max ratio licon area/gate area > 3
    INTERACT Gate_ant (INTERACT poly ar_licon)
}


CONNECT Li poly BY Licon
CONNECT Li SRCDRNTAP BY licon
CONNECT Li Ant_diode BY licon
CONNECT Li Ant_short BY licon


fgate_1 = NET AREA RATIO Gate_ant Ant_short == 0
ar_li = NET AREA RATIO fgate_1 Li Ant_diode > 0.0 [(((PERIMETER(Li) * 0.100000 / AREA(fgate_1))-75)/450)-(AREA(Ant_diode)*!!AREA(fgate_1))] RDB ar_Li.db fgate_1 Li Ant_diode BY LAYER
li.ANT.1 {
    @ li.ANT.1: Max ratio li perimeter/gate area > 75
    COPY ar_li
}


CONNECT li mcon


fgate_2 = NET AREA RATIO Gate_ant Ant_short == 0
ar_mcon = NET AREA RATIO fgate_2 mcon ANT_diode > 0.0 [(((AREA(mcon)/AREA(fgate_2))-3)/18)-(AREA(Ant_diode)*!!AREA(fgate_2))] RDB ar_mcon.db fgate_2 mcon ANT_diode BY LAYER
mcon.ANT.1 {
    @ mcon.ANT.1: Max ratio mcon area/gate area > 3
    COPY ar_mcon
}


CONNECT met1 li BY mcon


fgate_3 = NET AREA RATIO Gate_ant Ant_short == 0
ar_met1 = NET AREA RATIO fgate_3 Met1 Ant_diode > 0.0 [((((PERIMETER(Met1) * 0.350000 / AREA(fgate_3))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_3))] RDB ar_met1.db fgate_3 Met1 Ant_diode BY LAYER
met1.ANT.1 {
    @ met1.ANT.1: Max ratio met1 perimeter/gate area > 400
    COPY ar_met1
}


CONNECT Met1 Via1


fgate_4 = NET AREA RATIO Gate_ant Ant_short == 0
ar_via = NET AREA RATIO fgate_4 Via1 ANT_diode > 0.0 [(((AREA(Via1)/AREA(fgate_4))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_4))] RDB ar_via.db fgate_4 Via1 ANT_diode BY LAYER
via1.ANT.1 {
    @ via1.ANT.1: Max ratio via1 area/gate area > 6
    COPY ar_via
}


CONNECT Met2 Met1 BY Via1


fgate_5 = NET AREA RATIO Gate_ant Ant_short == 0
ar_met2 = NET AREA RATIO fgate_5 Met2 Ant_diode > 0.0 [((((PERIMETER(Met2) * 0.350000 / AREA(fgate_5))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_5))] RDB ar_met2.db fgate_5 Met2 Ant_diode BY LAYER
met2.ANT.1 {
    @ met2.ANT.1: Max ratio met2 perimeter/gate area > 400
    COPY ar_met2
}


CONNECT Met2 Via2


fgate_6 = NET AREA RATIO Gate_ant Ant_short == 0
ar_via2 = NET AREA RATIO fgate_6 Via2 ANT_diode > 0.0 [(((AREA(Via2)/AREA(fgate_6))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_6))] RDB ar_via2.db fgate_6 Via2 ANT_diode BY LAYER
via2.ANT.1 {
    @ via2.ANT.1: Max ratio via2 area/gate area > 6
    COPY ar_via2
}


CONNECT Met3 Met2 BY Via2


fgate_7 = NET AREA RATIO Gate_ant Ant_short == 0
ar_met3 = NET AREA RATIO fgate_7 Met3 Ant_diode > 0.0 [((((PERIMETER(Met3) * 0.800000 /AREA(fgate_7))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_7))] RDB ar_met3.db fgate_7 Met3 Ant_diode BY LAYER
met3.ANT.1 {
    @ met3.ANT.1: Max ratio met3 perimeter/gate area > 400
    COPY ar_met3
}


CONNECT Met3 Via3


fgate_8 = NET AREA RATIO Gate_ant Ant_short == 0
ar_via3 = NET AREA RATIO fgate_8 Via3 ANT_diode > 0.0 [(((AREA(Via3)/AREA(fgate_8))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_8))] RDB ar_via3.db fgate_8 Via3 ANT_diode BY LAYER
via3.ANT.1 {
    @ via3.ANT.1: Max ratio via3 area/gate area > 6
    COPY ar_via3
}


CONNECT Met4 Met3 BY Via3


fgate_9 = NET AREA RATIO Gate_ant Ant_short == 0
ar_met4 = NET AREA RATIO fgate_9 Met4 Ant_diode > 0.0 [((((PERIMETER(Met4) * 0.800000 /AREA(fgate_9))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_9))] RDB ar_met4.db fgate_9 Met4 Ant_diode BY LAYER
met4.ANT.1 {
    @ met4.ANT.1: Max ratio met4 perimeter/gate area > 400
    COPY ar_met4
}


CONNECT Met4 Via4


fgate_10 = NET AREA RATIO Gate_ant Ant_short == 0
ar_via4 = NET AREA RATIO fgate_10 Via4 ANT_diode > 0.0 [(((AREA(Via4)/AREA(fgate_10))-6)/36)-(AREA(Ant_diode)*!!AREA(fgate_10))] RDB ar_via4.db fgate_10 Via4 ANT_diode BY LAYER
via4.ANT.1 {
    @ via4.ANT.1: Max ratio via4 area/gate area > 6
    COPY ar_via4
}


CONNECT Met5 Met4 BY Via4


fgate_11 = NET AREA RATIO Gate_ant Ant_short == 0
ar_met5 = NET AREA RATIO fgate_11 Met5 Ant_diode > 0.0 [((((PERIMETER(Met5) * 1.200000 /AREA(fgate_11))-400)-(!!AREA(Ant_diode)*2200))/400)-(AREA(Ant_diode)*!!AREA(fgate_11))] RDB ar_met5.db fgate_11 Met5 Ant_diode BY LAYER
met5.ANT.1 {
    @ met5.ANT.1: Max ratio met5 perimeter/gate area > 400
    COPY ar_met5
}

#IFNDEF SKIP_RECOMMENDED_CHECKS
DISCONNECT
CONNECT met5 met4 BY via4
CONNECT met4 met3 BY via3
CONNECT met3 met2 BY via2
CONNECT met2 met1 BY via1
CONNECT met1 li BY mcon
CONNECT SRCDRN li BY licon
CONNECT tap li BY licon
CONNECT ptap li BY licon

met2Conntap = NET AREA RATIO met2 tap > 0
met2Conndiff = NET AREA RATIO met2 SRCDRN > 0
met2ConnPtap = NET AREA RATIO met2 PTAP > 0
met2Conndifftap = met2Conntap OR met2Conndiff
met2NotConndifftap = met2 NOT met2Conndifftap
met2NotConnVia = met2NotConndifftap INTERACT via2 > 2
met2GroundOrFloat = met2ConnPtap OR met2NotConndifftap
met2GroundOrFloatVia = met2GroundOrFloat INTERACT via2 > 2
met3_via2 = met3 INTERACT via2
met3_over_floatingm2 = met3_via2 AND met2GroundOrFloat

CONNECT met2NotConnVia met3_over_floatingm2 BY via2
CONNECT met2GroundOrFloatVia met3_over_floatingm2 BY via2

AR_MM2_more05 = NET AREA RATIO met2NotConnVia via2 >= 20.0 [(2*AREA(met2NotConnVia)+ PERIMETER(met2NotConnVia) * 0.35)/(AREA(via2))]
AR_MM2_less03 = NET AREA RATIO met2GroundOrFloatVia via2 <= 31.25 [(2*AREA(met2GroundOrFloatVia)+PERIMETER(met2GroundOrFloatVia)*0.35)/(AREA(via2))]
crater = (EXTERNAL AR_MM2_more05 AR_MM2_less03 == 0.14 ABUT<90 SINGULAR REGION EXCLUDE FALSE) NOT STDCID
met2.ANT.2 {
    @ met2.ANT.2: met2 spacing between (met2 areas with met2-to-via2 surface area ratio >=20.0) and (met2 areas with met2-to-via2 surface area ratio <= 31.25) == 0.14
    COPY crater
}
 
#ENDIF //Recomended
#ENDIF  //Antenna

 #IFNDEF SKIP_DENSITY_CHECKS 
chip_and_seal_hole = SIZE sealid_hole BY -13
chip_not_sealring_hole = boundary NOT chip_and_seal_hole
fill_extent = chip_and_seal_hole OR (boundary NOT INTERACT SEALID)
 #IFDEF GENERATE_PREDICTIVE_FILL 
keepout_1_met1 = SIZE met1i BY 0.3
keepout_2_met1 = SIZE capacitor BY 3
keepout_3_met1 = SIZE target BY 3.295
keepout_4_met1 = SIZE nsm BY 1
keepout_5_met1 = SIZE dieCut BY 3
keepout_6_met1 = SIZE MM1mk BY 0.3
keepout_7_met1 = SIZE (met1_block OR cmm1WaffleDrop) BY 0.3
keepout_met1_1st = OR keepout_1_met1 keepout_2_met1 keepout_3_met1 keepout_4_met1 keepout_5_met1 keepout_6_met1 keepout_7_met1
target_fill_area_met1_1st = fill_extent NOT keepout_met1_1st
psuedo_fill_met1_1st = RECTANGLES 2.0 2.0 0.2 INSIDE OF LAYER target_fill_area_met1_1st
target_fill_area_met1_2nd = target_fill_area_met1_1st NOT (SIZE psuedo_fill_met1_1st BY 0.3)
psuedo_fill_met1_2nd = RECTANGLES 1.0 1.0 0.2 INSIDE OF LAYER target_fill_area_met1_2nd
target_fill_area_met1_3rd = target_fill_area_met1_2nd NOT (SIZE psuedo_fill_met1_2nd BY 0.3)
psuedo_fill_met1_3rd = RECTANGLES 0.58 0.58 0.2 INSIDE OF LAYER target_fill_area_met1_3rd
psuedo_fill_met1 = OR psuedo_fill_met1_1st psuedo_fill_met1_2nd psuedo_fill_met1_3rd
view_met1_predictive_fill {
    COPY psuedo_fill_met1
}
 #ENDIF //predictive fill 
 #IFDEF GENERATE_PREDICTIVE_FILL 
layer_to_check_met1 = OR met1i psuedo_fill_met1 MM1mk
 #ENDIF  //predictive fill 
 #IFNDEF GENERATE_PREDICTIVE_FILL 
layer_to_check_met1 = (SIZE met1i BY 0.6) OR MM1mk
 #ENDIF  //predictive fill 
 #IFDEF GENERATE_LOCAL_DENSITY 
met1.local.low.DEN.1 {
    @ met1.local.low.DEN.1: Layer met1 local density (200 square micron window stepped at 100) < 30%
    DENSITY layer_to_check_met1 < .30 WINDOW 200 STEP 100 INSIDE OF LAYER fill_extent RDB met1_local_low_density.rdb
}
met1.local.high.DEN.2 {
    @ met1.local.high.DEN.2: Layer met1 local density (200 square micron window stepped at 100) > 80%
    DENSITY layer_to_check_met1 > .80 WINDOW 200 STEP 100 INSIDE OF LAYER fill_extent RDB met1_local_high_density.rdb
}
 #ENDIF 
met1.chip.low.DEN.3 {
    @ met1.chip.low.DEN.3: Layer met1 chip density (700 square micron window stepped at 70) < 30%
    DENSITY layer_to_check_met1 < .30 WINDOW 700 STEP 70 INSIDE OF LAYER fill_extent RDB met1_chip_low_density.rdb
}
met1.chip.high.DEN.4 {
    @ met1.chip.high.DEN.4: Layer met1 chip density (700) square micron window stepped at 70) > 80%
    DENSITY layer_to_check_met1 > .80 WINDOW 700 STEP 70 INSIDE OF LAYER fill_extent RDB met1_chip_high_density.rdb
}
 #IFDEF GENERATE_PREDICTIVE_FILL 
keepout_1_met2 = SIZE met2i BY 0.3
keepout_2_met2 = SIZE capacitor BY 3
keepout_3_met2 = SIZE target BY 3.295
keepout_4_met2 = SIZE nsm BY 1
keepout_5_met2 = SIZE dieCut BY 3
keepout_6_met2 = SIZE MM2mk BY 0.3
keepout_7_met2 = SIZE (met2_block OR cmm2WaffleDrop) BY 0.3
keepout_met2_1st = OR keepout_1_met2 keepout_2_met2 keepout_3_met2 keepout_4_met2 keepout_5_met2 keepout_6_met2 keepout_7_met2
target_fill_area_met2_1st = fill_extent NOT keepout_met2_1st
psuedo_fill_met2_1st = RECTANGLES 2.0 2.0 0.2 INSIDE OF LAYER target_fill_area_met2_1st
target_fill_area_met2_2nd = target_fill_area_met2_1st NOT (SIZE psuedo_fill_met2_1st BY 0.3)
psuedo_fill_met2_2nd = RECTANGLES 1.0 1.0 0.2 INSIDE OF LAYER target_fill_area_met2_2nd
target_fill_area_met2_3rd = target_fill_area_met2_2nd NOT (SIZE psuedo_fill_met2_2nd BY 0.3)
psuedo_fill_met2_3rd = RECTANGLES 0.58 0.58 0.2 INSIDE OF LAYER target_fill_area_met2_3rd
psuedo_fill_met2 = OR psuedo_fill_met2_1st psuedo_fill_met2_2nd psuedo_fill_met2_3rd
view_met2_predictive_fill {
    COPY psuedo_fill_met2
}
 #ENDIF //predictive fill 
 #IFDEF GENERATE_PREDICTIVE_FILL 
layer_to_check_met2 = OR met2i psuedo_fill_met2 MM2mk
 #ENDIF  //predictive fill 
 #IFNDEF GENERATE_PREDICTIVE_FILL 
layer_to_check_met2 = (SIZE met2i BY 0.6) OR MM2mk
 #ENDIF  //predictive fill 
 #IFDEF GENERATE_LOCAL_DENSITY 
met2.local.low.DEN.1 {
    @ met2.local.low.DEN.1: Layer met2 local density (200 square micron window stepped at 100) < 30%
    DENSITY layer_to_check_met2 < .30 WINDOW 200 STEP 100 INSIDE OF LAYER fill_extent RDB met2_local_low_density.rdb
}
met2.local.high.DEN.2 {
    @ met2.local.high.DEN.2: Layer met2 local density (200 square micron window stepped at 100) > 80%
    DENSITY layer_to_check_met2 > .80 WINDOW 200 STEP 100 INSIDE OF LAYER fill_extent RDB met2_local_high_density.rdb
}
 #ENDIF 
met2.chip.low.DEN.3 {
    @ met2.chip.low.DEN.3: Layer met2 chip density (700 square micron window stepped at 70) < 30%
    DENSITY layer_to_check_met2 < .30 WINDOW 700 STEP 70 INSIDE OF LAYER fill_extent RDB met2_chip_low_density.rdb
}
met2.chip.high.DEN.4 {
    @ met2.chip.high.DEN.4: Layer met2 chip density (700) square micron window stepped at 70) > 80%
    DENSITY layer_to_check_met2 > .80 WINDOW 700 STEP 70 INSIDE OF LAYER fill_extent RDB met2_chip_high_density.rdb
}
 #IFDEF GENERATE_PREDICTIVE_FILL 
keepout_1_met3 = SIZE met3i BY 0.3
keepout_2_met3 = SIZE capacitor BY 3
keepout_3_met3 = SIZE target BY 3.295
keepout_4_met3 = SIZE nsm BY 1
keepout_5_met3 = SIZE dieCut BY 3
keepout_6_met3 = SIZE MM3mk BY 0.3
keepout_7_met3 = SIZE (met3_block OR cmm3WaffleDrop) BY 0.3
keepout_met3_1st = OR keepout_1_met3 keepout_2_met3 keepout_3_met3 keepout_4_met3 keepout_5_met3 keepout_6_met3 keepout_7_met3
target_fill_area_met3_1st = fill_extent NOT keepout_met3_1st
psuedo_fill_met3_1st = RECTANGLES 2.0 2.0 0.3 INSIDE OF LAYER target_fill_area_met3_1st
target_fill_area_met3_2nd = target_fill_area_met3_1st NOT (SIZE psuedo_fill_met3_1st BY 0.3)
psuedo_fill_met3_2nd = RECTANGLES 1.0 1.0 0.3 INSIDE OF LAYER target_fill_area_met3_2nd
target_fill_area_met3_3rd = target_fill_area_met3_2nd NOT (SIZE psuedo_fill_met3_2nd BY 0.3)
psuedo_fill_met3_3rd = RECTANGLES 0.58 0.58 0.3 INSIDE OF LAYER target_fill_area_met3_3rd
psuedo_fill_met3 = OR psuedo_fill_met3_1st psuedo_fill_met3_2nd psuedo_fill_met3_3rd
view_met3_predictive_fill {
    COPY psuedo_fill_met3
}
 #ENDIF //predictive fill 
 #IFDEF GENERATE_PREDICTIVE_FILL 
layer_to_check_met3 = OR met3i psuedo_fill_met3 MM3mk
 #ENDIF  //predictive fill 
 #IFNDEF GENERATE_PREDICTIVE_FILL 
layer_to_check_met3 = (SIZE met3i BY 1.15) OR MM3mk
 #ENDIF  //predictive fill 
 #IFDEF GENERATE_LOCAL_DENSITY 
met3.local.low.DEN.1 {
    @ met3.local.low.DEN.1: Layer met3 local density (200 square micron window stepped at 100) < 30%
    DENSITY layer_to_check_met3 < .30 WINDOW 200 STEP 100 INSIDE OF LAYER fill_extent RDB met3_local_low_density.rdb
}
met3.local.high.DEN.2 {
    @ met3.local.high.DEN.2: Layer met3 local density (200 square micron window stepped at 100) > 80%
    DENSITY layer_to_check_met3 > .80 WINDOW 200 STEP 100 INSIDE OF LAYER fill_extent RDB met3_local_high_density.rdb
}
 #ENDIF 
met3.chip.low.DEN.3 {
    @ met3.chip.low.DEN.3: Layer met3 chip density (700 square micron window stepped at 70) < 30%
    DENSITY layer_to_check_met3 < .30 WINDOW 700 STEP 70 INSIDE OF LAYER fill_extent RDB met3_chip_low_density.rdb
}
met3.chip.high.DEN.4 {
    @ met3.chip.high.DEN.4: Layer met3 chip density (700) square micron window stepped at 70) > 80%
    DENSITY layer_to_check_met3 > .80 WINDOW 700 STEP 70 INSIDE OF LAYER fill_extent RDB met3_chip_high_density.rdb
}
 #IFDEF GENERATE_PREDICTIVE_FILL 
keepout_1_met4 = SIZE met4i BY 0.3
keepout_2_met4 = SIZE capacitor BY 3
keepout_3_met4 = SIZE target BY 3.295
keepout_4_met4 = SIZE nsm BY 1
keepout_5_met4 = SIZE dieCut BY 3
keepout_6_met4 = SIZE MM4mk BY 0.3
keepout_7_met4 = SIZE (met4_block OR cmm4WaffleDrop) BY 0.3
keepout_met4_1st = OR keepout_1_met4 keepout_2_met4 keepout_3_met4 keepout_4_met4 keepout_5_met4 keepout_6_met4 keepout_7_met4
target_fill_area_met4_1st = fill_extent NOT keepout_met4_1st
psuedo_fill_met4_1st = RECTANGLES 2.0 2.0 0.3 INSIDE OF LAYER target_fill_area_met4_1st
target_fill_area_met4_2nd = target_fill_area_met4_1st NOT (SIZE psuedo_fill_met4_1st BY 0.3)
psuedo_fill_met4_2nd = RECTANGLES 1.0 1.0 0.3 INSIDE OF LAYER target_fill_area_met4_2nd
target_fill_area_met4_3rd = target_fill_area_met4_2nd NOT (SIZE psuedo_fill_met4_2nd BY 0.3)
psuedo_fill_met4_3rd = RECTANGLES 0.58 0.58 0.3 INSIDE OF LAYER target_fill_area_met4_3rd
psuedo_fill_met4 = OR psuedo_fill_met4_1st psuedo_fill_met4_2nd psuedo_fill_met4_3rd
view_met4_predictive_fill {
    COPY psuedo_fill_met4
}
 #ENDIF //predictive fill 
 #IFDEF GENERATE_PREDICTIVE_FILL 
layer_to_check_met4 = OR met4i psuedo_fill_met4 MM4mk
 #ENDIF  //predictive fill 
 #IFNDEF GENERATE_PREDICTIVE_FILL 
layer_to_check_met4 = (SIZE met4i BY 1.15) OR MM4mk
 #ENDIF  //predictive fill 
 #IFDEF GENERATE_LOCAL_DENSITY 
met4.local.low.DEN.1 {
    @ met4.local.low.DEN.1: Layer met4 local density (200 square micron window stepped at 100) < 30%
    DENSITY layer_to_check_met4 < .30 WINDOW 200 STEP 100 INSIDE OF LAYER fill_extent RDB met4_local_low_density.rdb
}
met4.local.high.DEN.2 {
    @ met4.local.high.DEN.2: Layer met4 local density (200 square micron window stepped at 100) > 80%
    DENSITY layer_to_check_met4 > .80 WINDOW 200 STEP 100 INSIDE OF LAYER fill_extent RDB met4_local_high_density.rdb
}
 #ENDIF 
met4.chip.low.DEN.3 {
    @ met4.chip.low.DEN.3: Layer met4 chip density (700 square micron window stepped at 70) < 30%
    DENSITY layer_to_check_met4 < .30 WINDOW 700 STEP 70 INSIDE OF LAYER fill_extent RDB met4_chip_low_density.rdb
}
met4.chip.high.DEN.4 {
    @ met4.chip.high.DEN.4: Layer met4 chip density (700) square micron window stepped at 70) > 80%
    DENSITY layer_to_check_met4 > .80 WINDOW 700 STEP 70 INSIDE OF LAYER fill_extent RDB met4_chip_high_density.rdb
}
 #IFDEF GENERATE_PREDICTIVE_FILL 
keepout_1_met5 = SIZE met5i BY 3.0
keepout_2_met5 = SIZE (capm OR cap2m) BY 3
keepout_3_met5 = SIZE target BY 3.295
keepout_4_met5 = SIZE nsm BY 1
keepout_5_met5 = SIZE dieCut BY 3
keepout_6_met5 = SIZE MM5mk BY 0.3
keepout_7_met5 = SIZE (met5_block OR cmm5WaffleDrop) BY 3.0
keepout_met5 = OR keepout_1_met5 keepout_2_met5 keepout_3_met5 keepout_4_met5 keepout_5_met5 keepout_6_met5 keepout_7_met5
target_fill_area_met5 = fill_extent NOT keepout_met5
psuedo_fill_met5 = RECTANGLES 3.0 3.0 3.0 INSIDE OF LAYER target_fill_area_met5
view_met5_predictive_fill {
    COPY psuedo_fill_met5
}
 #ENDIF //predictive fill 
 #IFDEF GENERATE_PREDICTIVE_FILL 
layer_to_check_met5 = OR met5i psuedo_fill_met5 MM5mk
 #ENDIF  //predictive fill 
 #IFNDEF GENERATE_PREDICTIVE_FILL 
layer_to_check_met5 = (SIZE met5i BY 0.0) OR MM5mk
 #ENDIF  //predictive fill 
 #IFDEF GENERATE_LOCAL_DENSITY 
met5.local.low.DEN.1 {
    @ met5.local.low.DEN.1: Layer met5 local density (200 square micron window stepped at 100) < 19%
    DENSITY layer_to_check_met5 < .19 WINDOW 200 STEP 100 INSIDE OF LAYER fill_extent RDB met5_local_low_density.rdb
}
met5.local.high.DEN.2 {
    @ met5.local.high.DEN.2: Layer met5 local density (200 square micron window stepped at 100) > 60%
    DENSITY layer_to_check_met5 > .60 WINDOW 200 STEP 100 INSIDE OF LAYER fill_extent RDB met5_local_high_density.rdb
}
 #ENDIF 
met5.chip.low.DEN.3 {
    @ met5.chip.low.DEN.3: Layer met5 chip density (700 square micron window stepped at 70) < 19%
    DENSITY layer_to_check_met5 < .19 WINDOW 700 STEP 70 INSIDE OF LAYER fill_extent RDB met5_chip_low_density.rdb
}
met5.chip.high.DEN.4 {
    @ met5.chip.high.DEN.4: Layer met5 chip density (700) square micron window stepped at 70) > 60%
    DENSITY layer_to_check_met5 > .60 WINDOW 700 STEP 70 INSIDE OF LAYER fill_extent RDB met5_chip_high_density.rdb
}
chip = COPY boundary
chipAreaBigEnough = AREA chip > 40000.0
entireChipForDensity = chip INTERACT sealHoles
met1outOxide_drc = SIZE met1 BY 0.6
waffle1DropDensity70_met1 = DENSITY cmm1WaffleDrop == 1.0 WINDOW 700 STEP 70
met1_DensityUnder70 = DENSITY met1outOxide_drc < 0.7 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity70_met1 RDB met1.chip.low.DEN_under_100_fill_block.1.rdb
met1_DensityUnder70Chip = met1_DensityUnder70 INTERACT entireChipForDensity
met1_DensityUnder70tmp = met1_DensityUnder70 NOT met1_DensityUnder70Chip
met1_DensityUnder70IP = met1_DensityUnder70tmp AND chipAreaBigEnough
met1.low.DEN_under_100_fill_block.1_IP {
    @ met1.low.DEN_under_100_fill_block.1_IP: <70% met1 density when 700x700 window 100% covered by met1 fill block (IP) < 70%
    COPY met1_DensityUnder70IP
}
met1.low.DEN_under_100_fill_block.1_CHIP {
    @ met1.low.DEN_under_100_fill_block.1_CHIP: <70% met1 density when 700x700 window 100% covered by met1 fill block (CHIP) < 70%
    COPY met1_DensityUnder70Chip
}
waffle1DropDensity65_met1 = DENSITY cmm1WaffleDrop > 0.8 <= 1.0 WINDOW 700 STEP 70
met1_DensityUnder65 = DENSITY met1outOxide_drc < 0.65 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity65_met1 RDB met1.chip.low.DEN_under_80_fill_block.1.rdb
met1_DensityUnder65Chip = INTERACT met1_DensityUnder65 entireChipForDensity
met1_DensityUnder65tmp = met1_DensityUnder65 NOT met1_DensityUnder65Chip
met1_DensityUnder65IP = met1_DensityUnder65tmp AND chipAreaBigEnough
met1.low.DEN_under_80_fill_block.1_IP {
    @ met1.low.DEN_under_80_fill_block.1_IP: met1 density when 700x700 window 80-100% covered by met1 fill block (IP) < 65%
    COPY met1_DensityUnder65IP
}
met1.low.DEN_under_80_fill_block.1_CHIP {
    @ met1.low.DEN_under_80_fill_block.1_CHIP: met1 density when 700x700 window 80-100% covered by met1 fill block (CHIP) < 65%
    COPY met1_DensityUnder65Chip
}
waffle1DropDensity60_met1 = DENSITY cmm1WaffleDrop > 0.6 <= 0.8 WINDOW 700 STEP 70
met1_DensityUnder60 = DENSITY met1outOxide_drc < 0.6 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity60_met1 RDB met1.chip.low.DEN_under_60_fill_block.1.rdb
met1_DensityUnder60Chip = INTERACT met1_DensityUnder60 entireChipForDensity
met1_DensityUnder60tmp = met1_DensityUnder60 NOT met1_DensityUnder60Chip
met1_DensityUnder60IP = met1_DensityUnder60tmp AND chipAreaBigEnough
met1.low.DEN_under_60_fill_block.1_IP {
    @ met1.low.DEN_under_60_fill_block.1_IP: met1 density when 700x700 window 60-80% covered by met1 fill block (IP) < 60%
    COPY met1_DensityUnder60IP
}
met1.low.DEN_under_60_fill_block.1_CHIP {
    @ met1.low.DEN_under_60_fill_block.1_CHIP: met1 density when 700x700 window 60-80% covered by met1 fill block (CHIP) < 60%
    COPY met1_DensityUnder60Chip
}
waffle1DropDensity50_met1 = DENSITY cmm1WaffleDrop > 0.5 <= 0.6 WINDOW 700 STEP 70
met1_DensityUnder50 = DENSITY met1outOxide_drc < 0.5 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity50_met1 RDB met1.chip.low.DEN_under_50_fill_block.1.rdb
met1_DensityUnder50Chip = INTERACT met1_DensityUnder50 entireChipForDensity
met1_DensityUnder50tmp = met1_DensityUnder50 NOT met1_DensityUnder50Chip
met1_DensityUnder50IP = met1_DensityUnder50tmp AND chipAreaBigEnough
met1.low.DEN_under_50_fill_block.1_IP {
    @ met1.low.DEN_under_50_fill_block.1_IP: met1 density when 700x700 window 50-60% covered by met1 fill block (IP) < 50%
    COPY met1_DensityUnder50IP
}
met1.low.DEN_under_50_fill_block.1_CHIP {
    @ met1.low.DEN_under_50_fill_block.1_CHIP: met1 density when 700x700 window 50-60% covered by met1 fill block (CHIP)_ < 50%
    COPY met1_DensityUnder50Chip
}
waffle1DropDensity40_met1 = DENSITY cmm1WaffleDrop > 0.4 <= 0.5 WINDOW 700 STEP 70
met1_DensityUnder40 = DENSITY met1outOxide_drc < 0.4 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity40_met1 RDB met1.chip.low.DEN_under_40_fill_block.1.rdb
met1_DensityUnder40Chip = INTERACT met1_DensityUnder40 entireChipForDensity
met1_DensityUnder40tmp = met1_DensityUnder40 NOT met1_DensityUnder40Chip
met1_DensityUnder40IP = met1_DensityUnder40tmp AND chipAreaBigEnough
met1.low.DEN_under_40_fill_block.1_IP {
    @ met1.low.DEN_under_40_fill_block.1_IP: met1 density when 700x700 window 40-50% covered by met1 fill block (IP) < 40%
    COPY met1_DensityUnder40IP
}
met1.low.DEN_under_40_fill_block.1_CHIP {
    @ met1.low.DEN_under_40_fill_block.1_CHIP: met1 density when 700x700 window 40-50% covered by met1 fill block (CHIP) < 40%
    COPY met1_DensityUnder40Chip
}
waffle1DropDensity30_met1 = DENSITY cmm1WaffleDrop > 0.3 <= 0.4 WINDOW 700 STEP 70
met1_DensityUnder30 = DENSITY met1outOxide_drc < 0.3 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity30_met1 RDB met1.chip.low.DEN_under_30_fill_block.1.rdb
met1_DensityUnder30Chip = INTERACT met1_DensityUnder30 entireChipForDensity
met1_DensityUnder30tmp = met1_DensityUnder30 NOT met1_DensityUnder30Chip
met1_DensityUnder30IP = met1_DensityUnder30tmp AND chipAreaBigEnough
met1.low.DEN_under_30_fill_block.1_IP {
    @ met1.low.DEN_under_30_fill_block.1_IP: met1 density when 700x700 window 30-40% covered by met1 fill block (IP) < 30%
    COPY met1_DensityUnder30IP
}
met1.low.DEN_under_30_fill_block.1_CHIP {
    @ met1.low.DEN_under_30_fill_block.1_CHIP: met1 density when 700x700 window 30-40% covered by met1 fill block (CHIP) < 30%
    COPY met1_DensityUnder30Chip
}
met2outOxide_drc = SIZE met2 BY 0.6
waffle1DropDensity70_met2 = DENSITY cmm2WaffleDrop == 1.0 WINDOW 700 STEP 70
met2_DensityUnder70 = DENSITY met2outOxide_drc < 0.7 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity70_met2 RDB met2.chip.low.DEN_under_100_fill_block.1.rdb
met2_DensityUnder70Chip = met2_DensityUnder70 INTERACT entireChipForDensity
met2_DensityUnder70tmp = met2_DensityUnder70 NOT met2_DensityUnder70Chip
met2_DensityUnder70IP = met2_DensityUnder70tmp AND chipAreaBigEnough
met2.low.DEN_under_100_fill_block.1_IP {
    @ met2.low.DEN_under_100_fill_block.1_IP: <70% met2 density when 700x700 window 100% covered by met2 fill block (IP) < 70%
    COPY met2_DensityUnder70IP
}
met2.low.DEN_under_100_fill_block.1_CHIP {
    @ met2.low.DEN_under_100_fill_block.1_CHIP: <70% met2 density when 700x700 window 100% covered by met2 fill block (CHIP) < 70%
    COPY met2_DensityUnder70Chip
}
waffle1DropDensity65_met2 = DENSITY cmm2WaffleDrop > 0.8 <= 1.0 WINDOW 700 STEP 70
met2_DensityUnder65 = DENSITY met2outOxide_drc < 0.65 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity65_met2 RDB met2.chip.low.DEN_under_80_fill_block.1.rdb
met2_DensityUnder65Chip = INTERACT met2_DensityUnder65 entireChipForDensity
met2_DensityUnder65tmp = met2_DensityUnder65 NOT met2_DensityUnder65Chip
met2_DensityUnder65IP = met2_DensityUnder65tmp AND chipAreaBigEnough
met2.low.DEN_under_80_fill_block.1_IP {
    @ met2.low.DEN_under_80_fill_block.1_IP: met2 density when 700x700 window 80-100% covered by met2 fill block (IP) < 65%
    COPY met2_DensityUnder65IP
}
met2.low.DEN_under_80_fill_block.1_CHIP {
    @ met2.low.DEN_under_80_fill_block.1_CHIP: met2 density when 700x700 window 80-100% covered by met2 fill block (CHIP) < 65%
    COPY met2_DensityUnder65Chip
}
waffle1DropDensity60_met2 = DENSITY cmm2WaffleDrop > 0.6 <= 0.8 WINDOW 700 STEP 70
met2_DensityUnder60 = DENSITY met2outOxide_drc < 0.6 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity60_met2 RDB met2.chip.low.DEN_under_60_fill_block.1.rdb
met2_DensityUnder60Chip = INTERACT met2_DensityUnder60 entireChipForDensity
met2_DensityUnder60tmp = met2_DensityUnder60 NOT met2_DensityUnder60Chip
met2_DensityUnder60IP = met2_DensityUnder60tmp AND chipAreaBigEnough
met2.low.DEN_under_60_fill_block.1_IP {
    @ met2.low.DEN_under_60_fill_block.1_IP: met2 density when 700x700 window 60-80% covered by met2 fill block (IP) < 60%
    COPY met2_DensityUnder60IP
}
met2.low.DEN_under_60_fill_block.1_CHIP {
    @ met2.low.DEN_under_60_fill_block.1_CHIP: met2 density when 700x700 window 60-80% covered by met2 fill block (CHIP) < 60%
    COPY met2_DensityUnder60Chip
}
waffle1DropDensity50_met2 = DENSITY cmm2WaffleDrop > 0.5 <= 0.6 WINDOW 700 STEP 70
met2_DensityUnder50 = DENSITY met2outOxide_drc < 0.5 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity50_met2 RDB met2.chip.low.DEN_under_50_fill_block.1.rdb
met2_DensityUnder50Chip = INTERACT met2_DensityUnder50 entireChipForDensity
met2_DensityUnder50tmp = met2_DensityUnder50 NOT met2_DensityUnder50Chip
met2_DensityUnder50IP = met2_DensityUnder50tmp AND chipAreaBigEnough
met2.low.DEN_under_50_fill_block.1_IP {
    @ met2.low.DEN_under_50_fill_block.1_IP: met2 density when 700x700 window 50-60% covered by met2 fill block (IP) < 50%
    COPY met2_DensityUnder50IP
}
met2.low.DEN_under_50_fill_block.1_CHIP {
    @ met2.low.DEN_under_50_fill_block.1_CHIP: met2 density when 700x700 window 50-60% covered by met2 fill block (CHIP)_ < 50%
    COPY met2_DensityUnder50Chip
}
waffle1DropDensity40_met2 = DENSITY cmm2WaffleDrop > 0.4 <= 0.5 WINDOW 700 STEP 70
met2_DensityUnder40 = DENSITY met2outOxide_drc < 0.4 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity40_met2 RDB met2.chip.low.DEN_under_40_fill_block.1.rdb
met2_DensityUnder40Chip = INTERACT met2_DensityUnder40 entireChipForDensity
met2_DensityUnder40tmp = met2_DensityUnder40 NOT met2_DensityUnder40Chip
met2_DensityUnder40IP = met2_DensityUnder40tmp AND chipAreaBigEnough
met2.low.DEN_under_40_fill_block.1_IP {
    @ met2.low.DEN_under_40_fill_block.1_IP: met2 density when 700x700 window 40-50% covered by met2 fill block (IP) < 40%
    COPY met2_DensityUnder40IP
}
met2.low.DEN_under_40_fill_block.1_CHIP {
    @ met2.low.DEN_under_40_fill_block.1_CHIP: met2 density when 700x700 window 40-50% covered by met2 fill block (CHIP) < 40%
    COPY met2_DensityUnder40Chip
}
waffle1DropDensity30_met2 = DENSITY cmm2WaffleDrop > 0.3 <= 0.4 WINDOW 700 STEP 70
met2_DensityUnder30 = DENSITY met2outOxide_drc < 0.3 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity30_met2 RDB met2.chip.low.DEN_under_30_fill_block.1.rdb
met2_DensityUnder30Chip = INTERACT met2_DensityUnder30 entireChipForDensity
met2_DensityUnder30tmp = met2_DensityUnder30 NOT met2_DensityUnder30Chip
met2_DensityUnder30IP = met2_DensityUnder30tmp AND chipAreaBigEnough
met2.low.DEN_under_30_fill_block.1_IP {
    @ met2.low.DEN_under_30_fill_block.1_IP: met2 density when 700x700 window 30-40% covered by met2 fill block (IP) < 30%
    COPY met2_DensityUnder30IP
}
met2.low.DEN_under_30_fill_block.1_CHIP {
    @ met2.low.DEN_under_30_fill_block.1_CHIP: met2 density when 700x700 window 30-40% covered by met2 fill block (CHIP) < 30%
    COPY met2_DensityUnder30Chip
}
met3outOxide_drc = SIZE met3 BY 0.6
waffle1DropDensity70_met3 = DENSITY cmm3WaffleDrop == 1.0 WINDOW 700 STEP 70
met3_DensityUnder70 = DENSITY met3outOxide_drc < 0.7 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity70_met3 RDB met3.chip.low.DEN_under_100_fill_block.1.rdb
met3_DensityUnder70Chip = met3_DensityUnder70 INTERACT entireChipForDensity
met3_DensityUnder70tmp = met3_DensityUnder70 NOT met3_DensityUnder70Chip
met3_DensityUnder70IP = met3_DensityUnder70tmp AND chipAreaBigEnough
met3.low.DEN_under_100_fill_block.1_IP {
    @ met3.low.DEN_under_100_fill_block.1_IP: <70% met3 density when 700x700 window 100% covered by met3 fill block (IP) < 70%
    COPY met3_DensityUnder70IP
}
met3.low.DEN_under_100_fill_block.1_CHIP {
    @ met3.low.DEN_under_100_fill_block.1_CHIP: <70% met3 density when 700x700 window 100% covered by met3 fill block (CHIP) < 70%
    COPY met3_DensityUnder70Chip
}
waffle1DropDensity65_met3 = DENSITY cmm3WaffleDrop > 0.8 <= 1.0 WINDOW 700 STEP 70
met3_DensityUnder65 = DENSITY met3outOxide_drc < 0.65 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity65_met3 RDB met3.chip.low.DEN_under_80_fill_block.1.rdb
met3_DensityUnder65Chip = INTERACT met3_DensityUnder65 entireChipForDensity
met3_DensityUnder65tmp = met3_DensityUnder65 NOT met3_DensityUnder65Chip
met3_DensityUnder65IP = met3_DensityUnder65tmp AND chipAreaBigEnough
met3.low.DEN_under_80_fill_block.1_IP {
    @ met3.low.DEN_under_80_fill_block.1_IP: met3 density when 700x700 window 80-100% covered by met3 fill block (IP) < 65%
    COPY met3_DensityUnder65IP
}
met3.low.DEN_under_80_fill_block.1_CHIP {
    @ met3.low.DEN_under_80_fill_block.1_CHIP: met3 density when 700x700 window 80-100% covered by met3 fill block (CHIP) < 65%
    COPY met3_DensityUnder65Chip
}
waffle1DropDensity60_met3 = DENSITY cmm3WaffleDrop > 0.6 <= 0.8 WINDOW 700 STEP 70
met3_DensityUnder60 = DENSITY met3outOxide_drc < 0.6 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity60_met3 RDB met3.chip.low.DEN_under_60_fill_block.1.rdb
met3_DensityUnder60Chip = INTERACT met3_DensityUnder60 entireChipForDensity
met3_DensityUnder60tmp = met3_DensityUnder60 NOT met3_DensityUnder60Chip
met3_DensityUnder60IP = met3_DensityUnder60tmp AND chipAreaBigEnough
met3.low.DEN_under_60_fill_block.1_IP {
    @ met3.low.DEN_under_60_fill_block.1_IP: met3 density when 700x700 window 60-80% covered by met3 fill block (IP) < 60%
    COPY met3_DensityUnder60IP
}
met3.low.DEN_under_60_fill_block.1_CHIP {
    @ met3.low.DEN_under_60_fill_block.1_CHIP: met3 density when 700x700 window 60-80% covered by met3 fill block (CHIP) < 60%
    COPY met3_DensityUnder60Chip
}
waffle1DropDensity50_met3 = DENSITY cmm3WaffleDrop > 0.5 <= 0.6 WINDOW 700 STEP 70
met3_DensityUnder50 = DENSITY met3outOxide_drc < 0.5 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity50_met3 RDB met3.chip.low.DEN_under_50_fill_block.1.rdb
met3_DensityUnder50Chip = INTERACT met3_DensityUnder50 entireChipForDensity
met3_DensityUnder50tmp = met3_DensityUnder50 NOT met3_DensityUnder50Chip
met3_DensityUnder50IP = met3_DensityUnder50tmp AND chipAreaBigEnough
met3.low.DEN_under_50_fill_block.1_IP {
    @ met3.low.DEN_under_50_fill_block.1_IP: met3 density when 700x700 window 50-60% covered by met3 fill block (IP) < 50%
    COPY met3_DensityUnder50IP
}
met3.low.DEN_under_50_fill_block.1_CHIP {
    @ met3.low.DEN_under_50_fill_block.1_CHIP: met3 density when 700x700 window 50-60% covered by met3 fill block (CHIP)_ < 50%
    COPY met3_DensityUnder50Chip
}
waffle1DropDensity40_met3 = DENSITY cmm3WaffleDrop > 0.4 <= 0.5 WINDOW 700 STEP 70
met3_DensityUnder40 = DENSITY met3outOxide_drc < 0.4 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity40_met3 RDB met3.chip.low.DEN_under_40_fill_block.1.rdb
met3_DensityUnder40Chip = INTERACT met3_DensityUnder40 entireChipForDensity
met3_DensityUnder40tmp = met3_DensityUnder40 NOT met3_DensityUnder40Chip
met3_DensityUnder40IP = met3_DensityUnder40tmp AND chipAreaBigEnough
met3.low.DEN_under_40_fill_block.1_IP {
    @ met3.low.DEN_under_40_fill_block.1_IP: met3 density when 700x700 window 40-50% covered by met3 fill block (IP) < 40%
    COPY met3_DensityUnder40IP
}
met3.low.DEN_under_40_fill_block.1_CHIP {
    @ met3.low.DEN_under_40_fill_block.1_CHIP: met3 density when 700x700 window 40-50% covered by met3 fill block (CHIP) < 40%
    COPY met3_DensityUnder40Chip
}
waffle1DropDensity30_met3 = DENSITY cmm3WaffleDrop > 0.3 <= 0.4 WINDOW 700 STEP 70
met3_DensityUnder30 = DENSITY met3outOxide_drc < 0.3 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity30_met3 RDB met3.chip.low.DEN_under_30_fill_block.1.rdb
met3_DensityUnder30Chip = INTERACT met3_DensityUnder30 entireChipForDensity
met3_DensityUnder30tmp = met3_DensityUnder30 NOT met3_DensityUnder30Chip
met3_DensityUnder30IP = met3_DensityUnder30tmp AND chipAreaBigEnough
met3.low.DEN_under_30_fill_block.1_IP {
    @ met3.low.DEN_under_30_fill_block.1_IP: met3 density when 700x700 window 30-40% covered by met3 fill block (IP) < 30%
    COPY met3_DensityUnder30IP
}
met3.low.DEN_under_30_fill_block.1_CHIP {
    @ met3.low.DEN_under_30_fill_block.1_CHIP: met3 density when 700x700 window 30-40% covered by met3 fill block (CHIP) < 30%
    COPY met3_DensityUnder30Chip
}
met4outOxide_drc = SIZE met4 BY 0.6
waffle1DropDensity70_met4 = DENSITY cmm4WaffleDrop == 1.0 WINDOW 700 STEP 70
met4_DensityUnder70 = DENSITY met4outOxide_drc < 0.7 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity70_met4 RDB met4.chip.low.DEN_under_100_fill_block.1.rdb
met4_DensityUnder70Chip = met4_DensityUnder70 INTERACT entireChipForDensity
met4_DensityUnder70tmp = met4_DensityUnder70 NOT met4_DensityUnder70Chip
met4_DensityUnder70IP = met4_DensityUnder70tmp AND chipAreaBigEnough
met4.low.DEN_under_100_fill_block.1_IP {
    @ met4.low.DEN_under_100_fill_block.1_IP: <70% met4 density when 700x700 window 100% covered by met4 fill block (IP) < 70%
    COPY met4_DensityUnder70IP
}
met4.low.DEN_under_100_fill_block.1_CHIP {
    @ met4.low.DEN_under_100_fill_block.1_CHIP: <70% met4 density when 700x700 window 100% covered by met4 fill block (CHIP) < 70%
    COPY met4_DensityUnder70Chip
}
waffle1DropDensity65_met4 = DENSITY cmm4WaffleDrop > 0.8 <= 1.0 WINDOW 700 STEP 70
met4_DensityUnder65 = DENSITY met4outOxide_drc < 0.65 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity65_met4 RDB met4.chip.low.DEN_under_80_fill_block.1.rdb
met4_DensityUnder65Chip = INTERACT met4_DensityUnder65 entireChipForDensity
met4_DensityUnder65tmp = met4_DensityUnder65 NOT met4_DensityUnder65Chip
met4_DensityUnder65IP = met4_DensityUnder65tmp AND chipAreaBigEnough
met4.low.DEN_under_80_fill_block.1_IP {
    @ met4.low.DEN_under_80_fill_block.1_IP: met4 density when 700x700 window 80-100% covered by met4 fill block (IP) < 65%
    COPY met4_DensityUnder65IP
}
met4.low.DEN_under_80_fill_block.1_CHIP {
    @ met4.low.DEN_under_80_fill_block.1_CHIP: met4 density when 700x700 window 80-100% covered by met4 fill block (CHIP) < 65%
    COPY met4_DensityUnder65Chip
}
waffle1DropDensity60_met4 = DENSITY cmm4WaffleDrop > 0.6 <= 0.8 WINDOW 700 STEP 70
met4_DensityUnder60 = DENSITY met4outOxide_drc < 0.6 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity60_met4 RDB met4.chip.low.DEN_under_60_fill_block.1.rdb
met4_DensityUnder60Chip = INTERACT met4_DensityUnder60 entireChipForDensity
met4_DensityUnder60tmp = met4_DensityUnder60 NOT met4_DensityUnder60Chip
met4_DensityUnder60IP = met4_DensityUnder60tmp AND chipAreaBigEnough
met4.low.DEN_under_60_fill_block.1_IP {
    @ met4.low.DEN_under_60_fill_block.1_IP: met4 density when 700x700 window 60-80% covered by met4 fill block (IP) < 60%
    COPY met4_DensityUnder60IP
}
met4.low.DEN_under_60_fill_block.1_CHIP {
    @ met4.low.DEN_under_60_fill_block.1_CHIP: met4 density when 700x700 window 60-80% covered by met4 fill block (CHIP) < 60%
    COPY met4_DensityUnder60Chip
}
waffle1DropDensity50_met4 = DENSITY cmm4WaffleDrop > 0.5 <= 0.6 WINDOW 700 STEP 70
met4_DensityUnder50 = DENSITY met4outOxide_drc < 0.5 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity50_met4 RDB met4.chip.low.DEN_under_50_fill_block.1.rdb
met4_DensityUnder50Chip = INTERACT met4_DensityUnder50 entireChipForDensity
met4_DensityUnder50tmp = met4_DensityUnder50 NOT met4_DensityUnder50Chip
met4_DensityUnder50IP = met4_DensityUnder50tmp AND chipAreaBigEnough
met4.low.DEN_under_50_fill_block.1_IP {
    @ met4.low.DEN_under_50_fill_block.1_IP: met4 density when 700x700 window 50-60% covered by met4 fill block (IP) < 50%
    COPY met4_DensityUnder50IP
}
met4.low.DEN_under_50_fill_block.1_CHIP {
    @ met4.low.DEN_under_50_fill_block.1_CHIP: met4 density when 700x700 window 50-60% covered by met4 fill block (CHIP)_ < 50%
    COPY met4_DensityUnder50Chip
}
waffle1DropDensity40_met4 = DENSITY cmm4WaffleDrop > 0.4 <= 0.5 WINDOW 700 STEP 70
met4_DensityUnder40 = DENSITY met4outOxide_drc < 0.4 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity40_met4 RDB met4.chip.low.DEN_under_40_fill_block.1.rdb
met4_DensityUnder40Chip = INTERACT met4_DensityUnder40 entireChipForDensity
met4_DensityUnder40tmp = met4_DensityUnder40 NOT met4_DensityUnder40Chip
met4_DensityUnder40IP = met4_DensityUnder40tmp AND chipAreaBigEnough
met4.low.DEN_under_40_fill_block.1_IP {
    @ met4.low.DEN_under_40_fill_block.1_IP: met4 density when 700x700 window 40-50% covered by met4 fill block (IP) < 40%
    COPY met4_DensityUnder40IP
}
met4.low.DEN_under_40_fill_block.1_CHIP {
    @ met4.low.DEN_under_40_fill_block.1_CHIP: met4 density when 700x700 window 40-50% covered by met4 fill block (CHIP) < 40%
    COPY met4_DensityUnder40Chip
}
waffle1DropDensity30_met4 = DENSITY cmm4WaffleDrop > 0.3 <= 0.4 WINDOW 700 STEP 70
met4_DensityUnder30 = DENSITY met4outOxide_drc < 0.3 WINDOW 700 STEP 70 INSIDE of LAYER waffle1DropDensity30_met4 RDB met4.chip.low.DEN_under_30_fill_block.1.rdb
met4_DensityUnder30Chip = INTERACT met4_DensityUnder30 entireChipForDensity
met4_DensityUnder30tmp = met4_DensityUnder30 NOT met4_DensityUnder30Chip
met4_DensityUnder30IP = met4_DensityUnder30tmp AND chipAreaBigEnough
met4.low.DEN_under_30_fill_block.1_IP {
    @ met4.low.DEN_under_30_fill_block.1_IP: met4 density when 700x700 window 30-40% covered by met4 fill block (IP) < 30%
    COPY met4_DensityUnder30IP
}
met4.low.DEN_under_30_fill_block.1_CHIP {
    @ met4.low.DEN_under_30_fill_block.1_CHIP: met4 density when 700x700 window 30-40% covered by met4 fill block (CHIP) < 30%
    COPY met4_DensityUnder30Chip
}
 #IFDEF GENERATE_PREDICTIVE_FILL 
nwell_diff_keepout_1 = (SIZE nwell BY 0.34) NOT (SIZE NWELL BY -0.18)
nwell_diff_keepout_2 = (SIZE (HOLES nwell) BY 0.34) NOT (SIZE (HOLES NWELL) BY -0.18)
nwell_diff_poly_keepout = nwell_diff_keepout_1 OR nwell_diff_keepout_2
diff_poly_keepout = SIZE (OR pwbm pwres PHdiodeID) BY 0.5
diff_keepout_0 = SIZE (OR pwbm pwres PHdiodeID) BY 0.5
diff_keepout_1 = SIZE diffi BY 0.5
diff_keepout_2 = SIZE target BY 3.295
diff_keepout_3 = SIZE nsm BY 1
diff_keepout_4 = SIZE dieCut BY 3
diff_keepout_5 = SIZE fomWaffDrop BY 0.4
diff_keepout_6 = SIZE (OR diff_block polyi fomWaffDrop P1Mmk)  BY 0.30
diff_keepout = OR nwell_diff_poly_keepout diff_keepout_0 diff_keepout_1 diff_keepout_2 diff_keepout_3 diff_keepout_4 diff_keepout_5 diff_keepout_6
poly_keepout_1 = SIZE polyi BY 0.5
poly_keepout_2 = SIZE target BY 3.295
poly_keepout_3 = SIZE nsm BY 1
poly_keepout_4 = SIZE dieCut BY 3
poly_keepout_5 = SIZE (OR poly_block diffi cp1mWaffleDrop P1Mmk cfom)  BY 0.30
poly_keepout = OR diff_poly_keepout nwell_diff_poly_keepout poly_keepout_1 poly_keepout_2 poly_keepout_3 poly_keepout_4 poly_keepout_5
diff_target_fill_area_1st = fill_extent NOT diff_keepout
diff_psuedo_fill_1st = RECTANGLES 4.08 4.08 4.08 INSIDE OF LAYER diff_target_fill_area_1st
poly_target_fill_area_1st = fill_extent NOT (poly_keepout OR (SIZE diff_psuedo_fill_1st BY 0.3))
poly_psuedo_fill_1st = RECTANGLES 0.72 0.72 0.8 INSIDE OF LAYER poly_target_fill_area_1st OFFSET 1 1
diff_target_fill_area_2nd = diff_target_fill_area_1st NOT (OR (SIZE diff_psuedo_fill_1st BY 0.3) (SIZE poly_psuedo_fill_1st BY 0.3))
diff_psuedo_fill_2nd = RECTANGLES 2.05 2.05 1.32 INSIDE OF LAYER diff_target_fill_area_2nd
poly_target_fill_area_2nd = poly_target_fill_area_1st NOT (OR (SIZE poly_psuedo_fill_1st BY 0.26) (SIZE diff_target_fill_area_2nd BY 0.3))
poly_psuedo_fill_2nd = RECTANGLES 0.54 0.54 0.36 INSIDE OF LAYER poly_target_fill_area_2nd OFFSET 1 1
diff_target_fill_area_3rd = diff_target_fill_area_2nd NOT (OR (SIZE diff_psuedo_fill_2nd BY 0.3) (SIZE poly_psuedo_fill_2nd BY 0.3))
diff_psuedo_fill_3rd = RECTANGLES 1.5 1.5 1.32 INSIDE OF LAYER diff_target_fill_area_3rd OFFSET .5 .5
poly_target_fill_area_3rd = poly_target_fill_area_2nd NOT (OR (SIZE poly_psuedo_fill_2nd BY 0.26) (SIZE diff_psuedo_fill_3rd BY 0.3))
poly_psuedo_fill_3rd = RECTANGLES 0.48 0.48 0.36 INSIDE OF LAYER poly_target_fill_area_3rd OFFSET 1 1
diff_target_fill_area_4th = diff_target_fill_area_3rd NOT (OR (SIZE diff_psuedo_fill_3rd BY 0.3) (SIZE poly_psuedo_fill_3rd BY 0.3))
diff_psuedo_fill_4th = RECTANGLES 0.5 0.5 0.4 INSIDE OF LAYER diff_target_fill_area_4th
diff_psuedo_fill = OR diff_psuedo_fill_1st diff_psuedo_fill_2nd diff_psuedo_fill_3rd diff_psuedo_fill_4th
poly_psuedo_fill = OR poly_psuedo_fill_1st poly_psuedo_fill_2nd poly_psuedo_fill_3rd
 #ENDIF  //predictive fill
 #IFDEF GENERATE_PREDICTIVE_FILL 
diff_layer_to_check = OR diffi diff_psuedo_fill
poly_layer_to_check = OR polyi poly_psuedo_fill
view_diff_predictive_fill {
    COPY diff_psuedo_fill
}
view_poly_predictive_fill {
    COPY poly_psuedo_fill
}
 #ENDIF  //predictive fill
 #IFNDEF GENERATE_PREDICTIVE_FILL 
diff_layer_to_check = COPY diffi
poly_layer_to_check = COPY polyi
 #ENDIF  //predictive fill
 #IFDEF GENERATE_LOCAL_DENSITY 
diff.local.low.DEN.1 {
    @ diff.local.low.DEN.1: Layer diff local density (50 square micron window stepped at 25) < 28%
    DENSITY diff_layer_to_check < .28 WINDOW 50 STEP 25 INSIDE OF LAYER fill_extent RDB diff_local_low_density.rdb
}
diff.local.high.DEN.1 {
    @ diff.local.high.DEN.1: Layer diff local density (50 square micron window stepped at 25) > 62%
    DENSITY diff_layer_to_check > 0.62 WINDOW 50 STEP 25 INSIDE OF LAYER fill_extent RDB diff_local_high_density.rdb
}
 #ENDIF 
diff.chip.low.DEN.1 {
    @ diff.chip.low.DEN.1: Layer diff chip density (500 square micron window stepped at 100) < 28%
    DENSITY diff_layer_to_check < .28 WINDOW 500 STEP 100 INSIDE OF LAYER fill_extent RDB diff_chip_low_density.rdb
}
diff.chip.high.DEN.1 {
    @ diff.chip.high.DEN.1: Layer diff chip density (500 square micron window stepped at 100) > 62%
    DENSITY diff_layer_to_check > 0.62 WINDOW 500 STEP 100 INSIDE OF LAYER fill_extent RDB diff_chip_high_density.rdb
}
 #IFDEF GENERATE_LOCAL_DENSITY 
poly.local.low.DEN.1 {
    @ poly.local.low.DEN.1: Layer poly local density (50 square micron window stepped at 25) < 30%
    DENSITY poly_layer_to_check < .30 WINDOW 50 STEP 25 INSIDE OF LAYER fill_extent RDB poly_local_low_density.rdb
}
poly.local.high.DEN.1 {
    @ poly.local.high.DEN.1: Layer poly local density (50 square micron window stepped at 25) > 40%
    DENSITY poly_layer_to_check > 0.40 WINDOW 50 STEP 25 INSIDE OF LAYER fill_extent RDB poly_local_high_density.rdb
}
 #ENDIF 
poly.chip.low.DEN.1 {
    @ poly.chip.low.DEN.1: Layer poly chip density (500 square micron window stepped at 100) < 30%
    DENSITY poly_layer_to_check < .30 WINDOW 500 STEP 100 INSIDE OF LAYER fill_extent RDB poly_chip_low_density.rdb
}
poly.chip.high.DEN.1 {
    @ poly.chip.high.DEN.1: Layer poly chip density (500 square micron window stepped at 100) > 52%
    DENSITY poly_layer_to_check > 0.52 WINDOW 500 STEP 100 INSIDE OF LAYER fill_extent RDB poly_chip_high_density.rdb
}
 #ENDIF //skip density check
 

#IFNDEF SKIP_LATCHUP_CHECKS 


latchup.WARN.1 {
    @ latchup.WARN.1: No pads have any markers for IO, PWR or GND
    SIZE (boundary NOT INTERACT (OR (pad INTERACT pad_io) (pad INTERACT pad_gnd) (pad INTERACT pad_pwr))) BY -5.0
}
latchup.WARN.2 {
    @ latchup.WARN.2: pad does not have a marker for IO, PWR or GND
    pad NOT INTERACT (OR pad_io pad_gnd pad_pwr)
}
diff_and_nw = diffi AND nwell
diff_not_pdiff = diffi NOT diff_and_nw
tap_and_nw = tap AND nwell
tap_not_nw = tap NOT tap_and_nw
nsrcdrn_lu = diff_not_pdiff NOT (gate OR diffres)
psrcdrn_lu = diff_and_nw NOT (gate OR diffres)
poly_no_res = poly NOT polyres
poly_res_lu = poly AND polyres
ndiff_res_lu = diff_not_pdiff AND diffres
pdiff_res_lu = diff_and_nw AND diffres
metal1 = COPY met1i
metal2 = COPY met2i
metal3 = COPY met3i
metal4 = COPY met4i
metal5 = COPY met5i
met1res = COPY m1res
met2res = COPY m2res
met3res = COPY m3res
met4res = COPY m4res
met5res = COPY m5res
m1_esd_res = (metal1 AND met1res) AND ESDID
m1_not_esd_res = metal1 NOT m1_esd_res
m2_esd_res = (metal2 AND met2res) AND ESDID
m2_not_esd_res = metal2 NOT m2_esd_res
m3_esd_res = (metal3 AND met3res) AND ESDID
m3_not_esd_res = metal3 NOT m3_esd_res
m4_esd_res = (metal4 AND met4res) AND ESDID
m4_not_esd_res = metal4 NOT m4_esd_res
m5_esd_res = (metal5 AND met5res) AND ESDID
m5_not_esd_res = metal5 NOT m5_esd_res
licon_outs_diff = Licon OUTSIDE diffTap
licon_not_outs_diff = Licon NOT licon_outs_diff
licon_nfom = (licon_not_outs_diff AND diff_not_pdiff) OR (licon_not_outs_diff AND tap_and_nw)
licon_pfom = (licon_not_outs_diff AND diff_and_nw) OR (licon_not_outs_diff AND tap_not_nw)
licon_diff = licon_not_outs_diff AND diff
pad_not_probe = pad NOT (WITH TEXT pad "probe-only" textdraw)
probe_pad_not_probe = WITH TEXT pad "probe-only" textdraw
switched_intPower_met1 = WITH TEXT met1 "switched_power" textdraw
dnw_and_nw = dnwell AND nwell
iso_sub = boundary NOT ((dnwell NOT (SIZE dnwell BY -0.01)) OR dnw_and_nw)
local_sub_ring = localSub NOT (SIZE localSub BY -0.005)
sub_local2 = iso_sub NOT local_sub_ring
isolated_sub = COPY sub_local2
isolated_sub_no_pwr = isolated_sub NOT pwres
iso_sub_ptap = tap_not_nw AND isolated_sub_no_pwr

   DISCONNECT
   CONNECT nwell tap_and_nw
   CONNECT isolated_sub_no_pwr tap_not_nw BY iso_sub_ptap
   CONNECT li tap_not_nw BY licon_pfom
   CONNECT li tap_and_nw BY licon_nfom
   CONNECT li psrcdrn_lu BY licon_pfom
   CONNECT li nsrcdrn_lu BY licon_nfom
   CONNECT m1_not_esd_res li BY mcon
   CONNECT m2_not_esd_res m1_not_esd_res BY via1
   CONNECT m3_not_esd_res m2_not_esd_res BY via2
   CONNECT m3_not_esd_res met3
   CONNECT m2_not_esd_res met2
   CONNECT m1_not_esd_res met1
   CONNECT nsrcdrn_lu diff
   CONNECT psrcdrn_lu diff
   CONNECT switched_intPower_met1 m1_not_esd_res
   CONNECT li poly_no_res BY licon_outs_diff
   CONNECT poly_no_res gate
   CONNECT pad_not_probe m5_not_esd_res
   CONNECT probe_pad_not_probe m5_not_esd_res
   CONNECT m5_not_esd_res m4_not_esd_res BY via4_c
   CONNECT m4_not_esd_res m3_not_esd_res BY via3_c
   CONNECT rdl pad_not_probe BY pmm
   CONNECT rdl probe_pad_not_probe BY pmm

vccNetstap_and_nw = NET tap_and_nw "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccSiptap_and_nw = NET AREA RATIO tap_and_nw switched_intPower_met1 > 0
vcctap_and_nw = vccNetstap_and_nw OR vccSiptap_and_nw
vsstap_not_nw = NET tap_not_nw "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vcctap_not_nw = NET tap_not_nw "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vssNSD = NET nsrcdrn_lu "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vssPSD = NET psrcdrn_lu "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
vccNetsPSD = NET psrcdrn_lu "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccSipPSD = NET AREA RATIO psrcdrn_lu switched_intPower_met1 > 0
vccNetsNSD = NET nsrcdrn_lu "vpwr" "vpwr1" "vpwr3" "vpwr_prb" "vccio" "vpwr2"
vccSipNSD = NET AREA RATIO nsrcdrn_lu switched_intPower_met1 > 0
vccPSD = vccNetsPSD OR vccSipPSD
vccNSD = vccNetsNSD OR vccSipNSD
vssNwell = NET nwell "vgnd" "vgnd1" "vgnd3" "vgnd_prb" "vgnd_pad" "vssio"
lvvccNwell = COPY 4000
ioNSDnet = NET nsrcdrn_lu "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
ioPSDnet = NET psrcdrn_lu "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
iotap_and_nwnet = NET tap_and_nw "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
iotap_not_nwnet = NET tap_not_nw "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
ioPads = NET pad_not_probe "io" "io1" "io2" "io4" "io_prb" "pad5v" "io_pad" "pad"
ioPadConnNSDnet = NET AREA RATIO nsrcdrn_lu ioPads > 0
ioPadConnPSDnet = NET AREA RATIO psrcdrn_lu ioPads > 0
NSDsigPad = nsrcdrn_lu INSIDE SigPadDiff
PSDsigPad = psrcdrn_lu INSIDE SigPadDiff
SigPadNtr = SigPadMetNtr INSIDE SigPadDiff
NSDsigPadNtr = nsrcdrn_lu INSIDE SigPadNtr
PSDsigPadNtr = psrcdrn_lu INSIDE SigPadNtr
tap_and_nwsigPad = tap_and_nw INSIDE SigPadDiff
tap_not_nwsigPad = tap_not_nw INSIDE SigPadDiff
tap_and_nwsigPadNtr = tap_and_nw INSIDE SigPadNtr
tap_not_nwsigPadNtr = tap_not_nw INSIDE SigPadNtr
SigPadWellNtr = SigPadMetNtr INSIDE SigPadWell
nwellSigPadNtr = nwell INSIDE SigPadWellNtr
NSDsigPadConn = STAMP NSDSigPad BY nsrcdrn_lu
PSDsigPadConn = STAMP PSDSigPad BY psrcdrn_lu
tap_and_nwsigPadConn = STAMP tap_and_nwSigPad BY tap_and_nw
tap_not_nwsigPadConn = STAMP tap_not_nwSigPad BY tap_not_nw
ioNSD = NSDsigPad OR ioNSDnet
ioPSD = PSDsigPad OR ioPSDnet
iotap_and_nw = tap_and_nwsigPad OR iotap_and_nwnet
iotap_not_nw = tap_not_nwsigPad OR iotap_not_nwnet
ioPadConnNSD = NSDsigPadNtr OR ioPadConnNSDnet
ioPadConnPSD = PSDsigPadNtr OR ioPadConnPSDnet
ioNSDntr = (NSDsigPad AND sigPadMetNtr) OR ioNSDnet
ioPSDntr = (PSDsigPad AND sigPadMetNtr) OR ioPSDnet
ntapRing = (DONUT tap_and_nw) NOT SEALID
ptapRing = (DONUT tap_not_nw) NOT SEALID
ptapRingFilled = HOLES ptapRing
pTaplicon = licon AND tap_not_nw
nTaplicon = licon AND tap_and_nw
pTapliconVss = licon AND vsstap_not_nw
pTapliconNonVss = pTaplicon NOT pTapliconVss
nTapliconVcc = licon AND vcctap_and_nw
POLYanddiff_not_pdiff = poly AND diff_not_pdiff
POLYanddiff_and_nw = poly AND diff_and_nw
diffCore = diff AND COREID
ndiffPeri = diff_not_pdiff NOT diffCore
pdiffPeri = diff_and_nw NOT diffCore
nwellArea = (SIZE diff_and_nw BY 1.5) AND nwell
pwellArea = (SIZE diff_not_pdiff BY 1.5) NOT nwell
nonVccNwell = nwell OUTSIDE vcctap_and_nw
nonPnpNTap = tap_and_nw NOT pnp
nonPnpPTap = tap_not_nw NOT pnp
nDiffRing = DONUT diff_not_pdiff
nDiffHole = HOLES nDiffRing
nWellTap = nwell INSIDE tap_and_nw
nWellTapInHole = nDiffHole INSIDE nWellTap
ESDnWellTapTmp = nWellTapInHole AND ESDID
ESDnWellTap = STAMP ESDnWellTapTmp BY tap_and_nw
nwellDIOESD = nwell AND (ESDID AND DIODEID)
ESD_diode = nwellDIOESD OUTSIDE (ESDnWellTap OR poly)
ESD_diff = diff AND ESDID
vssNwellNoXmtCells = vssNwell NOT (INSIDE CELL nwell "s8iom0s8_top_lvc_b2b_wopad" "s8iom0s8_top_lvclamp" "s8atlasana_esd_gnd2gnd_sub_dnwl" "s8fpafeg1_tk_lvc_b2b_wopad")
ptapRingFilledNotRing = ptapRingFilled NOT ptapRing
ptapRingWithVssNwell = ptapRingFilledNotRing INTERACT vssNwellNoXmtCells
ptapRingNoVssNwell = ptapRing INTERACT (ptapRingFilledNotRing NOT INTERACT vssNwellNoXmtCells)
vssNwellPtapRing = (ptapRing NOT ptapRingNoVssNwell) OUTSIDE ptapRingWithVssNwell

DISCONNECT
CONNECT met5 met4 BY via4_c
CONNECT met4 met3 BY via3_c
CONNECT met4 m4_bot_plate BY cap2m_cont_dmy
CONNECT met3 met2 BY via2


CONNECT met3 m3_bot_plate BY capm_cont_dmy
CONNECT met2 met1 BY via1
CONNECT met1 li    BY mcon
CONNECT li nsd     BY licon
CONNECT li psd     BY licon
CONNECT li ntap    BY licon
CONNECT li ptap    BY licon
CONNECT li ptubtap BY licon
CONNECT li poly    BY licon

CONNECT ntap nwell
CONNECT ptap pwell
CONNECT ptubtap ptub
CONNECT nwell dnwell

CONNECT met5 pad
CONNECT met5 uprobe_pad
CONNECT met5 probe_pad
CONNECT rdl pad
CONNECT rdl uprobe_pad
CONNECT rdl probe_pad

gnd_pad = pad INTERACT pad_gnd
pad_gnd_net_m5 = NET AREA RATIO met5 gnd_pad > 0
pad_gnd_net_m4 = NET AREA RATIO met4 gnd_pad > 0
pad_gnd_net_m3 = NET AREA RATIO met3 gnd_pad > 0
pad_gnd_net_m2 = NET AREA RATIO met2 gnd_pad > 0
pad_gnd_net_m1 = NET AREA RATIO met1 gnd_pad > 0
pad_gnd_net_li = NET AREA RATIO li gnd_pad > 0
pad_gnd_net_nsd = NET AREA RATIO nsd gnd_pad > 0
pad_gnd_net_psd = NET AREA RATIO psd gnd_pad > 0
pad_gnd_net_poly = NET AREA RATIO poly gnd_pad > 0
pad_gnd_net_nw = NET AREA RATIO nwell gnd_pad > 0
pad_gnd_net_dnw = NET AREA RATIO dnwell gnd_pad > 0
pad_gnd_net_pw = NET AREA RATIO pwell gnd_pad > 0
pad_gnd_net_ntap = NET AREA RATIO ntap gnd_pad > 0
pad_gnd_net_ptap = NET AREA RATIO ptap gnd_pad > 0
gnd_net_to_pad1 = OR pad_gnd_net_m5 pad_gnd_net_m4 pad_gnd_net_m3 pad_gnd_net_m2 pad_gnd_net_m1
gnd_net_to_pad2 = OR gnd_net_to_pad1 pad_gnd_net_nsd pad_gnd_net_psd pad_gnd_net_poly
gnd_net_to_pad = OR gnd_net_to_pad2 pad_gnd_net_ntap pad_gnd_net_ptap pad_gnd_net_nw pad_gnd_net_pw
sig_pad = pad INTERACT pad_io
pad_sig_net_m5 = NET AREA RATIO met5 sig_pad > 0
pad_sig_net_m4 = NET AREA RATIO met4 sig_pad > 0
pad_sig_net_m3 = NET AREA RATIO met3 sig_pad > 0
pad_sig_net_m2 = NET AREA RATIO met2 sig_pad > 0
pad_sig_net_m1 = NET AREA RATIO met1 sig_pad > 0
pad_sig_net_li = NET AREA RATIO li sig_pad > 0
pad_sig_net_nsd = NET AREA RATIO nsd sig_pad > 0
pad_sig_net_psd = NET AREA RATIO psd sig_pad > 0
pad_sig_net_poly = NET AREA RATIO poly sig_pad > 0
pad_sig_net_nw = NET AREA RATIO nwell sig_pad > 0
pad_sig_net_dnw = NET AREA RATIO dnwell sig_pad > 0
pad_sig_net_pw = NET AREA RATIO pwell sig_pad > 0
pad_sig_net_ntap = NET AREA RATIO ntap sig_pad > 0
pad_sig_net_ptap = NET AREA RATIO ptap sig_pad > 0
sig_net_to_pad1 = OR pad_sig_net_m5 pad_sig_net_m4 pad_sig_net_m3 pad_sig_net_m2 pad_sig_net_m1
sig_net_to_pad2 = OR sig_net_to_pad1 pad_sig_net_nsd pad_sig_net_psd pad_sig_net_poly
sig_net_to_pad = OR sig_net_to_pad2 pad_sig_net_ntap pad_sig_net_ptap pad_sig_net_nw pad_sig_net_pw
pwr_pad = pad INTERACT pad_pwr
pad_pwr_net_m5 = NET AREA RATIO met5 pwr_pad > 0
pad_pwr_net_m4 = NET AREA RATIO met4 pwr_pad > 0
pad_pwr_net_m3 = NET AREA RATIO met3 pwr_pad > 0
pad_pwr_net_m2 = NET AREA RATIO met2 pwr_pad > 0
pad_pwr_net_m1 = NET AREA RATIO met1 pwr_pad > 0
pad_pwr_net_li = NET AREA RATIO li pwr_pad > 0
pad_pwr_net_nsd = NET AREA RATIO nsd pwr_pad > 0
pad_pwr_net_psd = NET AREA RATIO psd pwr_pad > 0
pad_pwr_net_ntap = NET AREA RATIO ntap pwr_pad > 0
pad_pwr_net_ptap = NET AREA RATIO ptap pwr_pad > 0
pad_pwr_net_poly = NET AREA RATIO poly pwr_pad > 0
pad_pwr_net_nw = NET AREA RATIO nwell pwr_pad > 0
pad_pwr_net_pw = NET AREA RATIO pwell pwr_pad > 0
pwr_net_to_pad1 = OR pad_pwr_net_m5 pad_pwr_net_m4 pad_pwr_net_m3 pad_pwr_net_m2 pad_pwr_net_m1
pwr_net_to_pad2 = OR pwr_net_to_pad1 pad_pwr_net_nsd pad_pwr_net_psd pad_pwr_net_poly
pwr_net_to_pad = OR pwr_net_to_pad2 pad_pwr_net_ntap pad_pwr_net_ptap pad_pwr_net_nw pad_pwr_net_pw
sealHole = HOLES SEALID
sig_pad_diff = OR pad_sig_net_nsd pad_sig_net_psd pad_sig_net_ntap pad_sig_net_ptap
io_region = SIZE sig_pad_diff BY 50 INSIDE OF sealHole STEP 5
ptap_licon = (ptap AND licon) NOT nwell
ntap_licon = (ntap AND licon) AND (nwell OR dnwell)
ptap_licon_size_6 = SIZE ptap_licon BY 6 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
ntap_licon_size_6 = SIZE ntap_licon BY 6 INSIDE OF (nwell OR dnwell) STEP 0.59 TRUNCATE 2.61
ptap_licon_size_15 = SIZE ptap_licon BY 15 OUTSIDE OF nwell STEP 0.59 TRUNCATE 2.61
ntap_licon_size_15 = SIZE ntap_licon BY 15 INSIDE OF (nwell OR dnwell) STEP 0.59 TRUNCATE 2.61
ndiff_in_ioregion = nsd AND io_region
pdiff_in_ioregion = psd AND io_region
pdiff_not_in_ioregion = psd NOT io_region
ndiff_not_in_ioregion = nsd NOT io_region
pwell_has_ptap_licon = ((pwell or ptub) AND sealHole) ENCLOSE ptap_licon
pwell_has_ptap_io_ndiff = ((pwell or ptub) AND sealHole) ENCLOSE ndiff_in_ioregion
pwell_has_ptap_no_io_ndiff = ((pwell or ptub) AND sealHole) NOT ENCLOSE ndiff_in_ioregion
pwell_has_both_io = pwell_has_ptap_licon AND pwell_has_ptap_io_ndiff
pwell_has_both_not_io = pwell_has_ptap_licon AND pwell_has_ptap_no_io_ndiff
nwell_has_ntap_licon = ((nwell or dnwell) AND sealHole) ENCLOSE ntap_licon
nwell_has_ntap_io_ndiff = ((nwell or dnwell) AND sealHole) ENCLOSE ndiff_in_ioregion
nwell_has_ntap_no_io_ndiff = ((nwell or dnwell) AND sealHole) NOT ENCLOSE ndiff_in_ioregion
nwell_has_both_io = nwell_has_ntap_licon AND nwell_has_ntap_io_ndiff
nwell_has_both_not_io = nwell_has_ntap_licon AND nwell_has_ntap_no_io_ndiff
latchup.generic.2a {
    @ latchup.generic.2a: Max spacing from center of ptap licon to any part of ndiff within the same ptub or pwell (< 50u away from diff connected to a signal pad) > 6
    (((ndiff_in_ioregion AND nsd) NOT ESDID) NOT ptap_licon_size_6) INSIDE pwell_has_both_io
}
latchup.generic.2b {
    @ latchup.generic.2b: Max spacing from center of ptap licon to any part of ndiff within the same ptub or pwell (>= 50u away from diff connected to a signal pad) > 15
    (((ndiff_not_in_ioregion AND nsd) NOT ESDID) NOT ptap_licon_size_15) INSIDE pwell_has_both_not_io
}
pos_pwr_pdiff = (ptap OR psd) AND pwr_net_to_pad
dnw_has_pos_pwr_pdiff = dnwell ENCLOSE pos_pwr_pdiff
nw_has_pos_pwr_pdiff = nwell INTERACT dnw_has_pos_pwr_pdiff
dnw_or_nw_pwr_pdiff = OR dnw_has_pos_pwr_pdiff nw_has_pos_pwr_pdiff
dnw_no_pos_pwr_pdiff = dnwell NOT ENCLOSE pos_pwr_pdiff
nw_no_pos_pwr_pdiff = (nwell INTERACT dnwell) NOT INTERACT dnw_has_pos_pwr_pdiff
dnw_or_nw_no_pwr_pdiff = OR dnw_no_pos_pwr_pdiff nw_no_pos_pwr_pdiff
latchup.generic.2.1a_b {
    @ latchup.generic.2.1a_b: Max spacing from center of ptap licon to N+ diff within the same pwell where the deep nwell or nwell forming the pwell, does NOT contain a pdiff connected to a power pad > 6
    ((((ndiff_in_ioregion AND nsd) NOT ESDID) NOT COREID) NOT ptap_licon_size_6) INSIDE dnw_or_nw_no_pwr_pdiff
}
latchup.generic.3a {
    @ latchup.generic.3a: Max spacing from center of ntap licon to pdiff within the same nwell or dnwell (< 50u away from diff connected to a signal pad ) > 6
    ((((pdiff_in_ioregion AND psd) NOT ESDID) NOT COREID) NOT ptap) NOT ntap_licon_size_6
}
latchup.generic.3b {
    @ latchup.generic.3a: Max spacing from center of ntap licon pdiff within the same nwell or dnwell (>= 50u away from diff connected signal pad) > 15
    ((((pdiff_not_in_ioregion AND psd) NOT ESDID) NOT COREID) NOT ptap) NOT ntap_licon_size_15
}
latchup.generic.4 {
    @ latchup.generic.4: Min distance from diffusion connected to a signal pad to areaid:core < 50.0
    EXT (COREID AND sealHole) (pad_sig_net_nsd AND sealHole) < 50.0 ABUT<90 REGION
    EXT (COREID AND sealHole) (pad_sig_net_psd AND sealHole) < 50.0 ABUT<90 REGION
    EXT (COREID AND sealHole) (pad_sig_net_ntap AND sealHole) < 50.0 ABUT<90 REGION
    (EXT COREID pad_sig_net_ptap < 50.0 ABUT<90 REGION) INSIDE sealHole
}
upad_probe_net_m5 = NET AREA RATIO met5 uprobe_pad > 0
upad_probe_net_m4 = NET AREA RATIO met4 uprobe_pad > 0
upad_probe_net_m3 = NET AREA RATIO met3 uprobe_pad > 0
upad_probe_net_m2 = NET AREA RATIO met2 uprobe_pad > 0
upad_probe_net_m1 = NET AREA RATIO met1 uprobe_pad > 0
upad_probe_net_li = NET AREA RATIO li uprobe_pad > 0
upad_probe_net_nsd = NET AREA RATIO nsd uprobe_pad > 0
upad_probe_net_psd = NET AREA RATIO psd uprobe_pad > 0
ppad_probe_net_m5 = NET AREA RATIO met5 probe_pad > 0
ppad_probe_net_m4 = NET AREA RATIO met4 probe_pad > 0
ppad_probe_net_m3 = NET AREA RATIO met3 probe_pad > 0
ppad_probe_net_m2 = NET AREA RATIO met2 probe_pad > 0
ppad_probe_net_m1 = NET AREA RATIO met1 probe_pad > 0
ppad_probe_net_li = NET AREA RATIO li probe_pad > 0
ppad_probe_net_nsd = NET AREA RATIO nsd probe_pad > 0
ppad_probe_net_psd = NET AREA RATIO psd probe_pad > 0
pad_probe_net_nsd = OR upad_probe_net_nsd ppad_probe_net_nsd
pad_probe_net_psd = OR upad_probe_net_psd ppad_probe_net_psd
latchup.generic.5a {
    @ latchup.generic.5a: Min. space N+ diff to unrelated N+ diff inside a common ptub or common pwell (metallically connected to separate pads or external nets - ground, power or signal) < 3
    exempt = OR ESDID pad_probe_net_nsd
    (EXT (pad_sig_net_nsd NOT exempt) (pad_pwr_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE pwell
    (EXT (pad_sig_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE pwell
    (EXT (pad_pwr_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE pwell
    (EXT (pad_sig_net_nsd NOT exempt) (pad_pwr_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE ptub
    (EXT (pad_sig_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE ptub
    (EXT (pad_pwr_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE ptub
    (EXT (pad_sig_net_nsd NOT exempt) (pad_pwr_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE localSub
    (EXT (pad_sig_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE localSub
    (EXT (pad_pwr_net_nsd NOT exempt) (pad_gnd_net_nsd NOT exempt) < 3.0 ABUT<90 REGION) INSIDE localSub
}
latchup.generic.5b {
    @ latchup.generic.5b: Min. space P+ diff to unrelated P+ diff inside a common nwell or dnwell (metallically connected to separate pads or external nets - ground, power or signal) < 3
    exempt = OR ESDID pad_probe_net_psd
    (EXT (pad_sig_net_psd NOT exempt) (pad_pwr_net_psd NOT exempt) < 3.0 ABUT<90 REGION NOT CONNECTED) INSIDE (OR nwell (dnwell NOT INTERACT ptub))
    (EXT (pad_sig_net_psd NOT exempt) (pad_gnd_net_psd NOT exempt) < 3.0 ABUT<90 REGION NOT CONNECTED) INSIDE (OR nwell (dnwell NOT INTERACT ptub))
    (EXT (pad_pwr_net_psd NOT exempt) (pad_gnd_net_psd NOT exempt) < 3.0 ABUT<90 REGION NOT CONNECTED) INSIDE (OR nwell (dnwell NOT INTERACT ptub))
}
ntap_grd_ring = HOLES ntap
ptap_grd_ring = HOLES ptap
latchup.signal.2 {
    @ latchup.signal.2: Signal connected nwell must be in a pair of guard rings
    pass_1 = pad_sig_net_nw INSIDE ntap_grd_ring
    pass_2 = pass_1 INSIDE ptap_grd_ring
    pad_sig_net_nw NOT pass_2
}
latchup.signal.2.1a {
    @ latchup.signal.2.1a: Signal pad connected deep nwell is not allowed
    COPY pad_sig_net_dnw
}
diff_res_gt_250ohm = diffres WITH TEXT "250Ohm" textdraw
diff_res_gt_1kohm = diffres WITH TEXT "1kOhm" textdraw
diff_res_lg_res = OR diff_res_gt_250ohm diff_res_gt_1kohm
poly_res_gt_250ohm = polyres WITH TEXT "250Ohm" textdraw
poly_res_gt_1kohm = polyres WITH TEXT "1kOhm" textdraw
poly_res_lg_res = OR poly_res_gt_250ohm poly_res_gt_1kohm
li_res_gt_250ohm = lires WITH TEXT "250Ohm" textdraw
li_res_gt_1kohm = lires WITH TEXT "1kOhm" textdraw
li_res_lg_res = OR li_res_gt_250ohm li_res_gt_1kohm
m1_res_gt_250ohm = m1res WITH TEXT "250Ohm" textdraw
m1_res_gt_1kohm = m1res WITH TEXT "1kOhm" textdraw
m1_res_lg_res = OR m1_res_gt_250ohm m1_res_gt_1kohm
m2_res_gt_250ohm = m2res WITH TEXT "250Ohm" textdraw
m2_res_gt_1kohm = m2res WITH TEXT "1kOhm" textdraw
m2_res_lg_res = OR m2_res_gt_250ohm m2_res_gt_1kohm
m3_res_gt_250ohm = m3res WITH TEXT "250Ohm" textdraw
m3_res_gt_1kohm = m3res WITH TEXT "1kOhm" textdraw
m3_res_lg_res = OR m3_res_gt_250ohm m3_res_gt_1kohm
m4_res_gt_250ohm = m4res WITH TEXT "250Ohm" textdraw
m4_res_gt_1kohm = m4res WITH TEXT "1kOhm" textdraw
m4_res_lg_res = OR m4_res_gt_250ohm m4_res_gt_1kohm
m5_res_gt_250ohm = m5res WITH TEXT "250Ohm" textdraw
m5_res_gt_1kohm = m5res WITH TEXT "1kOhm" textdraw
m5_res_lg_res = OR m5_res_gt_250ohm m5_res_gt_1kohm
pw_res_gt_250ohm = pwres WITH TEXT "250Ohm" textdraw
pw_res_gt_1kohm = pwres WITH TEXT "1kOhm" textdraw
pw_res_lg_res = OR pw_res_gt_250ohm pw_res_gt_1kohm
pw_lu = pwell NOT pw_res_lg_res
diff_lu = diffi NOT diff_res_lg_res
poly_lu = polyi NOT poly_res_lg_res
nsd_lu = nsd NOT diff_res_lg_res
psd_lu = psd NOT diff_res_lg_res
li_lu = li_i NOT li_res_lg_res
m1_lu = met1i NOT m1_res_lg_res
m2_lu = met2i NOT m2_res_lg_res
m3_lu = met3i NOT m3_res_lg_res
m4_lu = met4i NOT m4_res_lg_res
m5_lu = met5i NOT m5_res_lg_res

DISCONNECT
        CONNECT m5_lu m4_lu   BY via4_c
        CONNECT m4_lu m3_lu   BY via3_c
        CONNECT m3_lu m2_lu   BY via2
        CONNECT m2_lu m1_lu   BY via1
        CONNECT m1_lu li_lu   BY mcon
        CONNECT li_lu nsd_lu  BY licon
        CONNECT li_lu psd_lu  BY licon
        CONNECT li_lu ntap BY licon
        CONNECT li_lu ptap BY licon
        CONNECT li_lu ptubtap BY licon
        CONNECT li_lu poly BY licon

        CONNECT ntap nwell
        CONNECT ptap pw_lu
        CONNECT ptubtap ptub
        CONNECT nwell dnwell

        CONNECT m5_lu pad
        CONNECT m5_lu uprobe_pad
        CONNECT m5_lu probe_pad
        CONNECT rdl pad
        CONNECT rdl uprobe_pad
        CONNECT rdl probe_pad

gnd_pad2 = pad INTERACT pad_gnd
pad_gnd2_net_dnw = NET AREA RATIO dnwell gnd_pad2 > 0
pad_gnd2_net_nsd = NET AREA RATIO nsd_lu gnd_pad2 > 0
pad_gnd2_net_ntap = NET AREA RATIO ntap gnd_pad2 > 0
pad_gnd2_net_nw = NET AREA RATIO nwell gnd_pad2 > 0
latchup.signal.2.1b {
    @ latchup.signal.2.1b: Deep nwell tied to ground through a resistance of < 250 ohm is not allowed
    exempt_lu_sig_2p1b_a = NET AREA RATIO nsd_lu gnd_pad2 > 0
    exempt_lu_sig_2p1b_b = NET AREA RATIO dnwell gnd_pad2 > 0
    exempt_lu_sig_2p1b = exempt_lu_sig_2p1b_b ENCLOSE exempt_lu_sig_2p1b_a
    COPY (pad_gnd2_net_dnw NOT exempt_lu_sig_2p1b)
}

DISCONNECT
CONNECT met5 met4 BY via4_c
CONNECT met4 met3 BY via3_c
CONNECT met4 m4_bot_plate BY cap2m_cont_dmy
CONNECT met3 met2 BY via2


CONNECT met3 m3_bot_plate BY capm_cont_dmy
CONNECT met2 met1 BY via1
CONNECT met1 li    BY mcon
CONNECT li nsd     BY licon
CONNECT li psd     BY licon
CONNECT li ntap    BY licon
CONNECT li ptap    BY licon
CONNECT li ptubtap BY licon
CONNECT li poly    BY licon

CONNECT ntap nwell
CONNECT ptap pwell
CONNECT ptap localSub
CONNECT ptubtap ptub
CONNECT nwell dnwell

CONNECT met5 pad
CONNECT met5 uprobe_pad
CONNECT met5 probe_pad
CONNECT rdl pad
CONNECT rdl uprobe_pad
CONNECT rdl probe_pad

latchup.signal.3 {
    @ latchup.signal.3: All P+ diff or tap connected to signal pad must be in a pair of guard rings
    pass_1 = pad_sig_net_psd INSIDE ptap_grd_ring
    pass_2 = pass_1 INSIDE ntap_grd_ring
    pad_sig_net_psd NOT pass_2
    pass_1a = pad_sig_net_ptap INSIDE ptap_grd_ring
    pass_2a = pass_1a INSIDE ntap_grd_ring
    pad_sig_net_ptap NOT pass_2a
}
pwr2_pad = pad INTERACT pad_pwr
pad_pwr2_net_m5 = NET AREA RATIO met5 pwr2_pad > 0
pad_pwr2_net_m4 = NET AREA RATIO met4 pwr2_pad > 0
pad_pwr2_net_m3 = NET AREA RATIO met3 pwr2_pad > 0
pad_pwr2_net_m2 = NET AREA RATIO met2 pwr2_pad > 0
pad_pwr2_net_m1 = NET AREA RATIO met1 pwr2_pad > 0
pad_pwr2_net_li = NET AREA RATIO li pwr2_pad > 0
pad_pwr2_net_nsd = NET AREA RATIO nsd pwr2_pad > 0
pad_pwr2_net_psd = NET AREA RATIO psd pwr2_pad > 0
pad_pwr2_net_poly = NET AREA RATIO poly pwr2_pad > 0
pad_pwr2_net_nw = NET AREA RATIO nwell pwr2_pad > 0
pad_pwr2_net_pw = NET AREA RATIO pwell pwr2_pad > 0
pad_pwr2_net_ntap = NET AREA RATIO ntap pwr2_pad > 0
pad_pwr2_net_ptap = NET AREA RATIO ptap pwr2_pad > 0
pwr2_net_to_pad1 = OR pad_pwr2_net_m5 pad_pwr2_net_m4 pad_pwr2_net_m3 pad_pwr2_net_m2 pad_pwr2_net_m1
pwr2_net_to_pad2 = OR pwr2_net_to_pad1 pad_pwr2_net_nsd pad_pwr2_net_psd pad_pwr2_net_poly
pwr2_net_to_pad = OR pwr2_net_to_pad2 pad_pwr2_net_ntap pad_pwr2_net_ptap pad_pwr2_net_nw pad_pwr2_net_pw
latchup.signal.3.1a {
    @ latchup.signal.3.1a: signal connected ptap must have nwell/N+ guard ring connected to positive power pad
    (ntap INTERACT (ntap_grd_ring INTERACT pad_sig_net_ptap)) NOT pad_pwr2_net_ntap
}
gnd3_pad = pad INTERACT pad_gnd
pad_gnd3_net_m5 = NET AREA RATIO met5 gnd3_pad > 0
pad_gnd3_net_m4 = NET AREA RATIO met4 gnd3_pad > 0
pad_gnd3_net_m3 = NET AREA RATIO met3 gnd3_pad > 0
pad_gnd3_net_m2 = NET AREA RATIO met2 gnd3_pad > 0
pad_gnd3_net_m1 = NET AREA RATIO met1 gnd3_pad > 0
pad_gnd3_net_li = NET AREA RATIO li gnd3_pad > 0
pad_gnd3_net_nsd = NET AREA RATIO nsd gnd3_pad > 0
pad_gnd3_net_psd = NET AREA RATIO psd gnd3_pad > 0
pad_gnd3_net_poly = NET AREA RATIO poly gnd3_pad > 0
pad_gnd3_net_nw = NET AREA RATIO nwell gnd3_pad > 0
pad_gnd3_net_ntap = NET AREA RATIO ntap gnd3_pad > 0
pad_gnd3_net_ptap = NET AREA RATIO ptap gnd3_pad > 0
gnd3_net_to_pad1 = OR pad_gnd3_net_m5 pad_gnd3_net_m4 pad_gnd3_net_m3 pad_gnd3_net_m2 pad_gnd3_net_m1
gnd3_net_to_pad2 = OR gnd3_net_to_pad1 pad_gnd3_net_nsd pad_gnd3_net_psd pad_gnd3_net_poly
gnd3_net_to_pad = OR gnd3_net_to_pad2 pad_gnd3_net_ntap pad_gnd3_net_ptap pad_gnd3_net_nw
pwr3_pad = pad INTERACT pad_pwr
pad_pwr3_net_m5 = NET AREA RATIO met5 pwr3_pad > 0
pad_pwr3_net_m4 = NET AREA RATIO met4 pwr3_pad > 0
pad_pwr3_net_m3 = NET AREA RATIO met3 pwr3_pad > 0
pad_pwr3_net_m2 = NET AREA RATIO met2 pwr3_pad > 0
pad_pwr3_net_m1 = NET AREA RATIO met1 pwr3_pad > 0
pad_pwr3_net_li = NET AREA RATIO li pwr3_pad > 0
pad_pwr3_net_nsd = NET AREA RATIO nsd pwr3_pad > 0
pad_pwr3_net_psd = NET AREA RATIO psd pwr3_pad > 0
pad_pwr3_net_poly = NET AREA RATIO poly pwr3_pad > 0
pad_pwr3_net_nw = NET AREA RATIO nwell pwr3_pad > 0
pad_pwr3_net_pw = NET AREA RATIO pwell pwr3_pad > 0
pad_pwr3_net_ls = NET AREA RATIO localSub pwr3_pad > 0
pad_pwr3_net_pt = NET AREA RATIO ptub pwr3_pad > 0
pad_pwr3_net_ntap = NET AREA RATIO ntap pwr3_pad > 0
pad_pwr3_net_ptap = NET AREA RATIO ptap pwr3_pad > 0
pwr3_net_to_pad1 = OR pad_pwr3_net_m5 pad_pwr3_net_m4 pad_pwr3_net_m3 pad_pwr3_net_m2 pad_pwr3_net_m1
pwr3_net_to_pad2 = OR pwr3_net_to_pad1 pad_pwr3_net_nsd pad_pwr3_net_psd pad_pwr3_net_poly
pwr3_net_to_pad = OR pwr3_net_to_pad2 pad_pwr3_net_ntap pad_pwr3_net_ptap pad_pwr3_net_nw pad_pwr3_net_pw
sig2_pad = pad INTERACT pad_io
pad_sig2_net_m5 = NET AREA RATIO met5 sig2_pad > 0
pad_sig2_net_m4 = NET AREA RATIO met4 sig2_pad > 0
pad_sig2_net_m3 = NET AREA RATIO met3 sig2_pad > 0
pad_sig2_net_m2 = NET AREA RATIO met2 sig2_pad > 0
pad_sig2_net_m1 = NET AREA RATIO met1 sig2_pad > 0
pad_sig2_net_li = NET AREA RATIO li sig2_pad > 0
pad_sig2_net_nsd = NET AREA RATIO nsd sig2_pad > 0
pad_sig2_net_ntap = NET AREA RATIO ntap sig2_pad > 0
pad_sig2_net_psd = NET AREA RATIO psd sig2_pad > 0
pad_sig2_net_ptap = NET AREA RATIO ptap sig2_pad > 0
pad_sig2_net_poly = NET AREA RATIO poly sig2_pad > 0
pad_sig2_net_nw = NET AREA RATIO nwell sig2_pad > 0
pad_sig2_net_dnw = NET AREA RATIO dnwell sig2_pad > 0
pad_sig2_net_pw = NET AREA RATIO pwell sig2_pad > 0
pad_sig2_net_ls = NET AREA RATIO localSub sig2_pad > 0
pad_sig2_net_pt = NET AREA RATIO ptub sig2_pad > 0
pad_sig2_diff_all = OR pad_sig2_net_nsd pad_sig2_net_ntap pad_sig2_net_psd pad_sig2_net_ptap
latchup.signal.3.1b {
    @ latchup.signal.3.1b: signal connected ptap or P+ src/drn must have P+ tap guard ring connected to a ground pad
    ((ptap INTERACT (ptap_grd_ring INTERACT pad_sig_net_ptap)) NOT pad_gnd3_net_ptap) NOT pad_sig_net_ptap
    exempt1 = (pad_sig_net_psd INTERACT > 0 pad_sig2_net_nw BY NET) OR (pad_sig_net_psd INSIDE (nwell NOT pad_pwr3_net_nw))
    (pad_sig_net_psd NOT ptap_grd_ring) NOT exempt1
}
latchup.signal.12a {
    @ latchup.signal.12a: Minimum spacing between diff metallically connected to signal pad and grounded ndiff < 27.0
    exempt1 = pad_sig_net_psd INTERACT > 0 pad_sig2_net_nw BY NET
    EXT (pad_sig2_net_psd NOT exempt1) pad_gnd3_net_nsd < 27.0 ABUT<90 REGION
}
latchup.signal.12b {
    @ latchup.signal.12b: Minimum spacing between pwell metallically connected to signal pad and grounded ndiff < 40.0
    EXT pad_sig2_net_pw pad_gnd3_net_nsd < 40.0 ABUT<90 REGION
    EXT pad_sig2_net_ls pad_gnd3_net_nsd < 40.0 ABUT<90 REGION
    EXT pad_sig2_net_pt pad_gnd3_net_nsd < 40.0 ABUT<90 REGION
}
latchup.signal.12c {
    @ latchup.signal.12c: Minimum spacing between pdiff metallically connected to signal pad and grounded nwell < 40.0
    exempt1 = pad_sig_net_psd INTERACT > 0 pad_sig2_net_nw BY NET
    EXT (pad_sig2_net_psd NOT exempt1) pad_gnd3_net_nw < 40.0 ABUT<90 REGION
}
latchup.signal.12d {
    @ latchup.signal.12d: Minimum spacing between pwell metallically connected to signal pad and grounded nwell < 40.0
    EXT pad_sig2_net_pw pad_gnd3_net_nw < 40.0 ABUT<90 REGION
    EXT pad_sig2_net_ls pad_gnd3_net_nw < 40.0 ABUT<90 REGION
    EXT pad_sig2_net_pt pad_gnd3_net_nw < 40.0 ABUT<90 REGION
}
latchup.signal.12e {
    @ latchup.signal.12e: Minimum spacing between ndiff metallically connected to signal pad and positive power supply connected pdiff < 27.0
    exempt1 = pad_sig_net_nsd INTERACT > 0 pad_sig2_net_pw BY NET
    exempt2 = pad_sig_net_nsd INSIDE ptub
    exempt = OR exempt1 exempt2
    EXT (pad_sig2_net_nsd NOT exempt) pad_pwr3_net_psd < 27.0 ABUT<90 REGION
}
latchup.signal.12f {
    @ latchup.signal.12f: Minimum spacing between nwell metallically connected to signal pad and positive power supply connected pdiff < 40.0
    EXT pad_sig2_net_nw pad_pwr3_net_psd < 40.0 ABUT<90 REGION
}
latchup.signal.12g {
    @ latchup.signal.12g: Minimum spacing between non-isolated ndiff metallically connected to signal pad and positive power supply connected pwell < 40.0
    exempt1 = pad_sig_net_nsd INTERACT > 0 pad_sig2_net_pw BY NET
    nsd_in_ptub = nsd AND ptub
    EXT ((pad_sig2_net_nsd NOT nsd_in_ptub) NOT exempt1) pad_pwr3_net_pw < 40.0 ABUT<90 REGION
    EXT ((pad_sig2_net_nsd NOT nsd_in_ptub) NOT exempt1) pad_pwr3_net_ls < 40.0 ABUT<90 REGION
    EXT ((pad_sig2_net_nsd NOT nsd_in_ptub) NOT exempt1) pad_pwr3_net_pt < 40.0 ABUT<90 REGION
}
latchup.signal.12h {
    @ latchup.signal.12h: Minimum spacing between nwell metallically connected to signal pad and positive power supply connected pwell < 40.0
    EXT pad_sig2_net_nw pad_pwr3_net_pw < 40.0 ABUT<90 REGION
    EXT pad_sig2_net_nw pad_pwr3_net_ls < 40.0 ABUT<90 REGION
    EXT pad_sig2_net_nw pad_pwr3_net_pt < 40.0 ABUT<90 REGION
}
latchup.signal.12i {
    @ latchup.signal.12i: Minimum spacing between pdiff metallically connected to signal pad and ndiff metallically connected to a different signal pad < 27.0
    EXT pad_sig2_net_psd pad_sig2_net_nsd < 27.0 ABUT<90 REGION NOT CONNECTED
}
latchup.signal.12j {
    @ latchup.signal.12j: Minimum spacing between pdiff metallically connected to signal pad and nwell metallically connected to a different signal pad < 40.0
    exempt1 = pad_sig_net_psd INTERACT > 0 pad_sig2_net_nw BY NET
    EXT (pad_sig2_net_psd NOT exempt1) pad_sig2_net_nw < 40.0 ABUT<90 REGION NOT CONNECTED
}
latchup.signal.12k {
    @ latchup.signal.12k: Minimum spacing between pwell metallically connected to signal pad and ndiff metallically connected to a different signal pad < 40.0
    EXT pad_sig2_net_pw pad_sig2_net_nsd < 40.0 ABUT<90 REGION NOT CONNECTED
    EXT pad_sig2_net_ls pad_sig2_net_nsd < 40.0 ABUT<90 REGION NOT CONNECTED
    EXT pad_sig2_net_pt pad_sig2_net_nsd < 40.0 ABUT<90 REGION NOT CONNECTED
}
latchup.signal.12l {
    @ latchup.signal.12l: Minimum spacing between pwell metallically connected to signal pad and nwell metallically connected to a different signal pad < 40.0
    EXT pad_sig2_net_pw pad_sig2_net_nw < 40.0 ABUT<90 REGION NOT CONNECTED
    EXT pad_sig2_net_ls pad_sig2_net_nw < 40.0 ABUT<90 REGION NOT CONNECTED
    EXT pad_sig2_net_pt pad_sig2_net_nw < 40.0 ABUT<90 REGION NOT CONNECTED
}
hv_psd = pad_pwr3_net_psd AND (OR v5 v12 v20)
at_risk_non_vcc_nw = (nwell AND (NET AREA RATIO == 0 nwell pad_pwr3_net_psd)) ENCLOSE hv_psd
at_risk_non_vcc_nw_and_psd = at_risk_non_vcc_nw AND hv_psd
exempt3 = pad_sig2_net_pw ENCLOSE pad_sig2_net_nsd
exempt4 = pad_pwr3_net_nw ENCLOSE pad_pwr3_net_psd
latchup.signal.12m {
    @ latchup.signal.12m: Minimum spacing between ndiff metallically connected to signal pad and pdiff in an At RISK Non_Vcc_nwell < 33.0
    EXT (pad_sig2_net_nsd NOT exempt3) (at_risk_non_vcc_nw_and_psd NOT exempt4) < 33.0 ABUT<90 REGION
}
latchup.signal.12n {
    @ latchup.signal.12n: Minimum spacing between ndiff metallically connected to signal pad and At RISK Non_Vcc_nwell < 16.75
    EXT (pad_sig2_net_nsd NOT exempt3) (at_risk_non_vcc_nw NOT exempt4) < 16.75 ABUT<90 REGION
}
latchup.signal.12o {
    @ latchup.signal.12o: Minimum spacing between pdiff metallically connected to signal pad and nwell connected to 1.8V (LV) or lower < 27.0
    EXT pad_sig2_net_psd (nwell NOT (OR v5 v12 v20)) < 27.0 ABUT<90 REGION MEASURE ALL
}
latchup.signal.12p {
    @ latchup.signal.12p: Minimum spacing between pwell metallically connected to signal pad and nwell connected to 1.8V (LV) or lower < 40.0
    EXT pad_sig2_net_pw (nwell NOT (OR v5 v12 v20)) < 40.0 ABUT<90 REGION MEASURE ALL
    EXT pad_sig2_net_ls (nwell NOT (OR v5 v12 v20)) < 40.0 ABUT<90 REGION MEASURE ALL
    EXT pad_sig2_net_pt (nwell NOT (OR v5 v12 v20)) < 40.0 ABUT<90 REGION MEASURE ALL
}
holes_ptap_ring = HOLES ptap
holes_ntap_ring = (HOLES ntap) INTERACT (HOLES nwell)
ptap_ring = ptap TOUCH holes_ptap_ring
ntap_ring = (nwell INTERACT holes_ntap_ring) AND ntap
ptap_is_outer = ptap TOUCH ((HOLES ptap) ENCLOSE ntap_ring)
ntap_is_outer = ntap INTERACT ((HOLES ntap) ENCLOSE ptap_ring)
outer_ring = OR ptap_is_outer ntap_is_outer
ptap_is_inner = ptap INTERACT (ptap_ring INSIDE (HOLES ntap_ring))
ntap_is_inner = ntap INTERACT (ntap_ring INSIDE (HOLES ptap_ring))
inner_ring = OR ptap_is_inner ntap_is_inner
pmos_dev = ((diff AND poly) AND psdm) AND nwell
btw_rings = (HOLES outer_ring) NOT (inner_ring OR (HOLES inner_ring))
hole_is_outer_around_nsd_sig = (HOLES ntap_is_outer) INTERACT pad_sig2_net_nsd
nw_is_outer_around_nsd_sig = (DONUT nwell) INTERACT hole_is_outer_around_nsd_sig
btw_rings_sig_1 = (HOLES nw_is_outer_around_nsd_sig) ENCLOSE ptap_is_inner
btw_rings_sig_2 = btw_rings_sig_1 NOT ptap_is_inner
btw_rings_sig = btw_rings_sig_2 NOT (HOLES ptap_is_inner)
latchup.signal.13 {
    @ latchup.signal.13: P+ MOS device is not permitted between the inner p+ ring and outer n+/nwell ring or in the shared well of the outer N+/nwell ring
    part_1 = (pmos_dev AND btw_rings) INTERACT (HOLES nw_is_outer_around_nsd_sig)
    part_2 = (nw_is_outer_around_nsd_sig INTERACT outer_ring) AND pmos_dev
    MERGE (OR part_1 part_2)
}
diff_res = diffi AND diffres
latchup.signal.14 {
    @ latchup.signal.14: diff:res is not allowed inside diff connected to a signal pad or in the shared well of the outer n+/nwell ring
    part_1 = (diff_res AND btw_rings) INTERACT (HOLES nw_is_outer_around_nsd_sig)
    part_2 = (nw_is_outer_around_nsd_sig INTERACT outer_ring) AND diff_res
    MERGE (OR part_1 part_2)
}
danger_zone = SIZE pad_sig2_diff_all BY 100 BEVEL 3
mos_gate_in_dz = gate AND danger_zone
mos_sd_in_dz = (nsd OR psd) TOUCH mos_gate_in_dz
ptap_in_at_risk_nw = ptap INSIDE at_risk_non_vcc_nw
ntap_in_at_risk_nw = ntap INSIDE at_risk_non_vcc_nw
at_risk_nw_inner_ring = ptap TOUCH ((HOLES ptap) ENCLOSE at_risk_non_vcc_nw)
at_risk_nw_outer_ring = ntap TOUCH ((HOLES ntap) ENCLOSE at_risk_non_vcc_nw)
latchup.special.1a.1 {
    @ latchup.special.1a.1: At risk non-Vcc nwell must be in an inner P+ tap connected to ground
    at_risk_non_vcc_nw NOT INSIDE (at_risk_nw_inner_ring INTERACT pad_gnd_net_ptap)
}
li_in_at_risk_nw_ptap_ring = li_i ENCLOSE ((licon AND li_i) AND at_risk_nw_inner_ring)
latchup.special.1a.2 {
    @ latchup.special.1a.2: P+ tap around at risk Vcc nwell must be continuously strapped in local interconnect
    at_risk_non_vcc_nw NOT INSIDE (HOLES li_in_at_risk_nw_ptap_ring)
}
latchup.special.1b.1 {
    @ latchup.special.1b.1: At risk non-Vcc nwell must be in an outer N+/NW guard ring connected to power
    nw_outer_inter_gnd_net = at_risk_nw_outer_ring INTERACT pad_pwr_net_ntap
    nw_inner_inter_pad_net = at_risk_nw_inner_ring INTERACT pad_gnd_net_ptap
    holes_outer_gr_gnd = HOLES nw_outer_inter_gnd_net
    outer_gr_enc_inner_gr = holes_outer_gr_gnd ENCLOSE nw_inner_inter_pad_net
    at_risk_non_vcc_nw NOT INSIDE outer_gr_enc_inner_gr
}
latchup.special.1c.1 {
    @ latchup.special.1c.1: Maximum space between licons in inner P+ tap around at risk non-Vcc nwell > 2.0
    lic_size_atr_nw = SIZE (licon AND at_risk_nw_inner_ring) BY 1 INSIDE OF li_i 
    (li_i AND at_risk_nw_inner_ring) NOT lic_size_atr_nw
}
latchup.special.1c.2 {
    @ latchup.special.1c.2: Maximum space between licons in outer N+ tap around at risk non-Vcc nwell > 2.0
    lic_size_atr_nw = SIZE (licon AND at_risk_nw_outer_ring) BY 1 INSIDE OF li_i 
    (li_i AND at_risk_nw_outer_ring) NOT lic_size_atr_nw
}
li_in_at_risk_nw_ntap_ring = li_i ENCLOSE ((licon AND li_i) AND at_risk_nw_outer_ring)
latchup.special.1b.2 {
    @ latchup.special.1b.2: N+ tap around at risk non-Vcc nwell must be continuously strapped in local interconnect
    at_risk_non_vcc_nw NOT INSIDE (HOLES li_in_at_risk_nw_ptap_ring)
}
latchup.special.2a {
    @ latchup.special.2a: PNP bipolar transistor must be inside inner P+ guardring tied to ground
    pnp NOT INSIDE (HOLES (ptap_is_inner INTERACT pad_gnd_net_ptap))
}
latchup.special.2b {
    @ latchup.special.2b: PNP bipolar transistor must be inside outer NW/N+ tap guardring tied to power
    pnp NOT INSIDE (HOLES (ntap_is_outer INTERACT pad_pwr_net_ntap))
}
pnp_inner_ring = ptap TOUCH ((HOLES ptap_is_inner) ENCLOSE pnp)
lic_size_inner_pnp = SIZE (licon AND pnp_inner_ring) BY 1 INSIDE OF li_i 
pnp_outer_ring = ntap TOUCH ((HOLES ntap_is_outer) ENCLOSE pnp)
lic_size_outer_pnp = SIZE (licon AND pnp_outer_ring) BY 1 INSIDE OF li_i 
latchup.special.2c {
    @ latchup.special.2c: Maximum space between licons in inner P+ tap around pnp > 2.0
    (li_i AND pnp_inner_ring) NOT lic_size_inner_pnp
}
latchup.special.2d {
    @ latchup.special.2d: Maximum space between licons in outer N+ tap around pnp > 2.0
    (li_i AND pnp_outer_ring) NOT lic_size_outer_pnp
}
latchup.special.6 {
    @ latchup.special.6: There should not be any N+ diffusion between the P+ diffusion in the At Risk Non-Vcc nwell and the P+ tap ring
    at_risk_non_vcc_nw ENCLOSE (nsd NOT ntap)
}
latchup.special.7a {
    @ latchup.special.7a: Grounded nwell must be inside a P+ tap ring
    pad_gnd3_net_nw NOT INSIDE (HOLES ptap_ring)
}
latchup.special.7b {
    @ latchup.special.7b: Grounded nwell's P+ tap ring must be connected to gnd
    ((HOLES ptap_ring) ENCLOSE pad_gnd3_net_nw) NOT INTERACT pad_gnd3_net_ptap
}
pad_net_m5 = NET AREA RATIO met5 pad > 0
pad_net_m4 = NET AREA RATIO met4 pad > 0
pad_net_m3 = NET AREA RATIO met3 pad > 0
pad_net_m2 = NET AREA RATIO met2 pad > 0
pad_net_m1 = NET AREA RATIO met1 pad > 0
pad_net_li = NET AREA RATIO li  pad > 0
pad_net_nsd = NET AREA RATIO nsd pad > 0
pad_net_psd = NET AREA RATIO psd pad > 0
target_ngate = (gate NOT ESDID) TOUCH pad_net_nsd
target_ngate_2_pad = (gate NOT ESDID) INTERACT pad_net_nsd > 1 BY NET
target_pgate = (gate NOT ESDID) TOUCH pad_net_psd
target_pgate_2_pad = (gate NOT ESDID) INTERACT pad_net_psd > 1 BY NET
latchup.misc.4 {
    @ latchup.misc.4: Non-ESD nfet or pfet with src connected to one pad and drn connected to different pad min width < 2000.0
    mark1 = LENGTH (target_ngate_2_pad NOT COINCIDENT EDGE nsd) < 2000
    mark2 = LENGTH (target_pgate_2_pad NOT COINCIDENT EDGE psd) < 2000
    mark1_exp = EXPAND EDGE mark1 OUTSIDE BY 0.005
    mark2_exp = EXPAND EDGE mark2 OUTSIDE BY 0.005
    (gate NOT ESDID) INTERACT (OR mark1_exp mark2_exp)
}
pw_lu_x = pwell NOT pw_res_gt_1kohm
diff_lu_x = diffi NOT diff_res_gt_1kohm
nsd_lu_x = (((diffi AND nsdm) NOT poly) NOT nwell) NOT diff_res_gt_1kohm
psd_lu_x = (((diffi AND psdm) NOT poly) AND nwell) NOT diff_res_gt_1kohm
poly_lu_x = polyi NOT poly_res_gt_1kohm
li_lu_x = li_i NOT li_res_gt_1kohm
m1_lu_x = met1i NOT m1_res_gt_1kohm
m2_lu_x = met2i NOT m2_res_gt_1kohm
m3_lu_x = met3i NOT m3_res_gt_1kohm
m4_lu_x = met4i NOT m4_res_gt_1kohm
m5_lu_x = met5i NOT m5_res_gt_1kohm

DISCONNECT
CONNECT m5_lu_x m4_lu_x   BY via4_c
CONNECT m4_lu_x m3_lu_x   BY via3_c
CONNECT m3_lu_x m2_lu_x   BY via2
CONNECT m2_lu_x m1_lu_x   BY via1
CONNECT m1_lu_x li_lu_x   BY mcon
CONNECT li_lu_x nsd_lu_x  BY licon
CONNECT li_lu_x psd_lu_x  BY licon
CONNECT li_lu_x ntap  BY licon
CONNECT li_lu_x ptap  BY licon
CONNECT li_lu_x ptubtap BY licon
CONNECT li_lu_x poly_lu_x BY licon

CONNECT ntap nwell
CONNECT ptap pw_lu
CONNECT ptubtap ptub
CONNECT nwell dnwell

CONNECT m5_lu_x pad
CONNECT m5_lu_x uprobe_pad
CONNECT m5_lu_x probe_pad
CONNECT rdl pad
CONNECT rdl uprobe_pad
CONNECT rdl probe_pad


gnd_pad2_x = pad INTERACT pad_gnd
shv_gate = (gate AND (v12 OR v20)) AND thkox
dnw_with_shv_gate = dnwell ENCLOSE shv_gate
latchup.shv.1 {
    @ latchup.shv.1: DNW connected to ground < 1000 ohm is not allowed if the DNW contains super high voltage connected active NFETs or PFETs
    NET AREA RATIO dnw_with_shv_gate gnd_pad2_x > 0
}
pwr2_pad_y = pad INTERACT pad_pwr
pad_pwr2_net_m5_y = NET AREA RATIO m5_lu_x pwr2_pad_y > 0
pad_pwr2_net_m4_y = NET AREA RATIO m4_lu_x pwr2_pad_y > 0
pad_pwr2_net_m3_y = NET AREA RATIO m3_lu_x pwr2_pad_y > 0
pad_pwr2_net_m2_y = NET AREA RATIO m2_lu_x pwr2_pad_y > 0
pad_pwr2_net_m1_y = NET AREA RATIO m1_lu_x pwr2_pad_y > 0
pad_pwr2_net_li_y = NET AREA RATIO li_lu_x pwr2_pad_y > 0
pad_pwr2_net_nsd_y = NET AREA RATIO nsd_lu_x pwr2_pad_y > 0
pad_pwr2_net_ntap_y = NET AREA RATIO ntap pwr2_pad_y > 0
pad_pwr2_net_psd_y = NET AREA RATIO psd_lu_x pwr2_pad_y > 0
pad_pwr2_net_ptap_y = NET AREA RATIO ptap pwr2_pad_y > 0
pad_pwr2_net_poly_y = NET AREA RATIO poly_lu_x pwr2_pad_y > 0
pad_pwr2_net_pw_y = NET AREA RATIO pw_lu pwr2_pad_y > 0
latchup.shv.2 {
    @ latchup.shv.2: Minimum distance between NW/DNW connected metallically to SHV signal pad to a P+ diff connected to a positive power supply < 70 um
    pad_dnw_sig_v20 = pad_sig2_net_dnw AND (OR v12 v20)
    pad_nw_sig_v20 = pad_sig2_net_nw AND (OR v12 v20)
    EXT pad_dnw_sig_v20 pad_pwr2_net_psd_y < 70.0 ABUT<90 REGION
    EXT pad_nw_sig_v20 pad_pwr2_net_psd_y < 70.0 ABUT<90 REGION
    EXT pad_dnw_sig_v20 pad_pwr2_net_ptap_y < 70.0 ABUT<90 REGION
    EXT pad_nw_sig_v20 pad_pwr2_net_ptap_y < 70.0 ABUT<90 REGION
    EXT pad_dnw_sig_v20 pad_pwr2_net_pw_y < 70.0 ABUT<90 REGION MEASURE ALL
    EXT pad_nw_sig_v20 pad_pwr2_net_pw_y < 70.0 ABUT<90 REGION MEASURE ALL
}
latchup.shv.3 {
    @ latchup.shv.3: Minimum distance between PW connected metallically to SHV signal pad to any N+ diff/tap/NW/DNW connected to a ground < 100
    pad_pw_sig_v20a = pad_sig2_net_pw AND (OR v12 v20)
    pad_pw_sig_v20b = pad_sig2_net_ls AND (OR v12 v20)
    pad_pw_sig_v20c = pad_sig2_net_pt AND (OR v12 v20)
    pad_pw_sig_v20 = OR pad_pw_sig_v20a pad_pw_sig_v20b pad_pw_sig_v20c
    EXT pad_pw_sig_v20 pad_gnd2_net_ntap < 100 ABUT<90 REGION
    EXT pad_pw_sig_v20 pad_gnd2_net_nsd < 100 ABUT<90 REGION
    EXT pad_pw_sig_v20 pad_gnd2_net_nw < 100 ABUT<90 REGION
    EXT pad_pw_sig_v20 pad_gnd2_net_dnw < 100 ABUT<90 REGION
}

#ENDIF  //not skip latchup checks


//
// LONELY VIA/CONTACT rules
//

#IFNDEF SKIP_RECOMMENDED_CHECKS

//LICON (on poly):
// licon size     0.17
// licon space    0.17
// li enc licon   0.08
// poly enc licon 0.05


lipl = (li_i AND polyi) NOT diffi
lic_size_pl = SIZE licon BY .42 INSIDE of lipl
lic_space_size_pl = SIZE licon BY .17 INSIDE of lipl
lipl_no_lic = ((lipl ENCLOSE lic_size_pl) NOT lic_space_size_pl) NOT INTERACT licon
potential_area_for_lic_pl = WITH WIDTH lipl_no_lic > 0.29
pl_excl_area = polyii INSIDE CELL "esd*"
li_excl_area = li_ii INSIDE CELL "esd*"
lic_excl_area_pl = pl_excl_area OR li_excl_area
poly_gate_stub = (((RECTANGLE (polyii NOT gate)) TOUCH gate == 1) ENCLOSE licon == 1) NOT INTERACT met1
lonely.poly.licon.R {
    @ lonely.poly.licon.R: There may be room for additional licon(s) in this poly/li area
    (((lipl INTERACT potential_area_for_lic_pl) NOT lic_excl_area_pl) NOT INTERACT poly_gate_stub) ENCLOSE < 2 licon
}
potential_area_for_more_poly = (((polyi NOT gate) ENCLOSE licon == 1) AND li) NOT STDCID
potential_area_for_more_poly_size = SIZE potential_area_for_more_poly BY 0.51
potential_area_for_more_poly_size_halo = SIZE potential_area_for_more_poly_size BY 1
potential_area_for_more_poly_size_block1 = (potential_area_for_more_poly_size_halo AND (OR polyi diff1 licon)) NOT potential_area_for_more_poly
potential_area_for_more_poly_size_block = SIZE (poly AND potential_area_for_more_poly_size_block1) BY 0.34
potential_area_for_pl_lic_1 = potential_area_for_more_poly_size_block ENCLOSE (polyi AND potential_area_for_more_poly_size_block) < 2
potential_area_for_pl_lic_2 = potential_area_for_more_poly_size_block ENCLOSE (li AND potential_area_for_more_poly_size_block) < 2
potential_area_for_pl_lic_3 = potential_area_for_more_poly_size_block ENCLOSE (diffi AND potential_area_for_more_poly_size_block) < 1
potential_area_for_pl_lic_a = (potential_area_for_pl_lic_1 AND potential_area_for_pl_lic_2) NOT potential_area_for_pl_lic_3
sq_licon = RECTANGLE licon == 0.17 BY == 0.17
non_sq_licon = licon NOT sq_licon
potential_area_for_pl_lic = potential_area_for_pl_lic_a NOT INTERACT non_sq_licon
gate_extension_lt_pt_5 = (polyi NOT gate) INTERACT (INT (SIZE gate by 1 INSIDE OF polyi) < 0.505 ABUT<90 REGION)
potential_area_for_pl_lonely_yes = (((potential_area_for_pl_lic INTERACT potential_area_for_more_poly) OR potential_area_for_more_poly) ENCLOSE sq_licon == 1) NOT interact gate_extension_lt_pt_5
lonely.poly.licon.a.R {
    @ lonely.poly.licon.a.R: By adding additional poly and/or li, there may be room for additional licons
    COPY (MERGE ((((polyi AND li) NOT gate) AND potential_area_for_pl_lonely_yes) NOT poly_gate_stub))
}

//LICON (on diff):
// licon size     0.17
// licon space    0.17
// li enc licon   0.08
// diff enc licon 0.12

lidf = (li_i AND diffi) NOT polyi
lic_size_df = SIZE licon BY .54 INSIDE of lidf
lic_space_size_df = SIZE licon BY .17 INSIDE of lidf
lidf_no_lic = ((lidf ENCLOSE lic_size_df) NOT lic_space_size_df) NOT INTERACT licon
potential_area_for_lic_df = WITH WIDTH lidf_no_lic > 0.29
df_excl_area = diffii INSIDE CELL "esd*"
lic_excl_area_df = df_excl_area OR li_excl_area
lonely.diff.licon.R {
    @ lonely.diff.licon.R: There may be room for additional licon(s) in this diff/li area
    ((lidf INTERACT potential_area_for_lic_df) NOT lic_excl_area_df) ENCLOSE < 2 licon
}
potential_area_for_more_diff = (((diffi NOT gate) ENCLOSE licon == 1) AND li) NOT STDCID
potential_area_for_more_diff_size = SIZE potential_area_for_more_diff BY 0.51
potential_area_for_more_diff_size_halo = SIZE potential_area_for_more_diff_size BY 1
potential_area_for_more_diff_size_block1 = (potential_area_for_more_diff_size_halo AND (OR polyi diff1 licon)) NOT potential_area_for_more_diff
potential_area_for_more_diff_size_block = SIZE (diffi AND potential_area_for_more_diff_size_block1) BY 0.34
potential_area_for_df_lic_1 = potential_area_for_more_diff_size_block ENCLOSE (diffi AND potential_area_for_more_diff_size_block) < 2
potential_area_for_df_lic_2 = potential_area_for_more_diff_size_block ENCLOSE (li AND potential_area_for_more_diff_size_block) < 2
potential_area_for_df_lic_3 = potential_area_for_more_diff_size_block ENCLOSE ((SIZE licon BY 0.17) AND potential_area_for_more_diff_size_block) < 1
potential_area_for_df_lic_a = (potential_area_for_df_lic_1 AND potential_area_for_df_lic_2) NOT potential_area_for_df_lic_3
potential_area_for_df_lic = potential_area_for_df_lic_a NOT INTERACT non_sq_licon
potential_area_for_df_lonely_yes = (((potential_area_for_df_lic INTERACT potential_area_for_more_diff) OR potential_area_for_more_diff) ENCLOSE sq_licon == 1) NOT interact gate_extension_lt_pt_5
lonely.diff.licon.a.R {
    @ lonely.diff.licon.a.R: By adding additional diff and/or li, there may be room for additional licons
    COPY (MERGE (((diffi AND li) NOT gate) AND potential_area_for_df_lonely_yes))
}

// MCON:
// mcon size      0.17
// mcon space     0.19
// m1 enc mcon    0.03
// li enc mcon   0.0


m1l1 = met1i AND li_i
mcon_size = SIZE mcon BY .39 INSIDE OF m1l1
mcon_space_size = SIZE mcon BY .19 INSIDE OF m1l1
m1l1_no_mcon = ((m1l1 ENCLOSE mcon_size) NOT mcon_space_size) NOT INTERACT mcon
potential_area_for_mcon = WITH WIDTH m1l1_no_mcon >= 0.25
mcon_m1_excl_area = met1ii INSIDE CELL "esd*"
mcon_l1_excl_area = li_ii INSIDE CELL "esd*"
mcon_excl_area = mcon_m1_excl_area OR mcon_l1_excl_area
lonely.mcon.R {
    @ lonely.mcon.R: There may be room for additional metal contact(s)
    ((m1l1 INTERACT potential_area_for_mcon) NOT mcon_excl_area) ENCLOSE < 2 mcon
}
potential_area_for_more_mcon = ((met1i  AND li_i) ENCLOSE mcon == 1) NOT STDCID
potential_area_for_more_mcon_size = SIZE potential_area_for_more_mcon BY 0.53
potential_area_for_more_mcon_size_halo = SIZE potential_area_for_more_mcon_size BY 1
potential_area_for_more_mcon_size_block1 = (potential_area_for_more_mcon_size_halo AND (OR met1i li_i mcon)) NOT potential_area_for_more_mcon
potential_area_for_more_mcon_size_block = SIZE (met1i AND potential_area_for_more_mcon_size_block1) BY 0.28
potential_area_for_m1_lic_1 = potential_area_for_more_mcon_size_block ENCLOSE (met1i AND potential_area_for_more_mcon_size_block) < 2
potential_area_for_m1_lic_2 = potential_area_for_more_mcon_size_block ENCLOSE (li_i AND potential_area_for_more_mcon_size_block) < 2
potential_area_for_m1_lic_3 = potential_area_for_more_mcon_size_block ENCLOSE ((SIZE mcon BY 0.19) AND potential_area_for_more_mcon_size_block) < 1
potential_area_for_m1_lic = (potential_area_for_m1_lic_1 AND potential_area_for_m1_lic_2) NOT potential_area_for_m1_lic_3
potential_area_for_m1_lonely_yes = (potential_area_for_m1_lic INTERACT potential_area_for_more_mcon) OR potential_area_for_more_mcon
lonely.mcon.a.R {
    @ lonely.mcon.a.R: By adding additional met1 and/or li, there may be room for additional mcons
    COPY (MERGE ((met1i AND li) AND potential_area_for_m1_lonely_yes))
}

// VIA:
// via size     0.15
// m1 enc via   0.085 (adj sides)
// via space    0.17
// m2 enc via   0.085 (adj sides)

m1m2 = met1i AND met2i
via_size = SIZE via1 BY .405 INSIDE OF m1m2
via_space_size = SIZE via1 BY .17 INSIDE OF m1m2
m1m2_no_via = ((m1m2 ENCLOSE via_size) NOT via_space_size) NOT INTERACT via1
potential_area_for_via = WITH WIDTH m1m2_no_via >= 0.235
via_m1_excl_area = met1ii INSIDE CELL "esd*"
via_m2_excl_area = met2ii INSIDE CELL "esd*"
via_excl_area = via_m1_excl_area OR via_m2_excl_area
lonely.via1.R {
    @ lonely.via1.R: There may be room for additional via1(s)
    ((m1m2 INTERACT potential_area_for_via) NOT via_excl_area) ENCLOSE < 2 via1
}
potential_area_for_more_via = ((met1i  AND met2i) ENCLOSE via1 == 1) NOT STDCID
potential_area_for_more_via_size = SIZE potential_area_for_more_via BY 0.49
potential_area_for_more_via_size_halo = SIZE potential_area_for_more_via_size BY 1
potential_area_for_more_via_size_block1 = (potential_area_for_more_via_size_halo AND (OR met1i via1 met2i)) NOT potential_area_for_more_via
potential_area_for_more_via_size_block = SIZE (met1i AND potential_area_for_more_via_size_block1) BY 0.28
potential_area_for_v1_lic_1 = potential_area_for_more_via_size_block ENCLOSE (met1i AND potential_area_for_more_via_size_block) < 2
potential_area_for_v1_lic_2 = potential_area_for_more_via_size_block ENCLOSE (met2i AND potential_area_for_more_via_size_block) < 2
potential_area_for_v1_lic_3 = potential_area_for_more_via_size_block ENCLOSE ((SIZE via1 BY 0.17) AND potential_area_for_more_via_size_block) < 1
potential_area_for_v1_lic = (potential_area_for_v1_lic_1 AND potential_area_for_v1_lic_2) NOT potential_area_for_v1_lic_3
potential_area_for_v1_lonely_yes = (potential_area_for_v1_lic INTERACT potential_area_for_more_via) OR potential_area_for_more_via
lonely.via1.a.R {
    @ lonely.via1.a.R: By adding additional met1 and/or met2, there may be room for additional via1s
    COPY (MERGE ((met1i AND met2i) AND potential_area_for_v1_lonely_yes))
}

// VIA2:
// via2 size     0.2
// m2 enc via2   0.065 (adj sides)
// via2 space    0.20
// m3 enc via2   0.065 (adj sides)

m2m3 = met2i AND met3i
via2_size = SIZE via2 BY .465 INSIDE OF m2m3
via2_space_size = SIZE via2 BY .2 INSIDE OF m2m3
m2m3_no_via2 = ((m2m3 ENCLOSE via2_size) NOT via2_space_size) NOT INTERACT via2
potential_area_for_via2 = WITH WIDTH m2m3_no_via2 >= 0.265
via2_m2_excl_area = met2ii INSIDE CELL "esd*"
via2_m3_excl_area = met3ii INSIDE CELL "esd*"
via2_excl_area = via2_m2_excl_area OR via2_m3_excl_area
lonely.via2.R {
    @ lonely.via2.R: There may be room for additional via2(s)
    ((m2m3 INTERACT potential_area_for_via2) NOT via2_excl_area) ENCLOSE < 2 via2
}
small_v2 = RECTANGLE via2 == 0.2 BY == 0.2
potential_area_for_more_via2 = ((met2i AND met3i) ENCLOSE small_v2 == 1) NOT STDCID
potential_area_for_more_via2_size = SIZE potential_area_for_more_via2 BY 0.54
potential_area_for_more_via2_size_halo = SIZE potential_area_for_more_via2_size BY 1
potential_area_for_more_via2_size_block1 = (potential_area_for_more_via2_size_halo AND (OR met2i via1 met3i)) NOT potential_area_for_more_via2
potential_area_for_more_via2_size_block = SIZE (met2i AND potential_area_for_more_via2_size_block1) BY 0.28
potential_area_for_v2_lic_1 = potential_area_for_more_via2_size_block ENCLOSE (met2i AND potential_area_for_more_via2_size_block) < 2
potential_area_for_v2_lic_2 = potential_area_for_more_via2_size_block ENCLOSE (met3i AND potential_area_for_more_via2_size_block) < 2
potential_area_for_v2_lic_3 = potential_area_for_more_via2_size_block ENCLOSE ((SIZE via2 BY 0.17) AND potential_area_for_more_via2_size_block) < 1
potential_area_for_v2_lic = (potential_area_for_v2_lic_1 AND potential_area_for_v2_lic_2) NOT potential_area_for_v2_lic_3
potential_area_for_v2_lonely_yes = (potential_area_for_v2_lic INTERACT potential_area_for_more_via2) OR potential_area_for_more_via2
lonely.via2.a.R {
    @ lonely.via2.a.R: By adding additional met2 and/or met3, there may be room for additional via2s
    COPY (MERGE ((met2i AND met3i) AND potential_area_for_v2_lonely_yes))
}

// VIA3:
// via3 size     0.2
// m3 enc via3   0.09  (adj sides)
// via3 space    0.20
// m4 enc via3   0.065 (adj sides)

m3m4 = met3i AND met4i
via3_size = SIZE via3 BY .49 INSIDE OF m3m4
via3_space_size = SIZE via3 BY .2 INSIDE OF m3m4
m3m4_no_via3 = ((m3m4 ENCLOSE via3_size) NOT via3_space_size) NOT INTERACT via3
potential_area_for_via3 = WITH WIDTH m3m4_no_via3 >= 0.29
via3_m3_excl_area = met3ii INSIDE CELL "esd*"
via3_m4_excl_area = met4ii INSIDE CELL "esd*"
via3_excl_area = via3_m3_excl_area OR via3_m4_excl_area
lonely.via3.R {
    @ lonely.via3.R: There may be room for additional via3(s)
    ((m3m4 INTERACT potential_area_for_via3) NOT via3_excl_area) ENCLOSE < 2 via3
}
small_v3 = RECTANGLE via3 == 0.2 BY == 0.2
potential_area_for_more_via3 = ((met3i AND met4i) ENCLOSE small_v3 == 1) NOT STDCID
potential_area_for_more_via3_size = SIZE potential_area_for_more_via3 BY 0.54
potential_area_for_more_via3_size_halo = SIZE potential_area_for_more_via3_size BY 1
potential_area_for_more_via3_size_block1 = (potential_area_for_more_via3_size_halo AND (OR met3i via1 met4i)) NOT potential_area_for_more_via3
potential_area_for_more_via3_size_block = SIZE (met3i AND potential_area_for_more_via3_size_block1) BY 0.28
potential_area_for_v3_lic_1 = potential_area_for_more_via3_size_block ENCLOSE (met3i AND potential_area_for_more_via3_size_block) < 2
potential_area_for_v3_lic_2 = potential_area_for_more_via3_size_block ENCLOSE (met4i AND potential_area_for_more_via3_size_block) < 2
potential_area_for_v3_lic_3 = potential_area_for_more_via3_size_block ENCLOSE ((SIZE via3 BY 0.17) AND potential_area_for_more_via3_size_block) < 1
potential_area_for_v3_lic = (potential_area_for_v3_lic_1 AND potential_area_for_v3_lic_2) NOT potential_area_for_v3_lic_3
potential_area_for_v3_lonely_yes = (potential_area_for_v3_lic INTERACT potential_area_for_more_via3) OR potential_area_for_more_via3
lonely.via3.a.R {
    @ lonely.via3.a.R: By adding additional met3 and/or met4, there may be room for additional via3s
    COPY (MERGE ((met3i AND met4i) AND potential_area_for_v3_lonely_yes))
}

// VIA4:
// via4 size     0.8
// m4 enc via4   0.06  (adj sides)
// via4 space    0.80
// m5 enc via4   0.310 (adj sides)

m4m5 = met4i AND met5i
via4_size = SIZE via4 BY 1.91 INSIDE OF m4m5
via4_space_size = SIZE via4 BY 0.8 INSIDE OF m4m5
m4m5_no_via4 = ((m4m5 ENCLOSE via4_size) NOT via4_space_size) NOT INTERACT via4
potential_area_for_via4 = WITH WIDTH m4m5_no_via4 >= 1.11
via4_m4_excl_area = met4ii INSIDE CELL "esd*"
via4_m5_excl_area = met5ii INSIDE CELL "esd*"
via4_excl_area = via4_m4_excl_area OR via4_m5_excl_area
lonely.via4.R {
    @ lonely.via4.R: There may be room for additional via4(s)
    ((m4m5 INTERACT potential_area_for_via4) NOT via4_excl_area) ENCLOSE < 2 via4
}
potential_area_for_more_via4 = ((met4i AND met5i) ENCLOSE via4 == 1) NOT STDCID
potential_area_for_more_via4_size = SIZE potential_area_for_more_via3 BY 1.6
potential_area_for_more_via4_size_halo = SIZE potential_area_for_more_via4_size BY 1.5
potential_area_for_more_via4_size_block1 = (potential_area_for_more_via4_size_halo AND (OR met4i via1 met5i)) NOT potential_area_for_more_via4
potential_area_for_more_via4_size_block = SIZE (met4i AND potential_area_for_more_via4_size_block1) BY 0.3
potential_area_for_v4_lic_1 = potential_area_for_more_via4_size_block ENCLOSE (met4i AND potential_area_for_more_via4_size_block) < 2
potential_area_for_v4_lic_2 = potential_area_for_more_via4_size_block ENCLOSE (met5i AND potential_area_for_more_via4_size_block) < 2
potential_area_for_v4_lic_3 = potential_area_for_more_via4_size_block ENCLOSE ((SIZE via4 BY 0.8) AND potential_area_for_more_via4_size_block) < 1
potential_area_for_v4_lic = (potential_area_for_v4_lic_1 AND potential_area_for_v4_lic_2) NOT potential_area_for_v4_lic_3
potential_area_for_v4_lonely_yes = (potential_area_for_v4_lic INTERACT potential_area_for_more_via4) OR potential_area_for_more_via4
lonely.via4.a.R {
    @ lonely.via4.a.R: By adding additional met4 and/or met5, there may be room for additional via4s
    COPY (MERGE ((met4i AND met5i) AND potential_area_for_v4_lonely_yes))
}
 
#ENDIF


//
// FLOATING interconnect check
//

#IFNDEF SKIP_RECOMMENDED_CHECKS


ptap_1 = (((diff AND psdm) NOT nwell) NOT ptub) NOT ptubtap
ntap_1 = (diff AND nsdm) AND nwell
nsd1 = ((diff and nsdm) NOT nwell) NOT gate
psd1 = ((diff and psdm) AND nwell) NOT gate
ngate_de_12v_pw = (((((gate and nsdm) AND v12) AND ENID) NOT nwell) AND thkox) NOT (OR v5 v20 ESDID LVID pnp npn)
ngate_de_12v_gate_conn = ngate_de_12v_pw AND poly
nsrc_de_12v = nsd1 INTERACT ngate_de_12v_pw
ndrn_de_12v = ((((ENID ENCLOSE ntap_1) INTERACT ngate_de_12v_pw) NOT ngate_de_12v_pw) NOT nsrc_de_12v) AND nwell
pgate_de_12v_pw = (((((gate and psdm) AND v12) AND ENID) AND nwell) AND thkox) NOT (OR v5 v20 ESDID LVID pnp npn)
psrc_de_12v = psd1 INTERACT pgate_de_12v_pw
pdrn_de_12v = ((((ENID ENCLOSE ptap_1) ENCLOSE pgate_de_12v_pw) NOT pgate_de_12v_pw) NOT psrc_de_12v) NOT nwell
pgate_de_12v_gate_conn = pgate_de_12v_pw AND poly
pwres_rec = (pwres AND psdm) AND ((HOLES nwell) AND dnwell) 
pwres_term = ((psdm NOT pwres) ENCLOSE diff) TOUCH pwres_rec == 1
hp_poly_1 = poly AND polyres 
hp_poly_2 = hp_poly_1 AND npc
hp_poly_3 = hp_poly_2 AND psdm
hp_poly = hp_poly_3 AND rpm
hs_poly_1 = poly AND polyres 
hs_poly_2 = hs_poly_1 AND npc
hs_poly_3 = hs_poly_2 AND psdm
hs_poly = hs_poly_3 AND urpm
m4_cap_m45_con = met4 AND cap2m
m5_cap_m45_con = met5 AND cap2m
cap45_m4 = COPY m4_cap_m45_con
cap45_m5 = COPY m5_cap_m45_con
m3_cap_m34 = met3 AND capm
m3_cap_m34_con = met3 AND capm
m4_cap_m34_con = met4 AND capm
cap34_m3 = COPY m3_cap_m34_con
cap34_m4 = COPY m4_cap_m34_con
li_1 = li_i NOT lires
li_res_term = EXPAND EDGE (COIN OUTSIDE EDGE li_1 lires) INSIDE BY 0.005
li_res_cont = COPY li_res_term
m1 = met1 NOT m1res
m1_res_term = EXPAND EDGE (COIN OUTSIDE EDGE m1 m1res) INSIDE BY 0.005
m1_res_cont = COPY m1_res_term
m2 = met2 NOT m2res
m2_res_term = EXPAND EDGE (COIN OUTSIDE EDGE m2 m2res) INSIDE BY 0.005
m2_res_cont = COPY m2_res_term
m3 = met3 NOT m3res
m3_res_term = EXPAND EDGE (COIN OUTSIDE EDGE m3 m3res) INSIDE BY 0.005
m3_res_cont = COPY m3_res_term
m4 = met4 NOT m4res
m4_res_term = EXPAND EDGE (COIN OUTSIDE EDGE m4 m4res) INSIDE BY 0.005
m4_res_cont = COPY m4_res_term
m5 = met5 NOT m5res
m5_res_term = EXPAND EDGE (COIN OUTSIDE EDGE m5 m5res) INSIDE BY 0.005
m5_res_cont = COPY m5_res_term
ply = polyi NOT polyres
pl_res_term = EXPAND EDGE (COIN OUTSIDE EDGE ply polyres) INSIDE BY 0.005
pl_res_cont = COPY pl_res_term
df_res_nterm = EXPAND EDGE (COIN OUTSIDE EDGE nsd diffres) INSIDE BY 0.005
df_res_pterm = EXPAND EDGE (COIN OUTSIDE EDGE psd diffres) INSIDE BY 0.005
df_res_ncont = COPY df_res_nterm
df_res_pcont = COPY df_res_pterm

DISCONNECT

CONNECT rdl pad
CONNECT m5 pad
CONNECT m5 m4 BY via4_c
CONNECT m5 m5_res_term BY m5_res_cont
CONNECT m4 m3 BY via3_c
CONNECT m4 m4_res_term BY m4_res_cont
CONNECT m5 cap45_m5 BY m5_cap_m45_con
CONNECT m4 cap45_m4 BY m4_cap_m45_con
CONNECT m4 cap34_m4 BY m4_cap_m34_con
CONNECT m3 cap34_m3 BY m3_cap_m34_con
CONNECT m3 m2 BY via2
CONNECT m3 m3_res_term BY m3_res_cont
CONNECT m2 m1 BY via1
CONNECT m2 m2_res_term BY m2_res_cont
CONNECT m1 li BY mcon
CONNECT m1 m1_res_term BY m1_res_cont
CONNECT li li_res_term BY li_res_cont
CONNECT li ply BY licon
CONNECT li nsd BY licon
CONNECT li psd BY licon
CONNECT li ntap BY licon
CONNECT li ptap BY licon
CONNECT li ptubtap BY licon
CONNECT li pwres_term BY licon
CONNECT li nsrc_de_12v BY licon
CONNECT li ndrn_de_12v BY ntap
CONNECT li psrc_de_12v BY licon
CONNECT li pdrn_de_12v BY ptubtap
CONNECT ply pl_res_term BY pl_res_cont
CONNECT ply ngate_de_12v_pw BY ngate_de_12v_gate_conn
CONNECT ply pgate_de_12v_pw BY pgate_de_12v_gate_conn
CONNECT ply gate
CONNECT nsd df_res_nterm BY df_res_ncont
CONNECT psd df_res_pterm BY df_res_pcont

bad_li_1 = NET AREA RATIO li psd == 0
bad_li_2 = NET AREA RATIO bad_li_1 nsd == 0 
bad_li_3 = NET AREA RATIO bad_li_2 gate == 0
bad_li_4 = NET AREA RATIO bad_li_3 ntap == 0
bad_li_5 = NET AREA RATIO bad_li_4 ptap == 0
bad_li_6 = NET AREA RATIO bad_li_5 ptubtap == 0
bad_li_7 = NET AREA RATIO bad_li_6 pwres_term == 0
bad_li_8 = NET AREA RATIO bad_li_7 nsrc_de_12v == 0
bad_li_9 = NET AREA RATIO bad_li_8 ndrn_de_12v == 0
bad_li_10 = NET AREA RATIO bad_li_9 psrc_de_12v == 0
bad_li_11 = NET AREA RATIO bad_li_10 pdrn_de_12v == 0
bad_li_12 = NET AREA RATIO bad_li_11 ngate_de_12v_pw == 0
bad_li_13 = NET AREA RATIO bad_li_12 pgate_de_12v_pw == 0
bad_li_14 = NET AREA RATIO bad_li_13 cap45_m4 == 0
bad_li_15 = NET AREA RATIO bad_li_14 cap45_m5 == 0
bad_li_16 = NET AREA RATIO bad_li_15 cap34_m4 == 0
bad_li_17 = NET AREA RATIO bad_li_16 cap34_m3 == 0
bad_li_18 = NET AREA RATIO bad_li_17 li_res_term == 0
bad_li_19 = NET AREA RATIO bad_li_18 m1_res_term == 0
bad_li_20 = NET AREA RATIO bad_li_19 m2_res_term == 0
bad_li_21 = NET AREA RATIO bad_li_20 m3_res_term == 0
bad_li_22 = NET AREA RATIO bad_li_21 m4_res_term == 0
bad_li_23 = NET AREA RATIO bad_li_22 m5_res_term == 0
bad_li_24 = NET AREA RATIO bad_li_23 pl_res_term == 0
bad_li_25 = NET AREA RATIO bad_li_24 df_res_nterm == 0
bad_li = NET AREA RATIO bad_li_25 df_res_pterm == 0
bad_ply_1 = NET AREA RATIO ply psd == 0
bad_ply_2 = NET AREA RATIO bad_ply_1 nsd == 0 
bad_ply_3 = NET AREA RATIO bad_ply_2 gate == 0
bad_ply_4 = NET AREA RATIO bad_ply_3 ntap == 0
bad_ply_5 = NET AREA RATIO bad_ply_4 ptap == 0
bad_ply_6 = NET AREA RATIO bad_ply_5 ptubtap == 0
bad_ply_7 = NET AREA RATIO bad_ply_6 pwres_term == 0
bad_ply_8 = NET AREA RATIO bad_ply_7 nsrc_de_12v == 0
bad_ply_9 = NET AREA RATIO bad_ply_8 ndrn_de_12v == 0
bad_ply_10 = NET AREA RATIO bad_ply_9 psrc_de_12v == 0
bad_ply_11 = NET AREA RATIO bad_ply_10 pdrn_de_12v == 0
bad_ply_12 = NET AREA RATIO bad_ply_11 ngate_de_12v_pw == 0
bad_ply_13 = NET AREA RATIO bad_ply_12 pgate_de_12v_pw == 0
bad_ply_14 = NET AREA RATIO bad_ply_13 cap45_m4 == 0
bad_ply_15 = NET AREA RATIO bad_ply_14 cap45_m5 == 0
bad_ply_16 = NET AREA RATIO bad_ply_15 cap34_m4 == 0
bad_ply_17 = NET AREA RATIO bad_ply_16 cap34_m3 == 0
bad_ply_18 = NET AREA RATIO bad_ply_17 li_res_term == 0
bad_ply_19 = NET AREA RATIO bad_ply_18 m1_res_term == 0
bad_ply_20 = NET AREA RATIO bad_ply_19 m2_res_term == 0
bad_ply_21 = NET AREA RATIO bad_ply_20 m3_res_term == 0
bad_ply_22 = NET AREA RATIO bad_ply_21 m4_res_term == 0
bad_ply_23 = NET AREA RATIO bad_ply_22 m5_res_term == 0
bad_ply_24 = NET AREA RATIO bad_ply_23 pl_res_term == 0
bad_ply_25 = NET AREA RATIO bad_ply_24 df_res_nterm == 0
bad_ply = NET AREA RATIO bad_ply_25 df_res_pterm == 0
bad_m1_1 = NET AREA RATIO m1 psd == 0
bad_m1_2 = NET AREA RATIO bad_m1_1 nsd == 0 
bad_m1_3 = NET AREA RATIO bad_m1_2 gate == 0
bad_m1_4 = NET AREA RATIO bad_m1_3 ntap == 0
bad_m1_5 = NET AREA RATIO bad_m1_4 ptap == 0
bad_m1_6 = NET AREA RATIO bad_m1_5 ptubtap == 0
bad_m1_7 = NET AREA RATIO bad_m1_6 pwres_term == 0
bad_m1_8 = NET AREA RATIO bad_m1_7 nsrc_de_12v == 0
bad_m1_9 = NET AREA RATIO bad_m1_8 ndrn_de_12v == 0
bad_m1_10 = NET AREA RATIO bad_m1_9 psrc_de_12v == 0
bad_m1_11 = NET AREA RATIO bad_m1_10 pdrn_de_12v == 0
bad_m1_12 = NET AREA RATIO bad_m1_11 ngate_de_12v_pw == 0
bad_m1_13 = NET AREA RATIO bad_m1_12 pgate_de_12v_pw == 0
bad_m1_14 = NET AREA RATIO bad_m1_13 cap45_m4 == 0
bad_m1_15 = NET AREA RATIO bad_m1_14 cap45_m5 == 0
bad_m1_16 = NET AREA RATIO bad_m1_15 cap34_m4 == 0
bad_m1_17 = NET AREA RATIO bad_m1_16 cap34_m3 == 0
bad_m1_18 = NET AREA RATIO bad_m1_17 li_res_term == 0
bad_m1_19 = NET AREA RATIO bad_m1_18 m1_res_term == 0
bad_m1_20 = NET AREA RATIO bad_m1_19 m2_res_term == 0
bad_m1_21 = NET AREA RATIO bad_m1_20 m3_res_term == 0
bad_m1_22 = NET AREA RATIO bad_m1_21 m4_res_term == 0
bad_m1_23 = NET AREA RATIO bad_m1_22 m5_res_term == 0
bad_m1_24 = NET AREA RATIO bad_m1_23 pl_res_term == 0
bad_m1_25 = NET AREA RATIO bad_m1_24 df_res_nterm == 0
bad_m1 = NET AREA RATIO bad_m1_25 df_res_pterm == 0
bad_m2_1 = NET AREA RATIO m2 psd == 0
bad_m2_2 = NET AREA RATIO bad_m2_1 nsd == 0 
bad_m2_3 = NET AREA RATIO bad_m2_2 gate == 0
bad_m2_4 = NET AREA RATIO bad_m2_3 ntap == 0
bad_m2_5 = NET AREA RATIO bad_m2_4 ptap == 0
bad_m2_6 = NET AREA RATIO bad_m2_5 ptubtap == 0
bad_m2_7 = NET AREA RATIO bad_m2_6 pwres_term == 0
bad_m2_8 = NET AREA RATIO bad_m2_7 nsrc_de_12v == 0
bad_m2_9 = NET AREA RATIO bad_m2_8 ndrn_de_12v == 0
bad_m2_10 = NET AREA RATIO bad_m2_9 psrc_de_12v == 0
bad_m2_11 = NET AREA RATIO bad_m2_10 pdrn_de_12v == 0
bad_m2_12 = NET AREA RATIO bad_m2_11 ngate_de_12v_pw == 0
bad_m2_13 = NET AREA RATIO bad_m2_12 pgate_de_12v_pw == 0
bad_m2_14 = NET AREA RATIO bad_m2_13 cap45_m4 == 0
bad_m2_15 = NET AREA RATIO bad_m2_14 cap45_m5 == 0
bad_m2_16 = NET AREA RATIO bad_m2_15 cap34_m4 == 0
bad_m2_17 = NET AREA RATIO bad_m2_16 cap34_m3 == 0
bad_m2_18 = NET AREA RATIO bad_m2_17 li_res_term == 0
bad_m2_19 = NET AREA RATIO bad_m2_18 m1_res_term == 0
bad_m2_20 = NET AREA RATIO bad_m2_19 m2_res_term == 0
bad_m2_21 = NET AREA RATIO bad_m2_20 m3_res_term == 0
bad_m2_22 = NET AREA RATIO bad_m2_21 m4_res_term == 0
bad_m2_23 = NET AREA RATIO bad_m2_22 m5_res_term == 0
bad_m2_24 = NET AREA RATIO bad_m2_23 pl_res_term == 0
bad_m2_25 = NET AREA RATIO bad_m2_24 df_res_nterm == 0
bad_m2 = NET AREA RATIO bad_m2_25 df_res_pterm == 0
bad_m3_1 = NET AREA RATIO m3 psd == 0
bad_m3_2 = NET AREA RATIO bad_m3_1 nsd == 0 
bad_m3_3 = NET AREA RATIO bad_m3_2 gate == 0
bad_m3_4 = NET AREA RATIO bad_m3_3 ntap == 0
bad_m3_5 = NET AREA RATIO bad_m3_4 ptap == 0
bad_m3_6 = NET AREA RATIO bad_m3_5 ptubtap == 0
bad_m3_7 = NET AREA RATIO bad_m3_6 pwres_term == 0
bad_m3_8 = NET AREA RATIO bad_m3_7 nsrc_de_12v == 0
bad_m3_9 = NET AREA RATIO bad_m3_8 ndrn_de_12v == 0
bad_m3_10 = NET AREA RATIO bad_m3_9 psrc_de_12v == 0
bad_m3_11 = NET AREA RATIO bad_m3_10 pdrn_de_12v == 0
bad_m3_12 = NET AREA RATIO bad_m3_11 ngate_de_12v_pw == 0
bad_m3_13 = NET AREA RATIO bad_m3_12 pgate_de_12v_pw == 0
bad_m3_14 = NET AREA RATIO bad_m3_13 cap45_m4 == 0
bad_m3_15 = NET AREA RATIO bad_m3_14 cap45_m5 == 0
bad_m3_16 = NET AREA RATIO bad_m3_15 cap34_m4 == 0
bad_m3_17 = NET AREA RATIO bad_m3_16 cap34_m3 == 0
bad_m3_18 = NET AREA RATIO bad_m3_17 li_res_term == 0
bad_m3_19 = NET AREA RATIO bad_m3_18 m1_res_term == 0
bad_m3_20 = NET AREA RATIO bad_m3_19 m2_res_term == 0
bad_m3_21 = NET AREA RATIO bad_m3_20 m3_res_term == 0
bad_m3_22 = NET AREA RATIO bad_m3_21 m4_res_term == 0
bad_m3_23 = NET AREA RATIO bad_m3_22 m5_res_term == 0
bad_m3_24 = NET AREA RATIO bad_m3_23 pl_res_term == 0
bad_m3_25 = NET AREA RATIO bad_m3_24 df_res_nterm == 0
bad_m3 = NET AREA RATIO bad_m3_25 df_res_pterm == 0
bad_m4_1 = NET AREA RATIO m4 psd == 0
bad_m4_2 = NET AREA RATIO bad_m4_1 nsd == 0 
bad_m4_3 = NET AREA RATIO bad_m4_2 gate == 0
bad_m4_4 = NET AREA RATIO bad_m4_3 ntap == 0
bad_m4_5 = NET AREA RATIO bad_m4_4 ptap == 0
bad_m4_6 = NET AREA RATIO bad_m4_5 ptubtap == 0
bad_m4_7 = NET AREA RATIO bad_m4_6 pwres_term == 0
bad_m4_8 = NET AREA RATIO bad_m4_7 nsrc_de_12v == 0
bad_m4_9 = NET AREA RATIO bad_m4_8 ndrn_de_12v == 0
bad_m4_10 = NET AREA RATIO bad_m4_9 psrc_de_12v == 0
bad_m4_11 = NET AREA RATIO bad_m4_10 pdrn_de_12v == 0
bad_m4_12 = NET AREA RATIO bad_m4_11 ngate_de_12v_pw == 0
bad_m4_13 = NET AREA RATIO bad_m4_12 pgate_de_12v_pw == 0
bad_m4_14 = NET AREA RATIO bad_m4_13 cap45_m4 == 0
bad_m4_15 = NET AREA RATIO bad_m4_14 cap45_m5 == 0
bad_m4_16 = NET AREA RATIO bad_m4_15 cap34_m4 == 0
bad_m4_17 = NET AREA RATIO bad_m4_16 cap34_m3 == 0
bad_m4_18 = NET AREA RATIO bad_m4_17 li_res_term == 0
bad_m4_19 = NET AREA RATIO bad_m4_18 m1_res_term == 0
bad_m4_20 = NET AREA RATIO bad_m4_19 m2_res_term == 0
bad_m4_21 = NET AREA RATIO bad_m4_20 m3_res_term == 0
bad_m4_22 = NET AREA RATIO bad_m4_21 m4_res_term == 0
bad_m4_23 = NET AREA RATIO bad_m4_22 m5_res_term == 0
bad_m4_24 = NET AREA RATIO bad_m4_23 pl_res_term == 0
bad_m4_25 = NET AREA RATIO bad_m4_24 df_res_nterm == 0
bad_m4 = NET AREA RATIO bad_m4_25 df_res_pterm == 0
bad_m5_1 = NET AREA RATIO m5 psd == 0
bad_m5_2 = NET AREA RATIO bad_m5_1 nsd == 0 
bad_m5_3 = NET AREA RATIO bad_m5_2 gate == 0
bad_m5_4 = NET AREA RATIO bad_m5_3 ntap == 0
bad_m5_5 = NET AREA RATIO bad_m5_4 ptap == 0
bad_m5_6 = NET AREA RATIO bad_m5_5 ptubtap == 0
bad_m5_7 = NET AREA RATIO bad_m5_6 pwres_term == 0
bad_m5_8 = NET AREA RATIO bad_m5_7 nsrc_de_12v == 0
bad_m5_9 = NET AREA RATIO bad_m5_8 ndrn_de_12v == 0
bad_m5_10 = NET AREA RATIO bad_m5_9 psrc_de_12v == 0
bad_m5_11 = NET AREA RATIO bad_m5_10 pdrn_de_12v == 0
bad_m5_12 = NET AREA RATIO bad_m5_11 ngate_de_12v_pw == 0
bad_m5_13 = NET AREA RATIO bad_m5_12 pgate_de_12v_pw == 0
bad_m5_14 = NET AREA RATIO bad_m5_13 cap45_m4 == 0
bad_m5_15 = NET AREA RATIO bad_m5_14 cap45_m5 == 0
bad_m5_16 = NET AREA RATIO bad_m5_15 cap34_m4 == 0
bad_m5_17 = NET AREA RATIO bad_m5_16 cap34_m3 == 0
bad_m5_18 = NET AREA RATIO bad_m5_17 li_res_term == 0
bad_m5_19 = NET AREA RATIO bad_m5_18 m1_res_term == 0
bad_m5_20 = NET AREA RATIO bad_m5_19 m2_res_term == 0
bad_m5_21 = NET AREA RATIO bad_m5_20 m3_res_term == 0
bad_m5_22 = NET AREA RATIO bad_m5_21 m4_res_term == 0
bad_m5_23 = NET AREA RATIO bad_m5_22 m5_res_term == 0
bad_m5_24 = NET AREA RATIO bad_m5_23 pl_res_term == 0
bad_m5_25 = NET AREA RATIO bad_m5_24 df_res_nterm == 0
bad_m5 = NET AREA RATIO bad_m5_25 df_res_pterm == 0
bad_rdl_1 = NET AREA RATIO rdl psd == 0
bad_rdl_2 = NET AREA RATIO bad_rdl_1 nsd == 0 
bad_rdl_3 = NET AREA RATIO bad_rdl_2 gate == 0
bad_rdl_4 = NET AREA RATIO bad_rdl_3 ntap == 0
bad_rdl_5 = NET AREA RATIO bad_rdl_4 ptap == 0
bad_rdl_6 = NET AREA RATIO bad_rdl_5 ptubtap == 0
bad_rdl_7 = NET AREA RATIO bad_rdl_6 pwres_term == 0
bad_rdl_8 = NET AREA RATIO bad_rdl_7 nsrc_de_12v == 0
bad_rdl_9 = NET AREA RATIO bad_rdl_8 ndrn_de_12v == 0
bad_rdl_10 = NET AREA RATIO bad_rdl_9 psrc_de_12v == 0
bad_rdl_11 = NET AREA RATIO bad_rdl_10 pdrn_de_12v == 0
bad_rdl_12 = NET AREA RATIO bad_rdl_11 ngate_de_12v_pw == 0
bad_rdl_13 = NET AREA RATIO bad_rdl_12 pgate_de_12v_pw == 0
bad_rdl_14 = NET AREA RATIO bad_rdl_13 cap45_m4 == 0
bad_rdl_15 = NET AREA RATIO bad_rdl_14 cap45_m5 == 0
bad_rdl_16 = NET AREA RATIO bad_rdl_15 cap34_m4 == 0
bad_rdl_17 = NET AREA RATIO bad_rdl_16 cap34_m3 == 0
bad_rdl_18 = NET AREA RATIO bad_rdl_17 li_res_term == 0
bad_rdl_19 = NET AREA RATIO bad_rdl_18 m1_res_term == 0
bad_rdl_20 = NET AREA RATIO bad_rdl_19 m2_res_term == 0
bad_rdl_21 = NET AREA RATIO bad_rdl_20 m3_res_term == 0
bad_rdl_22 = NET AREA RATIO bad_rdl_21 m4_res_term == 0
bad_rdl_23 = NET AREA RATIO bad_rdl_22 m5_res_term == 0
bad_rdl_24 = NET AREA RATIO bad_rdl_23 pl_res_term == 0
bad_rdl_25 = NET AREA RATIO bad_rdl_24 df_res_nterm == 0
bad_rdl = NET AREA RATIO bad_rdl_25 df_res_pterm == 0
good_li_1 = NET AREA RATIO li psd > 0
good_li_2 = NET AREA RATIO good_li_1 nsd > 0 
good_li_3 = NET AREA RATIO good_li_2 gate > 0
good_li_4 = NET AREA RATIO good_li_3 ntap > 0
good_li_5 = NET AREA RATIO good_li_4 ptap > 0
good_li_6 = NET AREA RATIO good_li_5 ptubtap > 0
good_li_7 = NET AREA RATIO good_li_6 pwres_term > 0
good_li_8 = NET AREA RATIO good_li_7 nsrc_de_12v > 0
good_li_9 = NET AREA RATIO good_li_8 ndrn_de_12v > 0
good_li_10 = NET AREA RATIO good_li_9 psrc_de_12v > 0
good_li_11 = NET AREA RATIO good_li_10 pdrn_de_12v > 0
good_li_12 = NET AREA RATIO good_li_11 ngate_de_12v_pw > 0
good_li_13 = NET AREA RATIO good_li_12 pgate_de_12v_pw > 0
good_li_14 = NET AREA RATIO good_li_13 cap45_m4 > 0
good_li_15 = NET AREA RATIO good_li_14 cap45_m5 > 0
good_li_16 = NET AREA RATIO good_li_15 cap34_m4 > 0
good_li_17 = NET AREA RATIO good_li_16 cap34_m3 > 0
good_li_18 = NET AREA RATIO good_li_17 li_res_term > 0
good_li_19 = NET AREA RATIO good_li_18 m1_res_term > 0
good_li_20 = NET AREA RATIO good_li_19 m2_res_term > 0
good_li_21 = NET AREA RATIO good_li_20 m3_res_term > 0
good_li_22 = NET AREA RATIO good_li_21 m4_res_term > 0
good_li_23 = NET AREA RATIO good_li_22 m5_res_term > 0
good_li_24 = NET AREA RATIO good_li_23 pl_res_term > 0
good_li_25 = NET AREA RATIO good_li_24 df_res_nterm > 0
good_li = NET AREA RATIO good_li_25 df_res_pterm > 0
good_ply_1 = NET AREA RATIO ply psd > 0
good_ply_2 = NET AREA RATIO good_ply_1 nsd > 0 
good_ply_3 = NET AREA RATIO good_ply_2 gate > 0
good_ply_4 = NET AREA RATIO good_ply_3 ntap > 0
good_ply_5 = NET AREA RATIO good_ply_4 ptap > 0
good_ply_6 = NET AREA RATIO good_ply_5 ptubtap > 0
good_ply_7 = NET AREA RATIO good_ply_6 pwres_term > 0
good_ply_8 = NET AREA RATIO good_ply_7 nsrc_de_12v > 0
good_ply_9 = NET AREA RATIO good_ply_8 ndrn_de_12v > 0
good_ply_10 = NET AREA RATIO good_ply_9 psrc_de_12v > 0
good_ply_11 = NET AREA RATIO good_ply_10 pdrn_de_12v > 0
good_ply_12 = NET AREA RATIO good_ply_11 ngate_de_12v_pw > 0
good_ply_13 = NET AREA RATIO good_ply_12 pgate_de_12v_pw > 0
good_ply_14 = NET AREA RATIO good_ply_13 cap45_m4 > 0
good_ply_15 = NET AREA RATIO good_ply_14 cap45_m5 > 0
good_ply_16 = NET AREA RATIO good_ply_15 cap34_m4 > 0
good_ply_17 = NET AREA RATIO good_ply_16 cap34_m3 > 0
good_ply_18 = NET AREA RATIO good_ply_17 li_res_term > 0
good_ply_19 = NET AREA RATIO good_ply_18 m1_res_term > 0
good_ply_20 = NET AREA RATIO good_ply_19 m2_res_term > 0
good_ply_21 = NET AREA RATIO good_ply_20 m3_res_term > 0
good_ply_22 = NET AREA RATIO good_ply_21 m4_res_term > 0
good_ply_23 = NET AREA RATIO good_ply_22 m5_res_term > 0
good_ply_24 = NET AREA RATIO good_ply_23 pl_res_term > 0
good_ply_25 = NET AREA RATIO good_ply_24 df_res_nterm > 0
good_ply = NET AREA RATIO good_ply_25 df_res_pterm > 0
good_m1_1 = NET AREA RATIO m1 psd > 0
good_m1_2 = NET AREA RATIO good_m1_1 nsd > 0 
good_m1_3 = NET AREA RATIO good_m1_2 gate > 0
good_m1_4 = NET AREA RATIO good_m1_3 ntap > 0
good_m1_5 = NET AREA RATIO good_m1_4 ptap > 0
good_m1_6 = NET AREA RATIO good_m1_5 ptubtap > 0
good_m1_7 = NET AREA RATIO good_m1_6 pwres_term > 0
good_m1_8 = NET AREA RATIO good_m1_7 nsrc_de_12v > 0
good_m1_9 = NET AREA RATIO good_m1_8 ndrn_de_12v > 0
good_m1_10 = NET AREA RATIO good_m1_9 psrc_de_12v > 0
good_m1_11 = NET AREA RATIO good_m1_10 pdrn_de_12v > 0
good_m1_12 = NET AREA RATIO good_m1_11 ngate_de_12v_pw > 0
good_m1_13 = NET AREA RATIO good_m1_12 pgate_de_12v_pw > 0
good_m1_14 = NET AREA RATIO good_m1_13 cap45_m4 > 0
good_m1_15 = NET AREA RATIO good_m1_14 cap45_m5 > 0
good_m1_16 = NET AREA RATIO good_m1_15 cap34_m4 > 0
good_m1_17 = NET AREA RATIO good_m1_16 cap34_m3 > 0
good_m1_18 = NET AREA RATIO good_m1_17 li_res_term > 0
good_m1_19 = NET AREA RATIO good_m1_18 m1_res_term > 0
good_m1_20 = NET AREA RATIO good_m1_19 m2_res_term > 0
good_m1_21 = NET AREA RATIO good_m1_20 m3_res_term > 0
good_m1_22 = NET AREA RATIO good_m1_21 m4_res_term > 0
good_m1_23 = NET AREA RATIO good_m1_22 m5_res_term > 0
good_m1_24 = NET AREA RATIO good_m1_23 pl_res_term > 0
good_m1_25 = NET AREA RATIO good_m1_24 df_res_nterm > 0
good_m1 = NET AREA RATIO good_m1_25 df_res_pterm > 0
good_m2_1 = NET AREA RATIO m2 psd > 0
good_m2_2 = NET AREA RATIO good_m2_1 nsd > 0 
good_m2_3 = NET AREA RATIO good_m2_2 gate > 0
good_m2_4 = NET AREA RATIO good_m2_3 ntap > 0
good_m2_5 = NET AREA RATIO good_m2_4 ptap > 0
good_m2_6 = NET AREA RATIO good_m2_5 ptubtap > 0
good_m2_7 = NET AREA RATIO good_m2_6 pwres_term > 0
good_m2_8 = NET AREA RATIO good_m2_7 nsrc_de_12v > 0
good_m2_9 = NET AREA RATIO good_m2_8 ndrn_de_12v > 0
good_m2_10 = NET AREA RATIO good_m2_9 psrc_de_12v > 0
good_m2_11 = NET AREA RATIO good_m2_10 pdrn_de_12v > 0
good_m2_12 = NET AREA RATIO good_m2_11 ngate_de_12v_pw > 0
good_m2_13 = NET AREA RATIO good_m2_12 pgate_de_12v_pw > 0
good_m2_14 = NET AREA RATIO good_m2_13 cap45_m4 > 0
good_m2_15 = NET AREA RATIO good_m2_14 cap45_m5 > 0
good_m2_16 = NET AREA RATIO good_m2_15 cap34_m4 > 0
good_m2_17 = NET AREA RATIO good_m2_16 cap34_m3 > 0
good_m2_18 = NET AREA RATIO good_m2_17 li_res_term > 0
good_m2_19 = NET AREA RATIO good_m2_18 m1_res_term > 0
good_m2_20 = NET AREA RATIO good_m2_19 m2_res_term > 0
good_m2_21 = NET AREA RATIO good_m2_20 m3_res_term > 0
good_m2_22 = NET AREA RATIO good_m2_21 m4_res_term > 0
good_m2_23 = NET AREA RATIO good_m2_22 m5_res_term > 0
good_m2_24 = NET AREA RATIO good_m2_23 pl_res_term > 0
good_m2_25 = NET AREA RATIO good_m2_24 df_res_nterm > 0
good_m2 = NET AREA RATIO good_m2_25 df_res_pterm > 0
good_m3_1 = NET AREA RATIO m3 psd > 0
good_m3_2 = NET AREA RATIO good_m3_1 nsd > 0 
good_m3_3 = NET AREA RATIO good_m3_2 gate > 0
good_m3_4 = NET AREA RATIO good_m3_3 ntap > 0
good_m3_5 = NET AREA RATIO good_m3_4 ptap > 0
good_m3_6 = NET AREA RATIO good_m3_5 ptubtap > 0
good_m3_7 = NET AREA RATIO good_m3_6 pwres_term > 0
good_m3_8 = NET AREA RATIO good_m3_7 nsrc_de_12v > 0
good_m3_9 = NET AREA RATIO good_m3_8 ndrn_de_12v > 0
good_m3_10 = NET AREA RATIO good_m3_9 psrc_de_12v > 0
good_m3_11 = NET AREA RATIO good_m3_10 pdrn_de_12v > 0
good_m3_12 = NET AREA RATIO good_m3_11 ngate_de_12v_pw > 0
good_m3_13 = NET AREA RATIO good_m3_12 pgate_de_12v_pw > 0
good_m3_14 = NET AREA RATIO good_m3_13 cap45_m4 > 0
good_m3_15 = NET AREA RATIO good_m3_14 cap45_m5 > 0
good_m3_16 = NET AREA RATIO good_m3_15 cap34_m4 > 0
good_m3_17 = NET AREA RATIO good_m3_16 cap34_m3 > 0
good_m3_18 = NET AREA RATIO good_m3_17 li_res_term > 0
good_m3_19 = NET AREA RATIO good_m3_18 m1_res_term > 0
good_m3_20 = NET AREA RATIO good_m3_19 m2_res_term > 0
good_m3_21 = NET AREA RATIO good_m3_20 m3_res_term > 0
good_m3_22 = NET AREA RATIO good_m3_21 m4_res_term > 0
good_m3_23 = NET AREA RATIO good_m3_22 m5_res_term > 0
good_m3_24 = NET AREA RATIO good_m3_23 pl_res_term > 0
good_m3_25 = NET AREA RATIO good_m3_24 df_res_nterm > 0
good_m3 = NET AREA RATIO good_m3_25 df_res_pterm > 0
good_m4_1 = NET AREA RATIO m4 psd > 0
good_m4_2 = NET AREA RATIO good_m4_1 nsd > 0 
good_m4_3 = NET AREA RATIO good_m4_2 gate > 0
good_m4_4 = NET AREA RATIO good_m4_3 ntap > 0
good_m4_5 = NET AREA RATIO good_m4_4 ptap > 0
good_m4_6 = NET AREA RATIO good_m4_5 ptubtap > 0
good_m4_7 = NET AREA RATIO good_m4_6 pwres_term > 0
good_m4_8 = NET AREA RATIO good_m4_7 nsrc_de_12v > 0
good_m4_9 = NET AREA RATIO good_m4_8 ndrn_de_12v > 0
good_m4_10 = NET AREA RATIO good_m4_9 psrc_de_12v > 0
good_m4_11 = NET AREA RATIO good_m4_10 pdrn_de_12v > 0
good_m4_12 = NET AREA RATIO good_m4_11 ngate_de_12v_pw > 0
good_m4_13 = NET AREA RATIO good_m4_12 pgate_de_12v_pw > 0
good_m4_14 = NET AREA RATIO good_m4_13 cap45_m4 > 0
good_m4_15 = NET AREA RATIO good_m4_14 cap45_m5 > 0
good_m4_16 = NET AREA RATIO good_m4_15 cap34_m4 > 0
good_m4_17 = NET AREA RATIO good_m4_16 cap34_m3 > 0
good_m4_18 = NET AREA RATIO good_m4_17 li_res_term > 0
good_m4_19 = NET AREA RATIO good_m4_18 m1_res_term > 0
good_m4_20 = NET AREA RATIO good_m4_19 m2_res_term > 0
good_m4_21 = NET AREA RATIO good_m4_20 m3_res_term > 0
good_m4_22 = NET AREA RATIO good_m4_21 m4_res_term > 0
good_m4_23 = NET AREA RATIO good_m4_22 m5_res_term > 0
good_m4_24 = NET AREA RATIO good_m4_23 pl_res_term > 0
good_m4_25 = NET AREA RATIO good_m4_24 df_res_nterm > 0
good_m4 = NET AREA RATIO good_m4_25 df_res_pterm > 0
good_m5_1 = NET AREA RATIO m5 psd > 0
good_m5_2 = NET AREA RATIO good_m5_1 nsd > 0 
good_m5_3 = NET AREA RATIO good_m5_2 gate > 0
good_m5_4 = NET AREA RATIO good_m5_3 ntap > 0
good_m5_5 = NET AREA RATIO good_m5_4 ptap > 0
good_m5_6 = NET AREA RATIO good_m5_5 ptubtap > 0
good_m5_7 = NET AREA RATIO good_m5_6 pwres_term > 0
good_m5_8 = NET AREA RATIO good_m5_7 nsrc_de_12v > 0
good_m5_9 = NET AREA RATIO good_m5_8 ndrn_de_12v > 0
good_m5_10 = NET AREA RATIO good_m5_9 psrc_de_12v > 0
good_m5_11 = NET AREA RATIO good_m5_10 pdrn_de_12v > 0
good_m5_12 = NET AREA RATIO good_m5_11 ngate_de_12v_pw > 0
good_m5_13 = NET AREA RATIO good_m5_12 pgate_de_12v_pw > 0
good_m5_14 = NET AREA RATIO good_m5_13 cap45_m4 > 0
good_m5_15 = NET AREA RATIO good_m5_14 cap45_m5 > 0
good_m5_16 = NET AREA RATIO good_m5_15 cap34_m4 > 0
good_m5_17 = NET AREA RATIO good_m5_16 cap34_m3 > 0
good_m5_18 = NET AREA RATIO good_m5_17 li_res_term > 0
good_m5_19 = NET AREA RATIO good_m5_18 m1_res_term > 0
good_m5_20 = NET AREA RATIO good_m5_19 m2_res_term > 0
good_m5_21 = NET AREA RATIO good_m5_20 m3_res_term > 0
good_m5_22 = NET AREA RATIO good_m5_21 m4_res_term > 0
good_m5_23 = NET AREA RATIO good_m5_22 m5_res_term > 0
good_m5_24 = NET AREA RATIO good_m5_23 pl_res_term > 0
good_m5_25 = NET AREA RATIO good_m5_24 df_res_nterm > 0
good_m5 = NET AREA RATIO good_m5_25 df_res_pterm > 0
good_rdl_1 = NET AREA RATIO rdl psd > 0
good_rdl_2 = NET AREA RATIO good_rdl_1 nsd > 0 
good_rdl_3 = NET AREA RATIO good_rdl_2 gate > 0
good_rdl_4 = NET AREA RATIO good_rdl_3 ntap > 0
good_rdl_5 = NET AREA RATIO good_rdl_4 ptap > 0
good_rdl_6 = NET AREA RATIO good_rdl_5 ptubtap > 0
good_rdl_7 = NET AREA RATIO good_rdl_6 pwres_term > 0
good_rdl_8 = NET AREA RATIO good_rdl_7 nsrc_de_12v > 0
good_rdl_9 = NET AREA RATIO good_rdl_8 ndrn_de_12v > 0
good_rdl_10 = NET AREA RATIO good_rdl_9 psrc_de_12v > 0
good_rdl_11 = NET AREA RATIO good_rdl_10 pdrn_de_12v > 0
good_rdl_12 = NET AREA RATIO good_rdl_11 ngate_de_12v_pw > 0
good_rdl_13 = NET AREA RATIO good_rdl_12 pgate_de_12v_pw > 0
good_rdl_14 = NET AREA RATIO good_rdl_13 cap45_m4 > 0
good_rdl_15 = NET AREA RATIO good_rdl_14 cap45_m5 > 0
good_rdl_16 = NET AREA RATIO good_rdl_15 cap34_m4 > 0
good_rdl_17 = NET AREA RATIO good_rdl_16 cap34_m3 > 0
good_rdl_18 = NET AREA RATIO good_rdl_17 li_res_term > 0
good_rdl_19 = NET AREA RATIO good_rdl_18 m1_res_term > 0
good_rdl_20 = NET AREA RATIO good_rdl_19 m2_res_term > 0
good_rdl_21 = NET AREA RATIO good_rdl_20 m3_res_term > 0
good_rdl_22 = NET AREA RATIO good_rdl_21 m4_res_term > 0
good_rdl_23 = NET AREA RATIO good_rdl_22 m5_res_term > 0
good_rdl_24 = NET AREA RATIO good_rdl_23 pl_res_term > 0
good_rdl_25 = NET AREA RATIO good_rdl_24 df_res_nterm > 0
good_rdl = NET AREA RATIO good_rdl_25 df_res_pterm > 0
net_not_float = OR good_ply good_li good_m1 good_m2 good_m3 good_m4 good_m5 good_rdl
exempt_float_li_1 = li_ii INSIDE CELL "text_pcell*"
exempt_float_li_2 = li_ii INTERACT (OR critside ccorner)
exempt_float_li = OR exempt_float_li_1 exempt_float_li_2
floating.net.li.R {
    @ floating.net.li.R: Floating local interconnect nets - nets which do not connect to a defined device
    COPY ((bad_li NOT li_fill) NOT exempt_float_li)
}
exempt_float_ply_1 = polyii INSIDE CELL "text_pcell*"
exempt_float_ply_2 = polyii INTERACT (OR critside ccorner)
exempt_float_ply = OR exempt_float_ply_1 exempt_float_ply_2
floating.net.poly.R {
    @ floating.net.poly.R: Floating poly nets - nets which do not connect to a defined device
    COPY ((bad_ply NOT poly_fill) NOT exempt_float_ply)
}
exempt_float_m1_1 = met1ii INSIDE CELL "text_pcell*"
exempt_float_m1_2 = met1ii INTERACT (OR critside ccorner)
exempt_float_m1 = OR exempt_float_m1_1 exempt_float_m1_2
floating.net.met1.R {
    @ floating.net.met1.R: Floating met1 nets - nets which do not connect to a defined device
    COPY ((bad_m1 NOT m1_fill) NOT exempt_float_m1)
}
exempt_float_m2_1 = met2ii INSIDE CELL "text_pcell*"
exempt_float_m2_2 = met2ii INTERACT (OR critside ccorner)
exempt_float_m2 = OR exempt_float_m2_1 exempt_float_m2_2
floating.net.met2.R {
    @ floating.net.met2.R: Floating met2 nets - nets which do not connect to a defined device
    COPY ((bad_m2 NOT m2_fill) NOT exempt_float_m2)
}
exempt_float_m3_1 = met3ii INSIDE CELL "text_pcell*"
exempt_float_m3_2 = met3ii INTERACT (OR critside ccorner)
exempt_float_m3 = OR exempt_float_m3_1 exempt_float_m3_2
floating.net.met3.R {
    @ floating.net.met3.R: Floating met3 nets - nets which do not connect to a defined device
    COPY ((bad_m3 NOT m3_fill) NOT exempt_float_m3)
}
exempt_float_m4_1 = met4ii INSIDE CELL "text_pcell*"
exempt_float_m4_2 = met4ii INTERACT (OR critside ccorner)
exempt_float_m4 = OR exempt_float_m4_1 exempt_float_m4_2
floating.net.met4.R {
    @ floating.net.met4.R: Floating met4 nets - nets which do not connect to a defined device
    COPY ((bad_m4 NOT m4_fill) NOT exempt_float_m4)
}
exempt_float_m5 = met5ii INSIDE CELL "text_pcell*"
floating.net.met5.R {
    @ floating.net.met5.R: Floating met5 nets - nets which do not connect to a defined device
    COPY ((bad_m5 NOT m5_fill) NOT exempt_float_m5)
}
connect_nets = OR gate nsd psd ptap ntap m1res m2res m3res m4res m5res lires npn pnp diodeID capm cap2m pad
floating.net.ptap.R {
    @ floating.net.ptap.R: possible floating p+ tap - p+ tap not connected to pad
    NET AREA RATIO ptap pad == 0
}
floating.net.ntap.R {
    @ floating.net.ntap.R: possible floating n+ tap - n+ tap not connected to pad
    NET AREA RATIO ntap pad == 0
}
floating.net.pwell.R {
    @ floating.net.pwell.R: substrate not conected by ptap
    (pwell NOT INTERACT (HOLES pwbm INNER)) NOT ENCLOSE ptap
}
floating.net.ptub.R {
    @ floating.net.ptub.R: isolated substrate not connected by ptap
    ptub NOT ENCLOSE ptap
}
floating.net.localsub.R {
    @ floating.net.localsub.R: local substrate (areaid:substrateCut) not connected by ptap
    localSub NOT ENCLOSE ptap
}
 
#ENDIF


// Begin illegal device checks 

#IFNDEF SKIP_ILLEGAL_DEVICE_CHECKS

// 4/14/21 SWT changed to permit active under pad:
skip_pad = COPY 7000 
skip_res = COPY 7001
skip_dnw = COPY 7002

// NMOS:


mos_diff = diffi NOT (OR pnp npn ENID)
nmos_gate = (mos_diff AND polyi) NOT nwell
nmos_sd = (diffi INTERACT nmos_gate) NOT nmos_gate
nmos_1 = nmos_gate TOUCH nmos_sd == 2
nmos = nmos_1 NOT (OR ESDID thkox lvtn)
nmos.OVL.1 {
    @ nmos.OVL.1: Illegal nmos device: nmos must not overlap pwbm
    nmos AND pwbm
}
nmos.OVL.2 {
    @ nmos.OVL.2: Illegal nmos device: nmos must not overlap pwde
    nmos AND pwde
}
nmos.OVL.3 {
    @ nmos.OVL.3: Illegal nmos device: nmos must not overlap nwell
    nmos AND nwell
}
nmos.OVL.4 {
    @ nmos.OVL.4: Illegal nmos device: nmos must not overlap hvtp
    nmos AND hvtp
}
nmos.OVL.5 {
    @ nmos.OVL.5: Illegal nmos device: nmos must not overlap lvtn
    nmos AND lvtn
}
nmos.OVL.6 {
    @ nmos.OVL.6: Illegal nmos device: nmos must not overlap tunm
    nmos AND tunm
}
nmos.OVL.7 {
    @ nmos.OVL.7: Illegal nmos device: nmos must not overlap thkox
    nmos AND thkox
}
nmos.OVL.8 {
    @ nmos.OVL.8: Illegal nmos device: nmos must not overlap rpm
    nmos AND rpm
}
nmos.OVL.9 {
    @ nmos.OVL.9: Illegal nmos device: nmos must not overlap rrpm
    nmos AND rrpm
}
nmos.OVL.10 {
    @ nmos.OVL.10: Illegal nmos device: nmos must not overlap urpm
    nmos AND urpm
}
nmos.OVL.11 {
    @ nmos.OVL.11: Illegal nmos device: nmos must not overlap ldntm
    nmos AND ldntm
}
nmos.OVL.12 {
    @ nmos.OVL.12: Illegal nmos device: nmos must not overlap npc
    nmos AND npc
}
nmos.OVL.13 {
    @ nmos.OVL.13: Illegal nmos device: nmos must not overlap psdm
    nmos AND psdm
}
nmos.OVL.14 {
    @ nmos.OVL.14: Illegal nmos device: nmos must not overlap nsm
    nmos AND nsm
}
nmos.OVL.15 {
    @ nmos.OVL.15: Illegal nmos device: nmos must not overlap skip_pad
    nmos AND skip_pad
}
nmos.OVL.16 {
    @ nmos.OVL.16: Illegal nmos device: nmos must not overlap fuse
    nmos AND fuse
}
nmos.OVL.17 {
    @ nmos.OVL.17: Illegal nmos device: nmos must not overlap diff:res
    nmos AND diffres
}
nmos.OVL.18 {
    @ nmos.OVL.18: Illegal nmos device: nmos must not overlap pwell:res
    nmos AND pwres
}
nmos.OVL.19 {
    @ nmos.OVL.19: Illegal nmos device: nmos must not overlap poly:res
    nmos AND polyres
}
nmos.OVL.20 {
    @ nmos.OVL.20: Illegal nmos device: nmos must not overlap li:res
    nmos AND lires
}
nmos.OVL.21 {
    @ nmos.OVL.21: Illegal nmos device: nmos must not overlap skip_res
    nmos AND skip_res
}
nmos.OVL.22 {
    @ nmos.OVL.22: Illegal nmos device: nmos must not overlap skip_res
    nmos AND skip_res
}
nmos.OVL.23 {
    @ nmos.OVL.23: Illegal nmos device: nmos must not overlap skip_res
    nmos AND skip_res
}
nmos.OVL.24 {
    @ nmos.OVL.24: Illegal nmos device: nmos must not overlap skip_res
    nmos AND skip_res
}
nmos.OVL.25 {
    @ nmos.OVL.25: Illegal nmos device: nmos must not overlap skip_res
    nmos AND skip_res
}
nmos.OVL.26 {
    @ nmos.OVL.26: Illegal nmos device: nmos must not overlap areaid:lvNative
    nmos AND LVID
}
nmos.OVL.27 {
    @ nmos.OVL.27: Illegal nmos device: nmos must not overlap pnp
    nmos AND pnp
}
nmos.OVL.28 {
    @ nmos.OVL.28: Illegal nmos device: nmos must not overlap npn
    nmos AND npn
}
nmos.OVL.29 {
    @ nmos.OVL.29: Illegal nmos device: nmos must not overlap areaid:diode
    nmos AND DiodeID
}
nmos.OVL.30 {
    @ nmos.OVL.30: Illegal nmos device: nmos must not overlap areaid:photo
    nmos AND PHdiodeID
}
nmos.OVL.31 {
    @ nmos.OVL.31: Illegal nmos device: nmos must not overlap areaid:core
    nmos AND COREID
}
nmos.OVL.32 {
    @ nmos.OVL.32: Illegal nmos device: nmos must not overlap areaid:extendedDrain
    nmos AND ENID
}
nmos.OVL.33 {
    @ nmos.OVL.33: Illegal nmos device: nmos must not overlap areaid:seal
    nmos AND SEALID
}
nmos.OVL.34 {
    @ nmos.OVL.34: Illegal nmos device: nmos must not overlap v5
    nmos AND v5
}
nmos.OVL.35 {
    @ nmos.OVL.35: Illegal nmos device: nmos must not overlap v12
    nmos AND v12
}
nmos.OVL.36 {
    @ nmos.OVL.36: Illegal nmos device: nmos must not overlap v20
    nmos AND v20
}
nmos.OVL.37 {
    @ nmos.OVL.37: Illegal nmos device: nmos must not overlap poly:model
    nmos AND polyModel
}
exempt_sonos = ((nmos_1 AND COREID) AND ldntm) AND tunm
nmos_lvt = (((nmos_1 AND lvtn) NOT LVID) NOT thkox) NOT exempt_sonos
nmos_lvt.OVL.1 {
    @ nmos_lvt.OVL.1: Illegal nmos lvt device: nmos_lvt must not overlap pwbm
    nmos_lvt AND pwbm
}
nmos_lvt.OVL.2 {
    @ nmos_lvt.OVL.2: Illegal nmos lvt device: nmos_lvt must not overlap pwde
    nmos_lvt AND pwde
}
nmos_lvt.OVL.3 {
    @ nmos_lvt.OVL.3: Illegal nmos lvt device: nmos_lvt must not overlap nwell
    nmos_lvt AND nwell
}
nmos_lvt.OVL.4 {
    @ nmos_lvt.OVL.4: Illegal nmos lvt device: nmos_lvt must not overlap hvtp
    nmos_lvt AND hvtp
}
nmos_lvt.OVL.5 {
    @ nmos_lvt.OVL.5: Illegal nmos lvt device: nmos_lvt must not overlap tunm
    nmos_lvt AND tunm
}
nmos_lvt.OVL.6 {
    @ nmos_lvt.OVL.6: Illegal nmos lvt device: nmos_lvt must not overlap thkox
    nmos_lvt AND thkox
}
nmos_lvt.OVL.7 {
    @ nmos_lvt.OVL.7: Illegal nmos lvt device: nmos_lvt must not overlap rpm
    nmos_lvt AND rpm
}
nmos_lvt.OVL.8 {
    @ nmos_lvt.OVL.8: Illegal nmos lvt device: nmos_lvt must not overlap rrpm
    nmos_lvt AND rrpm
}
nmos_lvt.OVL.9 {
    @ nmos_lvt.OVL.9: Illegal nmos lvt device: nmos_lvt must not overlap urpm
    nmos_lvt AND urpm
}
nmos_lvt.OVL.10 {
    @ nmos_lvt.OVL.10: Illegal nmos lvt device: nmos_lvt must not overlap ldntm
    nmos_lvt AND ldntm
}
nmos_lvt.OVL.11 {
    @ nmos_lvt.OVL.11: Illegal nmos lvt device: nmos_lvt must not overlap npc
    nmos_lvt AND npc
}
nmos_lvt.OVL.12 {
    @ nmos_lvt.OVL.12: Illegal nmos lvt device: nmos_lvt must not overlap psdm
    nmos_lvt AND psdm
}
nmos_lvt.OVL.13 {
    @ nmos_lvt.OVL.13: Illegal nmos lvt device: nmos_lvt must not overlap nsm
    nmos_lvt AND nsm
}
nmos_lvt.OVL.14 {
    @ nmos_lvt.OVL.14: Illegal nmos lvt device: nmos_lvt must not overlap skip_pad
    nmos_lvt AND skip_pad
}
nmos_lvt.OVL.15 {
    @ nmos_lvt.OVL.15: Illegal nmos lvt device: nmos_lvt must not overlap fuse
    nmos_lvt AND fuse
}
nmos_lvt.OVL.16 {
    @ nmos_lvt.OVL.16: Illegal nmos lvt device: nmos_lvt must not overlap diff:res
    nmos_lvt AND diffres
}
nmos_lvt.OVL.17 {
    @ nmos_lvt.OVL.17: Illegal nmos lvt device: nmos_lvt must not overlap pwell:res
    nmos_lvt AND pwres
}
nmos_lvt.OVL.18 {
    @ nmos_lvt.OVL.18: Illegal nmos lvt device: nmos_lvt must not overlap poly:res
    nmos_lvt AND polyres
}
nmos_lvt.OVL.19 {
    @ nmos_lvt.OVL.19: Illegal nmos lvt device: nmos_lvt must not overlap li:res
    nmos_lvt AND lires
}
nmos_lvt.OVL.20 {
    @ nmos_lvt.OVL.20: Illegal nmos lvt device: nmos_lvt must not overlap skip_res
    nmos_lvt AND skip_res
}
nmos_lvt.OVL.21 {
    @ nmos_lvt.OVL.21: Illegal nmos lvt device: nmos_lvt must not overlap skip_res
    nmos_lvt AND skip_res
}
nmos_lvt.OVL.22 {
    @ nmos_lvt.OVL.22: Illegal nmos lvt device: nmos_lvt must not overlap skip_res
    nmos_lvt AND skip_res
}
nmos_lvt.OVL.23 {
    @ nmos_lvt.OVL.23: Illegal nmos lvt device: nmos_lvt must not overlap skip_res
    nmos_lvt AND skip_res
}
nmos_lvt.OVL.24 {
    @ nmos_lvt.OVL.24: Illegal nmos lvt device: nmos_lvt must not overlap skip_res
    nmos_lvt AND skip_res
}
nmos_lvt.OVL.25 {
    @ nmos_lvt.OVL.25: Illegal nmos lvt device: nmos_lvt must not overlap areaid:lvNative
    nmos_lvt AND LVID
}
nmos_lvt.OVL.26 {
    @ nmos_lvt.OVL.26: Illegal nmos lvt device: nmos_lvt must not overlap pnp
    nmos_lvt AND pnp
}
nmos_lvt.OVL.27 {
    @ nmos_lvt.OVL.27: Illegal nmos lvt device: nmos_lvt must not overlap npn
    nmos_lvt AND npn
}
nmos_lvt.OVL.28 {
    @ nmos_lvt.OVL.28: Illegal nmos lvt device: nmos_lvt must not overlap areaid:diode
    nmos_lvt AND DiodeID
}
nmos_lvt.OVL.29 {
    @ nmos_lvt.OVL.29: Illegal nmos lvt device: nmos_lvt must not overlap areaid:photo
    nmos_lvt AND PHdiodeID
}
nmos_lvt.OVL.30 {
    @ nmos_lvt.OVL.30: Illegal nmos lvt device: nmos_lvt must not overlap areaid:core
    nmos_lvt AND COREID
}
nmos_lvt.OVL.31 {
    @ nmos_lvt.OVL.31: Illegal nmos lvt device: nmos_lvt must not overlap areaid:esd
    nmos_lvt AND ESDID
}
nmos_lvt.OVL.32 {
    @ nmos_lvt.OVL.32: Illegal nmos lvt device: nmos_lvt must not overlap areaid:extendedDrain
    nmos_lvt AND ENID
}
nmos_lvt.OVL.33 {
    @ nmos_lvt.OVL.33: Illegal nmos lvt device: nmos_lvt must not overlap areaid:seal
    nmos_lvt AND SEALID
}
nmos_lvt.OVL.34 {
    @ nmos_lvt.OVL.34: Illegal nmos lvt device: nmos_lvt must not overlap v5
    nmos_lvt AND v5
}
nmos_lvt.OVL.35 {
    @ nmos_lvt.OVL.35: Illegal nmos lvt device: nmos_lvt must not overlap v12
    nmos_lvt AND v12
}
nmos_lvt.OVL.36 {
    @ nmos_lvt.OVL.36: Illegal nmos lvt device: nmos_lvt must not overlap v20
    nmos_lvt AND v20
}
nmos_lvt.OVL.37 {
    @ nmos_lvt.OVL.37: Illegal nmos lvt device: nmos_lvt must not overlap poly:model
    nmos_lvt AND polyModel
}
nmos_v5 = (nmos_1 AND (v5 AND thkox)) NOT (OR LVID lvtn ESDID)
nmos_v5.OVL.1 {
    @ nmos_v5.OVL.1: Illegal nmos_v5 device: nmos_v5 must not overlap pwbm
    nmos_v5 AND pwbm
}
nmos_v5.OVL.2 {
    @ nmos_v5.OVL.2: Illegal nmos_v5 device: nmos_v5 must not overlap pwde
    nmos_v5 AND pwde
}
nmos_v5.OVL.3 {
    @ nmos_v5.OVL.3: Illegal nmos_v5 device: nmos_v5 must not overlap nwell
    nmos_v5 AND nwell
}
nmos_v5.OVL.4 {
    @ nmos_v5.OVL.4: Illegal nmos_v5 device: nmos_v5 must not overlap hvtp
    nmos_v5 AND hvtp
}
nmos_v5.OVL.5 {
    @ nmos_v5.OVL.5: Illegal nmos_v5 device: nmos_v5 must not overlap lvtn
    nmos_v5 AND lvtn
}
nmos_v5.OVL.6 {
    @ nmos_v5.OVL.6: Illegal nmos_v5 device: nmos_v5 must not overlap tunm
    nmos_v5 AND tunm
}
nmos_v5.OVL.7 {
    @ nmos_v5.OVL.7: Illegal nmos_v5 device: nmos_v5 must not overlap rpm
    nmos_v5 AND rpm
}
nmos_v5.OVL.8 {
    @ nmos_v5.OVL.8: Illegal nmos_v5 device: nmos_v5 must not overlap rrpm
    nmos_v5 AND rrpm
}
nmos_v5.OVL.9 {
    @ nmos_v5.OVL.9: Illegal nmos_v5 device: nmos_v5 must not overlap urpm
    nmos_v5 AND urpm
}
nmos_v5.OVL.10 {
    @ nmos_v5.OVL.10: Illegal nmos_v5 device: nmos_v5 must not overlap ldntm
    nmos_v5 AND ldntm
}
nmos_v5.OVL.11 {
    @ nmos_v5.OVL.11: Illegal nmos_v5 device: nmos_v5 must not overlap npc
    nmos_v5 AND npc
}
nmos_v5.OVL.12 {
    @ nmos_v5.OVL.12: Illegal nmos_v5 device: nmos_v5 must not overlap psdm
    nmos_v5 AND psdm
}
nmos_v5.OVL.13 {
    @ nmos_v5.OVL.13: Illegal nmos_v5 device: nmos_v5 must not overlap nsm
    nmos_v5 AND nsm
}
nmos_v5.OVL.14 {
    @ nmos_v5.OVL.14: Illegal nmos_v5 device: nmos_v5 must not overlap skip_pad
    nmos_v5 AND skip_pad
}
nmos_v5.OVL.15 {
    @ nmos_v5.OVL.15: Illegal nmos_v5 device: nmos_v5 must not overlap fuse
    nmos_v5 AND fuse
}
nmos_v5.OVL.16 {
    @ nmos_v5.OVL.16: Illegal nmos_v5 device: nmos_v5 must not overlap diff:res
    nmos_v5 AND diffres
}
nmos_v5.OVL.17 {
    @ nmos_v5.OVL.17: Illegal nmos_v5 device: nmos_v5 must not overlap pwell:res
    nmos_v5 AND pwres
}
nmos_v5.OVL.18 {
    @ nmos_v5.OVL.18: Illegal nmos_v5 device: nmos_v5 must not overlap poly:res
    nmos_v5 AND polyres
}
nmos_v5.OVL.19 {
    @ nmos_v5.OVL.19: Illegal nmos_v5 device: nmos_v5 must not overlap li:res
    nmos_v5 AND lires
}
nmos_v5.OVL.20 {
    @ nmos_v5.OVL.20: Illegal nmos_v5 device: nmos_v5 must not overlap skip_res
    nmos_v5 AND skip_res
}
nmos_v5.OVL.21 {
    @ nmos_v5.OVL.21: Illegal nmos_v5 device: nmos_v5 must not overlap skip_res
    nmos_v5 AND skip_res
}
nmos_v5.OVL.22 {
    @ nmos_v5.OVL.22: Illegal nmos_v5 device: nmos_v5 must not overlap skip_res
    nmos_v5 AND skip_res
}
nmos_v5.OVL.23 {
    @ nmos_v5.OVL.23: Illegal nmos_v5 device: nmos_v5 must not overlap skip_res
    nmos_v5 AND skip_res
}
nmos_v5.OVL.24 {
    @ nmos_v5.OVL.24: Illegal nmos_v5 device: nmos_v5 must not overlap skip_res
    nmos_v5 AND skip_res
}
nmos_v5.OVL.25 {
    @ nmos_v5.OVL.25: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:lvNative
    nmos_v5 AND LVID
}
nmos_v5.OVL.26 {
    @ nmos_v5.OVL.26: Illegal nmos_v5 device: nmos_v5 must not overlap pnp
    nmos_v5 AND pnp
}
nmos_v5.OVL.27 {
    @ nmos_v5.OVL.27: Illegal nmos_v5 device: nmos_v5 must not overlap npn
    nmos_v5 AND npn
}
nmos_v5.OVL.28 {
    @ nmos_v5.OVL.28: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:diode
    nmos_v5 AND DiodeID
}
nmos_v5.OVL.29 {
    @ nmos_v5.OVL.29: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:photo
    nmos_v5 AND PHdiodeID
}
nmos_v5.OVL.30 {
    @ nmos_v5.OVL.30: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:core
    nmos_v5 AND COREID
}
nmos_v5.OVL.31 {
    @ nmos_v5.OVL.31: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:extendedDrain
    nmos_v5 AND ENID
}
nmos_v5.OVL.32 {
    @ nmos_v5.OVL.32: Illegal nmos_v5 device: nmos_v5 must not overlap areaid:seal
    nmos_v5 AND SEALID
}
nmos_v5.OVL.33 {
    @ nmos_v5.OVL.33: Illegal nmos_v5 device: nmos_v5 must not overlap v12
    nmos_v5 AND v12
}
nmos_v5.OVL.34 {
    @ nmos_v5.OVL.34: Illegal nmos_v5 device: nmos_v5 must not overlap v20
    nmos_v5 AND v20
}
nmos_v5.OVL.35 {
    @ nmos_v5.OVL.35: Illegal nmos_v5 device: nmos_v5 must not overlap poly:model
    nmos_v5 AND polyModel
}
nmos_nat_v3 = (nmos_1 AND ((v5 AND thkox) AND LVID)) AND lvtn
nmos_nat_v3.OVL.1 {
    @ nmos_nat_v3.OVL.1: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap pwbm
    nmos_nat_v3 AND pwbm
}
nmos_nat_v3.OVL.2 {
    @ nmos_nat_v3.OVL.2: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap pwde
    nmos_nat_v3 AND pwde
}
nmos_nat_v3.OVL.3 {
    @ nmos_nat_v3.OVL.3: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap nwell
    nmos_nat_v3 AND nwell
}
nmos_nat_v3.OVL.4 {
    @ nmos_nat_v3.OVL.4: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap hvtp
    nmos_nat_v3 AND hvtp
}
nmos_nat_v3.OVL.5 {
    @ nmos_nat_v3.OVL.5: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap tunm
    nmos_nat_v3 AND tunm
}
nmos_nat_v3.OVL.6 {
    @ nmos_nat_v3.OVL.6: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap rpm
    nmos_nat_v3 AND rpm
}
nmos_nat_v3.OVL.7 {
    @ nmos_nat_v3.OVL.7: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap rrpm
    nmos_nat_v3 AND rrpm
}
nmos_nat_v3.OVL.8 {
    @ nmos_nat_v3.OVL.8: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap urpm
    nmos_nat_v3 AND urpm
}
nmos_nat_v3.OVL.9 {
    @ nmos_nat_v3.OVL.9: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap ldntm
    nmos_nat_v3 AND ldntm
}
nmos_nat_v3.OVL.10 {
    @ nmos_nat_v3.OVL.10: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap npc
    nmos_nat_v3 AND npc
}
nmos_nat_v3.OVL.11 {
    @ nmos_nat_v3.OVL.11: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap psdm
    nmos_nat_v3 AND psdm
}
nmos_nat_v3.OVL.12 {
    @ nmos_nat_v3.OVL.12: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap nsm
    nmos_nat_v3 AND nsm
}
nmos_nat_v3.OVL.13 {
    @ nmos_nat_v3.OVL.13: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_pad
    nmos_nat_v3 AND skip_pad
}
nmos_nat_v3.OVL.14 {
    @ nmos_nat_v3.OVL.14: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap fuse
    nmos_nat_v3 AND fuse
}
nmos_nat_v3.OVL.15 {
    @ nmos_nat_v3.OVL.15: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap diff:res
    nmos_nat_v3 AND diffres
}
nmos_nat_v3.OVL.16 {
    @ nmos_nat_v3.OVL.16: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap pwell:res
    nmos_nat_v3 AND pwres
}
nmos_nat_v3.OVL.17 {
    @ nmos_nat_v3.OVL.17: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap poly:res
    nmos_nat_v3 AND polyres
}
nmos_nat_v3.OVL.18 {
    @ nmos_nat_v3.OVL.18: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap li:res
    nmos_nat_v3 AND lires
}
nmos_nat_v3.OVL.19 {
    @ nmos_nat_v3.OVL.19: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_res
    nmos_nat_v3 AND skip_res
}
nmos_nat_v3.OVL.20 {
    @ nmos_nat_v3.OVL.20: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_res
    nmos_nat_v3 AND skip_res
}
nmos_nat_v3.OVL.21 {
    @ nmos_nat_v3.OVL.21: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_res
    nmos_nat_v3 AND skip_res
}
nmos_nat_v3.OVL.22 {
    @ nmos_nat_v3.OVL.22: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_res
    nmos_nat_v3 AND skip_res
}
nmos_nat_v3.OVL.23 {
    @ nmos_nat_v3.OVL.23: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap skip_res
    nmos_nat_v3 AND skip_res
}
nmos_nat_v3.OVL.24 {
    @ nmos_nat_v3.OVL.24: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap pnp
    nmos_nat_v3 AND pnp
}
nmos_nat_v3.OVL.25 {
    @ nmos_nat_v3.OVL.25: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap npn
    nmos_nat_v3 AND npn
}
nmos_nat_v3.OVL.26 {
    @ nmos_nat_v3.OVL.26: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:diode
    nmos_nat_v3 AND DiodeID
}
nmos_nat_v3.OVL.27 {
    @ nmos_nat_v3.OVL.27: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:photo
    nmos_nat_v3 AND PHdiodeID
}
nmos_nat_v3.OVL.28 {
    @ nmos_nat_v3.OVL.28: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:core
    nmos_nat_v3 AND COREID
}
nmos_nat_v3.OVL.29 {
    @ nmos_nat_v3.OVL.29: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:extendedDrain
    nmos_nat_v3 AND ENID
}
nmos_nat_v3.OVL.30 {
    @ nmos_nat_v3.OVL.30: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:seal
    nmos_nat_v3 AND SEALID
}
nmos_nat_v3.OVL.31 {
    @ nmos_nat_v3.OVL.31: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap v12
    nmos_nat_v3 AND v12
}
nmos_nat_v3.OVL.32 {
    @ nmos_nat_v3.OVL.32: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap v20
    nmos_nat_v3 AND v20
}
nmos_nat_v3.OVL.33 {
    @ nmos_nat_v3.OVL.33: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap areaid:esd
    nmos_nat_v3 AND ESDID
}
nmos_nat_v3.OVL.34 {
    @ nmos_nat_v3.OVL.34: Illegal nmos_nat_v3 device: nmos_nat_v3 must not overlap poly:model
    nmos_nat_v3 AND polyModel
}
nmos_nat_v5 = ((nmos_1 AND ((v5 AND thkox) NOT LVID)) AND lvtn) NOT ESDID
nmos_nat_v5.OVL.1 {
    @ nmos_nat_v5.OVL.1: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap pwbm
    nmos_nat_v5 AND pwbm
}
nmos_nat_v5.OVL.2 {
    @ nmos_nat_v5.OVL.2: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap pwde
    nmos_nat_v5 AND pwde
}
nmos_nat_v5.OVL.3 {
    @ nmos_nat_v5.OVL.3: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap nwell
    nmos_nat_v5 AND nwell
}
nmos_nat_v5.OVL.4 {
    @ nmos_nat_v5.OVL.4: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap hvtp
    nmos_nat_v5 AND hvtp
}
nmos_nat_v5.OVL.5 {
    @ nmos_nat_v5.OVL.5: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap tunm
    nmos_nat_v5 AND tunm
}
nmos_nat_v5.OVL.6 {
    @ nmos_nat_v5.OVL.6: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap rpm
    nmos_nat_v5 AND rpm
}
nmos_nat_v5.OVL.7 {
    @ nmos_nat_v5.OVL.7: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap rrpm
    nmos_nat_v5 AND rrpm
}
nmos_nat_v5.OVL.8 {
    @ nmos_nat_v5.OVL.8: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap urpm
    nmos_nat_v5 AND urpm
}
nmos_nat_v5.OVL.9 {
    @ nmos_nat_v5.OVL.9: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap ldntm
    nmos_nat_v5 AND ldntm
}
nmos_nat_v5.OVL.10 {
    @ nmos_nat_v5.OVL.10: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap npc
    nmos_nat_v5 AND npc
}
nmos_nat_v5.OVL.11 {
    @ nmos_nat_v5.OVL.11: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap psdm
    nmos_nat_v5 AND psdm
}
nmos_nat_v5.OVL.12 {
    @ nmos_nat_v5.OVL.12: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap nsm
    nmos_nat_v5 AND nsm
}
nmos_nat_v5.OVL.13 {
    @ nmos_nat_v5.OVL.13: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_pad
    nmos_nat_v5 AND skip_pad
}
nmos_nat_v5.OVL.14 {
    @ nmos_nat_v5.OVL.14: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap fuse
    nmos_nat_v5 AND fuse
}
nmos_nat_v5.OVL.15 {
    @ nmos_nat_v5.OVL.15: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap diff:res
    nmos_nat_v5 AND diffres
}
nmos_nat_v5.OVL.16 {
    @ nmos_nat_v5.OVL.16: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap pwell:res
    nmos_nat_v5 AND pwres
}
nmos_nat_v5.OVL.17 {
    @ nmos_nat_v5.OVL.17: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap poly:res
    nmos_nat_v5 AND polyres
}
nmos_nat_v5.OVL.18 {
    @ nmos_nat_v5.OVL.18: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap li:res
    nmos_nat_v5 AND lires
}
nmos_nat_v5.OVL.19 {
    @ nmos_nat_v5.OVL.19: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_res
    nmos_nat_v5 AND skip_res
}
nmos_nat_v5.OVL.20 {
    @ nmos_nat_v5.OVL.20: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_res
    nmos_nat_v5 AND skip_res
}
nmos_nat_v5.OVL.21 {
    @ nmos_nat_v5.OVL.21: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_res
    nmos_nat_v5 AND skip_res
}
nmos_nat_v5.OVL.22 {
    @ nmos_nat_v5.OVL.22: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_res
    nmos_nat_v5 AND skip_res
}
nmos_nat_v5.OVL.23 {
    @ nmos_nat_v5.OVL.23: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap skip_res
    nmos_nat_v5 AND skip_res
}
nmos_nat_v5.OVL.24 {
    @ nmos_nat_v5.OVL.24: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap pnp
    nmos_nat_v5 AND pnp
}
nmos_nat_v5.OVL.25 {
    @ nmos_nat_v5.OVL.25: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap npn
    nmos_nat_v5 AND npn
}
nmos_nat_v5.OVL.26 {
    @ nmos_nat_v5.OVL.26: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:diode
    nmos_nat_v5 AND DiodeID
}
nmos_nat_v5.OVL.27 {
    @ nmos_nat_v5.OVL.27: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:photo
    nmos_nat_v5 AND PHdiodeID
}
nmos_nat_v5.OVL.28 {
    @ nmos_nat_v5.OVL.28: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:core
    nmos_nat_v5 AND COREID
}
nmos_nat_v5.OVL.29 {
    @ nmos_nat_v5.OVL.29: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:extendedDrain
    nmos_nat_v5 AND ENID
}
nmos_nat_v5.OVL.30 {
    @ nmos_nat_v5.OVL.30: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:seal
    nmos_nat_v5 AND SEALID
}
nmos_nat_v5.OVL.31 {
    @ nmos_nat_v5.OVL.31: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap v12
    nmos_nat_v5 AND v12
}
nmos_nat_v5.OVL.32 {
    @ nmos_nat_v5.OVL.32: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap v20
    nmos_nat_v5 AND v20
}
nmos_nat_v5.OVL.33 {
    @ nmos_nat_v5.OVL.33: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap areaid:esd
    nmos_nat_v5 AND ESDID
}
nmos_nat_v5.OVL.34 {
    @ nmos_nat_v5.OVL.34: Illegal nmos_nat_v5 device: nmos_nat_v5 must not overlap poly:model
    nmos_nat_v5 AND polyModel
}
nmos_de_v12 = ((((gate and nsdm) AND v12) AND ENID) NOT nwell) AND thkox
nmos_de_v12.OVL.1 {
    @ nmos_de_v12.OVL.1: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap pwbm
    nmos_de_v12 AND pwbm
}
nmos_de_v12.OVL.2 {
    @ nmos_de_v12.OVL.2: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap pwde
    nmos_de_v12 AND pwde
}
nmos_de_v12.OVL.3 {
    @ nmos_de_v12.OVL.3: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap hvtp
    nmos_de_v12 AND hvtp
}
nmos_de_v12.OVL.4 {
    @ nmos_de_v12.OVL.4: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap lvtn
    nmos_de_v12 AND lvtn
}
nmos_de_v12.OVL.5 {
    @ nmos_de_v12.OVL.5: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap tunm
    nmos_de_v12 AND tunm
}
nmos_de_v12.OVL.6 {
    @ nmos_de_v12.OVL.6: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap rpm
    nmos_de_v12 AND rpm
}
nmos_de_v12.OVL.7 {
    @ nmos_de_v12.OVL.7: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap rrpm
    nmos_de_v12 AND rrpm
}
nmos_de_v12.OVL.8 {
    @ nmos_de_v12.OVL.8: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap urpm
    nmos_de_v12 AND urpm
}
nmos_de_v12.OVL.9 {
    @ nmos_de_v12.OVL.9: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap ldntm
    nmos_de_v12 AND ldntm
}
nmos_de_v12.OVL.10 {
    @ nmos_de_v12.OVL.10: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap npc
    nmos_de_v12 AND npc
}
nmos_de_v12.OVL.11 {
    @ nmos_de_v12.OVL.11: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap psdm
    nmos_de_v12 AND psdm
}
nmos_de_v12.OVL.12 {
    @ nmos_de_v12.OVL.12: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap nsm
    nmos_de_v12 AND nsm
}
nmos_de_v12.OVL.13 {
    @ nmos_de_v12.OVL.13: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_pad
    nmos_de_v12 AND skip_pad
}
nmos_de_v12.OVL.14 {
    @ nmos_de_v12.OVL.14: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap fuse
    nmos_de_v12 AND fuse
}
nmos_de_v12.OVL.15 {
    @ nmos_de_v12.OVL.15: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap diff:res
    nmos_de_v12 AND diffres
}
nmos_de_v12.OVL.16 {
    @ nmos_de_v12.OVL.16: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap pwell:res
    nmos_de_v12 AND pwres
}
nmos_de_v12.OVL.17 {
    @ nmos_de_v12.OVL.17: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap poly:res
    nmos_de_v12 AND polyres
}
nmos_de_v12.OVL.18 {
    @ nmos_de_v12.OVL.18: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap li:res
    nmos_de_v12 AND lires
}
nmos_de_v12.OVL.19 {
    @ nmos_de_v12.OVL.19: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_res
    nmos_de_v12 AND skip_res
}
nmos_de_v12.OVL.20 {
    @ nmos_de_v12.OVL.20: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_res
    nmos_de_v12 AND skip_res
}
nmos_de_v12.OVL.21 {
    @ nmos_de_v12.OVL.21: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_res
    nmos_de_v12 AND skip_res
}
nmos_de_v12.OVL.22 {
    @ nmos_de_v12.OVL.22: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_res
    nmos_de_v12 AND skip_res
}
nmos_de_v12.OVL.23 {
    @ nmos_de_v12.OVL.23: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap skip_res
    nmos_de_v12 AND skip_res
}
nmos_de_v12.OVL.24 {
    @ nmos_de_v12.OVL.24: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:lvNative
    nmos_de_v12 AND LVID
}
nmos_de_v12.OVL.25 {
    @ nmos_de_v12.OVL.25: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap pnp
    nmos_de_v12 AND pnp
}
nmos_de_v12.OVL.26 {
    @ nmos_de_v12.OVL.26: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap npn
    nmos_de_v12 AND npn
}
nmos_de_v12.OVL.27 {
    @ nmos_de_v12.OVL.27: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:diode
    nmos_de_v12 AND DiodeID
}
nmos_de_v12.OVL.28 {
    @ nmos_de_v12.OVL.28: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:photo
    nmos_de_v12 AND PHdiodeID
}
nmos_de_v12.OVL.29 {
    @ nmos_de_v12.OVL.29: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:core
    nmos_de_v12 AND COREID
}
nmos_de_v12.OVL.30 {
    @ nmos_de_v12.OVL.30: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:seal
    nmos_de_v12 AND SEALID
}
nmos_de_v12.OVL.31 {
    @ nmos_de_v12.OVL.31: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap v5
    nmos_de_v12 AND v5
}
nmos_de_v12.OVL.32 {
    @ nmos_de_v12.OVL.32: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap v20
    nmos_de_v12 AND v20
}
nmos_de_v12.OVL.33 {
    @ nmos_de_v12.OVL.33: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap dnwell
    nmos_de_v12 AND dnwell
}
nmos_de_v12.OVL.34 {
    @ nmos_de_v12.OVL.34: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap areaid:esd
    nmos_de_v12 AND ESDID
}
nmos_de_v12.OVL.35 {
    @ nmos_de_v12.OVL.35: Illegal nmos_de_v12 device: nmos_de_v12 must not overlap poly:model
    nmos_de_v12 AND polyModel
}
nmos_de_v20 = ngate_v20 NOT (poly INTERACT (OR ngate_v20_nat ngate_v20_zvt ngate_v20_iso_rec))
nmos_de_v20.OVL.1 {
    @ nmos_de_v20.OVL.1: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap pwde
    nmos_de_v20 AND pwde
}
nmos_de_v20.OVL.2 {
    @ nmos_de_v20.OVL.2: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap hvtp
    nmos_de_v20 AND hvtp
}
nmos_de_v20.OVL.3 {
    @ nmos_de_v20.OVL.3: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap tunm
    nmos_de_v20 AND tunm
}
nmos_de_v20.OVL.4 {
    @ nmos_de_v20.OVL.4: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap rpm
    nmos_de_v20 AND rpm
}
nmos_de_v20.OVL.5 {
    @ nmos_de_v20.OVL.5: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap rrpm
    nmos_de_v20 AND rrpm
}
nmos_de_v20.OVL.6 {
    @ nmos_de_v20.OVL.6: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap urpm
    nmos_de_v20 AND urpm
}
nmos_de_v20.OVL.7 {
    @ nmos_de_v20.OVL.7: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap ldntm
    nmos_de_v20 AND ldntm
}
nmos_de_v20.OVL.8 {
    @ nmos_de_v20.OVL.8: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap npc
    nmos_de_v20 AND npc
}
nmos_de_v20.OVL.9 {
    @ nmos_de_v20.OVL.9: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap psdm
    nmos_de_v20 AND psdm
}
nmos_de_v20.OVL.10 {
    @ nmos_de_v20.OVL.10: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap nsm
    nmos_de_v20 AND nsm
}
nmos_de_v20.OVL.11 {
    @ nmos_de_v20.OVL.11: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_pad
    nmos_de_v20 AND skip_pad
}
nmos_de_v20.OVL.12 {
    @ nmos_de_v20.OVL.12: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap fuse
    nmos_de_v20 AND fuse
}
nmos_de_v20.OVL.13 {
    @ nmos_de_v20.OVL.13: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap diff:res
    nmos_de_v20 AND diffres
}
nmos_de_v20.OVL.14 {
    @ nmos_de_v20.OVL.14: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap pwell:res
    nmos_de_v20 AND pwres
}
nmos_de_v20.OVL.15 {
    @ nmos_de_v20.OVL.15: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap poly:res
    nmos_de_v20 AND polyres
}
nmos_de_v20.OVL.16 {
    @ nmos_de_v20.OVL.16: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap li:res
    nmos_de_v20 AND lires
}
nmos_de_v20.OVL.17 {
    @ nmos_de_v20.OVL.17: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_res
    nmos_de_v20 AND skip_res
}
nmos_de_v20.OVL.18 {
    @ nmos_de_v20.OVL.18: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_res
    nmos_de_v20 AND skip_res
}
nmos_de_v20.OVL.19 {
    @ nmos_de_v20.OVL.19: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_res
    nmos_de_v20 AND skip_res
}
nmos_de_v20.OVL.20 {
    @ nmos_de_v20.OVL.20: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_res
    nmos_de_v20 AND skip_res
}
nmos_de_v20.OVL.21 {
    @ nmos_de_v20.OVL.21: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap skip_res
    nmos_de_v20 AND skip_res
}
nmos_de_v20.OVL.22 {
    @ nmos_de_v20.OVL.22: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:lvNative
    nmos_de_v20 AND LVID
}
nmos_de_v20.OVL.23 {
    @ nmos_de_v20.OVL.23: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap pnp
    nmos_de_v20 AND pnp
}
nmos_de_v20.OVL.24 {
    @ nmos_de_v20.OVL.24: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap npn
    nmos_de_v20 AND npn
}
nmos_de_v20.OVL.25 {
    @ nmos_de_v20.OVL.25: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:diode
    nmos_de_v20 AND DiodeID
}
nmos_de_v20.OVL.26 {
    @ nmos_de_v20.OVL.26: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:photo
    nmos_de_v20 AND PHdiodeID
}
nmos_de_v20.OVL.27 {
    @ nmos_de_v20.OVL.27: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:core
    nmos_de_v20 AND COREID
}
nmos_de_v20.OVL.28 {
    @ nmos_de_v20.OVL.28: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:esd
    nmos_de_v20 AND ESDID
}
nmos_de_v20.OVL.29 {
    @ nmos_de_v20.OVL.29: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap areaid:seal
    nmos_de_v20 AND SEALID
}
nmos_de_v20.OVL.30 {
    @ nmos_de_v20.OVL.30: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap v5
    nmos_de_v20 AND v5
}
nmos_de_v20.OVL.31 {
    @ nmos_de_v20.OVL.31: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap v12
    nmos_de_v20 AND v12
}
nmos_de_v20.OVL.32 {
    @ nmos_de_v20.OVL.32: Illegal nmos_de_v20 device: nmos_de_v20 must not overlap poly:model
    nmos_de_v20 AND polyModel
}
nmos_de_iso_v20 = (((((gate and nsdm) AND v20) AND ENID) NOT nwell) AND thkox) INTERACT (HOLES pwbm)
nmos_de_iso_v20.OVL.1 {
    @ nmos_de_iso_v20.OVL.1: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap pwde
    nmos_de_iso_v20 AND pwde
}
nmos_de_iso_v20.OVL.2 {
    @ nmos_de_iso_v20.OVL.2: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap hvtp
    nmos_de_iso_v20 AND hvtp
}
nmos_de_iso_v20.OVL.3 {
    @ nmos_de_iso_v20.OVL.3: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap tunm
    nmos_de_iso_v20 AND tunm
}
nmos_de_iso_v20.OVL.4 {
    @ nmos_de_iso_v20.OVL.4: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap rpm
    nmos_de_iso_v20 AND rpm
}
nmos_de_iso_v20.OVL.5 {
    @ nmos_de_iso_v20.OVL.5: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap rrpm
    nmos_de_iso_v20 AND rrpm
}
nmos_de_iso_v20.OVL.6 {
    @ nmos_de_iso_v20.OVL.6: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap urpm
    nmos_de_iso_v20 AND urpm
}
nmos_de_iso_v20.OVL.7 {
    @ nmos_de_iso_v20.OVL.7: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap ldntm
    nmos_de_iso_v20 AND ldntm
}
nmos_de_iso_v20.OVL.8 {
    @ nmos_de_iso_v20.OVL.8: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap npc
    nmos_de_iso_v20 AND npc
}
nmos_de_iso_v20.OVL.9 {
    @ nmos_de_iso_v20.OVL.9: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap psdm
    nmos_de_iso_v20 AND psdm
}
nmos_de_iso_v20.OVL.10 {
    @ nmos_de_iso_v20.OVL.10: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap nsm
    nmos_de_iso_v20 AND nsm
}
nmos_de_iso_v20.OVL.11 {
    @ nmos_de_iso_v20.OVL.11: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_pad
    nmos_de_iso_v20 AND skip_pad
}
nmos_de_iso_v20.OVL.12 {
    @ nmos_de_iso_v20.OVL.12: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap fuse
    nmos_de_iso_v20 AND fuse
}
nmos_de_iso_v20.OVL.13 {
    @ nmos_de_iso_v20.OVL.13: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap diff:res
    nmos_de_iso_v20 AND diffres
}
nmos_de_iso_v20.OVL.14 {
    @ nmos_de_iso_v20.OVL.14: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap pwell:res
    nmos_de_iso_v20 AND pwres
}
nmos_de_iso_v20.OVL.15 {
    @ nmos_de_iso_v20.OVL.15: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap poly:res
    nmos_de_iso_v20 AND polyres
}
nmos_de_iso_v20.OVL.16 {
    @ nmos_de_iso_v20.OVL.16: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap li:res
    nmos_de_iso_v20 AND lires
}
nmos_de_iso_v20.OVL.17 {
    @ nmos_de_iso_v20.OVL.17: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_res
    nmos_de_iso_v20 AND skip_res
}
nmos_de_iso_v20.OVL.18 {
    @ nmos_de_iso_v20.OVL.18: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_res
    nmos_de_iso_v20 AND skip_res
}
nmos_de_iso_v20.OVL.19 {
    @ nmos_de_iso_v20.OVL.19: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_res
    nmos_de_iso_v20 AND skip_res
}
nmos_de_iso_v20.OVL.20 {
    @ nmos_de_iso_v20.OVL.20: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_res
    nmos_de_iso_v20 AND skip_res
}
nmos_de_iso_v20.OVL.21 {
    @ nmos_de_iso_v20.OVL.21: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap skip_res
    nmos_de_iso_v20 AND skip_res
}
nmos_de_iso_v20.OVL.22 {
    @ nmos_de_iso_v20.OVL.22: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:lvNative
    nmos_de_iso_v20 AND LVID
}
nmos_de_iso_v20.OVL.23 {
    @ nmos_de_iso_v20.OVL.23: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap pnp
    nmos_de_iso_v20 AND pnp
}
nmos_de_iso_v20.OVL.24 {
    @ nmos_de_iso_v20.OVL.24: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap npn
    nmos_de_iso_v20 AND npn
}
nmos_de_iso_v20.OVL.25 {
    @ nmos_de_iso_v20.OVL.25: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:diode
    nmos_de_iso_v20 AND DiodeID
}
nmos_de_iso_v20.OVL.26 {
    @ nmos_de_iso_v20.OVL.26: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:photo
    nmos_de_iso_v20 AND PHdiodeID
}
nmos_de_iso_v20.OVL.27 {
    @ nmos_de_iso_v20.OVL.27: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:core
    nmos_de_iso_v20 AND COREID
}
nmos_de_iso_v20.OVL.28 {
    @ nmos_de_iso_v20.OVL.28: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:esd
    nmos_de_iso_v20 AND ESDID
}
nmos_de_iso_v20.OVL.29 {
    @ nmos_de_iso_v20.OVL.29: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap areaid:seal
    nmos_de_iso_v20 AND SEALID
}
nmos_de_iso_v20.OVL.30 {
    @ nmos_de_iso_v20.OVL.30: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap v5
    nmos_de_iso_v20 AND v5
}
nmos_de_iso_v20.OVL.31 {
    @ nmos_de_iso_v20.OVL.31: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap v12
    nmos_de_iso_v20 AND v12
}
nmos_de_iso_v20.OVL.32 {
    @ nmos_de_iso_v20.OVL.32: Illegal nmos_de_iso_v20 device: nmos_de_iso_v20 must not overlap poly:model
    nmos_de_iso_v20 AND polyModel
}
nmos_de_nat_v20 = ((lvtn ENCLOSE nsdm) AND ngate_v20) NOT pwbm
nmos_de_nat_v20.OVL.1 {
    @ nmos_de_nat_v20.OVL.1: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap pwde
    nmos_de_nat_v20 AND pwde
}
nmos_de_nat_v20.OVL.2 {
    @ nmos_de_nat_v20.OVL.2: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap hvtp
    nmos_de_nat_v20 AND hvtp
}
nmos_de_nat_v20.OVL.3 {
    @ nmos_de_nat_v20.OVL.3: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap tunm
    nmos_de_nat_v20 AND tunm
}
nmos_de_nat_v20.OVL.4 {
    @ nmos_de_nat_v20.OVL.4: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap rpm
    nmos_de_nat_v20 AND rpm
}
nmos_de_nat_v20.OVL.5 {
    @ nmos_de_nat_v20.OVL.5: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap rrpm
    nmos_de_nat_v20 AND rrpm
}
nmos_de_nat_v20.OVL.6 {
    @ nmos_de_nat_v20.OVL.6: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap urpm
    nmos_de_nat_v20 AND urpm
}
nmos_de_nat_v20.OVL.7 {
    @ nmos_de_nat_v20.OVL.7: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap ldntm
    nmos_de_nat_v20 AND ldntm
}
nmos_de_nat_v20.OVL.8 {
    @ nmos_de_nat_v20.OVL.8: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap npc
    nmos_de_nat_v20 AND npc
}
nmos_de_nat_v20.OVL.9 {
    @ nmos_de_nat_v20.OVL.9: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap psdm
    nmos_de_nat_v20 AND psdm
}
nmos_de_nat_v20.OVL.10 {
    @ nmos_de_nat_v20.OVL.10: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap nsm
    nmos_de_nat_v20 AND nsm
}
nmos_de_nat_v20.OVL.11 {
    @ nmos_de_nat_v20.OVL.11: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_pad
    nmos_de_nat_v20 AND skip_pad
}
nmos_de_nat_v20.OVL.12 {
    @ nmos_de_nat_v20.OVL.12: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap fuse
    nmos_de_nat_v20 AND fuse
}
nmos_de_nat_v20.OVL.13 {
    @ nmos_de_nat_v20.OVL.13: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap diff:res
    nmos_de_nat_v20 AND diffres
}
nmos_de_nat_v20.OVL.14 {
    @ nmos_de_nat_v20.OVL.14: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap pwell:res
    nmos_de_nat_v20 AND pwres
}
nmos_de_nat_v20.OVL.15 {
    @ nmos_de_nat_v20.OVL.15: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap poly:res
    nmos_de_nat_v20 AND polyres
}
nmos_de_nat_v20.OVL.16 {
    @ nmos_de_nat_v20.OVL.16: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap li:res
    nmos_de_nat_v20 AND lires
}
nmos_de_nat_v20.OVL.17 {
    @ nmos_de_nat_v20.OVL.17: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_res
    nmos_de_nat_v20 AND skip_res
}
nmos_de_nat_v20.OVL.18 {
    @ nmos_de_nat_v20.OVL.18: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_res
    nmos_de_nat_v20 AND skip_res
}
nmos_de_nat_v20.OVL.19 {
    @ nmos_de_nat_v20.OVL.19: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_res
    nmos_de_nat_v20 AND skip_res
}
nmos_de_nat_v20.OVL.20 {
    @ nmos_de_nat_v20.OVL.20: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_res
    nmos_de_nat_v20 AND skip_res
}
nmos_de_nat_v20.OVL.21 {
    @ nmos_de_nat_v20.OVL.21: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap skip_res
    nmos_de_nat_v20 AND skip_res
}
nmos_de_nat_v20.OVL.22 {
    @ nmos_de_nat_v20.OVL.22: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:lvNative
    nmos_de_nat_v20 AND LVID
}
nmos_de_nat_v20.OVL.23 {
    @ nmos_de_nat_v20.OVL.23: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap pnp
    nmos_de_nat_v20 AND pnp
}
nmos_de_nat_v20.OVL.24 {
    @ nmos_de_nat_v20.OVL.24: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap npn
    nmos_de_nat_v20 AND npn
}
nmos_de_nat_v20.OVL.25 {
    @ nmos_de_nat_v20.OVL.25: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:diode
    nmos_de_nat_v20 AND DiodeID
}
nmos_de_nat_v20.OVL.26 {
    @ nmos_de_nat_v20.OVL.26: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:photo
    nmos_de_nat_v20 AND PHdiodeID
}
nmos_de_nat_v20.OVL.27 {
    @ nmos_de_nat_v20.OVL.27: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:core
    nmos_de_nat_v20 AND COREID
}
nmos_de_nat_v20.OVL.28 {
    @ nmos_de_nat_v20.OVL.28: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:esd
    nmos_de_nat_v20 AND ESDID
}
nmos_de_nat_v20.OVL.29 {
    @ nmos_de_nat_v20.OVL.29: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap areaid:seal
    nmos_de_nat_v20 AND SEALID
}
nmos_de_nat_v20.OVL.30 {
    @ nmos_de_nat_v20.OVL.30: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap v5
    nmos_de_nat_v20 AND v5
}
nmos_de_nat_v20.OVL.31 {
    @ nmos_de_nat_v20.OVL.31: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap v12
    nmos_de_nat_v20 AND v12
}
nmos_de_nat_v20.OVL.32 {
    @ nmos_de_nat_v20.OVL.32: Illegal nmos_de_nat_v20 device: nmos_de_nat_v20 must not overlap poly:model
    nmos_de_nat_v20 AND polyModel
}
nmos_de_zvt_v20 = (((lvtn CUT nsdm) NOT (lvtn ENCLOSE nsdm)) AND ngate_v20) NOT (OR ngate_v20_iso_rec ngate_v20_nat)
nmos_de_zvt_v20.OVL.1 {
    @ nmos_de_zvt_v20.OVL.1: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap pwde
    nmos_de_zvt_v20 AND pwde
}
nmos_de_zvt_v20.OVL.2 {
    @ nmos_de_zvt_v20.OVL.2: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap hvtp
    nmos_de_zvt_v20 AND hvtp
}
nmos_de_zvt_v20.OVL.3 {
    @ nmos_de_zvt_v20.OVL.3: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap tunm
    nmos_de_zvt_v20 AND tunm
}
nmos_de_zvt_v20.OVL.4 {
    @ nmos_de_zvt_v20.OVL.4: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap rpm
    nmos_de_zvt_v20 AND rpm
}
nmos_de_zvt_v20.OVL.5 {
    @ nmos_de_zvt_v20.OVL.5: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap rrpm
    nmos_de_zvt_v20 AND rrpm
}
nmos_de_zvt_v20.OVL.6 {
    @ nmos_de_zvt_v20.OVL.6: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap urpm
    nmos_de_zvt_v20 AND urpm
}
nmos_de_zvt_v20.OVL.7 {
    @ nmos_de_zvt_v20.OVL.7: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap ldntm
    nmos_de_zvt_v20 AND ldntm
}
nmos_de_zvt_v20.OVL.8 {
    @ nmos_de_zvt_v20.OVL.8: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap npc
    nmos_de_zvt_v20 AND npc
}
nmos_de_zvt_v20.OVL.9 {
    @ nmos_de_zvt_v20.OVL.9: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap psdm
    nmos_de_zvt_v20 AND psdm
}
nmos_de_zvt_v20.OVL.10 {
    @ nmos_de_zvt_v20.OVL.10: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap nsm
    nmos_de_zvt_v20 AND nsm
}
nmos_de_zvt_v20.OVL.11 {
    @ nmos_de_zvt_v20.OVL.11: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_pad
    nmos_de_zvt_v20 AND skip_pad
}
nmos_de_zvt_v20.OVL.12 {
    @ nmos_de_zvt_v20.OVL.12: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap fuse
    nmos_de_zvt_v20 AND fuse
}
nmos_de_zvt_v20.OVL.13 {
    @ nmos_de_zvt_v20.OVL.13: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap diff:res
    nmos_de_zvt_v20 AND diffres
}
nmos_de_zvt_v20.OVL.14 {
    @ nmos_de_zvt_v20.OVL.14: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap pwell:res
    nmos_de_zvt_v20 AND pwres
}
nmos_de_zvt_v20.OVL.15 {
    @ nmos_de_zvt_v20.OVL.15: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap poly:res
    nmos_de_zvt_v20 AND polyres
}
nmos_de_zvt_v20.OVL.16 {
    @ nmos_de_zvt_v20.OVL.16: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap li:res
    nmos_de_zvt_v20 AND lires
}
nmos_de_zvt_v20.OVL.17 {
    @ nmos_de_zvt_v20.OVL.17: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_res
    nmos_de_zvt_v20 AND skip_res
}
nmos_de_zvt_v20.OVL.18 {
    @ nmos_de_zvt_v20.OVL.18: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_res
    nmos_de_zvt_v20 AND skip_res
}
nmos_de_zvt_v20.OVL.19 {
    @ nmos_de_zvt_v20.OVL.19: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_res
    nmos_de_zvt_v20 AND skip_res
}
nmos_de_zvt_v20.OVL.20 {
    @ nmos_de_zvt_v20.OVL.20: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_res
    nmos_de_zvt_v20 AND skip_res
}
nmos_de_zvt_v20.OVL.21 {
    @ nmos_de_zvt_v20.OVL.21: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap skip_res
    nmos_de_zvt_v20 AND skip_res
}
nmos_de_zvt_v20.OVL.22 {
    @ nmos_de_zvt_v20.OVL.22: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:lvNative
    nmos_de_zvt_v20 AND LVID
}
nmos_de_zvt_v20.OVL.23 {
    @ nmos_de_zvt_v20.OVL.23: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap pnp
    nmos_de_zvt_v20 AND pnp
}
nmos_de_zvt_v20.OVL.24 {
    @ nmos_de_zvt_v20.OVL.24: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap npn
    nmos_de_zvt_v20 AND npn
}
nmos_de_zvt_v20.OVL.25 {
    @ nmos_de_zvt_v20.OVL.25: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:diode
    nmos_de_zvt_v20 AND DiodeID
}
nmos_de_zvt_v20.OVL.26 {
    @ nmos_de_zvt_v20.OVL.26: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:photo
    nmos_de_zvt_v20 AND PHdiodeID
}
nmos_de_zvt_v20.OVL.27 {
    @ nmos_de_zvt_v20.OVL.27: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:core
    nmos_de_zvt_v20 AND COREID
}
nmos_de_zvt_v20.OVL.28 {
    @ nmos_de_zvt_v20.OVL.28: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:esd
    nmos_de_zvt_v20 AND ESDID
}
nmos_de_zvt_v20.OVL.29 {
    @ nmos_de_zvt_v20.OVL.29: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap areaid:seal
    nmos_de_zvt_v20 AND SEALID
}
nmos_de_zvt_v20.OVL.30 {
    @ nmos_de_zvt_v20.OVL.30: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap v5
    nmos_de_zvt_v20 AND v5
}
nmos_de_zvt_v20.OVL.31 {
    @ nmos_de_zvt_v20.OVL.31: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap v12
    nmos_de_zvt_v20 AND v12
}
nmos_de_zvt_v20.OVL.32 {
    @ nmos_de_zvt_v20.OVL.32: Illegal nmos_de_zvt_v20 device: nmos_de_zvt_v20 must not overlap poly:model
    nmos_de_zvt_v20 AND polyModel
}


// PMOS:


pmos_gate = ((mos_diff AND polyi) AND nwell) NOT ENID
pmos_sd = (diffi INTERACT pmos_gate) NOT pmos_gate
pmos_1 = pmos_gate TOUCH pmos_sd == 2
pmos = (pmos_1 NOT thkox) NOT lvtn
pmos.OVL.1 {
    @ pmos.OVL.1: Illegal low voltage pmos device: pmos must not overlap pwbm
    pmos AND pwbm
}
pmos.OVL.2 {
    @ pmos.OVL.2: Illegal low voltage pmos device: pmos must not overlap pwde
    pmos AND pwde
}
pmos.OVL.3 {
    @ pmos.OVL.3: Illegal low voltage pmos device: pmos must not overlap lvtn
    pmos AND lvtn
}
pmos.OVL.4 {
    @ pmos.OVL.4: Illegal low voltage pmos device: pmos must not overlap tunm
    pmos AND tunm
}
pmos.OVL.5 {
    @ pmos.OVL.5: Illegal low voltage pmos device: pmos must not overlap thkox
    pmos AND thkox
}
pmos.OVL.6 {
    @ pmos.OVL.6: Illegal low voltage pmos device: pmos must not overlap rpm
    pmos AND rpm
}
pmos.OVL.7 {
    @ pmos.OVL.7: Illegal low voltage pmos device: pmos must not overlap rrpm
    pmos AND rrpm
}
pmos.OVL.8 {
    @ pmos.OVL.8: Illegal low voltage pmos device: pmos must not overlap urpm
    pmos AND urpm
}
pmos.OVL.9 {
    @ pmos.OVL.9: Illegal low voltage pmos device: pmos must not overlap ldntm
    pmos AND ldntm
}
pmos.OVL.10 {
    @ pmos.OVL.10: Illegal low voltage pmos device: pmos must not overlap npc
    pmos AND npc
}
pmos.OVL.11 {
    @ pmos.OVL.11: Illegal low voltage pmos device: pmos must not overlap nsdm
    pmos AND nsdm
}
pmos.OVL.12 {
    @ pmos.OVL.12: Illegal low voltage pmos device: pmos must not overlap nsm
    pmos AND nsm
}
pmos.OVL.13 {
    @ pmos.OVL.13: Illegal low voltage pmos device: pmos must not overlap skip_pad
    pmos AND skip_pad
}
pmos.OVL.14 {
    @ pmos.OVL.14: Illegal low voltage pmos device: pmos must not overlap fuse
    pmos AND fuse
}
pmos.OVL.15 {
    @ pmos.OVL.15: Illegal low voltage pmos device: pmos must not overlap diff:res
    pmos AND diffres
}
pmos.OVL.16 {
    @ pmos.OVL.16: Illegal low voltage pmos device: pmos must not overlap pwell:res
    pmos AND pwres
}
pmos.OVL.17 {
    @ pmos.OVL.17: Illegal low voltage pmos device: pmos must not overlap poly:res
    pmos AND polyres
}
pmos.OVL.18 {
    @ pmos.OVL.18: Illegal low voltage pmos device: pmos must not overlap li:res
    pmos AND lires
}
pmos.OVL.19 {
    @ pmos.OVL.19: Illegal low voltage pmos device: pmos must not overlap skip_res
    pmos AND skip_res
}
pmos.OVL.20 {
    @ pmos.OVL.20: Illegal low voltage pmos device: pmos must not overlap skip_res
    pmos AND skip_res
}
pmos.OVL.21 {
    @ pmos.OVL.21: Illegal low voltage pmos device: pmos must not overlap skip_res
    pmos AND skip_res
}
pmos.OVL.22 {
    @ pmos.OVL.22: Illegal low voltage pmos device: pmos must not overlap skip_res
    pmos AND skip_res
}
pmos.OVL.23 {
    @ pmos.OVL.23: Illegal low voltage pmos device: pmos must not overlap skip_res
    pmos AND skip_res
}
pmos.OVL.24 {
    @ pmos.OVL.24: Illegal low voltage pmos device: pmos must not overlap areaid:lvNative
    pmos AND LVID
}
pmos.OVL.25 {
    @ pmos.OVL.25: Illegal low voltage pmos device: pmos must not overlap pnp
    pmos AND pnp
}
pmos.OVL.26 {
    @ pmos.OVL.26: Illegal low voltage pmos device: pmos must not overlap npn
    pmos AND npn
}
pmos.OVL.27 {
    @ pmos.OVL.27: Illegal low voltage pmos device: pmos must not overlap areaid:diode
    pmos AND DiodeID
}
pmos.OVL.28 {
    @ pmos.OVL.28: Illegal low voltage pmos device: pmos must not overlap areaid:photo
    pmos AND PHdiodeID
}
pmos.OVL.29 {
    @ pmos.OVL.29: Illegal low voltage pmos device: pmos must not overlap areaid:core
    pmos AND COREID
}
pmos.OVL.30 {
    @ pmos.OVL.30: Illegal low voltage pmos device: pmos must not overlap areaid:seal
    pmos AND SEALID
}
pmos.OVL.31 {
    @ pmos.OVL.31: Illegal low voltage pmos device: pmos must not overlap v5
    pmos AND v5
}
pmos.OVL.32 {
    @ pmos.OVL.32: Illegal low voltage pmos device: pmos must not overlap v12
    pmos AND v12
}
pmos.OVL.33 {
    @ pmos.OVL.33: Illegal low voltage pmos device: pmos must not overlap v20
    pmos AND v20
}
pmos.OVL.34 {
    @ pmos.OVL.34: Illegal low voltage pmos device: pmos must not overlap areaid:extendedDrain
    pmos AND ENID
}
pmos.OVL.35 {
    @ pmos.OVL.35: Illegal low voltage pmos device: pmos must not overlap poly:model
    pmos AND polyModel
}
pmos_lvt = pmos_1 AND lvtn
pmos_lvt.OVL.1 {
    @ pmos_lvt.OVL.1: Illegal pmos_lvt device: pmos_lvt must not overlap pwbm
    pmos_lvt AND pwbm
}
pmos_lvt.OVL.2 {
    @ pmos_lvt.OVL.2: Illegal pmos_lvt device: pmos_lvt must not overlap pwde
    pmos_lvt AND pwde
}
pmos_lvt.OVL.3 {
    @ pmos_lvt.OVL.3: Illegal pmos_lvt device: pmos_lvt must not overlap tunm
    pmos_lvt AND tunm
}
pmos_lvt.OVL.4 {
    @ pmos_lvt.OVL.4: Illegal pmos_lvt device: pmos_lvt must not overlap thkox
    pmos_lvt AND thkox
}
pmos_lvt.OVL.5 {
    @ pmos_lvt.OVL.5: Illegal pmos_lvt device: pmos_lvt must not overlap rpm
    pmos_lvt AND rpm
}
pmos_lvt.OVL.6 {
    @ pmos_lvt.OVL.6: Illegal pmos_lvt device: pmos_lvt must not overlap rrpm
    pmos_lvt AND rrpm
}
pmos_lvt.OVL.7 {
    @ pmos_lvt.OVL.7: Illegal pmos_lvt device: pmos_lvt must not overlap urpm
    pmos_lvt AND urpm
}
pmos_lvt.OVL.8 {
    @ pmos_lvt.OVL.8: Illegal pmos_lvt device: pmos_lvt must not overlap ldntm
    pmos_lvt AND ldntm
}
pmos_lvt.OVL.9 {
    @ pmos_lvt.OVL.9: Illegal pmos_lvt device: pmos_lvt must not overlap npc
    pmos_lvt AND npc
}
pmos_lvt.OVL.10 {
    @ pmos_lvt.OVL.10: Illegal pmos_lvt device: pmos_lvt must not overlap nsdm
    pmos_lvt AND nsdm
}
pmos_lvt.OVL.11 {
    @ pmos_lvt.OVL.11: Illegal pmos_lvt device: pmos_lvt must not overlap nsm
    pmos_lvt AND nsm
}
pmos_lvt.OVL.12 {
    @ pmos_lvt.OVL.12: Illegal pmos_lvt device: pmos_lvt must not overlap skip_pad
    pmos_lvt AND skip_pad
}
pmos_lvt.OVL.13 {
    @ pmos_lvt.OVL.13: Illegal pmos_lvt device: pmos_lvt must not overlap fuse
    pmos_lvt AND fuse
}
pmos_lvt.OVL.14 {
    @ pmos_lvt.OVL.14: Illegal pmos_lvt device: pmos_lvt must not overlap diff:res
    pmos_lvt AND diffres
}
pmos_lvt.OVL.15 {
    @ pmos_lvt.OVL.15: Illegal pmos_lvt device: pmos_lvt must not overlap pwell:res
    pmos_lvt AND pwres
}
pmos_lvt.OVL.16 {
    @ pmos_lvt.OVL.16: Illegal pmos_lvt device: pmos_lvt must not overlap poly:res
    pmos_lvt AND polyres
}
pmos_lvt.OVL.17 {
    @ pmos_lvt.OVL.17: Illegal pmos_lvt device: pmos_lvt must not overlap li:res
    pmos_lvt AND lires
}
pmos_lvt.OVL.18 {
    @ pmos_lvt.OVL.18: Illegal pmos_lvt device: pmos_lvt must not overlap skip_res
    pmos_lvt AND skip_res
}
pmos_lvt.OVL.19 {
    @ pmos_lvt.OVL.19: Illegal pmos_lvt device: pmos_lvt must not overlap skip_res
    pmos_lvt AND skip_res
}
pmos_lvt.OVL.20 {
    @ pmos_lvt.OVL.20: Illegal pmos_lvt device: pmos_lvt must not overlap skip_res
    pmos_lvt AND skip_res
}
pmos_lvt.OVL.21 {
    @ pmos_lvt.OVL.21: Illegal pmos_lvt device: pmos_lvt must not overlap skip_res
    pmos_lvt AND skip_res
}
pmos_lvt.OVL.22 {
    @ pmos_lvt.OVL.22: Illegal pmos_lvt device: pmos_lvt must not overlap skip_res
    pmos_lvt AND skip_res
}
pmos_lvt.OVL.23 {
    @ pmos_lvt.OVL.23: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:lvNative
    pmos_lvt AND LVID
}
pmos_lvt.OVL.24 {
    @ pmos_lvt.OVL.24: Illegal pmos_lvt device: pmos_lvt must not overlap pnp
    pmos_lvt AND pnp
}
pmos_lvt.OVL.25 {
    @ pmos_lvt.OVL.25: Illegal pmos_lvt device: pmos_lvt must not overlap npn
    pmos_lvt AND npn
}
pmos_lvt.OVL.26 {
    @ pmos_lvt.OVL.26: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:diode
    pmos_lvt AND DiodeID
}
pmos_lvt.OVL.27 {
    @ pmos_lvt.OVL.27: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:photo
    pmos_lvt AND PHdiodeID
}
pmos_lvt.OVL.28 {
    @ pmos_lvt.OVL.28: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:core
    pmos_lvt AND COREID
}
pmos_lvt.OVL.29 {
    @ pmos_lvt.OVL.29: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:esd
    pmos_lvt AND ESDID
}
pmos_lvt.OVL.30 {
    @ pmos_lvt.OVL.30: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:seal
    pmos_lvt AND SEALID
}
pmos_lvt.OVL.31 {
    @ pmos_lvt.OVL.31: Illegal pmos_lvt device: pmos_lvt must not overlap v5
    pmos_lvt AND v5
}
pmos_lvt.OVL.32 {
    @ pmos_lvt.OVL.32: Illegal pmos_lvt device: pmos_lvt must not overlap v12
    pmos_lvt AND v12
}
pmos_lvt.OVL.33 {
    @ pmos_lvt.OVL.33: Illegal pmos_lvt device: pmos_lvt must not overlap v20
    pmos_lvt AND v20
}
pmos_lvt.OVL.34 {
    @ pmos_lvt.OVL.34: Illegal pmos_lvt device: pmos_lvt must not overlap hvtp
    pmos_lvt AND hvtp
}
pmos_lvt.OVL.35 {
    @ pmos_lvt.OVL.35: Illegal pmos_lvt device: pmos_lvt must not overlap areaid:extendedDrain
    pmos_lvt AND ENID
}
pmos_lvt.OVL.36 {
    @ pmos_lvt.OVL.36: Illegal pmos_lvt device: pmos_lvt must not overlap poly:model
    pmos_lvt AND polyModel
}
pmos_hvt = pmos_1 AND hvtp
pmos_hvt.OVL.1 {
    @ pmos_hvt.OVL.1: Illegal pmos_hvt device: pmos_hvt must not overlap pwbm
    pmos_hvt AND pwbm
}
pmos_hvt.OVL.2 {
    @ pmos_hvt.OVL.2: Illegal pmos_hvt device: pmos_hvt must not overlap pwde
    pmos_hvt AND pwde
}
pmos_hvt.OVL.3 {
    @ pmos_hvt.OVL.3: Illegal pmos_hvt device: pmos_hvt must not overlap tunm
    pmos_hvt AND tunm
}
pmos_hvt.OVL.4 {
    @ pmos_hvt.OVL.4: Illegal pmos_hvt device: pmos_hvt must not overlap thkox
    pmos_hvt AND thkox
}
pmos_hvt.OVL.5 {
    @ pmos_hvt.OVL.5: Illegal pmos_hvt device: pmos_hvt must not overlap rpm
    pmos_hvt AND rpm
}
pmos_hvt.OVL.6 {
    @ pmos_hvt.OVL.6: Illegal pmos_hvt device: pmos_hvt must not overlap rrpm
    pmos_hvt AND rrpm
}
pmos_hvt.OVL.7 {
    @ pmos_hvt.OVL.7: Illegal pmos_hvt device: pmos_hvt must not overlap urpm
    pmos_hvt AND urpm
}
pmos_hvt.OVL.8 {
    @ pmos_hvt.OVL.8: Illegal pmos_hvt device: pmos_hvt must not overlap ldntm
    pmos_hvt AND ldntm
}
pmos_hvt.OVL.9 {
    @ pmos_hvt.OVL.9: Illegal pmos_hvt device: pmos_hvt must not overlap npc
    pmos_hvt AND npc
}
pmos_hvt.OVL.10 {
    @ pmos_hvt.OVL.10: Illegal pmos_hvt device: pmos_hvt must not overlap nsdm
    pmos_hvt AND nsdm
}
pmos_hvt.OVL.11 {
    @ pmos_hvt.OVL.11: Illegal pmos_hvt device: pmos_hvt must not overlap nsm
    pmos_hvt AND nsm
}
pmos_hvt.OVL.12 {
    @ pmos_hvt.OVL.12: Illegal pmos_hvt device: pmos_hvt must not overlap skip_pad
    pmos_hvt AND skip_pad
}
pmos_hvt.OVL.13 {
    @ pmos_hvt.OVL.13: Illegal pmos_hvt device: pmos_hvt must not overlap fuse
    pmos_hvt AND fuse
}
pmos_hvt.OVL.14 {
    @ pmos_hvt.OVL.14: Illegal pmos_hvt device: pmos_hvt must not overlap diff:res
    pmos_hvt AND diffres
}
pmos_hvt.OVL.15 {
    @ pmos_hvt.OVL.15: Illegal pmos_hvt device: pmos_hvt must not overlap pwell:res
    pmos_hvt AND pwres
}
pmos_hvt.OVL.16 {
    @ pmos_hvt.OVL.16: Illegal pmos_hvt device: pmos_hvt must not overlap poly:res
    pmos_hvt AND polyres
}
pmos_hvt.OVL.17 {
    @ pmos_hvt.OVL.17: Illegal pmos_hvt device: pmos_hvt must not overlap li:res
    pmos_hvt AND lires
}
pmos_hvt.OVL.18 {
    @ pmos_hvt.OVL.18: Illegal pmos_hvt device: pmos_hvt must not overlap skip_res
    pmos_hvt AND skip_res
}
pmos_hvt.OVL.19 {
    @ pmos_hvt.OVL.19: Illegal pmos_hvt device: pmos_hvt must not overlap skip_res
    pmos_hvt AND skip_res
}
pmos_hvt.OVL.20 {
    @ pmos_hvt.OVL.20: Illegal pmos_hvt device: pmos_hvt must not overlap skip_res
    pmos_hvt AND skip_res
}
pmos_hvt.OVL.21 {
    @ pmos_hvt.OVL.21: Illegal pmos_hvt device: pmos_hvt must not overlap skip_res
    pmos_hvt AND skip_res
}
pmos_hvt.OVL.22 {
    @ pmos_hvt.OVL.22: Illegal pmos_hvt device: pmos_hvt must not overlap skip_res
    pmos_hvt AND skip_res
}
pmos_hvt.OVL.23 {
    @ pmos_hvt.OVL.23: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:lvNative
    pmos_hvt AND LVID
}
pmos_hvt.OVL.24 {
    @ pmos_hvt.OVL.24: Illegal pmos_hvt device: pmos_hvt must not overlap pnp
    pmos_hvt AND pnp
}
pmos_hvt.OVL.25 {
    @ pmos_hvt.OVL.25: Illegal pmos_hvt device: pmos_hvt must not overlap npn
    pmos_hvt AND npn
}
pmos_hvt.OVL.26 {
    @ pmos_hvt.OVL.26: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:diode
    pmos_hvt AND DiodeID
}
pmos_hvt.OVL.27 {
    @ pmos_hvt.OVL.27: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:photo
    pmos_hvt AND PHdiodeID
}
pmos_hvt.OVL.28 {
    @ pmos_hvt.OVL.28: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:core
    pmos_hvt AND COREID
}
pmos_hvt.OVL.29 {
    @ pmos_hvt.OVL.29: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:esd
    pmos_hvt AND ESDID
}
pmos_hvt.OVL.30 {
    @ pmos_hvt.OVL.30: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:seal
    pmos_hvt AND SEALID
}
pmos_hvt.OVL.31 {
    @ pmos_hvt.OVL.31: Illegal pmos_hvt device: pmos_hvt must not overlap v5
    pmos_hvt AND v5
}
pmos_hvt.OVL.32 {
    @ pmos_hvt.OVL.32: Illegal pmos_hvt device: pmos_hvt must not overlap v12
    pmos_hvt AND v12
}
pmos_hvt.OVL.33 {
    @ pmos_hvt.OVL.33: Illegal pmos_hvt device: pmos_hvt must not overlap v20
    pmos_hvt AND v20
}
pmos_hvt.OVL.34 {
    @ pmos_hvt.OVL.34: Illegal pmos_hvt device: pmos_hvt must not overlap areaid:extendedDrain
    pmos_hvt AND ENID
}
pmos_hvt.OVL.35 {
    @ pmos_hvt.OVL.35: Illegal pmos_hvt device: pmos_hvt must not overlap poly:model
    pmos_hvt AND polyModel
}
pmos_v5 = ((pmos_1 AND v5) AND thkox) NOT ESDID
pmos_v5.OVL.1 {
    @ pmos_v5.OVL.1: Illegal pmos_v5 device: pmos_v5 must not overlap pwbm
    pmos_v5 AND pwbm
}
pmos_v5.OVL.2 {
    @ pmos_v5.OVL.2: Illegal pmos_v5 device: pmos_v5 must not overlap pwde
    pmos_v5 AND pwde
}
pmos_v5.OVL.3 {
    @ pmos_v5.OVL.3: Illegal pmos_v5 device: pmos_v5 must not overlap hvtp
    pmos_v5 AND hvtp
}
pmos_v5.OVL.4 {
    @ pmos_v5.OVL.4: Illegal pmos_v5 device: pmos_v5 must not overlap lvtn
    pmos_v5 AND lvtn
}
pmos_v5.OVL.5 {
    @ pmos_v5.OVL.5: Illegal pmos_v5 device: pmos_v5 must not overlap tunm
    pmos_v5 AND tunm
}
pmos_v5.OVL.6 {
    @ pmos_v5.OVL.6: Illegal pmos_v5 device: pmos_v5 must not overlap rpm
    pmos_v5 AND rpm
}
pmos_v5.OVL.7 {
    @ pmos_v5.OVL.7: Illegal pmos_v5 device: pmos_v5 must not overlap rrpm
    pmos_v5 AND rrpm
}
pmos_v5.OVL.8 {
    @ pmos_v5.OVL.8: Illegal pmos_v5 device: pmos_v5 must not overlap urpm
    pmos_v5 AND urpm
}
pmos_v5.OVL.9 {
    @ pmos_v5.OVL.9: Illegal pmos_v5 device: pmos_v5 must not overlap ldntm
    pmos_v5 AND ldntm
}
pmos_v5.OVL.10 {
    @ pmos_v5.OVL.10: Illegal pmos_v5 device: pmos_v5 must not overlap npc
    pmos_v5 AND npc
}
pmos_v5.OVL.11 {
    @ pmos_v5.OVL.11: Illegal pmos_v5 device: pmos_v5 must not overlap nsdm
    pmos_v5 AND nsdm
}
pmos_v5.OVL.12 {
    @ pmos_v5.OVL.12: Illegal pmos_v5 device: pmos_v5 must not overlap nsm
    pmos_v5 AND nsm
}
pmos_v5.OVL.13 {
    @ pmos_v5.OVL.13: Illegal pmos_v5 device: pmos_v5 must not overlap skip_pad
    pmos_v5 AND skip_pad
}
pmos_v5.OVL.14 {
    @ pmos_v5.OVL.14: Illegal pmos_v5 device: pmos_v5 must not overlap fuse
    pmos_v5 AND fuse
}
pmos_v5.OVL.15 {
    @ pmos_v5.OVL.15: Illegal pmos_v5 device: pmos_v5 must not overlap diff:res
    pmos_v5 AND diffres
}
pmos_v5.OVL.16 {
    @ pmos_v5.OVL.16: Illegal pmos_v5 device: pmos_v5 must not overlap pwell:res
    pmos_v5 AND pwres
}
pmos_v5.OVL.17 {
    @ pmos_v5.OVL.17: Illegal pmos_v5 device: pmos_v5 must not overlap poly:res
    pmos_v5 AND polyres
}
pmos_v5.OVL.18 {
    @ pmos_v5.OVL.18: Illegal pmos_v5 device: pmos_v5 must not overlap li:res
    pmos_v5 AND lires
}
pmos_v5.OVL.19 {
    @ pmos_v5.OVL.19: Illegal pmos_v5 device: pmos_v5 must not overlap skip_res
    pmos_v5 AND skip_res
}
pmos_v5.OVL.20 {
    @ pmos_v5.OVL.20: Illegal pmos_v5 device: pmos_v5 must not overlap skip_res
    pmos_v5 AND skip_res
}
pmos_v5.OVL.21 {
    @ pmos_v5.OVL.21: Illegal pmos_v5 device: pmos_v5 must not overlap skip_res
    pmos_v5 AND skip_res
}
pmos_v5.OVL.22 {
    @ pmos_v5.OVL.22: Illegal pmos_v5 device: pmos_v5 must not overlap skip_res
    pmos_v5 AND skip_res
}
pmos_v5.OVL.23 {
    @ pmos_v5.OVL.23: Illegal pmos_v5 device: pmos_v5 must not overlap skip_res
    pmos_v5 AND skip_res
}
pmos_v5.OVL.24 {
    @ pmos_v5.OVL.24: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:lvNative
    pmos_v5 AND LVID
}
pmos_v5.OVL.25 {
    @ pmos_v5.OVL.25: Illegal pmos_v5 device: pmos_v5 must not overlap pnp
    pmos_v5 AND pnp
}
pmos_v5.OVL.26 {
    @ pmos_v5.OVL.26: Illegal pmos_v5 device: pmos_v5 must not overlap npn
    pmos_v5 AND npn
}
pmos_v5.OVL.27 {
    @ pmos_v5.OVL.27: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:diode
    pmos_v5 AND DiodeID
}
pmos_v5.OVL.28 {
    @ pmos_v5.OVL.28: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:photo
    pmos_v5 AND PHdiodeID
}
pmos_v5.OVL.29 {
    @ pmos_v5.OVL.29: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:core
    pmos_v5 AND COREID
}
pmos_v5.OVL.30 {
    @ pmos_v5.OVL.30: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:seal
    pmos_v5 AND SEALID
}
pmos_v5.OVL.31 {
    @ pmos_v5.OVL.31: Illegal pmos_v5 device: pmos_v5 must not overlap v12
    pmos_v5 AND v12
}
pmos_v5.OVL.32 {
    @ pmos_v5.OVL.32: Illegal pmos_v5 device: pmos_v5 must not overlap v20
    pmos_v5 AND v20
}
pmos_v5.OVL.33 {
    @ pmos_v5.OVL.33: Illegal pmos_v5 device: pmos_v5 must not overlap areaid:extendedDrain
    pmos_v5 AND ENID
}
pmos_v5.OVL.34 {
    @ pmos_v5.OVL.34: Illegal pmos_v5 device: pmos_v5 must not overlap poly:model
    pmos_v5 AND polyModel
}
pmos_de_v12 = ((gate and psdm) AND v12) AND ENID
pmos_de_v12.OVL.1 {
    @ pmos_de_v12.OVL.1: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap pwbm
    pmos_de_v12 AND pwbm
}
pmos_de_v12.OVL.2 {
    @ pmos_de_v12.OVL.2: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap pwde
    pmos_de_v12 AND pwde
}
pmos_de_v12.OVL.3 {
    @ pmos_de_v12.OVL.3: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap hvtp
    pmos_de_v12 AND hvtp
}
pmos_de_v12.OVL.4 {
    @ pmos_de_v12.OVL.4: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap lvtn
    pmos_de_v12 AND lvtn
}
pmos_de_v12.OVL.5 {
    @ pmos_de_v12.OVL.5: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap tunm
    pmos_de_v12 AND tunm
}
pmos_de_v12.OVL.6 {
    @ pmos_de_v12.OVL.6: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap rpm
    pmos_de_v12 AND rpm
}
pmos_de_v12.OVL.7 {
    @ pmos_de_v12.OVL.7: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap rrpm
    pmos_de_v12 AND rrpm
}
pmos_de_v12.OVL.8 {
    @ pmos_de_v12.OVL.8: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap urpm
    pmos_de_v12 AND urpm
}
pmos_de_v12.OVL.9 {
    @ pmos_de_v12.OVL.9: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap ldntm
    pmos_de_v12 AND ldntm
}
pmos_de_v12.OVL.10 {
    @ pmos_de_v12.OVL.10: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap npc
    pmos_de_v12 AND npc
}
pmos_de_v12.OVL.11 {
    @ pmos_de_v12.OVL.11: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap nsdm
    pmos_de_v12 AND nsdm
}
pmos_de_v12.OVL.12 {
    @ pmos_de_v12.OVL.12: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap nsm
    pmos_de_v12 AND nsm
}
pmos_de_v12.OVL.13 {
    @ pmos_de_v12.OVL.13: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_pad
    pmos_de_v12 AND skip_pad
}
pmos_de_v12.OVL.14 {
    @ pmos_de_v12.OVL.14: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap fuse
    pmos_de_v12 AND fuse
}
pmos_de_v12.OVL.15 {
    @ pmos_de_v12.OVL.15: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap diff:res
    pmos_de_v12 AND diffres
}
pmos_de_v12.OVL.16 {
    @ pmos_de_v12.OVL.16: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap pwell:res
    pmos_de_v12 AND pwres
}
pmos_de_v12.OVL.17 {
    @ pmos_de_v12.OVL.17: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap poly:res
    pmos_de_v12 AND polyres
}
pmos_de_v12.OVL.18 {
    @ pmos_de_v12.OVL.18: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap li:res
    pmos_de_v12 AND lires
}
pmos_de_v12.OVL.19 {
    @ pmos_de_v12.OVL.19: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_res
    pmos_de_v12 AND skip_res
}
pmos_de_v12.OVL.20 {
    @ pmos_de_v12.OVL.20: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_res
    pmos_de_v12 AND skip_res
}
pmos_de_v12.OVL.21 {
    @ pmos_de_v12.OVL.21: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_res
    pmos_de_v12 AND skip_res
}
pmos_de_v12.OVL.22 {
    @ pmos_de_v12.OVL.22: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_res
    pmos_de_v12 AND skip_res
}
pmos_de_v12.OVL.23 {
    @ pmos_de_v12.OVL.23: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap skip_res
    pmos_de_v12 AND skip_res
}
pmos_de_v12.OVL.24 {
    @ pmos_de_v12.OVL.24: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:lvNative
    pmos_de_v12 AND LVID
}
pmos_de_v12.OVL.25 {
    @ pmos_de_v12.OVL.25: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap pnp
    pmos_de_v12 AND pnp
}
pmos_de_v12.OVL.26 {
    @ pmos_de_v12.OVL.26: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap npn
    pmos_de_v12 AND npn
}
pmos_de_v12.OVL.27 {
    @ pmos_de_v12.OVL.27: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:diode
    pmos_de_v12 AND DiodeID
}
pmos_de_v12.OVL.28 {
    @ pmos_de_v12.OVL.28: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:photo
    pmos_de_v12 AND PHdiodeID
}
pmos_de_v12.OVL.29 {
    @ pmos_de_v12.OVL.29: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:core
    pmos_de_v12 AND COREID
}
pmos_de_v12.OVL.30 {
    @ pmos_de_v12.OVL.30: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:esd
    pmos_de_v12 AND ESDID
}
pmos_de_v12.OVL.31 {
    @ pmos_de_v12.OVL.31: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap areaid:seal
    pmos_de_v12 AND SEALID
}
pmos_de_v12.OVL.32 {
    @ pmos_de_v12.OVL.32: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap v5
    pmos_de_v12 AND v5
}
pmos_de_v12.OVL.33 {
    @ pmos_de_v12.OVL.33: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap v20
    pmos_de_v12 AND v20
}
pmos_de_v12.OVL.34 {
    @ pmos_de_v12.OVL.34: Illegal pmos_de_v12 device: pmos_de_v12 must not overlap poly:model
    pmos_de_v12 AND polyModel
}
pmos_de_v20 = ((gate and psdm) AND v20) AND ENID
pmos_de_v20.OVL.1 {
    @ pmos_de_v20.OVL.1: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap hvtp
    pmos_de_v20 AND hvtp
}
pmos_de_v20.OVL.2 {
    @ pmos_de_v20.OVL.2: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap tunm
    pmos_de_v20 AND tunm
}
pmos_de_v20.OVL.3 {
    @ pmos_de_v20.OVL.3: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap rpm
    pmos_de_v20 AND rpm
}
pmos_de_v20.OVL.4 {
    @ pmos_de_v20.OVL.4: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap rrpm
    pmos_de_v20 AND rrpm
}
pmos_de_v20.OVL.5 {
    @ pmos_de_v20.OVL.5: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap urpm
    pmos_de_v20 AND urpm
}
pmos_de_v20.OVL.6 {
    @ pmos_de_v20.OVL.6: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap ldntm
    pmos_de_v20 AND ldntm
}
pmos_de_v20.OVL.7 {
    @ pmos_de_v20.OVL.7: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap npc
    pmos_de_v20 AND npc
}
pmos_de_v20.OVL.8 {
    @ pmos_de_v20.OVL.8: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap nsdm
    pmos_de_v20 AND nsdm
}
pmos_de_v20.OVL.9 {
    @ pmos_de_v20.OVL.9: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap nsm
    pmos_de_v20 AND nsm
}
pmos_de_v20.OVL.10 {
    @ pmos_de_v20.OVL.10: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_pad
    pmos_de_v20 AND skip_pad
}
pmos_de_v20.OVL.11 {
    @ pmos_de_v20.OVL.11: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap fuse
    pmos_de_v20 AND fuse
}
pmos_de_v20.OVL.12 {
    @ pmos_de_v20.OVL.12: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap diff:res
    pmos_de_v20 AND diffres
}
pmos_de_v20.OVL.13 {
    @ pmos_de_v20.OVL.13: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap pwell:res
    pmos_de_v20 AND pwres
}
pmos_de_v20.OVL.14 {
    @ pmos_de_v20.OVL.14: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap poly:res
    pmos_de_v20 AND polyres
}
pmos_de_v20.OVL.15 {
    @ pmos_de_v20.OVL.15: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap li:res
    pmos_de_v20 AND lires
}
pmos_de_v20.OVL.16 {
    @ pmos_de_v20.OVL.16: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_res
    pmos_de_v20 AND skip_res
}
pmos_de_v20.OVL.17 {
    @ pmos_de_v20.OVL.17: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_res
    pmos_de_v20 AND skip_res
}
pmos_de_v20.OVL.18 {
    @ pmos_de_v20.OVL.18: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_res
    pmos_de_v20 AND skip_res
}
pmos_de_v20.OVL.19 {
    @ pmos_de_v20.OVL.19: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_res
    pmos_de_v20 AND skip_res
}
pmos_de_v20.OVL.20 {
    @ pmos_de_v20.OVL.20: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap skip_res
    pmos_de_v20 AND skip_res
}
pmos_de_v20.OVL.21 {
    @ pmos_de_v20.OVL.21: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:lvNative
    pmos_de_v20 AND LVID
}
pmos_de_v20.OVL.22 {
    @ pmos_de_v20.OVL.22: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap pnp
    pmos_de_v20 AND pnp
}
pmos_de_v20.OVL.23 {
    @ pmos_de_v20.OVL.23: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap npn
    pmos_de_v20 AND npn
}
pmos_de_v20.OVL.24 {
    @ pmos_de_v20.OVL.24: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:diode
    pmos_de_v20 AND DiodeID
}
pmos_de_v20.OVL.25 {
    @ pmos_de_v20.OVL.25: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:photo
    pmos_de_v20 AND PHdiodeID
}
pmos_de_v20.OVL.26 {
    @ pmos_de_v20.OVL.26: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:core
    pmos_de_v20 AND COREID
}
pmos_de_v20.OVL.27 {
    @ pmos_de_v20.OVL.27: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:esd
    pmos_de_v20 AND ESDID
}
pmos_de_v20.OVL.28 {
    @ pmos_de_v20.OVL.28: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap areaid:seal
    pmos_de_v20 AND SEALID
}
pmos_de_v20.OVL.29 {
    @ pmos_de_v20.OVL.29: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap v5
    pmos_de_v20 AND v5
}
pmos_de_v20.OVL.30 {
    @ pmos_de_v20.OVL.30: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap v12
    pmos_de_v20 AND v12
}
pmos_de_v20.OVL.31 {
    @ pmos_de_v20.OVL.31: Illegal pmos_de_v20 device: pmos_de_v20 must not overlap poly:model
    pmos_de_v20 AND polyModel
}


// RES:


hp_poly_1a = polyi AND polyres 
hp_poly_2a = hp_poly_1a AND npc
hp_poly_3a = hp_poly_2a AND psdm
hp_polya = hp_poly_3a AND rpm
rpoly_hp.OVL.1 {
    @ rpoly_hp.OVL.1: Illegal rpoly_hp device: rpoly_hp must not overlap diff
    hp_polya AND diffi
}
rpoly_hp.OVL.2 {
    @ rpoly_hp.OVL.2: Illegal rpoly_hp device: rpoly_hp must not overlap tunm
    hp_polya AND tunm
}
rpoly_hp.OVL.3 {
    @ rpoly_hp.OVL.3: Illegal rpoly_hp device: rpoly_hp must not overlap urpm
    hp_polya AND urpm
}
rpoly_hp.OVL.4 {
    @ rpoly_hp.OVL.4: Illegal rpoly_hp device: rpoly_hp must not overlap ldntm
    hp_polya AND ldntm
}
rpoly_hp.OVL.5 {
    @ rpoly_hp.OVL.5: Illegal rpoly_hp device: rpoly_hp must not overlap nsdm
    hp_polya AND nsdm
}
rpoly_hp.OVL.6 {
    @ rpoly_hp.OVL.6: Illegal rpoly_hp device: rpoly_hp must not overlap nsm
    hp_polya AND nsm
}
rpoly_hp.OVL.7 {
    @ rpoly_hp.OVL.7: Illegal rpoly_hp device: rpoly_hp must not overlap skip_pad
    hp_polya AND skip_pad
}
rpoly_hp.OVL.8 {
    @ rpoly_hp.OVL.8: Illegal rpoly_hp device: rpoly_hp must not overlap fuse
    hp_polya AND fuse
}
rpoly_hp.OVL.9 {
    @ rpoly_hp.OVL.9: Illegal rpoly_hp device: rpoly_hp must not overlap diff:res
    hp_polya AND diffres
}
rpoly_hp.OVL.10 {
    @ rpoly_hp.OVL.10: Illegal rpoly_hp device: rpoly_hp must not overlap pwell:res
    hp_polya AND pwres
}
rpoly_hp.OVL.11 {
    @ rpoly_hp.OVL.11: Illegal rpoly_hp device: rpoly_hp must not overlap li:res
    hp_polya AND lires
}
rpoly_hp.OVL.12 {
    @ rpoly_hp.OVL.12: Illegal rpoly_hp device: rpoly_hp must not overlap skip_res
    hp_polya AND skip_res
}
rpoly_hp.OVL.13 {
    @ rpoly_hp.OVL.13: Illegal rpoly_hp device: rpoly_hp must not overlap skip_res
    hp_polya AND skip_res
}
rpoly_hp.OVL.14 {
    @ rpoly_hp.OVL.14: Illegal rpoly_hp device: rpoly_hp must not overlap skip_res
    hp_polya AND skip_res
}
rpoly_hp.OVL.15 {
    @ rpoly_hp.OVL.15: Illegal rpoly_hp device: rpoly_hp must not overlap skip_res
    hp_polya AND skip_res
}
rpoly_hp.OVL.16 {
    @ rpoly_hp.OVL.16: Illegal rpoly_hp device: rpoly_hp must not overlap skip_res
    hp_polya AND skip_res
}
rpoly_hp.OVL.17 {
    @ rpoly_hp.OVL.17: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:lvNative
    hp_polya AND LVID
}
rpoly_hp.OVL.18 {
    @ rpoly_hp.OVL.18: Illegal rpoly_hp device: rpoly_hp must not overlap pnp
    hp_polya AND pnp
}
rpoly_hp.OVL.19 {
    @ rpoly_hp.OVL.19: Illegal rpoly_hp device: rpoly_hp must not overlap npn
    hp_polya AND npn
}
rpoly_hp.OVL.20 {
    @ rpoly_hp.OVL.20: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:diode
    hp_polya AND DiodeID
}
rpoly_hp.OVL.21 {
    @ rpoly_hp.OVL.21: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:photo
    hp_polya AND PHdiodeID
}
rpoly_hp.OVL.22 {
    @ rpoly_hp.OVL.22: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:core
    hp_polya AND COREID
}
rpoly_hp.OVL.23 {
    @ rpoly_hp.OVL.23: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:extendedDrain
    hp_polya AND ENID
}
rpoly_hp.OVL.24 {
    @ rpoly_hp.OVL.24: Illegal rpoly_hp device: rpoly_hp must not overlap areaid:seal
    hp_polya AND SEALID
}
rpoly_hp.OVL.25 {
    @ rpoly_hp.OVL.25: Illegal rpoly_hp device: rpoly_hp must not overlap poly:model
    hp_polya AND polyModel
}
hs_poly_1a = polyi AND polyres 
hs_poly_2a = hs_poly_1a AND npc
hs_poly_3a = hs_poly_2a AND psdm
hs_polya = hs_poly_3a AND urpm
rpoly_hs.OVL.1 {
    @ rpoly_hs.OVL.1: Illegal rpoly_hs device: rpoly_hs must not overlap diff
    hs_polya AND diffi
}
rpoly_hs.OVL.2 {
    @ rpoly_hs.OVL.2: Illegal rpoly_hs device: rpoly_hs must not overlap tunm
    hs_polya AND tunm
}
rpoly_hs.OVL.3 {
    @ rpoly_hs.OVL.3: Illegal rpoly_hs device: rpoly_hs must not overlap rrpm
    hs_polya AND rrpm
}
rpoly_hs.OVL.4 {
    @ rpoly_hs.OVL.4: Illegal rpoly_hs device: rpoly_hs must not overlap ldntm
    hs_polya AND ldntm
}
rpoly_hs.OVL.5 {
    @ rpoly_hs.OVL.5: Illegal rpoly_hs device: rpoly_hs must not overlap nsdm
    hs_polya AND nsdm
}
rpoly_hs.OVL.6 {
    @ rpoly_hs.OVL.6: Illegal rpoly_hs device: rpoly_hs must not overlap nsm
    hs_polya AND nsm
}
rpoly_hs.OVL.7 {
    @ rpoly_hs.OVL.7: Illegal rpoly_hs device: rpoly_hs must not overlap skip_pad
    hs_polya AND skip_pad
}
rpoly_hs.OVL.8 {
    @ rpoly_hs.OVL.8: Illegal rpoly_hs device: rpoly_hs must not overlap fuse
    hs_polya AND fuse
}
rpoly_hs.OVL.9 {
    @ rpoly_hs.OVL.9: Illegal rpoly_hs device: rpoly_hs must not overlap diff:res
    hs_polya AND diffres
}
rpoly_hs.OVL.10 {
    @ rpoly_hs.OVL.10: Illegal rpoly_hs device: rpoly_hs must not overlap pwell:res
    hs_polya AND pwres
}
rpoly_hs.OVL.11 {
    @ rpoly_hs.OVL.11: Illegal rpoly_hs device: rpoly_hs must not overlap li:res
    hs_polya AND lires
}
rpoly_hs.OVL.12 {
    @ rpoly_hs.OVL.12: Illegal rpoly_hs device: rpoly_hs must not overlap skip_res
    hs_polya AND skip_res
}
rpoly_hs.OVL.13 {
    @ rpoly_hs.OVL.13: Illegal rpoly_hs device: rpoly_hs must not overlap skip_res
    hs_polya AND skip_res
}
rpoly_hs.OVL.14 {
    @ rpoly_hs.OVL.14: Illegal rpoly_hs device: rpoly_hs must not overlap skip_res
    hs_polya AND skip_res
}
rpoly_hs.OVL.15 {
    @ rpoly_hs.OVL.15: Illegal rpoly_hs device: rpoly_hs must not overlap skip_res
    hs_polya AND skip_res
}
rpoly_hs.OVL.16 {
    @ rpoly_hs.OVL.16: Illegal rpoly_hs device: rpoly_hs must not overlap skip_res
    hs_polya AND skip_res
}
rpoly_hs.OVL.17 {
    @ rpoly_hs.OVL.17: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:lvNative
    hs_polya AND LVID
}
rpoly_hs.OVL.18 {
    @ rpoly_hs.OVL.18: Illegal rpoly_hs device: rpoly_hs must not overlap pnp
    hs_polya AND pnp
}
rpoly_hs.OVL.19 {
    @ rpoly_hs.OVL.19: Illegal rpoly_hs device: rpoly_hs must not overlap npn
    hs_polya AND npn
}
rpoly_hs.OVL.20 {
    @ rpoly_hs.OVL.20: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:diode
    hs_polya AND DiodeID
}
rpoly_hs.OVL.21 {
    @ rpoly_hs.OVL.21: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:photo
    hs_polya AND PHdiodeID
}
rpoly_hs.OVL.22 {
    @ rpoly_hs.OVL.22: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:core
    hs_polya AND COREID
}
rpoly_hs.OVL.23 {
    @ rpoly_hs.OVL.23: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:extendedDrain
    hs_polya AND ENID
}
rpoly_hs.OVL.24 {
    @ rpoly_hs.OVL.24: Illegal rpoly_hs device: rpoly_hs must not overlap areaid:seal
    hs_polya AND SEALID
}
rpoly_hs.OVL.25 {
    @ rpoly_hs.OVL.25: Illegal rpoly_hs device: rpoly_hs must not overlap poly:model
    hs_polya AND polyModel
}
rpoly_std = (polyi AND polyres) NOT (OR hp_polya hs_polya)
rpoly.OVL.1 {
    @ rpoly.OVL.1: Illegal rpoly device: rpoly must not overlap diff
    rpoly_std AND diffi
}
rpoly.OVL.2 {
    @ rpoly.OVL.2: Illegal rpoly device: rpoly must not overlap tunm
    rpoly_std AND tunm
}
rpoly.OVL.3 {
    @ rpoly.OVL.3: Illegal rpoly device: rpoly must not overlap rpm
    rpoly_std AND rpm
}
rpoly.OVL.4 {
    @ rpoly.OVL.4: Illegal rpoly device: rpoly must not overlap rrpm
    rpoly_std AND rrpm
}
rpoly.OVL.5 {
    @ rpoly.OVL.5: Illegal rpoly device: rpoly must not overlap urpm
    rpoly_std AND urpm
}
rpoly.OVL.6 {
    @ rpoly.OVL.6: Illegal rpoly device: rpoly must not overlap ldntm
    rpoly_std AND ldntm
}
rpoly.OVL.7 {
    @ rpoly.OVL.7: Illegal rpoly device: rpoly must not overlap psdm
    rpoly_std AND psdm
}
rpoly.OVL.8 {
    @ rpoly.OVL.8: Illegal rpoly device: rpoly must not overlap nsm
    rpoly_std AND nsm
}
rpoly.OVL.9 {
    @ rpoly.OVL.9: Illegal rpoly device: rpoly must not overlap skip_pad
    rpoly_std AND skip_pad
}
rpoly.OVL.10 {
    @ rpoly.OVL.10: Illegal rpoly device: rpoly must not overlap fuse
    rpoly_std AND fuse
}
rpoly.OVL.11 {
    @ rpoly.OVL.11: Illegal rpoly device: rpoly must not overlap diff:res
    rpoly_std AND diffres
}
rpoly.OVL.12 {
    @ rpoly.OVL.12: Illegal rpoly device: rpoly must not overlap pwell:res
    rpoly_std AND pwres
}
rpoly.OVL.13 {
    @ rpoly.OVL.13: Illegal rpoly device: rpoly must not overlap li:res
    rpoly_std AND lires
}
rpoly.OVL.14 {
    @ rpoly.OVL.14: Illegal rpoly device: rpoly must not overlap skip_res
    rpoly_std AND skip_res
}
rpoly.OVL.15 {
    @ rpoly.OVL.15: Illegal rpoly device: rpoly must not overlap skip_res
    rpoly_std AND skip_res
}
rpoly.OVL.16 {
    @ rpoly.OVL.16: Illegal rpoly device: rpoly must not overlap skip_res
    rpoly_std AND skip_res
}
rpoly.OVL.17 {
    @ rpoly.OVL.17: Illegal rpoly device: rpoly must not overlap skip_res
    rpoly_std AND skip_res
}
rpoly.OVL.18 {
    @ rpoly.OVL.18: Illegal rpoly device: rpoly must not overlap skip_res
    rpoly_std AND skip_res
}
rpoly.OVL.19 {
    @ rpoly.OVL.19: Illegal rpoly device: rpoly must not overlap areaid:lvNative
    rpoly_std AND LVID
}
rpoly.OVL.20 {
    @ rpoly.OVL.20: Illegal rpoly device: rpoly must not overlap pnp
    rpoly_std AND pnp
}
rpoly.OVL.21 {
    @ rpoly.OVL.21: Illegal rpoly device: rpoly must not overlap npn
    rpoly_std AND npn
}
rpoly.OVL.22 {
    @ rpoly.OVL.22: Illegal rpoly device: rpoly must not overlap areaid:diode
    rpoly_std AND DiodeID
}
rpoly.OVL.23 {
    @ rpoly.OVL.23: Illegal rpoly device: rpoly must not overlap areaid:photo
    rpoly_std AND PHdiodeID
}
rpoly.OVL.24 {
    @ rpoly.OVL.24: Illegal rpoly device: rpoly must not overlap areaid:core
    rpoly_std AND COREID
}
rpoly.OVL.25 {
    @ rpoly.OVL.25: Illegal rpoly device: rpoly must not overlap areaid:extendedDrain
    rpoly_std AND ENID
}
rpoly.OVL.26 {
    @ rpoly.OVL.26: Illegal rpoly device: rpoly must not overlap areaid:seal
    rpoly_std AND SEALID
}
rpoly.OVL.27 {
    @ rpoly.OVL.27: Illegal rpoly device: rpoly must not overlap poly:model
    rpoly_std AND polyModel
}
li1r = li_i AND lires
lires.OVL.1 {
    @ lires.OVL.1: Illegal lires device: lires must not overlap licon
    li1r AND licon
}
lires.OVL.2 {
    @ lires.OVL.2: Illegal lires device: lires must not overlap nsm
    li1r AND nsm
}
lires.OVL.3 {
    @ lires.OVL.3: Illegal lires device: lires must not overlap skip_pad
    li1r AND skip_pad
}
lires.OVL.4 {
    @ lires.OVL.4: Illegal lires device: lires must not overlap fuse
    li1r AND fuse
}
lires.OVL.5 {
    @ lires.OVL.5: Illegal lires device: lires must not overlap areaid:photo
    li1r AND PHdiodeID
}
lires.OVL.6 {
    @ lires.OVL.6: Illegal lires device: lires must not overlap areaid:core
    li1r AND COREID
}
lires.OVL.7 {
    @ lires.OVL.7: Illegal lires device: lires must not overlap areaid:extendedDrain
    li1r AND ENID
}
lires.OVL.8 {
    @ lires.OVL.8: Illegal lires device: lires must not overlap areaid:seal
    li1r AND SEALID
}
lires.OVL.9 {
    @ lires.OVL.9: Illegal lires device: lires must not overlap poly:model
    li1r AND polyModel
}
lires.OVL.10 {
    @ lires.OVL.10: Illegal lires device: lires must not overlap poly:res
    li1r AND polyres
}
m1r = met1i AND m1res
m1res.OVL.1 {
    @ m1res.OVL.1: Illegal m1res device: m1res must not overlap nsm
    m1r AND nsm
}
m1res.OVL.2 {
    @ m1res.OVL.2: Illegal m1res device: m1res must not overlap skip_pad
    m1r AND skip_pad
}
m1res.OVL.3 {
    @ m1res.OVL.3: Illegal m1res device: m1res must not overlap fuse
    m1r AND fuse
}
m1res.OVL.4 {
    @ m1res.OVL.4: Illegal m1res device: m1res must not overlap areaid:seal
    m1r AND SEALID
}
m1res.OVL.5 {
    @ m1res.OVL.5: Illegal m1res device: m1res must not overlap poly:model
    m1r AND polyModel
}
m1res.OVL.6 {
    @ m1res.OVL.6: Illegal m1res device: m1res must not overlap areaid:extendedDrain
    m1r AND ENID
}
m2r = met2i AND m2res
m2res.OVL.1 {
    @ m2res.OVL.1: Illegal m2res device: m2res must not overlap nsm
    m2r AND nsm
}
m2res.OVL.2 {
    @ m2res.OVL.2: Illegal m2res device: m2res must not overlap skip_pad
    m2r AND skip_pad
}
m2res.OVL.3 {
    @ m2res.OVL.3: Illegal m2res device: m2res must not overlap fuse
    m2r AND fuse
}
m2res.OVL.4 {
    @ m2res.OVL.4: Illegal m2res device: m2res must not overlap areaid:seal
    m2r AND SEALID
}
m2res.OVL.5 {
    @ m2res.OVL.5: Illegal m2res device: m2res must not overlap poly:model
    m2r AND polyModel
}
m2res.OVL.6 {
    @ m2res.OVL.6: Illegal m2res device: m2res must not overlap areaid:extendedDrain
    m2r AND ENID
}
m3r = met3i AND m3res
m3res.OVL.1 {
    @ m3res.OVL.1: Illegal m3res device: m3res must not overlap nsm
    m3r AND nsm
}
m3res.OVL.2 {
    @ m3res.OVL.2: Illegal m3res device: m3res must not overlap skip_pad
    m3r AND skip_pad
}
m3res.OVL.3 {
    @ m3res.OVL.3: Illegal m3res device: m3res must not overlap fuse
    m3r AND fuse
}
m3res.OVL.4 {
    @ m3res.OVL.4: Illegal m3res device: m3res must not overlap areaid:seal
    m3r AND SEALID
}
m3res.OVL.5 {
    @ m3res.OVL.5: Illegal m3res device: m3res must not overlap poly:model
    m3r AND polyModel
}
m3res.OVL.6 {
    @ m3res.OVL.6: Illegal m3res device: m3res must not overlap areaid:extendedDrain
    m3r AND ENID
}
m4r = met4i AND m4res
m4res.OVL.1 {
    @ m4res.OVL.1: Illegal m4res device: m4res must not overlap nsm
    m4r AND nsm
}
m4res.OVL.2 {
    @ m4res.OVL.2: Illegal m4res device: m4res must not overlap skip_pad
    m4r AND skip_pad
}
m4res.OVL.3 {
    @ m4res.OVL.3: Illegal m4res device: m4res must not overlap fuse
    m4r AND fuse
}
m4res.OVL.4 {
    @ m4res.OVL.4: Illegal m4res device: m4res must not overlap areaid:seal
    m4r AND SEALID
}
m4res.OVL.5 {
    @ m4res.OVL.5: Illegal m4res device: m4res must not overlap poly:model
    m4r AND polyModel
}
m4res.OVL.6 {
    @ m4res.OVL.6: Illegal m4res device: m4res must not overlap areaid:extendedDrain
    m4r AND ENID
}
m5r = met5i AND m5res
m5res.OVL.1 {
    @ m5res.OVL.1: Illegal m5res device: m5res must not overlap nsm
    m5r AND nsm
}
m5res.OVL.2 {
    @ m5res.OVL.2: Illegal m5res device: m5res must not overlap skip_pad
    m5r AND skip_pad
}
m5res.OVL.3 {
    @ m5res.OVL.3: Illegal m5res device: m5res must not overlap fuse
    m5r AND fuse
}
m5res.OVL.4 {
    @ m5res.OVL.4: Illegal m5res device: m5res must not overlap areaid:seal
    m5r AND SEALID
}
m5res.OVL.5 {
    @ m5res.OVL.5: Illegal m5res device: m5res must not overlap poly:model
    m5r AND polyModel
}
m5res.OVL.6 {
    @ m5res.OVL.6: Illegal m5res device: m5res must not overlap areaid:extendedDrain
    m5r AND ENID
}
rndiff_ill_dev = ((nsdm AND diffi) AND diffres) NOT v5
rndiff.OVL.1 {
    @ rndiff.OVL.1: Illegal rndiff device: rndiff must not overlap pwbm
    rndiff_ill_dev AND pwbm
}
rndiff.OVL.2 {
    @ rndiff.OVL.2: Illegal rndiff device: rndiff must not overlap nwell
    rndiff_ill_dev AND nwell
}
rndiff.OVL.3 {
    @ rndiff.OVL.3: Illegal rndiff device: rndiff must not overlap hvtp
    rndiff_ill_dev AND hvtp
}
rndiff.OVL.4 {
    @ rndiff.OVL.4: Illegal rndiff device: rndiff must not overlap lvtn
    rndiff_ill_dev AND lvtn
}
rndiff.OVL.5 {
    @ rndiff.OVL.5: Illegal rndiff device: rndiff must not overlap tunm
    rndiff_ill_dev AND tunm
}
rndiff.OVL.6 {
    @ rndiff.OVL.6: Illegal rndiff device: rndiff must not overlap thkox
    rndiff_ill_dev AND thkox
}
rndiff.OVL.7 {
    @ rndiff.OVL.7: Illegal rndiff device: rndiff must not overlap rpm
    rndiff_ill_dev AND rpm
}
rndiff.OVL.8 {
    @ rndiff.OVL.8: Illegal rndiff device: rndiff must not overlap rrpm
    rndiff_ill_dev AND rrpm
}
rndiff.OVL.9 {
    @ rndiff.OVL.9: Illegal rndiff device: rndiff must not overlap urpm
    rndiff_ill_dev AND urpm
}
rndiff.OVL.10 {
    @ rndiff.OVL.10: Illegal rndiff device: rndiff must not overlap ldntm
    rndiff_ill_dev AND ldntm
}
rndiff.OVL.11 {
    @ rndiff.OVL.11: Illegal rndiff device: rndiff must not overlap psdm
    rndiff_ill_dev AND psdm
}
rndiff.OVL.12 {
    @ rndiff.OVL.12: Illegal rndiff device: rndiff must not overlap nsm
    rndiff_ill_dev AND nsm
}
rndiff.OVL.13 {
    @ rndiff.OVL.13: Illegal rndiff device: rndiff must not overlap skip_pad
    rndiff_ill_dev AND skip_pad
}
rndiff.OVL.14 {
    @ rndiff.OVL.14: Illegal rndiff device: rndiff must not overlap fuse
    rndiff_ill_dev AND fuse
}
rndiff.OVL.15 {
    @ rndiff.OVL.15: Illegal rndiff device: rndiff must not overlap poly:res
    rndiff_ill_dev AND polyres
}
rndiff.OVL.16 {
    @ rndiff.OVL.16: Illegal rndiff device: rndiff must not overlap areaid:lvNative
    rndiff_ill_dev AND LVID
}
rndiff.OVL.17 {
    @ rndiff.OVL.17: Illegal rndiff device: rndiff must not overlap pnp
    rndiff_ill_dev AND pnp
}
rndiff.OVL.18 {
    @ rndiff.OVL.18: Illegal rndiff device: rndiff must not overlap npn
    rndiff_ill_dev AND npn
}
rndiff.OVL.19 {
    @ rndiff.OVL.19: Illegal rndiff device: rndiff must not overlap areaid:diode
    rndiff_ill_dev AND DiodeID
}
rndiff.OVL.20 {
    @ rndiff.OVL.20: Illegal rndiff device: rndiff must not overlap areaid:photo
    rndiff_ill_dev AND PHdiodeID
}
rndiff.OVL.21 {
    @ rndiff.OVL.21: Illegal rndiff device: rndiff must not overlap areaid:core
    rndiff_ill_dev AND COREID
}
rndiff.OVL.22 {
    @ rndiff.OVL.22: Illegal rndiff device: rndiff must not overlap areaid:extendedDrain
    rndiff_ill_dev AND ENID
}
rndiff.OVL.23 {
    @ rndiff.OVL.23: Illegal rndiff device: rndiff must not overlap areaid:seal
    rndiff_ill_dev AND SEALID
}
rndiff.OVL.24 {
    @ rndiff.OVL.24: Illegal rndiff device: rndiff must not overlap v5
    rndiff_ill_dev AND v5
}
rndiff.OVL.25 {
    @ rndiff.OVL.25: Illegal rndiff device: rndiff must not overlap v12
    rndiff_ill_dev AND v12
}
rndiff.OVL.26 {
    @ rndiff.OVL.26: Illegal rndiff device: rndiff must not overlap v20
    rndiff_ill_dev AND v20
}
rndiff.OVL.27 {
    @ rndiff.OVL.27: Illegal rndiff device: rndiff must not overlap poly:model
    rndiff_ill_dev AND polyModel
}
rndiff.OVL.28 {
    @ rndiff.OVL.28: Illegal rndiff device: rndiff must not overlap pwde
    rndiff_ill_dev AND pwde
}
rndiff.OVL.29 {
    @ rndiff.OVL.29: Illegal rndiff device: rndiff must not overlap poly
    rndiff_ill_dev AND polyi
}
rndiff.OVL.30 {
    @ rndiff.OVL.30: Illegal rndiff device: rndiff must not overlap npc
    rndiff_ill_dev AND npc
}
rndiff.OVL.31 {
    @ rndiff.OVL.31: Illegal rndiff device: rndiff must not overlap li:res
    rndiff_ill_dev AND lires
}
rpdiff_ill_dev = ((psdm AND diffi) AND diffres) NOT v5
rpdiff.OVL.1 {
    @ rpdiff.OVL.1: Illegal rpdiff device: rpdiff must not overlap pwbm
    rpdiff_ill_dev AND pwbm
}
rpdiff.OVL.2 {
    @ rpdiff.OVL.2: Illegal rpdiff device: rpdiff must not overlap hvtp
    rpdiff_ill_dev AND hvtp
}
rpdiff.OVL.3 {
    @ rpdiff.OVL.3: Illegal rpdiff device: rpdiff must not overlap lvtn
    rpdiff_ill_dev AND lvtn
}
rpdiff.OVL.4 {
    @ rpdiff.OVL.4: Illegal rpdiff device: rpdiff must not overlap tunm
    rpdiff_ill_dev AND tunm
}
rpdiff.OVL.5 {
    @ rpdiff.OVL.5: Illegal rpdiff device: rpdiff must not overlap thkox
    rpdiff_ill_dev AND thkox
}
rpdiff.OVL.6 {
    @ rpdiff.OVL.6: Illegal rpdiff device: rpdiff must not overlap rpm
    rpdiff_ill_dev AND rpm
}
rpdiff.OVL.7 {
    @ rpdiff.OVL.7: Illegal rpdiff device: rpdiff must not overlap rrpm
    rpdiff_ill_dev AND rrpm
}
rpdiff.OVL.8 {
    @ rpdiff.OVL.8: Illegal rpdiff device: rpdiff must not overlap urpm
    rpdiff_ill_dev AND urpm
}
rpdiff.OVL.9 {
    @ rpdiff.OVL.9: Illegal rpdiff device: rpdiff must not overlap ldntm
    rpdiff_ill_dev AND ldntm
}
rpdiff.OVL.10 {
    @ rpdiff.OVL.10: Illegal rpdiff device: rpdiff must not overlap nsdm
    rpdiff_ill_dev AND nsdm
}
rpdiff.OVL.11 {
    @ rpdiff.OVL.11: Illegal rpdiff device: rpdiff must not overlap nsm
    rpdiff_ill_dev AND nsm
}
rpdiff.OVL.12 {
    @ rpdiff.OVL.12: Illegal rpdiff device: rpdiff must not overlap skip_pad
    rpdiff_ill_dev AND skip_pad
}
rpdiff.OVL.13 {
    @ rpdiff.OVL.13: Illegal rpdiff device: rpdiff must not overlap fuse
    rpdiff_ill_dev AND fuse
}
rpdiff.OVL.14 {
    @ rpdiff.OVL.14: Illegal rpdiff device: rpdiff must not overlap poly:res
    rpdiff_ill_dev AND polyres
}
rpdiff.OVL.15 {
    @ rpdiff.OVL.15: Illegal rpdiff device: rpdiff must not overlap areaid:lvNative
    rpdiff_ill_dev AND LVID
}
rpdiff.OVL.16 {
    @ rpdiff.OVL.16: Illegal rpdiff device: rpdiff must not overlap pnp
    rpdiff_ill_dev AND pnp
}
rpdiff.OVL.17 {
    @ rpdiff.OVL.17: Illegal rpdiff device: rpdiff must not overlap npn
    rpdiff_ill_dev AND npn
}
rpdiff.OVL.18 {
    @ rpdiff.OVL.18: Illegal rpdiff device: rpdiff must not overlap areaid:diode
    rpdiff_ill_dev AND DiodeID
}
rpdiff.OVL.19 {
    @ rpdiff.OVL.19: Illegal rpdiff device: rpdiff must not overlap areaid:photo
    rpdiff_ill_dev AND PHdiodeID
}
rpdiff.OVL.20 {
    @ rpdiff.OVL.20: Illegal rpdiff device: rpdiff must not overlap areaid:core
    rpdiff_ill_dev AND COREID
}
rpdiff.OVL.21 {
    @ rpdiff.OVL.21: Illegal rpdiff device: rpdiff must not overlap areaid:extendedDrain
    rpdiff_ill_dev AND ENID
}
rpdiff.OVL.22 {
    @ rpdiff.OVL.22: Illegal rpdiff device: rpdiff must not overlap areaid:seal
    rpdiff_ill_dev AND SEALID
}
rpdiff.OVL.23 {
    @ rpdiff.OVL.23: Illegal rpdiff device: rpdiff must not overlap v5
    rpdiff_ill_dev AND v5
}
rpdiff.OVL.24 {
    @ rpdiff.OVL.24: Illegal rpdiff device: rpdiff must not overlap v12
    rpdiff_ill_dev AND v12
}
rpdiff.OVL.25 {
    @ rpdiff.OVL.25: Illegal rpdiff device: rpdiff must not overlap v20
    rpdiff_ill_dev AND v20
}
rpdiff.OVL.26 {
    @ rpdiff.OVL.26: Illegal rpdiff device: rpdiff must not overlap poly:model
    rpdiff_ill_dev AND polyModel
}
rpdiff.OVL.27 {
    @ rpdiff.OVL.27: Illegal rpdiff device: rpdiff must not overlap pwde
    rpdiff_ill_dev AND pwde
}
rpdiff.OVL.28 {
    @ rpdiff.OVL.28: Illegal rpdiff device: rpdiff must not overlap poly
    rpdiff_ill_dev AND polyi
}
rpdiff.OVL.29 {
    @ rpdiff.OVL.29: Illegal rpdiff device: rpdiff must not overlap npc
    rpdiff_ill_dev AND npc
}
rpdiff.OVL.30 {
    @ rpdiff.OVL.30: Illegal rpdiff device: rpdiff must not overlap li:res
    rpdiff_ill_dev AND lires
}
rndiff_v5 = ((nsdm AND diffi) AND diffres) AND v5
id_dummy3 = COPY 5000
rndiff_v5.OVL.1 {
    @ rndiff_v5.OVL.1: Illegal rndiff_v5 device: rndiff_v5 must not overlap pwbm
    rndiff_v5 AND pwbm
}
rndiff_v5.OVL.2 {
    @ rndiff_v5.OVL.2: Illegal rndiff_v5 device: rndiff_v5 must not overlap nwell
    rndiff_v5 AND nwell
}
rndiff_v5.OVL.3 {
    @ rndiff_v5.OVL.3: Illegal rndiff_v5 device: rndiff_v5 must not overlap hvtp
    rndiff_v5 AND hvtp
}
rndiff_v5.OVL.4 {
    @ rndiff_v5.OVL.4: Illegal rndiff_v5 device: rndiff_v5 must not overlap lvtn
    rndiff_v5 AND lvtn
}
rndiff_v5.OVL.5 {
    @ rndiff_v5.OVL.5: Illegal rndiff_v5 device: rndiff_v5 must not overlap tunm
    rndiff_v5 AND tunm
}
rndiff_v5.OVL.6 {
    @ rndiff_v5.OVL.6: Illegal rndiff_v5 device: rndiff_v5 must not overlap id_dummy3
    rndiff_v5 AND id_dummy3
}
rndiff_v5.OVL.7 {
    @ rndiff_v5.OVL.7: Illegal rndiff_v5 device: rndiff_v5 must not overlap rpm
    rndiff_v5 AND rpm
}
rndiff_v5.OVL.8 {
    @ rndiff_v5.OVL.8: Illegal rndiff_v5 device: rndiff_v5 must not overlap rrpm
    rndiff_v5 AND rrpm
}
rndiff_v5.OVL.9 {
    @ rndiff_v5.OVL.9: Illegal rndiff_v5 device: rndiff_v5 must not overlap urpm
    rndiff_v5 AND urpm
}
rndiff_v5.OVL.10 {
    @ rndiff_v5.OVL.10: Illegal rndiff_v5 device: rndiff_v5 must not overlap ldntm
    rndiff_v5 AND ldntm
}
rndiff_v5.OVL.11 {
    @ rndiff_v5.OVL.11: Illegal rndiff_v5 device: rndiff_v5 must not overlap psdm
    rndiff_v5 AND psdm
}
rndiff_v5.OVL.12 {
    @ rndiff_v5.OVL.12: Illegal rndiff_v5 device: rndiff_v5 must not overlap nsm
    rndiff_v5 AND nsm
}
rndiff_v5.OVL.13 {
    @ rndiff_v5.OVL.13: Illegal rndiff_v5 device: rndiff_v5 must not overlap skip_pad
    rndiff_v5 AND skip_pad
}
rndiff_v5.OVL.14 {
    @ rndiff_v5.OVL.14: Illegal rndiff_v5 device: rndiff_v5 must not overlap fuse
    rndiff_v5 AND fuse
}
rndiff_v5.OVL.15 {
    @ rndiff_v5.OVL.15: Illegal rndiff_v5 device: rndiff_v5 must not overlap poly:res
    rndiff_v5 AND polyres
}
rndiff_v5.OVL.16 {
    @ rndiff_v5.OVL.16: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:lvNative
    rndiff_v5 AND LVID
}
rndiff_v5.OVL.17 {
    @ rndiff_v5.OVL.17: Illegal rndiff_v5 device: rndiff_v5 must not overlap pnp
    rndiff_v5 AND pnp
}
rndiff_v5.OVL.18 {
    @ rndiff_v5.OVL.18: Illegal rndiff_v5 device: rndiff_v5 must not overlap npn
    rndiff_v5 AND npn
}
rndiff_v5.OVL.19 {
    @ rndiff_v5.OVL.19: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:diode
    rndiff_v5 AND DiodeID
}
rndiff_v5.OVL.20 {
    @ rndiff_v5.OVL.20: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:photo
    rndiff_v5 AND PHdiodeID
}
rndiff_v5.OVL.21 {
    @ rndiff_v5.OVL.21: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:core
    rndiff_v5 AND COREID
}
rndiff_v5.OVL.22 {
    @ rndiff_v5.OVL.22: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:extendedDrain
    rndiff_v5 AND ENID
}
rndiff_v5.OVL.23 {
    @ rndiff_v5.OVL.23: Illegal rndiff_v5 device: rndiff_v5 must not overlap areaid:seal
    rndiff_v5 AND SEALID
}
rndiff_v5.OVL.24 {
    @ rndiff_v5.OVL.24: Illegal rndiff_v5 device: rndiff_v5 must not overlap v12
    rndiff_v5 AND v12
}
rndiff_v5.OVL.25 {
    @ rndiff_v5.OVL.25: Illegal rndiff_v5 device: rndiff_v5 must not overlap v20
    rndiff_v5 AND v20
}
rndiff_v5.OVL.26 {
    @ rndiff_v5.OVL.26: Illegal rndiff_v5 device: rndiff_v5 must not overlap poly:model
    rndiff_v5 AND polyModel
}
rndiff_v5.OVL.27 {
    @ rndiff_v5.OVL.27: Illegal rndiff_v5 device: rndiff_v5 must not overlap pwde
    rndiff_v5 AND pwde
}
rndiff_v5.OVL.28 {
    @ rndiff_v5.OVL.28: Illegal rndiff_v5 device: rndiff_v5 must not overlap poly
    rndiff_v5 AND polyi
}
rndiff_v5.OVL.29 {
    @ rndiff_v5.OVL.29: Illegal rndiff_v5 device: rndiff_v5 must not overlap npc
    rndiff_v5 AND npc
}
rndiff_v5.OVL.30 {
    @ rndiff_v5.OVL.30: Illegal rndiff_v5 device: rndiff_v5 must not overlap li:res
    rndiff_v5 AND lires
}
rpdiff_v5 = ((psdm AND diffi) AND diffres) AND v5
rpdiff_v5.OVL.1 {
    @ rpdiff_v5.OVL.1: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap pwbm
    rpdiff_v5 AND pwbm
}
rpdiff_v5.OVL.2 {
    @ rpdiff_v5.OVL.2: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap hvtp
    rpdiff_v5 AND hvtp
}
rpdiff_v5.OVL.3 {
    @ rpdiff_v5.OVL.3: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap lvtn
    rpdiff_v5 AND lvtn
}
rpdiff_v5.OVL.4 {
    @ rpdiff_v5.OVL.4: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap tunm
    rpdiff_v5 AND tunm
}
rpdiff_v5.OVL.5 {
    @ rpdiff_v5.OVL.5: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap id_dummy3
    rpdiff_v5 AND id_dummy3
}
rpdiff_v5.OVL.6 {
    @ rpdiff_v5.OVL.6: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap rpm
    rpdiff_v5 AND rpm
}
rpdiff_v5.OVL.7 {
    @ rpdiff_v5.OVL.7: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap rrpm
    rpdiff_v5 AND rrpm
}
rpdiff_v5.OVL.8 {
    @ rpdiff_v5.OVL.8: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap urpm
    rpdiff_v5 AND urpm
}
rpdiff_v5.OVL.9 {
    @ rpdiff_v5.OVL.9: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap ldntm
    rpdiff_v5 AND ldntm
}
rpdiff_v5.OVL.10 {
    @ rpdiff_v5.OVL.10: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap nsdm
    rpdiff_v5 AND nsdm
}
rpdiff_v5.OVL.11 {
    @ rpdiff_v5.OVL.11: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap nsm
    rpdiff_v5 AND nsm
}
rpdiff_v5.OVL.12 {
    @ rpdiff_v5.OVL.12: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap skip_pad
    rpdiff_v5 AND skip_pad
}
rpdiff_v5.OVL.13 {
    @ rpdiff_v5.OVL.13: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap fuse
    rpdiff_v5 AND fuse
}
rpdiff_v5.OVL.14 {
    @ rpdiff_v5.OVL.14: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap poly:res
    rpdiff_v5 AND polyres
}
rpdiff_v5.OVL.15 {
    @ rpdiff_v5.OVL.15: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:lvNative
    rpdiff_v5 AND LVID
}
rpdiff_v5.OVL.16 {
    @ rpdiff_v5.OVL.16: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap pnp
    rpdiff_v5 AND pnp
}
rpdiff_v5.OVL.17 {
    @ rpdiff_v5.OVL.17: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap npn
    rpdiff_v5 AND npn
}
rpdiff_v5.OVL.18 {
    @ rpdiff_v5.OVL.18: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:diode
    rpdiff_v5 AND DiodeID
}
rpdiff_v5.OVL.19 {
    @ rpdiff_v5.OVL.19: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:photo
    rpdiff_v5 AND PHdiodeID
}
rpdiff_v5.OVL.20 {
    @ rpdiff_v5.OVL.20: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:core
    rpdiff_v5 AND COREID
}
rpdiff_v5.OVL.21 {
    @ rpdiff_v5.OVL.21: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:extendedDrain
    rpdiff_v5 AND ENID
}
rpdiff_v5.OVL.22 {
    @ rpdiff_v5.OVL.22: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap areaid:seal
    rpdiff_v5 AND SEALID
}
rpdiff_v5.OVL.23 {
    @ rpdiff_v5.OVL.23: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap v12
    rpdiff_v5 AND v12
}
rpdiff_v5.OVL.24 {
    @ rpdiff_v5.OVL.24: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap v20
    rpdiff_v5 AND v20
}
rpdiff_v5.OVL.25 {
    @ rpdiff_v5.OVL.25: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap poly:model
    rpdiff_v5 AND polyModel
}
rpdiff_v5.OVL.26 {
    @ rpdiff_v5.OVL.26: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap pwde
    rpdiff_v5 AND pwde
}
rpdiff_v5.OVL.27 {
    @ rpdiff_v5.OVL.27: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap poly
    rpdiff_v5 AND polyi
}
rpdiff_v5.OVL.28 {
    @ rpdiff_v5.OVL.28: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap npc
    rpdiff_v5 AND npc
}
rpdiff_v5.OVL.29 {
    @ rpdiff_v5.OVL.29: Illegal rpdiff_v5 device: rpdiff_v5 must not overlap li:res
    rpdiff_v5 AND lires
}
rpwell = (pwres AND psdm) AND ((HOLES nwell) AND dnwell)
id_dummy2 = COPY 4998
rpwell.OVL.1 {
    @ rpwell.OVL.1: Illegal rpwell device: rpwell must not overlap pwbm
    rpwell AND pwbm
}
rpwell.OVL.2 {
    @ rpwell.OVL.2: Illegal rpwell device: rpwell must not overlap pwde
    rpwell AND pwde
}
rpwell.OVL.3 {
    @ rpwell.OVL.3: Illegal rpwell device: rpwell must not overlap hvtp
    rpwell AND hvtp
}
rpwell.OVL.4 {
    @ rpwell.OVL.4: Illegal rpwell device: rpwell must not overlap lvtn
    rpwell AND lvtn
}
rpwell.OVL.5 {
    @ rpwell.OVL.5: Illegal rpwell device: rpwell must not overlap tunm
    rpwell AND tunm
}
rpwell.OVL.6 {
    @ rpwell.OVL.6: Illegal rpwell device: rpwell must not overlap thkox
    rpwell AND thkox
}
rpwell.OVL.7 {
    @ rpwell.OVL.7: Illegal rpwell device: rpwell must not overlap rpm
    rpwell AND rpm
}
rpwell.OVL.8 {
    @ rpwell.OVL.8: Illegal rpwell device: rpwell must not overlap rrpm
    rpwell AND rrpm
}
rpwell.OVL.9 {
    @ rpwell.OVL.9: Illegal rpwell device: rpwell must not overlap urpm
    rpwell AND urpm
}
rpwell.OVL.10 {
    @ rpwell.OVL.10: Illegal rpwell device: rpwell must not overlap poly
    rpwell AND polyi
}
rpwell.OVL.11 {
    @ rpwell.OVL.11: Illegal rpwell device: rpwell must not overlap ldntm
    rpwell AND ldntm
}
rpwell.OVL.12 {
    @ rpwell.OVL.12: Illegal rpwell device: rpwell must not overlap npc
    rpwell AND npc
}
rpwell.OVL.13 {
    @ rpwell.OVL.13: Illegal rpwell device: rpwell must not overlap nsm
    rpwell AND nsm
}
rpwell.OVL.14 {
    @ rpwell.OVL.14: Illegal rpwell device: rpwell must not overlap skip_pad
    rpwell AND skip_pad
}
rpwell.OVL.15 {
    @ rpwell.OVL.15: Illegal rpwell device: rpwell must not overlap fuse
    rpwell AND fuse
}
rpwell.OVL.16 {
    @ rpwell.OVL.16: Illegal rpwell device: rpwell must not overlap poly:res
    rpwell AND polyres
}
rpwell.OVL.17 {
    @ rpwell.OVL.17: Illegal rpwell device: rpwell must not overlap areaid:lvNative
    rpwell AND LVID
}
rpwell.OVL.18 {
    @ rpwell.OVL.18: Illegal rpwell device: rpwell must not overlap id_dummy
    rpwell AND id_dummy
}
rpwell.OVL.19 {
    @ rpwell.OVL.19: Illegal rpwell device: rpwell must not overlap id_dummy2
    rpwell AND id_dummy2
}
rpwell.OVL.20 {
    @ rpwell.OVL.20: Illegal rpwell device: rpwell must not overlap areaid:photo
    rpwell AND PHdiodeID
}
rpwell.OVL.21 {
    @ rpwell.OVL.21: Illegal rpwell device: rpwell must not overlap areaid:core
    rpwell AND COREID
}
rpwell.OVL.22 {
    @ rpwell.OVL.22: Illegal rpwell device: rpwell must not overlap areaid:extendedDrain
    rpwell AND ENID
}
rpwell.OVL.23 {
    @ rpwell.OVL.23: Illegal rpwell device: rpwell must not overlap areaid:seal
    rpwell AND SEALID
}
rpwell.OVL.24 {
    @ rpwell.OVL.24: Illegal rpwell device: rpwell must not overlap v5
    rpwell AND v5
}
rpwell.OVL.25 {
    @ rpwell.OVL.25: Illegal rpwell device: rpwell must not overlap v12
    rpwell AND v12
}
rpwell.OVL.26 {
    @ rpwell.OVL.26: Illegal rpwell device: rpwell must not overlap v20
    rpwell AND v20
}
rpwell.OVL.27 {
    @ rpwell.OVL.27: Illegal rpwell device: rpwell must not overlap poly:model
    rpwell AND polyModel
}
rpwell.OVL.28 {
    @ rpwell.OVL.28: Illegal rpwell device: rpwell must not overlap nwell
    rpwell AND nwell
}
rpwell.OVL.29 {
    @ rpwell.OVL.29: Illegal rpwell device: rpwell must not overlap diff:res
    rpwell AND diffres
}
rpwell.OVL.30 {
    @ rpwell.OVL.30: Illegal rpwell device: rpwell must not overlap li:res
    rpwell AND lires
}


// CAP:


cap_34a = (met3 AND met4) AND capm
capm3m4.OVL.1 {
    @ capm3m4.OVL.1: Illegal capm3m4 device: capm3m4 must not overlap nsm
    cap_34a AND nsm
}
capm3m4.OVL.2 {
    @ capm3m4.OVL.2: Illegal capm3m4 device: capm3m4 must not overlap skip_pad
    cap_34a AND skip_pad
}
capm3m4.OVL.3 {
    @ capm3m4.OVL.3: Illegal capm3m4 device: capm3m4 must not overlap areaid:lvNative
    cap_34a AND LVID
}
capm3m4.OVL.4 {
    @ capm3m4.OVL.4: Illegal capm3m4 device: capm3m4 must not overlap areaid:photo
    cap_34a AND PHdiodeID
}
capm3m4.OVL.5 {
    @ capm3m4.OVL.5: Illegal capm3m4 device: capm3m4 must not overlap areaid:core
    cap_34a AND COREID
}
capm3m4.OVL.6 {
    @ capm3m4.OVL.6: Illegal capm3m4 device: capm3m4 must not overlap areaid:extendedDrain
    cap_34a AND ENID
}
capm3m4.OVL.7 {
    @ capm3m4.OVL.7: Illegal capm3m4 device: capm3m4 must not overlap fuse
    cap_34a AND fuse
}
capm3m4.OVL.8 {
    @ capm3m4.OVL.8: Illegal capm3m4 device: capm3m4 must not overlap areaid:seal
    cap_34a AND SEALID
}
capm3m4.OVL.9 {
    @ capm3m4.OVL.9: Illegal capm3m4 device: capm3m4 must not overlap poly:model
    cap_34a AND polyModel
}
cap_45a = (met4 AND met5) AND cap2m
capm4m5.OVL.1 {
    @ capm4m5.OVL.1: Illegal capm4m5 device: capm4m5 must not overlap nsm
    cap_45a AND nsm
}
capm4m5.OVL.2 {
    @ capm4m5.OVL.2: Illegal capm4m5 device: capm4m5 must not overlap skip_pad
    cap_45a AND skip_pad
}
capm4m5.OVL.3 {
    @ capm4m5.OVL.3: Illegal capm4m5 device: capm4m5 must not overlap areaid:lvNative
    cap_45a AND LVID
}
capm4m5.OVL.4 {
    @ capm4m5.OVL.4: Illegal capm4m5 device: capm4m5 must not overlap areaid:photo
    cap_45a AND PHdiodeID
}
capm4m5.OVL.5 {
    @ capm4m5.OVL.5: Illegal capm4m5 device: capm4m5 must not overlap areaid:core
    cap_45a AND COREID
}
capm4m5.OVL.6 {
    @ capm4m5.OVL.6: Illegal capm4m5 device: capm4m5 must not overlap areaid:extendedDrain
    cap_45a AND ENID
}
capm4m5.OVL.7 {
    @ capm4m5.OVL.7: Illegal capm4m5 device: capm4m5 must not overlap fuse
    cap_45a AND fuse
}
capm4m5.OVL.8 {
    @ capm4m5.OVL.8: Illegal capm4m5 device: capm4m5 must not overlap areaid:seal
    cap_45a AND SEALID
}
capm4m5.OVL.9 {
    @ capm4m5.OVL.9: Illegal capm4m5 device: capm4m5 must not overlap poly:model
    cap_45a AND polyModel
}


// DIO:


diode_dnsd_pw = (((diodeID AND nsdm) NOT nwell) AND diffi) NOT (OR ESDID v5 v12 v20 lvtn hvtp LVID)
dnsd_pw.OVL.1 {
    @ dnsd_pw.OVL.1: Illegal dnsd_pw device: dnsd_pw must not overlap pwbm
    diode_dnsd_pw AND pwbm
}
dnsd_pw.OVL.2 {
    @ dnsd_pw.OVL.2: Illegal dnsd_pw device: dnsd_pw must not overlap nwell
    diode_dnsd_pw AND nwell
}
dnsd_pw.OVL.3 {
    @ dnsd_pw.OVL.3: Illegal dnsd_pw device: dnsd_pw must not overlap hvtp
    diode_dnsd_pw AND hvtp
}
dnsd_pw.OVL.4 {
    @ dnsd_pw.OVL.4: Illegal dnsd_pw device: dnsd_pw must not overlap lvtn
    diode_dnsd_pw AND lvtn
}
dnsd_pw.OVL.5 {
    @ dnsd_pw.OVL.5: Illegal dnsd_pw device: dnsd_pw must not overlap tunm
    diode_dnsd_pw AND tunm
}
dnsd_pw.OVL.6 {
    @ dnsd_pw.OVL.6: Illegal dnsd_pw device: dnsd_pw must not overlap thkox
    diode_dnsd_pw AND thkox
}
dnsd_pw.OVL.7 {
    @ dnsd_pw.OVL.7: Illegal dnsd_pw device: dnsd_pw must not overlap rpm
    diode_dnsd_pw AND rpm
}
dnsd_pw.OVL.8 {
    @ dnsd_pw.OVL.8: Illegal dnsd_pw device: dnsd_pw must not overlap rrpm
    diode_dnsd_pw AND rrpm
}
dnsd_pw.OVL.9 {
    @ dnsd_pw.OVL.9: Illegal dnsd_pw device: dnsd_pw must not overlap urpm
    diode_dnsd_pw AND urpm
}
dnsd_pw.OVL.10 {
    @ dnsd_pw.OVL.10: Illegal dnsd_pw device: dnsd_pw must not overlap poly
    diode_dnsd_pw AND polyi
}
dnsd_pw.OVL.11 {
    @ dnsd_pw.OVL.11: Illegal dnsd_pw device: dnsd_pw must not overlap ldntm
    diode_dnsd_pw AND ldntm
}
dnsd_pw.OVL.12 {
    @ dnsd_pw.OVL.12: Illegal dnsd_pw device: dnsd_pw must not overlap psdm
    diode_dnsd_pw AND psdm
}
dnsd_pw.OVL.13 {
    @ dnsd_pw.OVL.13: Illegal dnsd_pw device: dnsd_pw must not overlap nsm
    diode_dnsd_pw AND nsm
}
dnsd_pw.OVL.14 {
    @ dnsd_pw.OVL.14: Illegal dnsd_pw device: dnsd_pw must not overlap skip_pad
    diode_dnsd_pw AND skip_pad
}
dnsd_pw.OVL.15 {
    @ dnsd_pw.OVL.15: Illegal dnsd_pw device: dnsd_pw must not overlap fuse
    diode_dnsd_pw AND fuse
}
dnsd_pw.OVL.16 {
    @ dnsd_pw.OVL.16: Illegal dnsd_pw device: dnsd_pw must not overlap diff:res
    diode_dnsd_pw AND diffres
}
dnsd_pw.OVL.17 {
    @ dnsd_pw.OVL.17: Illegal dnsd_pw device: dnsd_pw must not overlap poly:res
    diode_dnsd_pw AND polyres
}
dnsd_pw.OVL.18 {
    @ dnsd_pw.OVL.18: Illegal dnsd_pw device: dnsd_pw must not overlap li:res
    diode_dnsd_pw AND lires
}
dnsd_pw.OVL.19 {
    @ dnsd_pw.OVL.19: Illegal dnsd_pw device: dnsd_pw must not overlap areaid:lvNative
    diode_dnsd_pw AND LVID
}
dnsd_pw.OVL.20 {
    @ dnsd_pw.OVL.20: Illegal dnsd_pw device: dnsd_pw must not overlap pnp
    diode_dnsd_pw AND pnp
}
dnsd_pw.OVL.21 {
    @ dnsd_pw.OVL.21: Illegal dnsd_pw device: dnsd_pw must not overlap npn
    diode_dnsd_pw AND npn
}
dnsd_pw.OVL.22 {
    @ dnsd_pw.OVL.22: Illegal dnsd_pw device: dnsd_pw must not overlap areaid:photo
    diode_dnsd_pw AND PHdiodeID
}
dnsd_pw.OVL.23 {
    @ dnsd_pw.OVL.23: Illegal dnsd_pw device: dnsd_pw must not overlap areaid:extendedDrain
    diode_dnsd_pw AND ENID
}
dnsd_pw.OVL.24 {
    @ dnsd_pw.OVL.24: Illegal dnsd_pw device: dnsd_pw must not overlap v5
    diode_dnsd_pw AND v5
}
dnsd_pw.OVL.25 {
    @ dnsd_pw.OVL.25: Illegal dnsd_pw device: dnsd_pw must not overlap v12
    diode_dnsd_pw AND v12
}
dnsd_pw.OVL.26 {
    @ dnsd_pw.OVL.26: Illegal dnsd_pw device: dnsd_pw must not overlap v20
    diode_dnsd_pw AND v20
}
dnsd_pw.OVL.27 {
    @ dnsd_pw.OVL.27: Illegal dnsd_pw device: dnsd_pw must not overlap npc
    diode_dnsd_pw AND npc
}
dnsd_pw.OVL.28 {
    @ dnsd_pw.OVL.28: Illegal dnsd_pw device: dnsd_pw must not overlap areaid:seal
    diode_dnsd_pw AND SEALID
}
dnsd_pw.OVL.29 {
    @ dnsd_pw.OVL.29: Illegal dnsd_pw device: dnsd_pw must not overlap poly:model
    diode_dnsd_pw AND polyModel
}
diode_dnsd_pw_v5 = (((((diodeID AND nsdm) NOT nwell) AND diffi) AND v5) AND thkox) NOT (OR v12 v20 lvtn hvtp ESDID LVID)
dnsd_pw_v5.OVL.1 {
    @ dnsd_pw_v5.OVL.1: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap pwbm
    diode_dnsd_pw_v5 AND pwbm
}
dnsd_pw_v5.OVL.2 {
    @ dnsd_pw_v5.OVL.2: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap nwell
    diode_dnsd_pw_v5 AND nwell
}
dnsd_pw_v5.OVL.3 {
    @ dnsd_pw_v5.OVL.3: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap hvtp
    diode_dnsd_pw_v5 AND hvtp
}
dnsd_pw_v5.OVL.4 {
    @ dnsd_pw_v5.OVL.4: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap lvtn
    diode_dnsd_pw_v5 AND lvtn
}
dnsd_pw_v5.OVL.5 {
    @ dnsd_pw_v5.OVL.5: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap tunm
    diode_dnsd_pw_v5 AND tunm
}
dnsd_pw_v5.OVL.6 {
    @ dnsd_pw_v5.OVL.6: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap rpm
    diode_dnsd_pw_v5 AND rpm
}
dnsd_pw_v5.OVL.7 {
    @ dnsd_pw_v5.OVL.7: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap rrpm
    diode_dnsd_pw_v5 AND rrpm
}
dnsd_pw_v5.OVL.8 {
    @ dnsd_pw_v5.OVL.8: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap urpm
    diode_dnsd_pw_v5 AND urpm
}
dnsd_pw_v5.OVL.9 {
    @ dnsd_pw_v5.OVL.9: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap poly
    diode_dnsd_pw_v5 AND polyi
}
dnsd_pw_v5.OVL.10 {
    @ dnsd_pw_v5.OVL.10: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap ldntm
    diode_dnsd_pw_v5 AND ldntm
}
dnsd_pw_v5.OVL.11 {
    @ dnsd_pw_v5.OVL.11: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap psdm
    diode_dnsd_pw_v5 AND psdm
}
dnsd_pw_v5.OVL.12 {
    @ dnsd_pw_v5.OVL.12: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap nsm
    diode_dnsd_pw_v5 AND nsm
}
dnsd_pw_v5.OVL.13 {
    @ dnsd_pw_v5.OVL.13: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap skip_pad
    diode_dnsd_pw_v5 AND skip_pad
}
dnsd_pw_v5.OVL.14 {
    @ dnsd_pw_v5.OVL.14: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap fuse
    diode_dnsd_pw_v5 AND fuse
}
dnsd_pw_v5.OVL.15 {
    @ dnsd_pw_v5.OVL.15: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap diff:res
    diode_dnsd_pw_v5 AND diffres
}
dnsd_pw_v5.OVL.16 {
    @ dnsd_pw_v5.OVL.16: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap poly:res
    diode_dnsd_pw_v5 AND polyres
}
dnsd_pw_v5.OVL.17 {
    @ dnsd_pw_v5.OVL.17: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap li:res
    diode_dnsd_pw_v5 AND lires
}
dnsd_pw_v5.OVL.18 {
    @ dnsd_pw_v5.OVL.18: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap areaid:lvNative
    diode_dnsd_pw_v5 AND LVID
}
dnsd_pw_v5.OVL.19 {
    @ dnsd_pw_v5.OVL.19: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap pnp
    diode_dnsd_pw_v5 AND pnp
}
dnsd_pw_v5.OVL.20 {
    @ dnsd_pw_v5.OVL.20: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap npn
    diode_dnsd_pw_v5 AND npn
}
dnsd_pw_v5.OVL.21 {
    @ dnsd_pw_v5.OVL.21: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap areaid:photo
    diode_dnsd_pw_v5 AND PHdiodeID
}
dnsd_pw_v5.OVL.22 {
    @ dnsd_pw_v5.OVL.22: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap areaid:core
    diode_dnsd_pw_v5 AND COREID
}
dnsd_pw_v5.OVL.23 {
    @ dnsd_pw_v5.OVL.23: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap areaid:extendedDrain
    diode_dnsd_pw_v5 AND ENID
}
dnsd_pw_v5.OVL.24 {
    @ dnsd_pw_v5.OVL.24: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap v12
    diode_dnsd_pw_v5 AND v12
}
dnsd_pw_v5.OVL.25 {
    @ dnsd_pw_v5.OVL.25: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap v20
    diode_dnsd_pw_v5 AND v20
}
dnsd_pw_v5.OVL.26 {
    @ dnsd_pw_v5.OVL.26: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap npc
    diode_dnsd_pw_v5 AND npc
}
dnsd_pw_v5.OVL.27 {
    @ dnsd_pw_v5.OVL.27: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap areaid:seal
    diode_dnsd_pw_v5 AND SEALID
}
dnsd_pw_v5.OVL.28 {
    @ dnsd_pw_v5.OVL.28: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap poly:model
    diode_dnsd_pw_v5 AND polyModel
}
dnsd_pw_v5.OVL.29 {
    @ dnsd_pw_v5.OVL.29: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap pwde
    diode_dnsd_pw_v5 AND pwde
}
dnsd_pw_v5.OVL.30 {
    @ dnsd_pw_v5.OVL.30: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap pwell:res
    diode_dnsd_pw_v5 AND pwres
}
dnsd_pw_v5.OVL.31 {
    @ dnsd_pw_v5.OVL.31: Illegal dnsd_pw_v5 device: dnsd_pw_v5 must not overlap poly:res
    diode_dnsd_pw_v5 AND polyres
}
diode_dnsd_pw_lvt = ((((diodeID AND nsdm) NOT nwell) AND diffi) AND lvtn) NOT (OR v5 v12 v20 hvtp ESDID LVID)
dnsd_pw_lvt.OVL.1 {
    @ dnsd_pw_lvt.OVL.1: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap pwbm
    diode_dnsd_pw_lvt AND pwbm
}
dnsd_pw_lvt.OVL.2 {
    @ dnsd_pw_lvt.OVL.2: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap pwde
    diode_dnsd_pw_lvt AND pwde
}
dnsd_pw_lvt.OVL.3 {
    @ dnsd_pw_lvt.OVL.3: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap tunm
    diode_dnsd_pw_lvt AND tunm
}
dnsd_pw_lvt.OVL.4 {
    @ dnsd_pw_lvt.OVL.4: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap rpm
    diode_dnsd_pw_lvt AND rpm
}
dnsd_pw_lvt.OVL.5 {
    @ dnsd_pw_lvt.OVL.5: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap rrpm
    diode_dnsd_pw_lvt AND rrpm
}
dnsd_pw_lvt.OVL.6 {
    @ dnsd_pw_lvt.OVL.6: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap urpm
    diode_dnsd_pw_lvt AND urpm
}
dnsd_pw_lvt.OVL.7 {
    @ dnsd_pw_lvt.OVL.7: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap poly
    diode_dnsd_pw_lvt AND polyi
}
dnsd_pw_lvt.OVL.8 {
    @ dnsd_pw_lvt.OVL.8: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap ldntm
    diode_dnsd_pw_lvt AND ldntm
}
dnsd_pw_lvt.OVL.9 {
    @ dnsd_pw_lvt.OVL.9: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap npc
    diode_dnsd_pw_lvt AND npc
}
dnsd_pw_lvt.OVL.10 {
    @ dnsd_pw_lvt.OVL.10: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap psdm
    diode_dnsd_pw_lvt AND psdm
}
dnsd_pw_lvt.OVL.11 {
    @ dnsd_pw_lvt.OVL.11: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap nsm
    diode_dnsd_pw_lvt AND nsm
}
dnsd_pw_lvt.OVL.12 {
    @ dnsd_pw_lvt.OVL.12: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap skip_pad
    diode_dnsd_pw_lvt AND skip_pad
}
dnsd_pw_lvt.OVL.13 {
    @ dnsd_pw_lvt.OVL.13: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap fuse
    diode_dnsd_pw_lvt AND fuse
}
dnsd_pw_lvt.OVL.14 {
    @ dnsd_pw_lvt.OVL.14: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap pwell:res
    diode_dnsd_pw_lvt AND pwres
}
dnsd_pw_lvt.OVL.15 {
    @ dnsd_pw_lvt.OVL.15: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap poly:res
    diode_dnsd_pw_lvt AND polyres
}
dnsd_pw_lvt.OVL.16 {
    @ dnsd_pw_lvt.OVL.16: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap poly:model
    diode_dnsd_pw_lvt AND polyModel
}
dnsd_pw_lvt.OVL.17 {
    @ dnsd_pw_lvt.OVL.17: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap PHDiodeID
    diode_dnsd_pw_lvt AND PHDiodeID
}
dnsd_pw_lvt.OVL.18 {
    @ dnsd_pw_lvt.OVL.18: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap areaid:extendedDrain
    diode_dnsd_pw_lvt AND ENID
}
dnsd_pw_lvt.OVL.19 {
    @ dnsd_pw_lvt.OVL.19: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap areaid:seal
    diode_dnsd_pw_lvt AND SEALID
}
dnsd_pw_lvt.OVL.20 {
    @ dnsd_pw_lvt.OVL.20: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap v5
    diode_dnsd_pw_lvt AND v5
}
dnsd_pw_lvt.OVL.21 {
    @ dnsd_pw_lvt.OVL.21: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap V12
    diode_dnsd_pw_lvt AND V12
}
dnsd_pw_lvt.OVL.22 {
    @ dnsd_pw_lvt.OVL.22: Illegal dnsd_pw_lvt device: dnsd_pw_lvt must not overlap v20
    diode_dnsd_pw_lvt AND v20
}
diode_dnsd_pw_nat = (((((diodeID AND nsdm) NOT nwell) AND diffi) AND LVID) AND lvtn) NOT (OR ESDID v5 v12 v20 hvtp)
id_dummy = COPY 4999
dnsd_pw_nat.OVL.1 {
    @ dnsd_pw_nat.OVL.1: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap pwbm
    diode_dnsd_pw_nat AND pwbm
}
dnsd_pw_nat.OVL.2 {
    @ dnsd_pw_nat.OVL.2: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap tunm
    diode_dnsd_pw_nat AND tunm
}
dnsd_pw_nat.OVL.3 {
    @ dnsd_pw_nat.OVL.3: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap id_dummy
    diode_dnsd_pw_nat AND id_dummy
}
dnsd_pw_nat.OVL.4 {
    @ dnsd_pw_nat.OVL.4: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap rpm
    diode_dnsd_pw_nat AND rpm
}
dnsd_pw_nat.OVL.5 {
    @ dnsd_pw_nat.OVL.5: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap rrpm
    diode_dnsd_pw_nat AND rrpm
}
dnsd_pw_nat.OVL.6 {
    @ dnsd_pw_nat.OVL.6: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap urpm
    diode_dnsd_pw_nat AND urpm
}
dnsd_pw_nat.OVL.7 {
    @ dnsd_pw_nat.OVL.7: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap poly
    diode_dnsd_pw_nat AND polyi
}
dnsd_pw_nat.OVL.8 {
    @ dnsd_pw_nat.OVL.8: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap ldntm
    diode_dnsd_pw_nat AND ldntm
}
dnsd_pw_nat.OVL.9 {
    @ dnsd_pw_nat.OVL.9: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap npc
    diode_dnsd_pw_nat AND npc
}
dnsd_pw_nat.OVL.10 {
    @ dnsd_pw_nat.OVL.10: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap psdm
    diode_dnsd_pw_nat AND psdm
}
dnsd_pw_nat.OVL.11 {
    @ dnsd_pw_nat.OVL.11: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap nsm
    diode_dnsd_pw_nat AND nsm
}
dnsd_pw_nat.OVL.12 {
    @ dnsd_pw_nat.OVL.12: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap skip_pad
    diode_dnsd_pw_nat AND skip_pad
}
dnsd_pw_nat.OVL.13 {
    @ dnsd_pw_nat.OVL.13: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap fuse
    diode_dnsd_pw_nat AND fuse
}
dnsd_pw_nat.OVL.14 {
    @ dnsd_pw_nat.OVL.14: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap areaid:photo
    diode_dnsd_pw_nat AND PHdiodeID
}
dnsd_pw_nat.OVL.15 {
    @ dnsd_pw_nat.OVL.15: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap areaid:extendedDrain
    diode_dnsd_pw_nat AND ENID
}
dnsd_pw_nat.OVL.16 {
    @ dnsd_pw_nat.OVL.16: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap areaid:seal
    diode_dnsd_pw_nat AND SEALID
}
dnsd_pw_nat.OVL.17 {
    @ dnsd_pw_nat.OVL.17: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap v5
    diode_dnsd_pw_nat AND v5
}
dnsd_pw_nat.OVL.18 {
    @ dnsd_pw_nat.OVL.18: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap v12
    diode_dnsd_pw_nat AND v12
}
dnsd_pw_nat.OVL.19 {
    @ dnsd_pw_nat.OVL.19: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap v20
    diode_dnsd_pw_nat AND v20
}
dnsd_pw_nat.OVL.20 {
    @ dnsd_pw_nat.OVL.20: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap poly:model
    diode_dnsd_pw_nat AND polyModel
}
dnsd_pw_nat.OVL.21 {
    @ dnsd_pw_nat.OVL.21: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap pwde
    diode_dnsd_pw_nat AND pwde
}
dnsd_pw_nat.OVL.22 {
    @ dnsd_pw_nat.OVL.22: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap pwell:res
    diode_dnsd_pw_nat AND pwres
}
dnsd_pw_nat.OVL.23 {
    @ dnsd_pw_nat.OVL.23: Illegal dnsd_pw_nat device: dnsd_pw_nat must not overlap poly:res
    diode_dnsd_pw_nat AND polyres
}
diode_dpsd_nw = (((diodeID AND psdm) AND nwell) AND diffi) NOT (OR thkox v5 v12 v20 lvtn hvtp ESDID LVID)
dpsd_nw.OVL.1 {
    @ dpsd_nw.OVL.1: Illegal dpsd_nw device: dpsd_nw must not overlap pwbm
    diode_dpsd_nw AND pwbm
}
dpsd_nw.OVL.2 {
    @ dpsd_nw.OVL.2: Illegal dpsd_nw device: dpsd_nw must not overlap hvtp
    diode_dpsd_nw AND hvtp
}
dpsd_nw.OVL.3 {
    @ dpsd_nw.OVL.3: Illegal dpsd_nw device: dpsd_nw must not overlap lvtn
    diode_dpsd_nw AND lvtn
}
dpsd_nw.OVL.4 {
    @ dpsd_nw.OVL.4: Illegal dpsd_nw device: dpsd_nw must not overlap tunm
    diode_dpsd_nw AND tunm
}
dpsd_nw.OVL.5 {
    @ dpsd_nw.OVL.5: Illegal dpsd_nw device: dpsd_nw must not overlap thkox
    diode_dpsd_nw AND thkox
}
dpsd_nw.OVL.6 {
    @ dpsd_nw.OVL.6: Illegal dpsd_nw device: dpsd_nw must not overlap rpm
    diode_dpsd_nw AND rpm
}
dpsd_nw.OVL.7 {
    @ dpsd_nw.OVL.7: Illegal dpsd_nw device: dpsd_nw must not overlap rrpm
    diode_dpsd_nw AND rrpm
}
dpsd_nw.OVL.8 {
    @ dpsd_nw.OVL.8: Illegal dpsd_nw device: dpsd_nw must not overlap urpm
    diode_dpsd_nw AND urpm
}
dpsd_nw.OVL.9 {
    @ dpsd_nw.OVL.9: Illegal dpsd_nw device: dpsd_nw must not overlap poly
    diode_dpsd_nw AND polyi
}
dpsd_nw.OVL.10 {
    @ dpsd_nw.OVL.10: Illegal dpsd_nw device: dpsd_nw must not overlap ldntm
    diode_dpsd_nw AND ldntm
}
dpsd_nw.OVL.11 {
    @ dpsd_nw.OVL.11: Illegal dpsd_nw device: dpsd_nw must not overlap npc
    diode_dpsd_nw AND npc
}
dpsd_nw.OVL.12 {
    @ dpsd_nw.OVL.12: Illegal dpsd_nw device: dpsd_nw must not overlap nsdm
    diode_dpsd_nw AND nsdm
}
dpsd_nw.OVL.13 {
    @ dpsd_nw.OVL.13: Illegal dpsd_nw device: dpsd_nw must not overlap nsm
    diode_dpsd_nw AND nsm
}
dpsd_nw.OVL.14 {
    @ dpsd_nw.OVL.14: Illegal dpsd_nw device: dpsd_nw must not overlap skip_pad
    diode_dpsd_nw AND skip_pad
}
dpsd_nw.OVL.15 {
    @ dpsd_nw.OVL.15: Illegal dpsd_nw device: dpsd_nw must not overlap fuse
    diode_dpsd_nw AND fuse
}
dpsd_nw.OVL.16 {
    @ dpsd_nw.OVL.16: Illegal dpsd_nw device: dpsd_nw must not overlap diff:res
    diode_dpsd_nw AND diffres
}
dpsd_nw.OVL.17 {
    @ dpsd_nw.OVL.17: Illegal dpsd_nw device: dpsd_nw must not overlap poly:res
    diode_dpsd_nw AND polyres
}
dpsd_nw.OVL.18 {
    @ dpsd_nw.OVL.18: Illegal dpsd_nw device: dpsd_nw must not overlap li:res
    diode_dpsd_nw AND lires
}
dpsd_nw.OVL.19 {
    @ dpsd_nw.OVL.19: Illegal dpsd_nw device: dpsd_nw must not overlap areaid:lvNative
    diode_dpsd_nw AND LVID
}
dpsd_nw.OVL.20 {
    @ dpsd_nw.OVL.20: Illegal dpsd_nw device: dpsd_nw must not overlap areaid:extendedDrain
    diode_dpsd_nw AND ENID
}
dpsd_nw.OVL.21 {
    @ dpsd_nw.OVL.21: Illegal dpsd_nw device: dpsd_nw must not overlap areaid:seal
    diode_dpsd_nw AND SEALID
}
dpsd_nw.OVL.22 {
    @ dpsd_nw.OVL.22: Illegal dpsd_nw device: dpsd_nw must not overlap v5
    diode_dpsd_nw AND v5
}
dpsd_nw.OVL.23 {
    @ dpsd_nw.OVL.23: Illegal dpsd_nw device: dpsd_nw must not overlap v12
    diode_dpsd_nw AND v12
}
dpsd_nw.OVL.24 {
    @ dpsd_nw.OVL.24: Illegal dpsd_nw device: dpsd_nw must not overlap v20
    diode_dpsd_nw AND v20
}
dpsd_nw.OVL.25 {
    @ dpsd_nw.OVL.25: Illegal dpsd_nw device: dpsd_nw must not overlap poly:model
    diode_dpsd_nw AND polyModel
}
dpsd_nw.OVL.26 {
    @ dpsd_nw.OVL.26: Illegal dpsd_nw device: dpsd_nw must not overlap pwde
    diode_dpsd_nw AND pwde
}
dpsd_nw.OVL.27 {
    @ dpsd_nw.OVL.27: Illegal dpsd_nw device: dpsd_nw must not overlap pwell:res
    diode_dpsd_nw AND pwres
}
dpsd_nw.OVL.28 {
    @ dpsd_nw.OVL.28: Illegal dpsd_nw device: dpsd_nw must not overlap poly:res
    diode_dpsd_nw AND polyres
}
dpsd_nw.OVL.29 {
    @ dpsd_nw.OVL.29: Illegal dpsd_nw device: dpsd_nw must not overlap pnp
    diode_dpsd_nw AND pnp
}
dpsd_nw.OVL.30 {
    @ dpsd_nw.OVL.30: Illegal dpsd_nw device: dpsd_nw must not overlap npn
    diode_dpsd_nw AND npn
}
diode_dpsd_nw_v5 = (((((diodeID AND psdm) AND nwell) AND diffi) AND thkox) AND v5) NOT (OR v12 v20 lvtn hvtp ESDID LVID)
dpsd_nw_v5.OVL.1 {
    @ dpsd_nw_v5.OVL.1: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap pwbm
    diode_dpsd_nw_v5 AND pwbm
}
dpsd_nw_v5.OVL.2 {
    @ dpsd_nw_v5.OVL.2: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap hvtp
    diode_dpsd_nw_v5 AND hvtp
}
dpsd_nw_v5.OVL.3 {
    @ dpsd_nw_v5.OVL.3: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap lvtn
    diode_dpsd_nw_v5 AND lvtn
}
dpsd_nw_v5.OVL.4 {
    @ dpsd_nw_v5.OVL.4: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap tunm
    diode_dpsd_nw_v5 AND tunm
}
dpsd_nw_v5.OVL.5 {
    @ dpsd_nw_v5.OVL.5: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap rpm
    diode_dpsd_nw_v5 AND rpm
}
dpsd_nw_v5.OVL.6 {
    @ dpsd_nw_v5.OVL.6: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap rrpm
    diode_dpsd_nw_v5 AND rrpm
}
dpsd_nw_v5.OVL.7 {
    @ dpsd_nw_v5.OVL.7: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap urpm
    diode_dpsd_nw_v5 AND urpm
}
dpsd_nw_v5.OVL.8 {
    @ dpsd_nw_v5.OVL.8: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap poly
    diode_dpsd_nw_v5 AND polyi
}
dpsd_nw_v5.OVL.9 {
    @ dpsd_nw_v5.OVL.9: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap ldntm
    diode_dpsd_nw_v5 AND ldntm
}
dpsd_nw_v5.OVL.10 {
    @ dpsd_nw_v5.OVL.10: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap npc
    diode_dpsd_nw_v5 AND npc
}
dpsd_nw_v5.OVL.11 {
    @ dpsd_nw_v5.OVL.11: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap nsdm
    diode_dpsd_nw_v5 AND nsdm
}
dpsd_nw_v5.OVL.12 {
    @ dpsd_nw_v5.OVL.12: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap nsm
    diode_dpsd_nw_v5 AND nsm
}
dpsd_nw_v5.OVL.13 {
    @ dpsd_nw_v5.OVL.13: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap skip_pad
    diode_dpsd_nw_v5 AND skip_pad
}
dpsd_nw_v5.OVL.14 {
    @ dpsd_nw_v5.OVL.14: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap fuse
    diode_dpsd_nw_v5 AND fuse
}
dpsd_nw_v5.OVL.15 {
    @ dpsd_nw_v5.OVL.15: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap diff:res
    diode_dpsd_nw_v5 AND diffres
}
dpsd_nw_v5.OVL.16 {
    @ dpsd_nw_v5.OVL.16: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap poly:res
    diode_dpsd_nw_v5 AND polyres
}
dpsd_nw_v5.OVL.17 {
    @ dpsd_nw_v5.OVL.17: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap li:res
    diode_dpsd_nw_v5 AND lires
}
dpsd_nw_v5.OVL.18 {
    @ dpsd_nw_v5.OVL.18: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap areaid:lvNative
    diode_dpsd_nw_v5 AND LVID
}
dpsd_nw_v5.OVL.19 {
    @ dpsd_nw_v5.OVL.19: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap areaid:extendedDrain
    diode_dpsd_nw_v5 AND ENID
}
dpsd_nw_v5.OVL.20 {
    @ dpsd_nw_v5.OVL.20: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap areaid:seal
    diode_dpsd_nw_v5 AND SEALID
}
dpsd_nw_v5.OVL.21 {
    @ dpsd_nw_v5.OVL.21: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap v12
    diode_dpsd_nw_v5 AND v12
}
dpsd_nw_v5.OVL.22 {
    @ dpsd_nw_v5.OVL.22: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap v20
    diode_dpsd_nw_v5 AND v20
}
dpsd_nw_v5.OVL.23 {
    @ dpsd_nw_v5.OVL.23: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap poly:model
    diode_dpsd_nw_v5 AND polyModel
}
dpsd_nw_v5.OVL.24 {
    @ dpsd_nw_v5.OVL.24: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap pwde
    diode_dpsd_nw_v5 AND pwde
}
dpsd_nw_v5.OVL.25 {
    @ dpsd_nw_v5.OVL.25: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap pwell:res
    diode_dpsd_nw_v5 AND pwres
}
dpsd_nw_v5.OVL.26 {
    @ dpsd_nw_v5.OVL.26: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap pnp
    diode_dpsd_nw_v5 AND pnp
}
dpsd_nw_v5.OVL.27 {
    @ dpsd_nw_v5.OVL.27: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap npn
    diode_dpsd_nw_v5 AND npn
}
dpsd_nw_v5.OVL.28 {
    @ dpsd_nw_v5.OVL.28: Illegal dpsd_nw_v5 device: dpsd_nw_v5 must not overlap areaid:photo
    diode_dpsd_nw_v5 AND PHdiodeID
}
diode_dpsd_nw_lvt = ((((diodeID AND psdm) AND nwell) AND diffi) AND lvtn) NOT (OR thkox v5 v12 v20 hvtp ESDID LVID)
dpsd_nw_lvt.OVL.1 {
    @ dpsd_nw_lvt.OVL.1: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap pwbm
    diode_dpsd_nw_lvt AND pwbm
}
dpsd_nw_lvt.OVL.2 {
    @ dpsd_nw_lvt.OVL.2: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap hvtp
    diode_dpsd_nw_lvt AND hvtp
}
dpsd_nw_lvt.OVL.3 {
    @ dpsd_nw_lvt.OVL.3: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap tunm
    diode_dpsd_nw_lvt AND tunm
}
dpsd_nw_lvt.OVL.4 {
    @ dpsd_nw_lvt.OVL.4: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap rpm
    diode_dpsd_nw_lvt AND rpm
}
dpsd_nw_lvt.OVL.5 {
    @ dpsd_nw_lvt.OVL.5: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap rrpm
    diode_dpsd_nw_lvt AND rrpm
}
dpsd_nw_lvt.OVL.6 {
    @ dpsd_nw_lvt.OVL.6: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap urpm
    diode_dpsd_nw_lvt AND urpm
}
dpsd_nw_lvt.OVL.7 {
    @ dpsd_nw_lvt.OVL.7: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap poly
    diode_dpsd_nw_lvt AND polyi
}
dpsd_nw_lvt.OVL.8 {
    @ dpsd_nw_lvt.OVL.8: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap ldntm
    diode_dpsd_nw_lvt AND ldntm
}
dpsd_nw_lvt.OVL.9 {
    @ dpsd_nw_lvt.OVL.9: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap npc
    diode_dpsd_nw_lvt AND npc
}
dpsd_nw_lvt.OVL.10 {
    @ dpsd_nw_lvt.OVL.10: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap nsdm
    diode_dpsd_nw_lvt AND nsdm
}
dpsd_nw_lvt.OVL.11 {
    @ dpsd_nw_lvt.OVL.11: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap nsm
    diode_dpsd_nw_lvt AND nsm
}
dpsd_nw_lvt.OVL.12 {
    @ dpsd_nw_lvt.OVL.12: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap skip_pad
    diode_dpsd_nw_lvt AND skip_pad
}
dpsd_nw_lvt.OVL.13 {
    @ dpsd_nw_lvt.OVL.13: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap fuse
    diode_dpsd_nw_lvt AND fuse
}
dpsd_nw_lvt.OVL.14 {
    @ dpsd_nw_lvt.OVL.14: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap diff:res
    diode_dpsd_nw_lvt AND diffres
}
dpsd_nw_lvt.OVL.15 {
    @ dpsd_nw_lvt.OVL.15: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap poly:res
    diode_dpsd_nw_lvt AND polyres
}
dpsd_nw_lvt.OVL.16 {
    @ dpsd_nw_lvt.OVL.16: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap li:res
    diode_dpsd_nw_lvt AND lires
}
dpsd_nw_lvt.OVL.17 {
    @ dpsd_nw_lvt.OVL.17: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap areaid:lvNative
    diode_dpsd_nw_lvt AND LVID
}
dpsd_nw_lvt.OVL.18 {
    @ dpsd_nw_lvt.OVL.18: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap pnp
    diode_dpsd_nw_lvt AND pnp
}
dpsd_nw_lvt.OVL.19 {
    @ dpsd_nw_lvt.OVL.19: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap npn
    diode_dpsd_nw_lvt AND npn
}
dpsd_nw_lvt.OVL.20 {
    @ dpsd_nw_lvt.OVL.20: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap areaid:photo
    diode_dpsd_nw_lvt AND PHdiodeID
}
dpsd_nw_lvt.OVL.21 {
    @ dpsd_nw_lvt.OVL.21: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap areaid:extendedDrain
    diode_dpsd_nw_lvt AND ENID
}
dpsd_nw_lvt.OVL.22 {
    @ dpsd_nw_lvt.OVL.22: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap areaid:core
    diode_dpsd_nw_lvt AND COREID
}
dpsd_nw_lvt.OVL.23 {
    @ dpsd_nw_lvt.OVL.23: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap areaid:seal
    diode_dpsd_nw_lvt AND SEALID
}
dpsd_nw_lvt.OVL.24 {
    @ dpsd_nw_lvt.OVL.24: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap v5
    diode_dpsd_nw_lvt AND v5
}
dpsd_nw_lvt.OVL.25 {
    @ dpsd_nw_lvt.OVL.25: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap v12
    diode_dpsd_nw_lvt AND v12
}
dpsd_nw_lvt.OVL.26 {
    @ dpsd_nw_lvt.OVL.26: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap v20
    diode_dpsd_nw_lvt AND v20
}
dpsd_nw_lvt.OVL.27 {
    @ dpsd_nw_lvt.OVL.27: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap thkox
    diode_dpsd_nw_lvt AND thkox
}
dpsd_nw_lvt.OVL.28 {
    @ dpsd_nw_lvt.OVL.28: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap poly:model
    diode_dpsd_nw_lvt AND polyModel
}
dpsd_nw_lvt.OVL.29 {
    @ dpsd_nw_lvt.OVL.29: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap pwde
    diode_dpsd_nw_lvt AND pwde
}
dpsd_nw_lvt.OVL.30 {
    @ dpsd_nw_lvt.OVL.30: Illegal dpsd_nw_lvt device: dpsd_nw_lvt must not overlap pwell:res
    diode_dpsd_nw_lvt AND pwres
}
diode_dpsd_nw_hvt = ((((diodeID AND psdm) AND nwell) AND diffi) AND hvtp) NOT (OR thkox v5 v12 v20 lvtn ESDID LVID)
dpsd_nw_hvt.OVL.1 {
    @ dpsd_nw_hvt.OVL.1: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap pwbm
    diode_dpsd_nw_hvt AND pwbm
}
dpsd_nw_hvt.OVL.2 {
    @ dpsd_nw_hvt.OVL.2: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap tunm
    diode_dpsd_nw_hvt AND tunm
}
dpsd_nw_hvt.OVL.3 {
    @ dpsd_nw_hvt.OVL.3: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap thkox
    diode_dpsd_nw_hvt AND thkox
}
dpsd_nw_hvt.OVL.4 {
    @ dpsd_nw_hvt.OVL.4: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap rpm
    diode_dpsd_nw_hvt AND rpm
}
dpsd_nw_hvt.OVL.5 {
    @ dpsd_nw_hvt.OVL.5: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap rrpm
    diode_dpsd_nw_hvt AND rrpm
}
dpsd_nw_hvt.OVL.6 {
    @ dpsd_nw_hvt.OVL.6: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap urpm
    diode_dpsd_nw_hvt AND urpm
}
dpsd_nw_hvt.OVL.7 {
    @ dpsd_nw_hvt.OVL.7: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap poly
    diode_dpsd_nw_hvt AND polyi
}
dpsd_nw_hvt.OVL.8 {
    @ dpsd_nw_hvt.OVL.8: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap ldntm
    diode_dpsd_nw_hvt AND ldntm
}
dpsd_nw_hvt.OVL.9 {
    @ dpsd_nw_hvt.OVL.9: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap npc
    diode_dpsd_nw_hvt AND npc
}
dpsd_nw_hvt.OVL.10 {
    @ dpsd_nw_hvt.OVL.10: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap nsdm
    diode_dpsd_nw_hvt AND nsdm
}
dpsd_nw_hvt.OVL.11 {
    @ dpsd_nw_hvt.OVL.11: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap nsm
    diode_dpsd_nw_hvt AND nsm
}
dpsd_nw_hvt.OVL.12 {
    @ dpsd_nw_hvt.OVL.12: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap skip_pad
    diode_dpsd_nw_hvt AND skip_pad
}
dpsd_nw_hvt.OVL.13 {
    @ dpsd_nw_hvt.OVL.13: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap fuse
    diode_dpsd_nw_hvt AND fuse
}
dpsd_nw_hvt.OVL.14 {
    @ dpsd_nw_hvt.OVL.14: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap areaid:photo
    diode_dpsd_nw_hvt AND PHdiodeID
}
dpsd_nw_hvt.OVL.15 {
    @ dpsd_nw_hvt.OVL.15: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap areaid:extendedDrain
    diode_dpsd_nw_hvt AND ENID
}
dpsd_nw_hvt.OVL.16 {
    @ dpsd_nw_hvt.OVL.16: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap areaid:seal
    diode_dpsd_nw_hvt AND SEALID
}
dpsd_nw_hvt.OVL.17 {
    @ dpsd_nw_hvt.OVL.17: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap v5
    diode_dpsd_nw_hvt AND v5
}
dpsd_nw_hvt.OVL.18 {
    @ dpsd_nw_hvt.OVL.18: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap v12
    diode_dpsd_nw_hvt AND v12
}
dpsd_nw_hvt.OVL.19 {
    @ dpsd_nw_hvt.OVL.19: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap v20
    diode_dpsd_nw_hvt AND v20
}
dpsd_nw_hvt.OVL.20 {
    @ dpsd_nw_hvt.OVL.20: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap poly:model
    diode_dpsd_nw_hvt AND polyModel
}
dpsd_nw_hvt.OVL.21 {
    @ dpsd_nw_hvt.OVL.21: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap pwde
    diode_dpsd_nw_hvt AND pwde
}
dpsd_nw_hvt.OVL.22 {
    @ dpsd_nw_hvt.OVL.22: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap diff:res
    diode_dpsd_nw_hvt AND diffres
}
dpsd_nw_hvt.OVL.23 {
    @ dpsd_nw_hvt.OVL.23: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap poly:res
    diode_dpsd_nw_hvt AND polyres
}
dpsd_nw_hvt.OVL.24 {
    @ dpsd_nw_hvt.OVL.24: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap pwell:res
    diode_dpsd_nw_hvt AND pwres
}
dpsd_nw_hvt.OVL.25 {
    @ dpsd_nw_hvt.OVL.25: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap areaid:lvNative
    diode_dpsd_nw_hvt AND LVID
}
dpsd_nw_hvt.OVL.26 {
    @ dpsd_nw_hvt.OVL.26: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap pnp
    diode_dpsd_nw_hvt AND pnp
}
dpsd_nw_hvt.OVL.27 {
    @ dpsd_nw_hvt.OVL.27: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap npn
    diode_dpsd_nw_hvt AND npn
}
dpsd_nw_hvt.OVL.28 {
    @ dpsd_nw_hvt.OVL.28: Illegal dpsd_nw_hvt device: dpsd_nw_hvt must not overlap areaid:core
    diode_dpsd_nw_hvt AND COREID
}


// BJT:


pnp1x = (pnp INTERACT (RECTANGLE (pnp AND diffi) == 0.68 ASPECT == 1)) NOT (OR thkox v5 v12 v20)
pnp.OVL.1 {
    @ pnp.OVL.1: Illegal pnp device: pnp must not overlap dnwell
    pnp1x AND dnwell
}
pnp.OVL.2 {
    @ pnp.OVL.2: Illegal pnp device: pnp must not overlap pwbm
    pnp1x AND pwbm
}
pnp.OVL.3 {
    @ pnp.OVL.3: Illegal pnp device: pnp must not overlap pwde
    pnp1x AND pwde
}
pnp.OVL.4 {
    @ pnp.OVL.4: Illegal pnp device: pnp must not overlap id_dummy
    pnp1x AND id_dummy
}
pnp.OVL.5 {
    @ pnp.OVL.5: Illegal pnp device: pnp must not overlap lvtn
    pnp1x AND lvtn
}
pnp.OVL.6 {
    @ pnp.OVL.6: Illegal pnp device: pnp must not overlap tunm
    pnp1x AND tunm
}
pnp.OVL.7 {
    @ pnp.OVL.7: Illegal pnp device: pnp must not overlap thkox
    pnp1x AND thkox
}
pnp.OVL.8 {
    @ pnp.OVL.8: Illegal pnp device: pnp must not overlap rpm
    pnp1x AND rpm
}
pnp.OVL.9 {
    @ pnp.OVL.9: Illegal pnp device: pnp must not overlap rrpm
    pnp1x AND rrpm
}
pnp.OVL.10 {
    @ pnp.OVL.10: Illegal pnp device: pnp must not overlap urpm
    pnp1x AND urpm
}
pnp.OVL.11 {
    @ pnp.OVL.11: Illegal pnp device: pnp must not overlap poly
    pnp1x AND polyi
}
pnp.OVL.12 {
    @ pnp.OVL.12: Illegal pnp device: pnp must not overlap ldntm
    pnp1x AND ldntm
}
pnp.OVL.13 {
    @ pnp.OVL.13: Illegal pnp device: pnp must not overlap npc
    pnp1x AND npc
}
pnp.OVL.14 {
    @ pnp.OVL.14: Illegal pnp device: pnp must not overlap nsm
    pnp1x AND nsm
}
pnp.OVL.15 {
    @ pnp.OVL.15: Illegal pnp device: pnp must not overlap skip_pad
    pnp1x AND skip_pad
}
pnp.OVL.16 {
    @ pnp.OVL.16: Illegal pnp device: pnp must not overlap fuse
    pnp1x AND fuse
}
pnp.OVL.17 {
    @ pnp.OVL.17: Illegal pnp device: pnp must not overlap diff:res
    pnp1x AND diffres
}
pnp.OVL.18 {
    @ pnp.OVL.18: Illegal pnp device: pnp must not overlap pwell:res
    pnp1x AND pwres
}
pnp.OVL.19 {
    @ pnp.OVL.19: Illegal pnp device: pnp must not overlap poly:res
    pnp1x AND polyres
}
pnp.OVL.20 {
    @ pnp.OVL.20: Illegal pnp device: pnp must not overlap poly:model
    pnp1x AND polyModel
}
pnp.OVL.21 {
    @ pnp.OVL.21: Illegal pnp device: pnp must not overlap li:res
    pnp1x AND lires
}
pnp.OVL.22 {
    @ pnp.OVL.22: Illegal pnp device: pnp must not overlap skip_res
    pnp1x AND skip_res
}
pnp.OVL.23 {
    @ pnp.OVL.23: Illegal pnp device: pnp must not overlap skip_res
    pnp1x AND skip_res
}
pnp.OVL.24 {
    @ pnp.OVL.24: Illegal pnp device: pnp must not overlap skip_res
    pnp1x AND skip_res
}
pnp.OVL.25 {
    @ pnp.OVL.25: Illegal pnp device: pnp must not overlap skip_res
    pnp1x AND skip_res
}
pnp.OVL.26 {
    @ pnp.OVL.26: Illegal pnp device: pnp must not overlap skip_res
    pnp1x AND skip_res
}
pnp.OVL.27 {
    @ pnp.OVL.27: Illegal pnp device: pnp must not overlap areaid:lvNative
    pnp1x AND LVID
}
pnp.OVL.28 {
    @ pnp.OVL.28: Illegal pnp device: pnp must not overlap npn
    pnp1x AND npn
}
pnp.OVL.29 {
    @ pnp.OVL.29: Illegal pnp device: pnp must not overlap areaid:diode
    pnp1x AND DiodeID
}
pnp.OVL.30 {
    @ pnp.OVL.30: Illegal pnp device: pnp must not overlap areaid:photo
    pnp1x AND PHdiodeID
}
pnp.OVL.31 {
    @ pnp.OVL.31: Illegal pnp device: pnp must not overlap areaid:core
    pnp1x AND COREID
}
pnp.OVL.32 {
    @ pnp.OVL.32: Illegal pnp device: pnp must not overlap areaid:esd
    pnp1x AND ESDID
}
pnp.OVL.33 {
    @ pnp.OVL.33: Illegal pnp device: pnp must not overlap areaid:extendedDrain
    pnp1x AND ENID
}
pnp.OVL.34 {
    @ pnp.OVL.34: Illegal pnp device: pnp must not overlap areaid:seal
    pnp1x AND SEALID
}
pnp.OVL.35 {
    @ pnp.OVL.35: Illegal pnp device: pnp must not overlap v5
    pnp1x AND v5
}
pnp.OVL.36 {
    @ pnp.OVL.36: Illegal pnp device: pnp must not overlap v12
    pnp1x AND v12
}
pnp.OVL.37 {
    @ pnp.OVL.37: Illegal pnp device: pnp must not overlap v20
    pnp1x AND v20
}
pnp5x = (pnp INTERACT (RECTANGLE (pnp AND diffi) == 3.4 ASPECT == 1)) NOT (OR thkox v5 v12 v20)
pnp_5x.OVL.1 {
    @ pnp.OVL_5x.1: Illegal pnp_5x device: pnp_5x must not overlap dnwell
    pnp5x AND dnwell
}
pnp_5x.OVL.2 {
    @ pnp.OVL_5x.2: Illegal pnp_5x device: pnp_5x must not overlap pwbm
    pnp5x AND pwbm
}
pnp_5x.OVL.3 {
    @ pnp.OVL_5x.3: Illegal pnp_5x device: pnp_5x must not overlap pwde
    pnp5x AND pwde
}
pnp_5x.OVL.4 {
    @ pnp.OVL_5x.4: Illegal pnp_5x device: pnp_5x must not overlap id_dummy
    pnp5x AND id_dummy
}
pnp_5x.OVL.5 {
    @ pnp.OVL_5x.5: Illegal pnp_5x device: pnp_5x must not overlap lvtn
    pnp5x AND lvtn
}
pnp_5x.OVL.6 {
    @ pnp.OVL_5x.6: Illegal pnp_5x device: pnp_5x must not overlap tunm
    pnp5x AND tunm
}
pnp_5x.OVL.7 {
    @ pnp.OVL_5x.7: Illegal pnp_5x device: pnp_5x must not overlap thkox
    pnp5x AND thkox
}
pnp_5x.OVL.8 {
    @ pnp.OVL_5x.8: Illegal pnp_5x device: pnp_5x must not overlap rpm
    pnp5x AND rpm
}
pnp_5x.OVL.9 {
    @ pnp.OVL_5x.9: Illegal pnp_5x device: pnp_5x must not overlap rrpm
    pnp5x AND rrpm
}
pnp_5x.OVL.10 {
    @ pnp.OVL_5x.10: Illegal pnp_5x device: pnp_5x must not overlap urpm
    pnp5x AND urpm
}
pnp_5x.OVL.11 {
    @ pnp.OVL_5x.11: Illegal pnp_5x device: pnp_5x must not overlap poly
    pnp5x AND polyi
}
pnp_5x.OVL.12 {
    @ pnp.OVL_5x.12: Illegal pnp_5x device: pnp_5x must not overlap ldntm
    pnp5x AND ldntm
}
pnp_5x.OVL.13 {
    @ pnp.OVL_5x.13: Illegal pnp_5x device: pnp_5x must not overlap npc
    pnp5x AND npc
}
pnp_5x.OVL.14 {
    @ pnp.OVL_5x.14: Illegal pnp_5x device: pnp_5x must not overlap nsm
    pnp5x AND nsm
}
pnp_5x.OVL.15 {
    @ pnp.OVL_5x.15: Illegal pnp_5x device: pnp_5x must not overlap skip_pad
    pnp5x AND skip_pad
}
pnp_5x.OVL.16 {
    @ pnp.OVL_5x.16: Illegal pnp_5x device: pnp_5x must not overlap fuse
    pnp5x AND fuse
}
pnp_5x.OVL.17 {
    @ pnp.OVL_5x.17: Illegal pnp_5x device: pnp_5x must not overlap diff:res
    pnp5x AND diffres
}
pnp_5x.OVL.18 {
    @ pnp.OVL_5x.18: Illegal pnp_5x device: pnp_5x must not overlap pwell:res
    pnp5x AND pwres
}
pnp_5x.OVL.19 {
    @ pnp.OVL_5x.19: Illegal pnp_5x device: pnp_5x must not overlap poly:res
    pnp5x AND polyres
}
pnp_5x.OVL.20 {
    @ pnp.OVL_5x.20: Illegal pnp_5x device: pnp_5x must not overlap poly:model
    pnp5x AND polyModel
}
pnp_5x.OVL.21 {
    @ pnp.OVL_5x.21: Illegal pnp_5x device: pnp_5x must not overlap li:res
    pnp5x AND lires
}
pnp_5x.OVL.22 {
    @ pnp.OVL_5x.22: Illegal pnp_5x device: pnp_5x must not overlap skip_res
    pnp5x AND skip_res
}
pnp_5x.OVL.23 {
    @ pnp.OVL_5x.23: Illegal pnp_5x device: pnp_5x must not overlap skip_res
    pnp5x AND skip_res
}
pnp_5x.OVL.24 {
    @ pnp.OVL_5x.24: Illegal pnp_5x device: pnp_5x must not overlap skip_res
    pnp5x AND skip_res
}
pnp_5x.OVL.25 {
    @ pnp.OVL_5x.25: Illegal pnp_5x device: pnp_5x must not overlap skip_res
    pnp5x AND skip_res
}
pnp_5x.OVL.26 {
    @ pnp.OVL_5x.26: Illegal pnp_5x device: pnp_5x must not overlap skip_res
    pnp5x AND skip_res
}
pnp_5x.OVL.27 {
    @ pnp.OVL_5x.27: Illegal pnp_5x device: pnp_5x must not overlap areaid:lvNative
    pnp5x AND LVID
}
pnp_5x.OVL.28 {
    @ pnp.OVL_5x.28: Illegal pnp_5x device: pnp_5x must not overlap npn
    pnp5x AND npn
}
pnp_5x.OVL.29 {
    @ pnp.OVL_5x.29: Illegal pnp_5x device: pnp_5x must not overlap areaid:diode
    pnp5x AND DiodeID
}
pnp_5x.OVL.30 {
    @ pnp.OVL_5x.30: Illegal pnp_5x device: pnp_5x must not overlap areaid:photo
    pnp5x AND PHdiodeID
}
pnp_5x.OVL.31 {
    @ pnp.OVL_5x.31: Illegal pnp_5x device: pnp_5x must not overlap areaid:core
    pnp5x AND COREID
}
pnp_5x.OVL.32 {
    @ pnp.OVL_5x.32: Illegal pnp_5x device: pnp_5x must not overlap areaid:esd
    pnp5x AND ESDID
}
pnp_5x.OVL.33 {
    @ pnp.OVL_5x.33: Illegal pnp_5x device: pnp_5x must not overlap areaid:extendedDrain
    pnp5x AND ENID
}
pnp_5x.OVL.34 {
    @ pnp.OVL_5x.34: Illegal pnp_5x device: pnp_5x must not overlap areaid:seal
    pnp5x AND SEALID
}
pnp_5x.OVL.35 {
    @ pnp.OVL_5x.35: Illegal pnp_5x device: pnp_5x must not overlap v5
    pnp5x AND v5
}
pnp_5x.OVL.36 {
    @ pnp.OVL_5x.36: Illegal pnp_5x device: pnp_5x must not overlap v12
    pnp5x AND v12
}
pnp_5x.OVL.37 {
    @ pnp.OVL_5x.37: Illegal pnp_5x device: pnp_5x must not overlap v20
    pnp5x AND v20
}
npn_ndiff = ((npn AND diffi) AND nsdm) INSIDE npn_1
npn_emit = npn_ndiff NOT nwell
donut_nw = HOLES nwell
dnw_over_nw_hole = dnwell ENCLOSE donut_nw
npn_1 = (nwell or (HOLES nwell)) ENCLOSE dnw_over_nw_hole
npn1x = (npn_1 ENCLOSE (AREA npn_emit == 1)) NOT (OR thkox v5 v12 v20)
npn.OVL.1 {
    @ npn.OVL_5x.1: Illegal npn device: npn must not overlap pwbm
    npn1x AND pwbm
}
npn.OVL.2 {
    @ npn.OVL_5x.2: Illegal npn device: npn must not overlap pwde
    npn1x AND pwde
}
npn.OVL.3 {
    @ npn.OVL_5x.3: Illegal npn device: npn must not overlap lvtn
    npn1x AND lvtn
}
npn.OVL.4 {
    @ npn.OVL_5x.4: Illegal npn device: npn must not overlap tunm
    npn1x AND tunm
}
npn.OVL.5 {
    @ npn.OVL_5x.5: Illegal npn device: npn must not overlap rpm
    npn1x AND rpm
}
npn.OVL.6 {
    @ npn.OVL_5x.6: Illegal npn device: npn must not overlap rrpm
    npn1x AND rrpm
}
npn.OVL.7 {
    @ npn.OVL_5x.7: Illegal npn device: npn must not overlap urpm
    npn1x AND urpm
}
npn.OVL.8 {
    @ npn.OVL_5x.8: Illegal npn device: npn must not overlap nsm
    npn1x AND nsm
}
npn.OVL.9 {
    @ npn.OVL_5x.9: Illegal npn device: npn must not overlap skip_pad
    npn1x AND skip_pad
}
npn.OVL.10 {
    @ npn.OVL_5x.10: Illegal npn device: npn must not overlap fuse
    npn1x AND fuse
}
npn.OVL.11 {
    @ npn.OVL_5x.11: Illegal npn device: npn must not overlap diff:res
    npn1x AND diffres
}
npn.OVL.12 {
    @ npn.OVL_5x.12: Illegal npn device: npn must not overlap pwell:res
    npn1x AND pwres
}
npn.OVL.13 {
    @ npn.OVL_5x.13: Illegal npn device: npn must not overlap poly:res
    npn1x AND polyres
}
npn.OVL.14 {
    @ npn.OVL_5x.14: Illegal npn device: npn must not overlap poly:model
    npn1x AND polyModel
}
npn.OVL.15 {
    @ npn.OVL_5x.15: Illegal npn device: npn must not overlap li:res
    npn1x AND lires
}
npn.OVL.16 {
    @ npn.OVL_5x.16: Illegal npn device: npn must not overlap areaid:lvNative
    npn1x AND LVID
}
npn.OVL.17 {
    @ npn.OVL_5x.17: Illegal npn device: npn must not overlap pnp
    npn1x AND pnp
}
npn.OVL.18 {
    @ npn.OVL_5x.18: Illegal npn device: npn must not overlap areaid:diode
    npn1x AND DiodeID
}
npn.OVL.19 {
    @ npn.OVL_5x.19: Illegal npn device: npn must not overlap areaid:photo
    npn1x AND PHdiodeID
}
npn.OVL.20 {
    @ npn.OVL_5x.20: Illegal npn device: npn must not overlap areaid:core
    npn1x AND COREID
}
npn.OVL.21 {
    @ npn.OVL_5x.21: Illegal npn device: npn must not overlap areaid:esd
    npn1x AND ESDID
}
npn.OVL.22 {
    @ npn.OVL_5x.22: Illegal npn device: npn must not overlap areaid:extendedDrain
    npn1x AND ENID
}
npn.OVL.23 {
    @ npn.OVL_5x.23: Illegal npn device: npn must not overlap areaid:seal
    npn1x AND SEALID
}
npn.OVL.24 {
    @ npn.OVL_5x.24: Illegal npn device: npn must not overlap v5
    npn1x AND v5
}
npn.OVL.25 {
    @ npn.OVL_5x.25: Illegal npn device: npn must not overlap v12
    npn1x AND v12
}
npn.OVL.26 {
    @ npn.OVL_5x.26: Illegal npn device: npn must not overlap v20
    npn1x AND v20
}
npn.OVL.27 {
    @ npn.OVL_5x.27: Illegal npn device: npn must not overlap thkox
    npn1x AND thkox
}
npn.OVL.28 {
    @ npn.OVL_5x.28: Illegal npn device: npn must not overlap poly
    npn1x AND polyi
}
npn_ndiff_oct_1 = EXPAND EDGE (ANGLE npn_ndiff == 45) OUTSIDE BY 0.005
npn_ndiff_oct = (VERTEX == 8 npn_ndiff) INTERACT npn_ndiff_oct_1 == 4
npn_v5 = (npn_1 ENCLOSE npn_ndiff_oct) AND (thkox AND v5)
npn_v5.OVL.1 {
    @ npn.OVL_v5.1: Illegal npn_v5 device: npn_v5 must not overlap pwbm
    npn_v5 AND pwbm
}
npn_v5.OVL.2 {
    @ npn.OVL_v5.2: Illegal npn_v5 device: npn_v5 must not overlap pwde
    npn_v5 AND pwde
}
npn_v5.OVL.3 {
    @ npn.OVL_v5.3: Illegal npn_v5 device: npn_v5 must not overlap lvtn
    npn_v5 AND lvtn
}
npn_v5.OVL.4 {
    @ npn.OVL_v5.4: Illegal npn_v5 device: npn_v5 must not overlap tunm
    npn_v5 AND tunm
}
npn_v5.OVL.5 {
    @ npn.OVL_v5.5: Illegal npn_v5 device: npn_v5 must not overlap rpm
    npn_v5 AND rpm
}
npn_v5.OVL.6 {
    @ npn.OVL_v5.6: Illegal npn_v5 device: npn_v5 must not overlap rrpm
    npn_v5 AND rrpm
}
npn_v5.OVL.7 {
    @ npn.OVL_v5.7: Illegal npn_v5 device: npn_v5 must not overlap urpm
    npn_v5 AND urpm
}
npn_v5.OVL.8 {
    @ npn.OVL_v5.8: Illegal npn_v5 device: npn_v5 must not overlap nsm
    npn_v5 AND nsm
}
npn_v5.OVL.9 {
    @ npn.OVL_v5.9: Illegal npn_v5 device: npn_v5 must not overlap skip_pad
    npn_v5 AND skip_pad
}
npn_v5.OVL.10 {
    @ npn.OVL_v5.10: Illegal npn_v5 device: npn_v5 must not overlap fuse
    npn_v5 AND fuse
}
npn_v5.OVL.11 {
    @ npn.OVL_v5.11: Illegal npn_v5 device: npn_v5 must not overlap diff:res
    npn_v5 AND diffres
}
npn_v5.OVL.12 {
    @ npn.OVL_v5.12: Illegal npn_v5 device: npn_v5 must not overlap pwell:res
    npn_v5 AND pwres
}
npn_v5.OVL.13 {
    @ npn.OVL_v5.13: Illegal npn_v5 device: npn_v5 must not overlap poly:res
    npn_v5 AND polyres
}
npn_v5.OVL.14 {
    @ npn.OVL_v5.14: Illegal npn_v5 device: npn_v5 must not overlap poly:model
    npn_v5 AND polyModel
}
npn_v5.OVL.15 {
    @ npn.OVL_v5.15: Illegal npn_v5 device: npn_v5 must not overlap li:res
    npn_v5 AND lires
}
npn_v5.OVL.16 {
    @ npn.OVL_v5.16: Illegal npn_v5 device: npn_v5 must not overlap areaid:lvNative
    npn_v5 AND LVID
}
npn_v5.OVL.17 {
    @ npn.OVL_v5.17: Illegal npn_v5 device: npn_v5 must not overlap pnp
    npn_v5 AND pnp
}
npn_v5.OVL.18 {
    @ npn.OVL_v5.18: Illegal npn_v5 device: npn_v5 must not overlap areaid:diode
    npn_v5 AND DiodeID
}
npn_v5.OVL.19 {
    @ npn.OVL_v5.19: Illegal npn_v5 device: npn_v5 must not overlap areaid:photo
    npn_v5 AND PHdiodeID
}
npn_v5.OVL.20 {
    @ npn.OVL_v5.20: Illegal npn_v5 device: npn_v5 must not overlap areaid:core
    npn_v5 AND COREID
}
npn_v5.OVL.21 {
    @ npn.OVL_v5.21: Illegal npn_v5 device: npn_v5 must not overlap areaid:esd
    npn_v5 AND ESDID
}
npn_v5.OVL.22 {
    @ npn.OVL_v5.22: Illegal npn_v5 device: npn_v5 must not overlap areaid:extendedDrain
    npn_v5 AND ENID
}
npn_v5.OVL.23 {
    @ npn.OVL_v5.23: Illegal npn_v5 device: npn_v5 must not overlap areaid:seal
    npn_v5 AND SEALID
}
npn_v5.OVL.24 {
    @ npn.OVL_v5.24: Illegal npn_v5 device: npn_v5 must not overlap v12
    npn_v5 AND v12
}
npn_v5.OVL.25 {
    @ npn.OVL_v5.25: Illegal npn_v5 device: npn_v5 must not overlap v20
    npn_v5 AND v20
}
npn_1x2 = (npn_1 ENCLOSE (AREA npn_emit == 2)) NOT (OR thkox v5 v12 v20)
npn_1x2.OVL.1 {
    @ npn.OVL_1x2.1: Illegal npn_1x2 device: npn_1x2 must not overlap pwbm
    npn_1x2 AND pwbm
}
npn_1x2.OVL.2 {
    @ npn.OVL_1x2.2: Illegal npn_1x2 device: npn_1x2 must not overlap pwde
    npn_1x2 AND pwde
}
npn_1x2.OVL.3 {
    @ npn.OVL_1x2.3: Illegal npn_1x2 device: npn_1x2 must not overlap lvtn
    npn_1x2 AND lvtn
}
npn_1x2.OVL.4 {
    @ npn.OVL_1x2.4: Illegal npn_1x2 device: npn_1x2 must not overlap tunm
    npn_1x2 AND tunm
}
npn_1x2.OVL.5 {
    @ npn.OVL_1x2.5: Illegal npn_1x2 device: npn_1x2 must not overlap thkox
    npn_1x2 AND thkox
}
npn_1x2.OVL.6 {
    @ npn.OVL_1x2.6: Illegal npn_1x2 device: npn_1x2 must not overlap poly
    npn_1x2 AND polyi
}
npn_1x2.OVL.7 {
    @ npn.OVL_1x2.7: Illegal npn_1x2 device: npn_1x2 must not overlap nsm
    npn_1x2 AND nsm
}
npn_1x2.OVL.8 {
    @ npn.OVL_1x2.8: Illegal npn_1x2 device: npn_1x2 must not overlap skip_pad
    npn_1x2 AND skip_pad
}
npn_1x2.OVL.9 {
    @ npn.OVL_1x2.9: Illegal npn_1x2 device: npn_1x2 must not overlap fuse
    npn_1x2 AND fuse
}
npn_1x2.OVL.10 {
    @ npn.OVL_1x2.10: Illegal npn_1x2 device: npn_1x2 must not overlap diff:res
    npn_1x2 AND diffres
}
npn_1x2.OVL.11 {
    @ npn.OVL_1x2.11: Illegal npn_1x2 device: npn_1x2 must not overlap pwell:res
    npn_1x2 AND pwres
}
npn_1x2.OVL.12 {
    @ npn.OVL_1x2.12: Illegal npn_1x2 device: npn_1x2 must not overlap poly:res
    npn_1x2 AND polyres
}
npn_1x2.OVL.13 {
    @ npn.OVL_1x2.13: Illegal npn_1x2 device: npn_1x2 must not overlap poly:model
    npn_1x2 AND polyModel
}
npn_1x2.OVL.14 {
    @ npn.OVL_1x2.14: Illegal npn_1x2 device: npn_1x2 must not overlap li:res
    npn_1x2 AND lires
}
npn_1x2.OVL.15 {
    @ npn.OVL_1x2.15: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:lvNative
    npn_1x2 AND LVID
}
npn_1x2.OVL.16 {
    @ npn.OVL_1x2.16: Illegal npn_1x2 device: npn_1x2 must not overlap pnp
    npn_1x2 AND pnp
}
npn_1x2.OVL.17 {
    @ npn.OVL_1x2.17: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:diode
    npn_1x2 AND DiodeID
}
npn_1x2.OVL.18 {
    @ npn.OVL_1x2.18: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:photo
    npn_1x2 AND PHdiodeID
}
npn_1x2.OVL.19 {
    @ npn.OVL_1x2.19: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:core
    npn_1x2 AND COREID
}
npn_1x2.OVL.20 {
    @ npn.OVL_1x2.20: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:esd
    npn_1x2 AND ESDID
}
npn_1x2.OVL.21 {
    @ npn.OVL_1x2.21: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:extendedDrain
    npn_1x2 AND ENID
}
npn_1x2.OVL.22 {
    @ npn.OVL_1x2.22: Illegal npn_1x2 device: npn_1x2 must not overlap areaid:seal
    npn_1x2 AND SEALID
}
npn_1x2.OVL.23 {
    @ npn.OVL_1x2.23: Illegal npn_1x2 device: npn_1x2 must not overlap v5
    npn_1x2 AND v5
}
npn_1x2.OVL.24 {
    @ npn.OVL_1x2.24: Illegal npn_1x2 device: npn_1x2 must not overlap v12
    npn_1x2 AND v12
}
npn_1x2.OVL.25 {
    @ npn.OVL_1x2.25: Illegal npn_1x2 device: npn_1x2 must not overlap v20
    npn_1x2 AND v20
}
npn_1x2.OVL.26 {
    @ npn.OVL_1x2.26: Illegal npn_1x2 device: npn_1x2 must not overlap rpm
    npn_1x2 AND rpm
}
npn_1x2.OVL.27 {
    @ npn.OVL_1x2.27: Illegal npn_1x2 device: npn_1x2 must not overlap rrpm
    npn_1x2 AND rrpm
}
npn_1x2.OVL.28 {
    @ npn.OVL_1x2.28: Illegal npn_1x2 device: npn_1x2 must not overlap urpm
    npn_1x2 AND urpm
}


// PAD:


pad.OVL.2 {
    @ pad.OVL.2: Illegal pad device: pad must not overlap nsm
    pad AND nsm
}
pad.OVL.3 {
    @ pad.OVL.3: Illegal pad device: pad must not overlap fuse
    pad AND fuse
}
pad.OVL.4 {
    @ pad.OVL.4: Illegal pad device: pad must not overlap areaid:seal
    pad AND SEALID
}
pad.OVL.5 {
    @ pad.OVL.5: Illegal pad device: pad must not overlap met4
    pad AND met4i
}
seal.OVL.1 {
    @ seal.OVL.1: Illegal seal device: areaid:seal must not overlap dnwell
    SEALID AND dnwell
}
seal.OVL.2 {
    @ seal.OVL.2: Illegal seal device: areaid:seal must not overlap pwbm
    SEALID AND pwbm
}
seal.OVL.3 {
    @ seal.OVL.3: Illegal seal device: areaid:seal must not overlap pwde
    SEALID AND pwde
}
seal.OVL.4 {
    @ seal.OVL.4: Illegal seal device: areaid:seal must not overlap nwell
    SEALID AND nwell
}
seal.OVL.5 {
    @ seal.OVL.5: Illegal seal device: areaid:seal must not overlap hvtp
    SEALID AND hvtp
}
seal.OVL.6 {
    @ seal.OVL.6: Illegal seal device: areaid:seal must not overlap lvtn
    SEALID AND lvtn
}
seal.OVL.7 {
    @ seal.OVL.7: Illegal seal device: areaid:seal must not overlap tunm
    SEALID AND tunm
}
seal.OVL.8 {
    @ seal.OVL.8: Illegal seal device: areaid:seal must not overlap thkox
    SEALID AND thkox
}
seal.OVL.9 {
    @ seal.OVL.9: Illegal seal device: areaid:seal must not overlap rpm
    SEALID AND rpm
}
seal.OVL.10 {
    @ seal.OVL.10: Illegal seal device: areaid:seal must not overlap rrpm
    SEALID AND rrpm
}
seal.OVL.11 {
    @ seal.OVL.11: Illegal seal device: areaid:seal must not overlap urpm
    SEALID AND urpm
}
seal.OVL.12 {
    @ seal.OVL.12: Illegal seal device: areaid:seal must not overlap poly
    SEALID AND polyi
}
seal.OVL.13 {
    @ seal.OVL.13: Illegal seal device: areaid:seal must not overlap ldntm
    SEALID AND ldntm
}
seal.OVL.14 {
    @ seal.OVL.14: Illegal seal device: areaid:seal must not overlap npc
    SEALID AND npc
}
seal.OVL.15 {
    @ seal.OVL.15: Illegal seal device: areaid:seal must not overlap nsdm
    SEALID AND nsdm
}
seal.OVL.16 {
    @ seal.OVL.16: Illegal seal device: areaid:seal must not overlap psdm
    SEALID AND psdm
}
seal.OVL.17 {
    @ seal.OVL.17: Illegal seal device: areaid:seal must not overlap licon
    SEALID AND licon
}
seal.OVL.18 {
    @ seal.OVL.18: Illegal seal device: areaid:seal must not overlap li
    SEALID AND li_i
}
seal.OVL.19 {
    @ seal.OVL.19: Illegal seal device: areaid:seal must not overlap capm
    SEALID AND capm
}
seal.OVL.20 {
    @ seal.OVL.20: Illegal seal device: areaid:seal must not overlap cap2m
    SEALID AND cap2m
}
seal.OVL.21 {
    @ seal.OVL.21: Illegal seal device: areaid:seal must not overlap met1
    SEALID AND met1i
}
seal.OVL.22 {
    @ seal.OVL.22: Illegal seal device: areaid:seal must not overlap met2
    SEALID AND met2i
}
seal.OVL.23 {
    @ seal.OVL.23: Illegal seal device: areaid:seal must not overlap met3
    SEALID AND met3i
}
seal.OVL.24 {
    @ seal.OVL.24: Illegal seal device: areaid:seal must not overlap met4
    SEALID AND met4i
}
seal.OVL.25 {
    @ seal.OVL.25: Illegal seal device: areaid:seal must not overlap met5
    SEALID AND met5i
}
seal.OVL.26 {
    @ seal.OVL.26: Illegal seal device: areaid:seal must not overlap pad
    SEALID AND pad
}
seal.OVL.27 {
    @ seal.OVL.27: Illegal seal device: areaid:seal must not overlap rdl
    SEALID AND rdl
}
seal.OVL.28 {
    @ seal.OVL.28: Illegal seal device: areaid:seal must not overlap fuse
    SEALID AND fuse
}
seal.OVL.29 {
    @ seal.OVL.29: Illegal seal device: areaid:seal must not overlap diff:res
    SEALID AND diffres
}
seal.OVL.30 {
    @ seal.OVL.30: Illegal seal device: areaid:seal must not overlap pwell:res
    SEALID AND pwres
}
seal.OVL.31 {
    @ seal.OVL.31: Illegal seal device: areaid:seal must not overlap poly:res
    SEALID AND polyres
}
seal.OVL.32 {
    @ seal.OVL.32: Illegal seal device: areaid:seal must not overlap li:res
    SEALID AND lires
}
seal.OVL.33 {
    @ seal.OVL.33: Illegal seal device: areaid:seal must not overlap met1:res
    SEALID AND m1res
}
seal.OVL.34 {
    @ seal.OVL.34: Illegal seal device: areaid:seal must not overlap met2:res
    SEALID AND m2res
}
seal.OVL.35 {
    @ seal.OVL.35: Illegal seal device: areaid:seal must not overlap met3:res
    SEALID AND m3res
}
seal.OVL.36 {
    @ seal.OVL.36: Illegal seal device: areaid:seal must not overlap met4:res
    SEALID AND m4res
}
seal.OVL.37 {
    @ seal.OVL.37: Illegal seal device: areaid:seal must not overlap met5:res
    SEALID AND m5res
}
seal.OVL.38 {
    @ seal.OVL.38: Illegal seal device: areaid:seal must not overlap areaid:lvNative
    SEALID AND LVID
}
seal.OVL.39 {
    @ seal.OVL.39: Illegal seal device: areaid:seal must not overlap pnp
    SEALID AND pnp
}
seal.OVL.40 {
    @ seal.OVL.40: Illegal seal device: areaid:seal must not overlap npn
    SEALID AND npn
}
seal.OVL.41 {
    @ seal.OVL.41: Illegal seal device: areaid:seal must not overlap localSub
    SEALID AND localSub
}
seal.OVL.42 {
    @ seal.OVL.42: Illegal seal device: areaid:seal must not overlap areaid:diode
    SEALID AND DiodeID
}
seal.OVL.43 {
    @ seal.OVL.43: Illegal seal device: areaid:seal must not overlap areaid:photo
    SEALID AND PHdiodeID
}
seal.OVL.44 {
    @ seal.OVL.44: Illegal seal device: areaid:seal must not overlap areaid:core
    SEALID AND COREID
}
seal.OVL.45 {
    @ seal.OVL.45: Illegal seal device: areaid:seal must not overlap areaid:esd
    SEALID AND ESDID
}
seal.OVL.46 {
    @ seal.OVL.46: Illegal seal device: areaid:seal must not overlap areaid:extendedDrain
    SEALID AND ENID
}
seal.OVL.47 {
    @ seal.OVL.47: Illegal seal device: areaid:seal must not overlap v5
    SEALID AND v5
}
seal.OVL.48 {
    @ seal.OVL.48: Illegal seal device: areaid:seal must not overlap v12
    SEALID AND v12
}
seal.OVL.49 {
    @ seal.OVL.49: Illegal seal device: areaid:seal must not overlap v20
    SEALID AND v20
}
seal.OVL.50 {
    @ seal.OVL.50: Illegal seal device: areaid:seal must not overlap poly:model
    SEALID AND polyModel
}


// FUSE:


// ESD MOS:


nmos_esd_5v = ((((gate AND nsdm) AND v5) AND ESDID) AND thkox) NOT (OR v12 v20 lvtn LVID pnp npn)
nmos_esd_5v.OVL.1 {
    @ nmos_esd_5v.OVL.1: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap pwbm
    nmos_esd_5v AND pwbm
}
nmos_esd_5v.OVL.2 {
    @ nmos_esd_5v.OVL.2: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap pwde
    nmos_esd_5v AND pwde
}
nmos_esd_5v.OVL.3 {
    @ nmos_esd_5v.OVL.3: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap hvtp
    nmos_esd_5v AND hvtp
}
nmos_esd_5v.OVL.4 {
    @ nmos_esd_5v.OVL.4: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap lvtn
    nmos_esd_5v AND lvtn
}
nmos_esd_5v.OVL.5 {
    @ nmos_esd_5v.OVL.5: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap tunm
    nmos_esd_5v AND tunm
}
nmos_esd_5v.OVL.6 {
    @ nmos_esd_5v.OVL.6: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap rpm
    nmos_esd_5v AND rpm
}
nmos_esd_5v.OVL.7 {
    @ nmos_esd_5v.OVL.7: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap rrpm
    nmos_esd_5v AND rrpm
}
nmos_esd_5v.OVL.8 {
    @ nmos_esd_5v.OVL.8: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap urpm
    nmos_esd_5v AND urpm
}
nmos_esd_5v.OVL.9 {
    @ nmos_esd_5v.OVL.9: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap ldntm
    nmos_esd_5v AND ldntm
}
nmos_esd_5v.OVL.10 {
    @ nmos_esd_5v.OVL.10: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap npc
    nmos_esd_5v AND npc
}
nmos_esd_5v.OVL.11 {
    @ nmos_esd_5v.OVL.11: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap psdm
    nmos_esd_5v AND psdm
}
nmos_esd_5v.OVL.12 {
    @ nmos_esd_5v.OVL.12: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap nsm
    nmos_esd_5v AND nsm
}
nmos_esd_5v.OVL.13 {
    @ nmos_esd_5v.OVL.13: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap skip_pad
    nmos_esd_5v AND skip_pad
}
nmos_esd_5v.OVL.14 {
    @ nmos_esd_5v.OVL.14: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap fuse
    nmos_esd_5v AND fuse
}
nmos_esd_5v.OVL.15 {
    @ nmos_esd_5v.OVL.15: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap diff:res
    nmos_esd_5v AND diffres
}
nmos_esd_5v.OVL.16 {
    @ nmos_esd_5v.OVL.16: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap pwell:res
    nmos_esd_5v AND pwres
}
nmos_esd_5v.OVL.17 {
    @ nmos_esd_5v.OVL.17: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap poly:res
    nmos_esd_5v AND polyres
}
nmos_esd_5v.OVL.18 {
    @ nmos_esd_5v.OVL.18: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap li:res
    nmos_esd_5v AND lires
}
nmos_esd_5v.OVL.19 {
    @ nmos_esd_5v.OVL.19: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:lvNative
    nmos_esd_5v AND LVID
}
nmos_esd_5v.OVL.20 {
    @ nmos_esd_5v.OVL.20: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap pnp
    nmos_esd_5v AND pnp
}
nmos_esd_5v.OVL.21 {
    @ nmos_esd_5v.OVL.21: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap npn
    nmos_esd_5v AND npn
}
nmos_esd_5v.OVL.22 {
    @ nmos_esd_5v.OVL.22: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:diode
    nmos_esd_5v AND DiodeID
}
nmos_esd_5v.OVL.23 {
    @ nmos_esd_5v.OVL.23: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:photo
    nmos_esd_5v AND PHdiodeID
}
nmos_esd_5v.OVL.24 {
    @ nmos_esd_5v.OVL.24: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:core
    nmos_esd_5v AND COREID
}
nmos_esd_5v.OVL.25 {
    @ nmos_esd_5v.OVL.25: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:extendedDrain
    nmos_esd_5v AND ENID
}
nmos_esd_5v.OVL.26 {
    @ nmos_esd_5v.OVL.26: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap areaid:seal
    nmos_esd_5v AND SEALID
}
nmos_esd_5v.OVL.27 {
    @ nmos_esd_5v.OVL.27: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap v12
    nmos_esd_5v AND v12
}
nmos_esd_5v.OVL.28 {
    @ nmos_esd_5v.OVL.28: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap v20
    nmos_esd_5v AND v20
}
nmos_esd_5v.OVL.29 {
    @ nmos_esd_5v.OVL.29: Illegal nmos_esd_5v device: nmos_esd_5v must not overlap nwell
    nmos_esd_5v AND nwell
}
nmos_esd_nat_5v = ((((gate and nsdm) AND lvtn) AND v5) AND thkox) NOT (OR v12 v20 LVID pnp npn)
nmos_esd_nat_5v.OVL.1 {
    @ nmos_esd_nat_5v.OVL.1: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap pwbm
    nmos_esd_nat_5v AND pwbm
}
nmos_esd_nat_5v.OVL.2 {
    @ nmos_esd_nat_5v.OVL.2: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap pwde
    nmos_esd_nat_5v AND pwde
}
nmos_esd_nat_5v.OVL.3 {
    @ nmos_esd_nat_5v.OVL.3: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap nwell
    nmos_esd_nat_5v AND nwell
}
nmos_esd_nat_5v.OVL.4 {
    @ nmos_esd_nat_5v.OVL.4: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap hvtp
    nmos_esd_nat_5v AND hvtp
}
nmos_esd_nat_5v.OVL.5 {
    @ nmos_esd_nat_5v.OVL.5: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap tunm
    nmos_esd_nat_5v AND tunm
}
nmos_esd_nat_5v.OVL.6 {
    @ nmos_esd_nat_5v.OVL.6: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap rpm
    nmos_esd_nat_5v AND rpm
}
nmos_esd_nat_5v.OVL.7 {
    @ nmos_esd_nat_5v.OVL.7: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap rrpm
    nmos_esd_nat_5v AND rrpm
}
nmos_esd_nat_5v.OVL.8 {
    @ nmos_esd_nat_5v.OVL.8: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap urpm
    nmos_esd_nat_5v AND urpm
}
nmos_esd_nat_5v.OVL.9 {
    @ nmos_esd_nat_5v.OVL.9: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap ldntm
    nmos_esd_nat_5v AND ldntm
}
nmos_esd_nat_5v.OVL.10 {
    @ nmos_esd_nat_5v.OVL.10: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap npc
    nmos_esd_nat_5v AND npc
}
nmos_esd_nat_5v.OVL.11 {
    @ nmos_esd_nat_5v.OVL.11: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap psdm
    nmos_esd_nat_5v AND psdm
}
nmos_esd_nat_5v.OVL.12 {
    @ nmos_esd_nat_5v.OVL.12: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap nsm
    nmos_esd_nat_5v AND nsm
}
nmos_esd_nat_5v.OVL.13 {
    @ nmos_esd_nat_5v.OVL.13: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap skip_pad
    nmos_esd_nat_5v AND skip_pad
}
nmos_esd_nat_5v.OVL.14 {
    @ nmos_esd_nat_5v.OVL.14: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap fuse
    nmos_esd_nat_5v AND fuse
}
nmos_esd_nat_5v.OVL.15 {
    @ nmos_esd_nat_5v.OVL.15: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap diff:res
    nmos_esd_nat_5v AND diffres
}
nmos_esd_nat_5v.OVL.16 {
    @ nmos_esd_nat_5v.OVL.16: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap pwell:res
    nmos_esd_nat_5v AND pwres
}
nmos_esd_nat_5v.OVL.17 {
    @ nmos_esd_nat_5v.OVL.17: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap poly:res
    nmos_esd_nat_5v AND polyres
}
nmos_esd_nat_5v.OVL.18 {
    @ nmos_esd_nat_5v.OVL.18: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap li:res
    nmos_esd_nat_5v AND lires
}
nmos_esd_nat_5v.OVL.19 {
    @ nmos_esd_nat_5v.OVL.19: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:lvNative
    nmos_esd_nat_5v AND LVID
}
nmos_esd_nat_5v.OVL.20 {
    @ nmos_esd_nat_5v.OVL.20: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap pnp
    nmos_esd_nat_5v AND pnp
}
nmos_esd_nat_5v.OVL.21 {
    @ nmos_esd_nat_5v.OVL.21: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap npn
    nmos_esd_nat_5v AND npn
}
nmos_esd_nat_5v.OVL.22 {
    @ nmos_esd_nat_5v.OVL.22: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:diode
    nmos_esd_nat_5v AND DiodeID
}
nmos_esd_nat_5v.OVL.23 {
    @ nmos_esd_nat_5v.OVL.23: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:photo
    nmos_esd_nat_5v AND PHdiodeID
}
nmos_esd_nat_5v.OVL.24 {
    @ nmos_esd_nat_5v.OVL.24: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:core
    nmos_esd_nat_5v AND COREID
}
nmos_esd_nat_5v.OVL.25 {
    @ nmos_esd_nat_5v.OVL.25: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:extendedDrain
    nmos_esd_nat_5v AND ENID
}
nmos_esd_nat_5v.OVL.26 {
    @ nmos_esd_nat_5v.OVL.26: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap areaid:seal
    nmos_esd_nat_5v AND SEALID
}
nmos_esd_nat_5v.OVL.27 {
    @ nmos_esd_nat_5v.OVL.27: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap v12
    nmos_esd_nat_5v AND v12
}
nmos_esd_nat_5v.OVL.28 {
    @ nmos_esd_nat_5v.OVL.28: Illegal nmos_esd_nat_5v device: nmos_esd_nat_5v must not overlap v20
    nmos_esd_nat_5v AND v20
}
nmos_esd = ((gate and nsdm) AND ESDID) NOT (OR v5 v12 v20 LVID pnp npn lvtn)
nmos_esd.OVL.1 {
    @ nmos_esd.OVL.1: Illegal nmos_esd device: nmos_esd must not overlap pwbm
    nmos_esd AND pwbm
}
nmos_esd.OVL.2 {
    @ nmos_esd.OVL.2: Illegal nmos_esd device: nmos_esd must not overlap pwde
    nmos_esd AND pwde
}
nmos_esd.OVL.3 {
    @ nmos_esd.OVL.3: Illegal nmos_esd device: nmos_esd must not overlap hvtp
    nmos_esd AND hvtp
}
nmos_esd.OVL.4 {
    @ nmos_esd.OVL.4: Illegal nmos_esd device: nmos_esd must not overlap lvtn
    nmos_esd AND lvtn
}
nmos_esd.OVL.5 {
    @ nmos_esd.OVL.5: Illegal nmos_esd device: nmos_esd must not overlap tunm
    nmos_esd AND tunm
}
nmos_esd.OVL.6 {
    @ nmos_esd.OVL.6: Illegal nmos_esd device: nmos_esd must not overlap rpm
    nmos_esd AND rpm
}
nmos_esd.OVL.7 {
    @ nmos_esd.OVL.7: Illegal nmos_esd device: nmos_esd must not overlap rrpm
    nmos_esd AND rrpm
}
nmos_esd.OVL.8 {
    @ nmos_esd.OVL.8: Illegal nmos_esd device: nmos_esd must not overlap urpm
    nmos_esd AND urpm
}
nmos_esd.OVL.9 {
    @ nmos_esd.OVL.9: Illegal nmos_esd device: nmos_esd must not overlap ldntm
    nmos_esd AND ldntm
}
nmos_esd.OVL.10 {
    @ nmos_esd.OVL.10: Illegal nmos_esd device: nmos_esd must not overlap npc
    nmos_esd AND npc
}
nmos_esd.OVL.11 {
    @ nmos_esd.OVL.11: Illegal nmos_esd device: nmos_esd must not overlap psdm
    nmos_esd AND psdm
}
nmos_esd.OVL.12 {
    @ nmos_esd.OVL.12: Illegal nmos_esd device: nmos_esd must not overlap nsm
    nmos_esd AND nsm
}
nmos_esd.OVL.13 {
    @ nmos_esd.OVL.13: Illegal nmos_esd device: nmos_esd must not overlap skip_pad
    nmos_esd AND skip_pad
}
nmos_esd.OVL.14 {
    @ nmos_esd.OVL.14: Illegal nmos_esd device: nmos_esd must not overlap fuse
    nmos_esd AND fuse
}
nmos_esd.OVL.15 {
    @ nmos_esd.OVL.15: Illegal nmos_esd device: nmos_esd must not overlap areaid:lvNative
    nmos_esd AND LVID
}
nmos_esd.OVL.16 {
    @ nmos_esd.OVL.16: Illegal nmos_esd device: nmos_esd must not overlap pnp
    nmos_esd AND pnp
}
nmos_esd.OVL.17 {
    @ nmos_esd.OVL.17: Illegal nmos_esd device: nmos_esd must not overlap npn
    nmos_esd AND npn
}
nmos_esd.OVL.18 {
    @ nmos_esd.OVL.18: Illegal nmos_esd device: nmos_esd must not overlap areaid:diode
    nmos_esd AND DiodeID
}
nmos_esd.OVL.19 {
    @ nmos_esd.OVL.19: Illegal nmos_esd device: nmos_esd must not overlap areaid:photo
    nmos_esd AND PHdiodeID
}
nmos_esd.OVL.20 {
    @ nmos_esd.OVL.20: Illegal nmos_esd device: nmos_esd must not overlap areaid:core
    nmos_esd AND COREID
}
nmos_esd.OVL.21 {
    @ nmos_esd.OVL.21: Illegal nmos_esd device: nmos_esd must not overlap areaid:extendedDrain
    nmos_esd AND ENID
}
nmos_esd.OVL.22 {
    @ nmos_esd.OVL.22: Illegal nmos_esd device: nmos_esd must not overlap areaid:seal
    nmos_esd AND SEALID
}
nmos_esd.OVL.23 {
    @ nmos_esd.OVL.23: Illegal nmos_esd device: nmos_esd must not overlap v5
    nmos_esd AND v5
}
nmos_esd.OVL.24 {
    @ nmos_esd.OVL.24: Illegal nmos_esd device: nmos_esd must not overlap v12
    nmos_esd AND v12
}
nmos_esd.OVL.25 {
    @ nmos_esd.OVL.25: Illegal nmos_esd device: nmos_esd must not overlap v20
    nmos_esd AND v20
}
nmos_esd.OVL.26 {
    @ nmos_esd.OVL.26: Illegal nmos_esd device: nmos_esd must not overlap nwell
    nmos_esd AND nwell
}
nmos_esd.OVL.27 {
    @ nmos_esd.OVL.27: Illegal nmos_esd device: nmos_esd must not overlap thkox
    nmos_esd AND thkox
}
pmos_esd_5v = ((((gate and psdm) AND v5) AND ESDID) AND thkox) NOT (OR v12 v20 LVID npn pnp ENID)
pmos_esd_5v.OVL.1 {
    @ pmos_esd_5v.OVL.1: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap pwbm
    pmos_esd_5v AND pwbm
}
pmos_esd_5v.OVL.2 {
    @ pmos_esd_5v.OVL.2: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap pwde
    pmos_esd_5v AND pwde
}
pmos_esd_5v.OVL.3 {
    @ pmos_esd_5v.OVL.3: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap hvtp
    pmos_esd_5v AND hvtp
}
pmos_esd_5v.OVL.4 {
    @ pmos_esd_5v.OVL.4: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap lvtn
    pmos_esd_5v AND lvtn
}
pmos_esd_5v.OVL.5 {
    @ pmos_esd_5v.OVL.5: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap tunm
    pmos_esd_5v AND tunm
}
pmos_esd_5v.OVL.6 {
    @ pmos_esd_5v.OVL.6: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap rpm
    pmos_esd_5v AND rpm
}
pmos_esd_5v.OVL.7 {
    @ pmos_esd_5v.OVL.7: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap rrpm
    pmos_esd_5v AND rrpm
}
pmos_esd_5v.OVL.8 {
    @ pmos_esd_5v.OVL.8: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap urpm
    pmos_esd_5v AND urpm
}
pmos_esd_5v.OVL.9 {
    @ pmos_esd_5v.OVL.9: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap ldntm
    pmos_esd_5v AND ldntm
}
pmos_esd_5v.OVL.10 {
    @ pmos_esd_5v.OVL.10: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap npc
    pmos_esd_5v AND npc
}
pmos_esd_5v.OVL.11 {
    @ pmos_esd_5v.OVL.11: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap nsdm
    pmos_esd_5v AND nsdm
}
pmos_esd_5v.OVL.12 {
    @ pmos_esd_5v.OVL.12: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap nsm
    pmos_esd_5v AND nsm
}
pmos_esd_5v.OVL.13 {
    @ pmos_esd_5v.OVL.13: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap skip_pad
    pmos_esd_5v AND skip_pad
}
pmos_esd_5v.OVL.14 {
    @ pmos_esd_5v.OVL.14: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap fuse
    pmos_esd_5v AND fuse
}
pmos_esd_5v.OVL.15 {
    @ pmos_esd_5v.OVL.15: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap diff:res
    pmos_esd_5v AND diffres
}
pmos_esd_5v.OVL.16 {
    @ pmos_esd_5v.OVL.16: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap pwell:res
    pmos_esd_5v AND pwres
}
pmos_esd_5v.OVL.17 {
    @ pmos_esd_5v.OVL.17: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap poly:res
    pmos_esd_5v AND polyres
}
pmos_esd_5v.OVL.18 {
    @ pmos_esd_5v.OVL.18: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap li:res
    pmos_esd_5v AND lires
}
pmos_esd_5v.OVL.19 {
    @ pmos_esd_5v.OVL.19: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:lvNative
    pmos_esd_5v AND LVID
}
pmos_esd_5v.OVL.20 {
    @ pmos_esd_5v.OVL.20: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap pnp
    pmos_esd_5v AND pnp
}
pmos_esd_5v.OVL.21 {
    @ pmos_esd_5v.OVL.21: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap npn
    pmos_esd_5v AND npn
}
pmos_esd_5v.OVL.22 {
    @ pmos_esd_5v.OVL.22: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:diode
    pmos_esd_5v AND DiodeID
}
pmos_esd_5v.OVL.23 {
    @ pmos_esd_5v.OVL.23: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:photo
    pmos_esd_5v AND PHdiodeID
}
pmos_esd_5v.OVL.24 {
    @ pmos_esd_5v.OVL.24: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:core
    pmos_esd_5v AND COREID
}
pmos_esd_5v.OVL.25 {
    @ pmos_esd_5v.OVL.25: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:extendedDrain
    pmos_esd_5v AND ENID
}
pmos_esd_5v.OVL.26 {
    @ pmos_esd_5v.OVL.26: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap areaid:seal
    pmos_esd_5v AND SEALID
}
pmos_esd_5v.OVL.27 {
    @ pmos_esd_5v.OVL.27: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap v12
    pmos_esd_5v AND v12
}
pmos_esd_5v.OVL.28 {
    @ pmos_esd_5v.OVL.28: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap v20
    pmos_esd_5v AND v20
}
pmos_esd_5v.OVL.29 {
    @ pmos_esd_5v.OVL.29: Illegal pmos_esd_5v device: pmos_esd_5v must not overlap poly:model
    pmos_esd_5v AND polyModel
}
nsd_pw_esd = ((((diodeID AND nsdm) NOT nwell) AND diffi) AND ESDID) NOT (OR v5 v12 v20 lvtn hvtp LVID)
dnsd_pw_esd.OVL.1 {
    @ nsd_pw_esd.OVL.1: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap pwbm
    nsd_pw_esd AND pwbm
}
dnsd_pw_esd.OVL.2 {
    @ nsd_pw_esd.OVL.2: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap hvtp
    nsd_pw_esd AND hvtp
}
dnsd_pw_esd.OVL.3 {
    @ nsd_pw_esd.OVL.3: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap lvtn
    nsd_pw_esd AND lvtn
}
dnsd_pw_esd.OVL.4 {
    @ nsd_pw_esd.OVL.4: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap tunm
    nsd_pw_esd AND tunm
}
dnsd_pw_esd.OVL.5 {
    @ nsd_pw_esd.OVL.5: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap thkox
    nsd_pw_esd AND thkox
}
dnsd_pw_esd.OVL.6 {
    @ nsd_pw_esd.OVL.6: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap psdm
    nsd_pw_esd AND psdm
}
dnsd_pw_esd.OVL.7 {
    @ nsd_pw_esd.OVL.7: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap nsm
    nsd_pw_esd AND nsm
}
dnsd_pw_esd.OVL.8 {
    @ nsd_pw_esd.OVL.8: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap skip_pad
    nsd_pw_esd AND skip_pad
}
dnsd_pw_esd.OVL.9 {
    @ nsd_pw_esd.OVL.9: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap fuse
    nsd_pw_esd AND fuse
}
dnsd_pw_esd.OVL.10 {
    @ nsd_pw_esd.OVL.10: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap diff:res
    nsd_pw_esd AND diffres
}
dnsd_pw_esd.OVL.11 {
    @ nsd_pw_esd.OVL.11: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap pwell:res
    nsd_pw_esd AND pwres
}
dnsd_pw_esd.OVL.12 {
    @ nsd_pw_esd.OVL.12: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap poly:res
    nsd_pw_esd AND polyres
}
dnsd_pw_esd.OVL.13 {
    @ nsd_pw_esd.OVL.13: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap li:res
    nsd_pw_esd AND lires
}
dnsd_pw_esd.OVL.14 {
    @ nsd_pw_esd.OVL.14: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap areaid:lvNative
    nsd_pw_esd AND LVID
}
dnsd_pw_esd.OVL.15 {
    @ nsd_pw_esd.OVL.15: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap pnp
    nsd_pw_esd AND pnp
}
dnsd_pw_esd.OVL.16 {
    @ nsd_pw_esd.OVL.16: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap npn
    nsd_pw_esd AND npn
}
dnsd_pw_esd.OVL.17 {
    @ nsd_pw_esd.OVL.17: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap areaid:photo
    nsd_pw_esd AND PHdiodeID
}
dnsd_pw_esd.OVL.18 {
    @ nsd_pw_esd.OVL.18: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap areaid:core
    nsd_pw_esd AND COREID
}
dnsd_pw_esd.OVL.19 {
    @ nsd_pw_esd.OVL.19: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap areaid:extendedDrain
    nsd_pw_esd AND ENID
}
dnsd_pw_esd.OVL.20 {
    @ nsd_pw_esd.OVL.20: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap areaid:seal
    nsd_pw_esd AND SEALID
}
dnsd_pw_esd.OVL.21 {
    @ nsd_pw_esd.OVL.21: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap v5
    nsd_pw_esd AND v5
}
dnsd_pw_esd.OVL.22 {
    @ nsd_pw_esd.OVL.22: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap v12
    nsd_pw_esd AND v12
}
dnsd_pw_esd.OVL.23 {
    @ nsd_pw_esd.OVL.23: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap v20
    nsd_pw_esd AND v20
}
dnsd_pw_esd.OVL.24 {
    @ nsd_pw_esd.OVL.24: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap nwell
    nsd_pw_esd AND nwell
}
dnsd_pw_esd.OVL.25 {
    @ nsd_pw_esd.OVL.25: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap poly
    nsd_pw_esd AND polyi
}
dnsd_pw_esd.OVL.26 {
    @ nsd_pw_esd.OVL.26: Illegal nsd_pw_esd device: nsd_pw_esd must not overlap poly:model
    nsd_pw_esd AND polyModel
}
psd_nw_esd = ((((diodeID AND psdm) AND nwell) AND diffi) AND ESDID) NOT (OR v5 v12 v20 lvtn hvtp LVID)
dpsd_nw_esd.OVL.1 {
    @ psd_nw_esd.OVL.1: Illegal psd_nw_esd device: psd_nw_esd must not overlap pwbm
    psd_nw_esd AND pwbm
}
dpsd_nw_esd.OVL.2 {
    @ psd_nw_esd.OVL.2: Illegal psd_nw_esd device: psd_nw_esd must not overlap hvtp
    psd_nw_esd AND hvtp
}
dpsd_nw_esd.OVL.3 {
    @ psd_nw_esd.OVL.3: Illegal psd_nw_esd device: psd_nw_esd must not overlap lvtn
    psd_nw_esd AND lvtn
}
dpsd_nw_esd.OVL.4 {
    @ psd_nw_esd.OVL.4: Illegal psd_nw_esd device: psd_nw_esd must not overlap tunm
    psd_nw_esd AND tunm
}
dpsd_nw_esd.OVL.5 {
    @ psd_nw_esd.OVL.5: Illegal psd_nw_esd device: psd_nw_esd must not overlap thkox
    psd_nw_esd AND thkox
}
dpsd_nw_esd.OVL.6 {
    @ psd_nw_esd.OVL.6: Illegal psd_nw_esd device: psd_nw_esd must not overlap poly
    psd_nw_esd AND polyi
}
dpsd_nw_esd.OVL.7 {
    @ psd_nw_esd.OVL.7: Illegal psd_nw_esd device: psd_nw_esd must not overlap nsdm
    psd_nw_esd AND nsdm
}
dpsd_nw_esd.OVL.8 {
    @ psd_nw_esd.OVL.8: Illegal psd_nw_esd device: psd_nw_esd must not overlap nsm
    psd_nw_esd AND nsm
}
dpsd_nw_esd.OVL.9 {
    @ psd_nw_esd.OVL.9: Illegal psd_nw_esd device: psd_nw_esd must not overlap skip_pad
    psd_nw_esd AND skip_pad
}
dpsd_nw_esd.OVL.10 {
    @ psd_nw_esd.OVL.10: Illegal psd_nw_esd device: psd_nw_esd must not overlap fuse
    psd_nw_esd AND fuse
}
dpsd_nw_esd.OVL.11 {
    @ psd_nw_esd.OVL.11: Illegal psd_nw_esd device: psd_nw_esd must not overlap diff:res
    psd_nw_esd AND diffres
}
dpsd_nw_esd.OVL.12 {
    @ psd_nw_esd.OVL.12: Illegal psd_nw_esd device: psd_nw_esd must not overlap pwell:res
    psd_nw_esd AND pwres
}
dpsd_nw_esd.OVL.13 {
    @ psd_nw_esd.OVL.13: Illegal psd_nw_esd device: psd_nw_esd must not overlap poly:res
    psd_nw_esd AND polyres
}
dpsd_nw_esd.OVL.14 {
    @ psd_nw_esd.OVL.14: Illegal psd_nw_esd device: psd_nw_esd must not overlap li:res
    psd_nw_esd AND lires
}
dpsd_nw_esd.OVL.15 {
    @ psd_nw_esd.OVL.15: Illegal psd_nw_esd device: psd_nw_esd must not overlap areaid:lvNative
    psd_nw_esd AND LVID
}
dpsd_nw_esd.OVL.16 {
    @ psd_nw_esd.OVL.16: Illegal psd_nw_esd device: psd_nw_esd must not overlap pnp
    psd_nw_esd AND pnp
}
dpsd_nw_esd.OVL.17 {
    @ psd_nw_esd.OVL.17: Illegal psd_nw_esd device: psd_nw_esd must not overlap npn
    psd_nw_esd AND npn
}
dpsd_nw_esd.OVL.18 {
    @ psd_nw_esd.OVL.18: Illegal psd_nw_esd device: psd_nw_esd must not overlap areaid:photo
    psd_nw_esd AND PHdiodeID
}
dpsd_nw_esd.OVL.19 {
    @ psd_nw_esd.OVL.19: Illegal psd_nw_esd device: psd_nw_esd must not overlap areaid:core
    psd_nw_esd AND COREID
}
dpsd_nw_esd.OVL.20 {
    @ psd_nw_esd.OVL.20: Illegal psd_nw_esd device: psd_nw_esd must not overlap areaid:extendedDrain
    psd_nw_esd AND ENID
}
dpsd_nw_esd.OVL.21 {
    @ psd_nw_esd.OVL.21: Illegal psd_nw_esd device: psd_nw_esd must not overlap areaid:seal
    psd_nw_esd AND SEALID
}
dpsd_nw_esd.OVL.22 {
    @ psd_nw_esd.OVL.22: Illegal psd_nw_esd device: psd_nw_esd must not overlap v5
    psd_nw_esd AND v5
}
dpsd_nw_esd.OVL.23 {
    @ psd_nw_esd.OVL.23: Illegal psd_nw_esd device: psd_nw_esd must not overlap v12
    psd_nw_esd AND v12
}
dpsd_nw_esd.OVL.24 {
    @ psd_nw_esd.OVL.24: Illegal psd_nw_esd device: psd_nw_esd must not overlap v20
    psd_nw_esd AND v20
}
dpsd_nw_esd.OVL.25 {
    @ psd_nw_esd.OVL.25: Illegal psd_nw_esd device: psd_nw_esd must not overlap poly:model
    psd_nw_esd AND polyModel
}
nsd_pw_esd_v5_a = diodeID AND nsdm
nsd_pw_esd_v5_b = nsd_pw_esd_v5_a NOT nwell
nsd_pw_esd_v5_c = nsd_pw_esd_v5_b AND diffi
nsd_pw_esd_v5_d = nsd_pw_esd_v5_c AND ESDID
nsd_pw_esd_v5_e = nsd_pw_esd_v5_d AND v5
nsd_pw_esd_v5_f = nsd_pw_esd_v5_e AND thkox
nsd_pw_esd_v5 = nsd_pw_esd_v5_f NOT (OR v12 v20 lvtn hvtp LVID)
dnsd_pw_esd_v5.OVL.1 {
    @ nsd_pw_esd_v5.OVL.1: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap skip_dnw
    nsd_pw_esd_v5 AND skip_dnw
}
dnsd_pw_esd_v5.OVL.2 {
    @ nsd_pw_esd_v5.OVL.2: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap pwbm
    nsd_pw_esd_v5 AND pwbm
}
dnsd_pw_esd_v5.OVL.3 {
    @ nsd_pw_esd_v5.OVL.3: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap nwell
    nsd_pw_esd_v5 AND nwell
}
dnsd_pw_esd_v5.OVL.4 {
    @ nsd_pw_esd_v5.OVL.4: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap hvtp
    nsd_pw_esd_v5 AND hvtp
}
dnsd_pw_esd_v5.OVL.5 {
    @ nsd_pw_esd_v5.OVL.5: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap lvtn
    nsd_pw_esd_v5 AND lvtn
}
dnsd_pw_esd_v5.OVL.6 {
    @ nsd_pw_esd_v5.OVL.6: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap tunm
    nsd_pw_esd_v5 AND tunm
}
dnsd_pw_esd_v5.OVL.7 {
    @ nsd_pw_esd_v5.OVL.7: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap rpm
    nsd_pw_esd_v5 AND rpm
}
dnsd_pw_esd_v5.OVL.8 {
    @ nsd_pw_esd_v5.OVL.8: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap rrpm
    nsd_pw_esd_v5 AND rrpm
}
dnsd_pw_esd_v5.OVL.9 {
    @ nsd_pw_esd_v5.OVL.9: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap urpm
    nsd_pw_esd_v5 AND urpm
}
dnsd_pw_esd_v5.OVL.10 {
    @ nsd_pw_esd_v5.OVL.10: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap poly
    nsd_pw_esd_v5 AND polyi
}
dnsd_pw_esd_v5.OVL.11 {
    @ nsd_pw_esd_v5.OVL.11: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap psdm
    nsd_pw_esd_v5 AND psdm
}
dnsd_pw_esd_v5.OVL.12 {
    @ nsd_pw_esd_v5.OVL.12: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap nsm
    nsd_pw_esd_v5 AND nsm
}
dnsd_pw_esd_v5.OVL.13 {
    @ nsd_pw_esd_v5.OVL.13: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap skip_pad
    nsd_pw_esd_v5 AND skip_pad
}
dnsd_pw_esd_v5.OVL.14 {
    @ nsd_pw_esd_v5.OVL.14: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap fuse
    nsd_pw_esd_v5 AND fuse
}
dnsd_pw_esd_v5.OVL.15 {
    @ nsd_pw_esd_v5.OVL.15: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap diff:res
    nsd_pw_esd_v5 AND diffres
}
dnsd_pw_esd_v5.OVL.16 {
    @ nsd_pw_esd_v5.OVL.16: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap pwell:res
    nsd_pw_esd_v5 AND pwres
}
dnsd_pw_esd_v5.OVL.17 {
    @ nsd_pw_esd_v5.OVL.17: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap poly:res
    nsd_pw_esd_v5 AND polyres
}
dnsd_pw_esd_v5.OVL.18 {
    @ nsd_pw_esd_v5.OVL.18: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap li:res
    nsd_pw_esd_v5 AND lires
}
dnsd_pw_esd_v5.OVL.19 {
    @ nsd_pw_esd_v5.OVL.19: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap areaid:lvNative
    nsd_pw_esd_v5 AND LVID
}
dnsd_pw_esd_v5.OVL.20 {
    @ nsd_pw_esd_v5.OVL.20: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap pnp
    nsd_pw_esd_v5 AND pnp
}
dnsd_pw_esd_v5.OVL.21 {
    @ nsd_pw_esd_v5.OVL.21: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap npn
    nsd_pw_esd_v5 AND npn
}
dnsd_pw_esd_v5.OVL.22 {
    @ nsd_pw_esd_v5.OVL.22: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap areaid:photo
    nsd_pw_esd_v5 AND PHdiodeID
}
dnsd_pw_esd_v5.OVL.23 {
    @ nsd_pw_esd_v5.OVL.23: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap areaid:core
    nsd_pw_esd_v5 AND COREID
}
dnsd_pw_esd_v5.OVL.24 {
    @ nsd_pw_esd_v5.OVL.24: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap areaid:extendedDrain
    nsd_pw_esd_v5 AND ENID
}
dnsd_pw_esd_v5.OVL.25 {
    @ nsd_pw_esd_v5.OVL.25: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap areaid:seal
    nsd_pw_esd_v5 AND SEALID
}
dnsd_pw_esd_v5.OVL.26 {
    @ nsd_pw_esd_v5.OVL.26: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap v12
    nsd_pw_esd_v5 AND v12
}
dnsd_pw_esd_v5.OVL.27 {
    @ nsd_pw_esd_v5.OVL.27: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap v20
    nsd_pw_esd_v5 AND v20
}
dnsd_pw_esd_v5.OVL.28 {
    @ nsd_pw_esd_v5.OVL.28: Illegal nsd_pw_esd_v5 device: nsd_pw_esd_v5 must not overlap poly:model
    nsd_pw_esd_v5 AND polyModel
}
psd_nw_esd_v5_a = diodeID AND psdm
psd_nw_esd_v5_b = psd_nw_esd_v5_a AND nwell
psd_nw_esd_v5_c = psd_nw_esd_v5_b AND diffi
psd_nw_esd_v5_d = psd_nw_esd_v5_c AND ESDID
psd_nw_esd_v5_e = psd_nw_esd_v5_d AND v5
psd_nw_esd_v5_f = psd_nw_esd_v5_e AND thkox
psd_nw_esd_v5 = psd_nw_esd_v5_f NOT (OR v12 v20 lvtn hvtp LVID)
dpsd_nw_esd_v5.OVL.1 {
    @ psd_nw_esd_v5.OVL.1: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap pwbm
    psd_nw_esd_v5 AND pwbm
}
dpsd_nw_esd_v5.OVL.2 {
    @ psd_nw_esd_v5.OVL.2: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap hvtp
    psd_nw_esd_v5 AND hvtp
}
dpsd_nw_esd_v5.OVL.3 {
    @ psd_nw_esd_v5.OVL.3: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap lvtn
    psd_nw_esd_v5 AND lvtn
}
dpsd_nw_esd_v5.OVL.4 {
    @ psd_nw_esd_v5.OVL.4: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap tunm
    psd_nw_esd_v5 AND tunm
}
dpsd_nw_esd_v5.OVL.5 {
    @ psd_nw_esd_v5.OVL.5: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap rpm
    psd_nw_esd_v5 AND rpm
}
dpsd_nw_esd_v5.OVL.6 {
    @ psd_nw_esd_v5.OVL.6: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap rrpm
    psd_nw_esd_v5 AND rrpm
}
dpsd_nw_esd_v5.OVL.7 {
    @ psd_nw_esd_v5.OVL.7: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap urpm
    psd_nw_esd_v5 AND urpm
}
dpsd_nw_esd_v5.OVL.8 {
    @ psd_nw_esd_v5.OVL.8: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap poly
    psd_nw_esd_v5 AND polyi
}
dpsd_nw_esd_v5.OVL.9 {
    @ psd_nw_esd_v5.OVL.9: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap nsdm
    psd_nw_esd_v5 AND nsdm
}
dpsd_nw_esd_v5.OVL.10 {
    @ psd_nw_esd_v5.OVL.10: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap nsm
    psd_nw_esd_v5 AND nsm
}
dpsd_nw_esd_v5.OVL.11 {
    @ psd_nw_esd_v5.OVL.11: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap skip_pad
    psd_nw_esd_v5 AND skip_pad
}
dpsd_nw_esd_v5.OVL.12 {
    @ psd_nw_esd_v5.OVL.12: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap fuse
    psd_nw_esd_v5 AND fuse
}
dpsd_nw_esd_v5.OVL.13 {
    @ psd_nw_esd_v5.OVL.13: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap diff:res
    psd_nw_esd_v5 AND diffres
}
dpsd_nw_esd_v5.OVL.14 {
    @ psd_nw_esd_v5.OVL.14: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap pwell:res
    psd_nw_esd_v5 AND pwres
}
dpsd_nw_esd_v5.OVL.15 {
    @ psd_nw_esd_v5.OVL.15: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap poly:res
    psd_nw_esd_v5 AND polyres
}
dpsd_nw_esd_v5.OVL.16 {
    @ psd_nw_esd_v5.OVL.16: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap li:res
    psd_nw_esd_v5 AND lires
}
dpsd_nw_esd_v5.OVL.17 {
    @ psd_nw_esd_v5.OVL.17: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap areaid:lvNative
    psd_nw_esd_v5 AND LVID
}
dpsd_nw_esd_v5.OVL.18 {
    @ psd_nw_esd_v5.OVL.18: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap pnp
    psd_nw_esd_v5 AND pnp
}
dpsd_nw_esd_v5.OVL.19 {
    @ psd_nw_esd_v5.OVL.19: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap npn
    psd_nw_esd_v5 AND npn
}
dpsd_nw_esd_v5.OVL.20 {
    @ psd_nw_esd_v5.OVL.20: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap areaid:photo
    psd_nw_esd_v5 AND PHdiodeID
}
dpsd_nw_esd_v5.OVL.21 {
    @ psd_nw_esd_v5.OVL.21: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap areaid:core
    psd_nw_esd_v5 AND COREID
}
dpsd_nw_esd_v5.OVL.22 {
    @ psd_nw_esd_v5.OVL.22: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap areaid:extendedDrain
    psd_nw_esd_v5 AND ENID
}
dpsd_nw_esd_v5.OVL.23 {
    @ psd_nw_esd_v5.OVL.23: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap areaid:seal
    psd_nw_esd_v5 AND SEALID
}
dpsd_nw_esd_v5.OVL.24 {
    @ psd_nw_esd_v5.OVL.24: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap v12
    psd_nw_esd_v5 AND v12
}
dpsd_nw_esd_v5.OVL.25 {
    @ psd_nw_esd_v5.OVL.25: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap v20
    psd_nw_esd_v5 AND v20
}
dpsd_nw_esd_v5.OVL.26 {
    @ psd_nw_esd_v5.OVL.26: Illegal psd_nw_esd_v5 device: psd_nw_esd_v5 must not overlap poly:model
    psd_nw_esd_v5 AND polyModel
}
 
#ENDIF
// end illegal device checks 


//
// Fill checks
//


fill.OVL.1 {
    @ fill.OVL.1: Layer diff_fill must be outside diff/drawing
    diff_fill AND diffii
}
fill.OVL.2 {
    @ fill.OVL.2: Layer poly_fill must be outside poly/drawing
    poly_fill AND polyii
}
fill.OVL.3 {
    @ fill.OVL.3: Layer li_fill must be outside poly/drawing
    li_fill AND polyii
}
fill.OVL.4 {
    @ fill.OVL.4: Layer m1_fill must be outside met1/drawing
    m1_fill AND met1ii
}
fill.OVL.5 {
    @ fill.OVL.5: Layer m2_fill must be outside met2/drawing
    m2_fill AND met2ii
}
fill.OVL.6 {
    @ fill.OVL.6: Layer m3_fill must be outside met3/drawing
    m3_fill AND met3ii
}
fill.OVL.7 {
    @ fill.OVL.7: Layer m4_fill must be outside met4/drawing
    m4_fill AND met4ii
}
fill.OVL.8 {
    @ fill.OVL.8: Layer m5_fill must be outside met5/drawing
    m5_fill AND met5ii
}
fill.CON.1 {
    @ fill.CON.1: Layer diff_fill must float
    (diff_fill NOT (OR critSide ccorner))  INTERACT licon
}
fill.CON.2 {
    @ fill.CON.2: Layer poly_fill must float
    (poly_fill NOT (OR critSide ccorner)) INTERACT licon
}
fill.CON.3 {
    @ fill.CON.3: Layer li_fill must float
    (li_fill NOT (OR critSide ccorner)) INTERACT licon
    (li_fill NOT (OR critSide ccorner)) INTERACT mcon
}
fill.CON.4 {
    @ fill.CON.4: Layer m1_fill must float
    (m1_fill NOT (OR critSide ccorner)) INTERACT mcon
    (m1_fill NOT (OR critSide ccorner)) INTERACT via1
}
fill.CON.5 {
    @ fill.CON.5: Layer m2_fill must float
    (m2_fill NOT (OR critSide ccorner)) INTERACT via1
    (m2_fill NOT (OR critSide ccorner)) INTERACT via2
}
fill.CON.6 {
    @ fill.CON.6: Layer m3_fill must float
    (m3_fill NOT (OR critSide ccorner)) INTERACT via2
    (m3_fill NOT (OR critSide ccorner)) INTERACT via3
}
fill.CON.7 {
    @ fill.CON.7: Layer m4_fill must float
    (m4_fill NOT (OR critSide ccorner)) INTERACT via3
    (m4_fill NOT (OR critSide ccorner)) INTERACT via4
}
fill.CON.8 {
    @ fill.CON.8: Layer m5_fill must float
    m5_fill INTERACT via4
}