`celldefine
`timescale 1ns / 1ps
module scs8hdll_a211o_1  (
output X,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&C1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&C1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&C1==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , C1 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a211o_2  (
output X,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&C1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&C1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&C1==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , C1 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a211o_4  (
output X,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&C1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&C1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&C1==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , C1 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a211oi_1  (
output Y,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_274 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , csi_opt_274 , B1 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a211oi_2  (
output Y,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_274 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , csi_opt_274 , B1 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a211oi_4  (
output Y,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_274 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , csi_opt_274 , B1 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21bo_1  (
output X,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_289;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1N==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1N==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N -=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  nand ( csi_opt_289 , A2 , A1 ) ;
  nand  ( UDP_IN_X , B1N , csi_opt_289 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21bo_2  (
output X,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_289;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1N==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1N==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N -=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  nand ( csi_opt_289 , A2 , A1 ) ;
  nand  ( UDP_IN_X , B1N , csi_opt_289 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21bo_4  (
output X,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_289;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1N==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1N==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N -=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  nand ( csi_opt_289 , A2 , A1 ) ;
  nand  ( UDP_IN_X , B1N , csi_opt_289 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21boi_1  (
output Y,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire b;
   not (b,B1N);
   and ( csi_opt_273 , A1 , A2 ) ;
   nor  ( UDP_IN_Y , b , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
// modification by B1NB, based on SPR13943.  need to have
`ifdef functional
`else
  specify
    if (A2==1'b1&&B1N==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1N==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N +=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif
   
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21boi_2  (
output Y,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire b;
   not (b,B1N);
   and ( csi_opt_273 , A1 , A2 ) ;
   nor  ( UDP_IN_Y , b , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
// modification by B1NB, based on SPR13943.  need to have
`ifdef functional
`else
  specify
    if (A2==1'b1&&B1N==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1N==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N +=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif
   
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21boi_4  (
output Y,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire b;
   not (b,B1N);
   and ( csi_opt_273 , A1 , A2 ) ;
   nor  ( UDP_IN_Y , b , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
// modification by B1NB, based on SPR13943.  need to have
`ifdef functional
`else
  specify
    if (A2==1'b1&&B1N==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1N==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N +=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif
   
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21o_1  (
output X,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21o_2  (
output X,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21o_4  (
output X,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21o_6  (
output X,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21o_8  (
output X,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21oi_1  (
output Y,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , B1 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21oi_2  (
output Y,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , B1 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a21oi_4  (
output Y,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , B1 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a221oi_1  (
output Y,

input A1,
input A2,
input B1,
input B2,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_275;
  wire csi_opt_276;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&C1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&C1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&C1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_275 , B1 , B2 ) ;
  and ( csi_opt_276 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , csi_opt_275 , C1 , csi_opt_276 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a221oi_2  (
output Y,

input A1,
input A2,
input B1,
input B2,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_275;
  wire csi_opt_276;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&C1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&C1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&C1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_275 , B1 , B2 ) ;
  and ( csi_opt_276 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , csi_opt_275 , C1 , csi_opt_276 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a221oi_4  (
output Y,

input A1,
input A2,
input B1,
input B2,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_275;
  wire csi_opt_276;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1&&C1==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&C1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&C1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&C1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_275 , B1 , B2 ) ;
  and ( csi_opt_276 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , csi_opt_275 , C1 , csi_opt_276 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a222oi_1  (
output Y,
input A1,
input A2,
input B1,
input B2,
input C1,
input C2


`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_298;
  wire csi_opt_296;
  wire csi_opt_297;

// modification by BNB, based on SPR13943.  need to have
// the reg and specify gone when using a functional model.
`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b0&&C2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b0&&C2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b1&&C2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b0&&C2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b0&&C2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b1&&C2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b0&&C2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b0&&C2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b1&&C2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b0&&C2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b0&&C2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b1&&C2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b0&&C2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b0&&C2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b1&&C2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b0&&C2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b0&&C2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b1&&C2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1&&C1==1'b0&&C2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1&&C1==1'b0&&C2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1&&C1==1'b1&&C2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1&&C1==1'b0&&C2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1&&C1==1'b0&&C2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1&&C1==1'b1&&C2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1&&C1==1'b0&&C2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1&&C1==1'b0&&C2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1&&C1==1'b1&&C2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&C1==1'b0&&C2==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&C1==1'b0&&C2==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&C1==1'b1&&C2==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&C1==1'b0&&C2==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&C1==1'b0&&C2==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&C1==1'b1&&C2==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&C1==1'b0&&C2==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&C1==1'b0&&C2==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&C1==1'b1&&C2==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b0&&C2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b1&&C2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b0&&C2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b0&&C2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1&&C2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0&&C2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b0&&C2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1&&C2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0&&C2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b0&&C1==1'b1) (C2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (C2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (C2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b0&&C1==1'b1) (C2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1&&C1==1'b1) (C2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0&&C1==1'b1) (C2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b0&&C1==1'b1) (C2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (C2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (C2 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  nand ( csi_opt_298 , A2 , A1 ) ;
  nand ( csi_opt_296 , B2 , B1 ) ;
  nand ( csi_opt_297 , C2 , C1 ) ;

  and  ( UDP_IN_Y , csi_opt_298 , csi_opt_296, csi_opt_297 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ; 
  buf  (Y, UDP_OUT_Y) ;   
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a22o_1  (
output X,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , B1 , B2 ) ;
  and ( csi_opt_274 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a22o_2  (
output X,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , B1 , B2 ) ;
  and ( csi_opt_274 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a22o_4  (
output X,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , B1 , B2 ) ;
  and ( csi_opt_274 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a22oi_1  (
output Y,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_298;
  wire csi_opt_296;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  nand ( csi_opt_298 , A2 , A1 ) ;
  nand ( csi_opt_296 , B2 , B1 ) ;
  and  ( UDP_IN_Y , csi_opt_298 , csi_opt_296 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a22oi_2  (
output Y,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_298;
  wire csi_opt_296;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  nand ( csi_opt_298 , A2 , A1 ) ;
  nand ( csi_opt_296 , B2 , B1 ) ;
  and  ( UDP_IN_Y , csi_opt_298 , csi_opt_296 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a22oi_4  (
output Y,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_298;
  wire csi_opt_296;

`ifdef functional
`else
  specify
    if (A2==1'b1&&B1==1'b0&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  nand ( csi_opt_298 , A2 , A1 ) ;
  nand ( csi_opt_296 , B2 , B1 ) ;
  and  ( UDP_IN_Y , csi_opt_298 , csi_opt_296 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a2bb2o_1  (
output X,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2N==1'b0&&B1==1'b0&&B2==1'b0) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b0&&B2==1'b1) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b1&&B2==1'b0) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b0) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b1) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b1&&B2==1'b0) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , B1 , B2 ) ;
  nor ( csi_opt_274 , A1N , A2N ) ;
  or  ( UDP_IN_X , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a2bb2o_2  (
output X,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2N==1'b0&&B1==1'b0&&B2==1'b0) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b0&&B2==1'b1) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b1&&B2==1'b0) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b0) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b1) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b1&&B2==1'b0) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , B1 , B2 ) ;
  nor ( csi_opt_274 , A1N , A2N ) ;
  or  ( UDP_IN_X , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a2bb2o_4  (
output X,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2N==1'b0&&B1==1'b0&&B2==1'b0) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b0&&B2==1'b1) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b1&&B2==1'b0) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b0) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b1) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b1&&B2==1'b0) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , B1 , B2 ) ;
  nor ( csi_opt_274 , A1N , A2N ) ;
  or  ( UDP_IN_X , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a2bb2oi_1  (
output Y,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2N==1'b0&&B1==1'b0&&B2==1'b0) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b0&&B2==1'b1) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b1&&B2==1'b0) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b0) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b1) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b1&&B2==1'b0) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , B1 , B2 ) ;
  nor ( csi_opt_274 , A1N , A2N ) ;
  nor  ( UDP_IN_Y , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a2bb2oi_2  (
output Y,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2N==1'b0&&B1==1'b0&&B2==1'b0) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b0&&B2==1'b1) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b1&&B2==1'b0) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b0) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b1) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b1&&B2==1'b0) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , B1 , B2 ) ;
  nor ( csi_opt_274 , A1N , A2N ) ;
  nor  ( UDP_IN_Y , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a2bb2oi_4  (
output Y,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_473;
  wire csi_opt_474;

`ifdef functional
`else
  specify
    if (A2N==1'b0&&B1==1'b0&&B2==1'b0) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b0&&B2==1'b1) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b0&&B1==1'b1&&B2==1'b0) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b0) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b0&&B2==1'b1) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&B1==1'b1&&B2==1'b0) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_473 , B1 , B2 ) ;
  nor ( csi_opt_474 , A1N , A2N ) ;
  nor  ( UDP_IN_Y , csi_opt_474 , csi_opt_473 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a31o_1  (
output X,

input A1,
input A2,
input A3,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A3 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a31o_2  (
output X,

input A1,
input A2,
input A3,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A3 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a31o_4  (
output X,

input A1,
input A2,
input A3,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A3 , A1 , A2 ) ;
  or  ( UDP_IN_X , csi_opt_273 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a31oi_1  (
output Y,

input A1,
input A2,
input A3,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A3 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , B1 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a31oi_2  (
output Y,

input A1,
input A2,
input A3,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A3 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , B1 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a31oi_4  (
output Y,

input A1,
input A2,
input A3,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A3 , A1 , A2 ) ;
  nor  ( UDP_IN_Y , B1 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a32o_1  (
output X,

input A1,
input A2,
input A3,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b0) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A3 , A1 , A2 ) ;
  and ( csi_opt_274 , B1 , B2 ) ;
  or  ( UDP_IN_X , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a32o_2  (
output X,

input A1,
input A2,
input A3,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b0) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A3 , A1 , A2 ) ;
  and ( csi_opt_274 , B1 , B2 ) ;
  or  ( UDP_IN_X , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a32o_4  (
output X,

input A1,
input A2,
input A3,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b0) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (A3 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and ( csi_opt_273 , A3 , A1 , A2 ) ;
  and ( csi_opt_274 , B1 , B2 ) ;
  or  ( UDP_IN_X , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_a32oi_1  (
output Y,

input A1,
input A2,
input A3,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_304;
  wire csi_opt_302;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  nand ( csi_opt_304 , A2 , A1 , A3 ) ;
  nand ( csi_opt_302 , B2 , B1 ) ;
  and  ( UDP_IN_Y , csi_opt_304 , csi_opt_302 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a32oi_2  (
output Y,

input A1,
input A2,
input A3,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_304;
  wire csi_opt_302;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  nand ( csi_opt_304 , A2 , A1 , A3 ) ;
  nand ( csi_opt_302 , B2 , B1 ) ;
  and  ( UDP_IN_Y , csi_opt_304 , csi_opt_302 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_a32oi_4  (
output Y,

input A1,
input A2,
input A3,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_304;
  wire csi_opt_302;

`ifdef functional
`else
  specify
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A3==1'b1&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  nand ( csi_opt_304 , A2 , A1 , A3 ) ;
  nand ( csi_opt_302 , B2 , B1 ) ;
  and  ( UDP_IN_Y , csi_opt_304 , csi_opt_302 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and2_1  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (B +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and2_2  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (B +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and2_4  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (B +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and2_6  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (B +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and2_8  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (B +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and2b_1  (
output X,

input AN,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
  specify
    if (B==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0) (B +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  not ( csi_opt_276 , AN ) ;
  and  ( UDP_IN_X , csi_opt_276 , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and2b_2  (
output X,

input AN,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
  specify
    if (B==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0) (B +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  not ( csi_opt_276 , AN ) ;
  and  ( UDP_IN_X , csi_opt_276 , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and2b_4  (
output X,

input AN,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
  specify
    if (B==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0) (B +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  not ( csi_opt_276 , AN ) ;
  and  ( UDP_IN_X , csi_opt_276 , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and3_1  (
output X,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , C , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and3_2  (
output X,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , C , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and3_4  (
output X,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , C , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and3b_1  (
output X,

input AN,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_280;

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  not ( csi_opt_280 , AN ) ;
  and  ( UDP_IN_X , C , csi_opt_280 , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_and3b_2  (
output X,

input AN,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_280;

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  not ( csi_opt_280 , AN ) ;
  and  ( UDP_IN_X , C , csi_opt_280 , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and3b_4  (
output X,

input AN,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_280;

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  not ( csi_opt_280 , AN ) ;
  and  ( UDP_IN_X , C , csi_opt_280 , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and4_1  (
output X,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1&&D==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&D==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&C==1'b1) (D +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , A , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and4_2  (
output X,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1&&D==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&D==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&C==1'b1) (D +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , A , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and4_4  (
output X,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1&&D==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&D==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&C==1'b1) (D +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  and  ( UDP_IN_X , A , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and4b_1  (
output X,

input AN,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_284;

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&D==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&C==1'b1) (D +=> X)=(0:0:0, 0:0:0);
endspecify
`endif

  not ( csi_opt_284 , AN ) ;
  and  ( UDP_IN_X , csi_opt_284 , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and4b_2  (
output X,

input AN,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_284;

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&D==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&C==1'b1) (D +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  not ( csi_opt_284 , AN ) ;
  and  ( UDP_IN_X , csi_opt_284 , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and4b_4  (
output X,

input AN,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_284;

`ifdef functional
`else
  specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&D==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&C==1'b1) (D +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  not ( csi_opt_284 , AN ) ;
  and  ( UDP_IN_X , csi_opt_284 , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and4bb_1  (
output X,

input AN,
input BN,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_278;

`ifdef functional
`else
  specify
    if (BN==1'b0&&C==1'b1&&D==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (BN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&D==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&C==1'b1) (D +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  nor ( csi_opt_278 , AN , BN ) ;
  and  ( UDP_IN_X , csi_opt_278 , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and4bb_2  (
output X,

input AN,
input BN,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_278;

`ifdef functional
`else
  specify
    if (BN==1'b0&&C==1'b1&&D==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (BN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&D==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&C==1'b1) (D +=> X)=(0:0:0, 0:0:0);
endspecify
`endif

  nor ( csi_opt_278 , AN , BN ) ;
  and  ( UDP_IN_X , csi_opt_278 , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_and4bb_4  (
output X,

input AN,
input BN,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_278;

`ifdef functional
`else
  specify
    if (BN==1'b0&&C==1'b1&&D==1'b1) (AN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (BN -=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&D==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&C==1'b1) (D +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  nor ( csi_opt_278 , AN , BN ) ;
  and  ( UDP_IN_X , csi_opt_278 , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_buf_12  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_buf_16  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_buf_1  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_buf_2  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_buf_4  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_buf_6  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_buf_8  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_bufbuf_16  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_bufbuf_8  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_bufinv_16  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_bufinv_8  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkbuf_16  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkbuf_1  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkbuf_2  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkbuf_4  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkbuf_8  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkbuf_6  (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkbuf_12 (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkinv_16  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkinv_1  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkinv_2  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkinv_4  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkinv_8  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkinv_12 (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkinvlp_2  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkinvlp_4  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A -=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

module scs8hdll_clkmux2_1  (
output X,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1 (UDP_IN_X, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkmux2_2  (
output X,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1 (UDP_IN_X, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_clkmux2_4  (
output X,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1 (UDP_IN_X, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_conb_1  (
output HI,
output LO

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef SC_USE_PG_PIN
   pullup (UDP_IN_HI);
   scs8hdll_pg_U_VPWR (HI, UDP_IN_HI, vpwr);
   pulldown (UDP_IN_LO);
   scs8hdll_pg_U_VGND (LO, UDP_IN_LO, vgnd);
`else
  pullup (HI);
  pulldown (LO);
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dfrtp_1  (
output Q,

input CLK,
input D,
input RESETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire buf_Q;
  wire reset;

`ifdef functional
  not ( reset , RESETB ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_R_NO_pg #0.001 ( buf_Q , D , CLK , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_R #0.001 ( buf_Q , D , CLK , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire RESETB_delayed;
  wire CLK_delayed;
  not ( reset , RESETB_delayed ) ; 
scs8hdll_pg_U_DF_P_R_NO_pg ( buf_Q , D_delayed , CLK_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
  assign COND1 = ( AWAKE && ( RESETB === 1'b1 ) ) ; 
  specify
    if (CLK==1'b0&&D==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
     
    $recrem ( posedge RESETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
     
    $width ( posedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dfrtp_2  (
output Q,

input CLK,
input D,
input RESETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire buf_Q;
  wire reset;

`ifdef functional
  not ( reset , RESETB ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_R_NO_pg #0.001 ( buf_Q , D , CLK , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_R #0.001 ( buf_Q , D , CLK , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire RESETB_delayed;
  wire CLK_delayed;
  not ( reset , RESETB_delayed ) ; 
scs8hdll_pg_U_DF_P_R_NO_pg ( buf_Q , D_delayed , CLK_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
  assign COND1 = ( AWAKE && ( RESETB === 1'b1 ) ) ; 
  specify
    if (CLK==1'b0&&D==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
     
    $recrem ( posedge RESETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
     
    $width ( posedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_dfrtp_4  (
output Q,

input CLK,
input D,
input RESETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire reset;

`ifdef functional
  not ( reset , RESETB ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_R_NO_pg #0.001 ( buf_Q , D , CLK , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_R #0.001 ( buf_Q , D , CLK , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire RESETB_delayed;
  wire CLK_delayed;
  not ( reset , RESETB_delayed ) ; 
scs8hdll_pg_U_DF_P_R_NO_pg ( buf_Q , D_delayed , CLK_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
  assign COND1 = ( AWAKE && ( RESETB === 1'b1 ) ) ; 
  specify
    if (CLK==1'b0&&D==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
     
    $recrem ( posedge RESETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
     
    $width ( posedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dfstp_1  (
output Q,

input CLK,
input D,
input SETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire buf_Q;
  wire set;

`ifdef functional
  not ( set , SETB ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_S_NO_pg #0.001 ( buf_Q , D , CLK , set ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_S #0.001 ( buf_Q , D , CLK , set ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SETB_delayed;
  wire CLK_delayed;
  not ( set , SETB_delayed ) ; 
scs8hdll_pg_U_DF_P_S_NO_pg ( buf_Q , D_delayed , CLK_delayed , set , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( SETB_delayed === 1'b1 ) ; 
  assign COND1 = ( SETB === 1'b1 ) ; 
  specify
    if (CLK==1'b0&&D==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    
    $recrem ( posedge SETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
    
    $width ( posedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dfstp_2  (
output Q,

input CLK,
input D,
input SETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire buf_Q;
  wire set;

`ifdef functional
  not ( set , SETB ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_S_NO_pg #0.001 ( buf_Q , D , CLK , set ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_S #0.001 ( buf_Q , D , CLK , set ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SETB_delayed;
  wire CLK_delayed;
  not ( set , SETB_delayed ) ; 
scs8hdll_pg_U_DF_P_S_NO_pg ( buf_Q , D_delayed , CLK_delayed , set , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( SETB_delayed === 1'b1 ) ; 
  assign COND1 = ( SETB === 1'b1 ) ; 
  specify
    if (CLK==1'b0&&D==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    
    $recrem ( posedge SETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
    
    $width ( posedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dfstp_4  (
output Q,

input CLK,
input D,
input SETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire buf_Q;
  wire set;

`ifdef functional
  not ( set , SETB ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_S_NO_pg #0.001 ( buf_Q , D , CLK , set ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_S #0.001 ( buf_Q , D , CLK , set ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SETB_delayed;
  wire CLK_delayed;
  not ( set , SETB_delayed ) ; 
scs8hdll_pg_U_DF_P_S_NO_pg ( buf_Q , D_delayed , CLK_delayed , set , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( SETB_delayed === 1'b1 ) ; 
  assign COND1 = ( SETB === 1'b1 ) ; 
  specify
    if (CLK==1'b0&&D==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    
    $recrem ( posedge SETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , CLK_delayed , D_delayed ) ; 
    
    $width ( posedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dlrtn_1  (
output Q,
input RESETB,
input D,
input GATEN
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire reset;
  wire gate;

`ifdef functional
  not ( reset , RESETB ) ; 
  not ( gate , GATEN ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_R_NO_pg #0.001 ( buf_Q , D , gate , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P_R #0.001 ( buf_Q , D , gate , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire GATEN_delayed;
  wire RESET_delayed;
  not ( reset , RESETB_delayed ) ; 
  not ( gate , GATEN_delayed ) ; 
scs8hdll_pg_U_DL_P_R_NO_pg ( buf_Q , D_delayed , gate , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
  assign COND1 = ( AWAKE && ( RESETB === 1'b1 ) ) ; 
  specify
    ( negedge RESETB => ( Q +: RESETB ) ) = ( 0:0:0 , 0:0:0 ) ;  // delay is tfall
    ( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
    ( negedge GATEN => ( Q : GATEN ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall

    $recrem ( posedge RESETB , posedge GATEN , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , GATEN_delayed ) ; 
    $setuphold ( posedge GATEN , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATEN_delayed , D_delayed ) ; 
    $setuphold ( posedge GATEN , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATEN_delayed , D_delayed ) ; 
    $width ( negedge GATEN &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( posedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif
buf ( Q , buf_Q ) ; 
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dlrtn_2  (
output Q,
input RESETB,
input D,
input GATEN
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire reset;
  wire gate;

`ifdef functional
  not ( reset , RESETB ) ; 
  not ( gate , GATEN ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_R_NO_pg #0.001 ( buf_Q , D , gate , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P_R #0.001 ( buf_Q , D , gate , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire GATEN_delayed;
  wire RESET_delayed;
  not ( reset , RESETB_delayed ) ; 
  not ( gate , GATEN_delayed ) ; 
scs8hdll_pg_U_DL_P_R_NO_pg ( buf_Q , D_delayed , gate , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
  assign COND1 = ( AWAKE && ( RESETB === 1'b1 ) ) ; 
  specify
    ( negedge RESETB => ( Q +: RESETB ) ) = ( 0:0:0 , 0:0:0 ) ;  // delay is tfall
    ( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
    ( negedge GATEN => ( Q : GATEN ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall

    $recrem ( posedge RESETB , posedge GATEN , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , GATEN_delayed ) ; 
    $setuphold ( posedge GATEN , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATEN_delayed , D_delayed ) ; 
    $setuphold ( posedge GATEN , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATEN_delayed , D_delayed ) ; 
    $width ( negedge GATEN &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( posedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif
buf ( Q , buf_Q ) ; 
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dlrtn_4  (
output Q,
input RESETB,
input D,
input GATEN
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire reset;
  wire gate;

`ifdef functional
  not ( reset , RESETB ) ; 
  not ( gate , GATEN ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_R_NO_pg #0.001 ( buf_Q , D , gate , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P_R #0.001 ( buf_Q , D , gate , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire GATEN_delayed;
  wire RESET_delayed;
  not ( reset , RESETB_delayed ) ; 
  not ( gate , GATEN_delayed ) ; 
scs8hdll_pg_U_DL_P_R_NO_pg ( buf_Q , D_delayed , gate , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
  assign COND1 = ( AWAKE && ( RESETB === 1'b1 ) ) ; 
  specify
    ( negedge RESETB => ( Q +: RESETB ) ) = ( 0:0:0 , 0:0:0 ) ;  // delay is tfall
    ( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
    ( negedge GATEN => ( Q : GATEN ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall

    $recrem ( posedge RESETB , posedge GATEN , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , GATEN_delayed ) ; 
    $setuphold ( posedge GATEN , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATEN_delayed , D_delayed ) ; 
    $setuphold ( posedge GATEN , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATEN_delayed , D_delayed ) ; 
    $width ( negedge GATEN &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( posedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif
buf ( Q , buf_Q ) ; 
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dlrtp_1  (
output Q,
input RESETB,
input D,
input GATE
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);
`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif
  wire reset;

`ifdef functional
  not ( reset , RESETB ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_R_NO_pg #0.001 ( buf_Q , D , GATE , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P_R #0.001 ( buf_Q , D , GATE , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire GATE_delayed;
  wire RESET_delayed;
  not ( reset , RESETB_delayed ) ; 
scs8hdll_pg_U_DL_P_R_NO_pg ( buf_Q , D_delayed , GATE_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
  assign COND1 = ( AWAKE && ( RESETB === 1'b1 ) ) ; 
  specify
    ( negedge RESETB => ( Q +: RESETB ) ) = ( 0:0:0 , 0:0:0 ) ;  // delay is tfall
    ( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
    ( posedge GATE => ( Q : GATE ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall

    $recrem ( posedge RESETB , negedge GATE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , GATE_delayed ) ; 
    $setuphold ( negedge GATE , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ; 
    $setuphold ( negedge GATE , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ; 
    $width ( posedge GATE &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( posedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif
buf ( Q , buf_Q ) ; 
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dlrtp_2  (
output Q,
input RESETB,
input D,
input GATE
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);
`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif
  wire reset;

`ifdef functional
  not ( reset , RESETB ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_R_NO_pg #0.001 ( buf_Q , D , GATE , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P_R #0.001 ( buf_Q , D , GATE , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire GATE_delayed;
  wire RESET_delayed;
  not ( reset , RESETB_delayed ) ; 
scs8hdll_pg_U_DL_P_R_NO_pg ( buf_Q , D_delayed , GATE_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
  assign COND1 = ( AWAKE && ( RESETB === 1'b1 ) ) ; 
  specify
    ( negedge RESETB => ( Q +: RESETB ) ) = ( 0:0:0 , 0:0:0 ) ;  // delay is tfall
    ( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
    ( posedge GATE => ( Q : GATE ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall

    $recrem ( posedge RESETB , negedge GATE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , GATE_delayed ) ; 
    $setuphold ( negedge GATE , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ; 
    $setuphold ( negedge GATE , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ; 
    $width ( posedge GATE &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( posedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif
buf ( Q , buf_Q ) ; 
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dlrtp_4  (
output Q,
input RESETB,
input D,
input GATE
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);
`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif
  wire reset;

`ifdef functional
  not ( reset , RESETB ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_R_NO_pg #0.001 ( buf_Q , D , GATE , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P_R #0.001 ( buf_Q , D , GATE , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire GATE_delayed;
  wire RESET_delayed;
  not ( reset , RESETB_delayed ) ; 
scs8hdll_pg_U_DL_P_R_NO_pg ( buf_Q , D_delayed , GATE_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
  assign COND1 = ( AWAKE && ( RESETB === 1'b1 ) ) ; 
  specify
    ( negedge RESETB => ( Q +: RESETB ) ) = ( 0:0:0 , 0:0:0 ) ;  // delay is tfall
    ( D +=> Q ) = ( 0:0:0 , 0:0:0 ) ;  // delays are tris , tfall
    ( posedge GATE => ( Q : GATE ) ) = ( 0:0:0 , 0:0:0 ) ; // delays are tris , tfall

    $recrem ( posedge RESETB , negedge GATE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , GATE_delayed ) ; 
    $setuphold ( negedge GATE , posedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ; 
    $setuphold ( negedge GATE , negedge D , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , GATE_delayed , D_delayed ) ; 
    $width ( posedge GATE &&& COND1 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( posedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif
buf ( Q , buf_Q ) ; 
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dlxtn_1  (
output Q,

input D,
input GATEN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire gate;
  wire buf_Q;

`ifdef functional
    not ( gate , GATEN ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_NO_pg  ( buf_Q , D , gate ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P  ( buf_Q , D , gate ) ;
`endif 
`else
  wire GATEN_delayed;
  wire D_delayed;
  reg notifier ; 
  not ( gate , GATEN_delayed ) ; 
scs8hdll_pg_U_DL_P_NO_pg ( buf_Q , D_delayed , gate , notifier , vpwr , vgnd ) ; 
`endif

  buf ( Q , buf_Q ) ; 

`ifdef functional
`else
  wire AWAKE;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
	specify
    if (GATEN==1'b0) (D +=> Q)=(0:0:0, 0:0:0);
    if (D==1'b1) (negedge GATEN => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0) (negedge GATEN => (Q +: 1'b1))=(0:0:0, 0:0:0);
    
		$width ( negedge GATEN &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    
    $setuphold ( posedge GATEN , posedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATEN_delayed , D_delayed ) ; 
    $setuphold ( posedge GATEN , negedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATEN_delayed , D_delayed ) ; 
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dlxtn_2  (
output Q,

input D,
input GATEN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire gate;
  wire buf_Q;

`ifdef functional
    not ( gate , GATEN ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_NO_pg  ( buf_Q , D , gate ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P  ( buf_Q , D , gate ) ;
`endif 
`else
  wire GATEN_delayed;
  wire D_delayed;
  reg notifier ; 
  not ( gate , GATEN_delayed ) ; 
scs8hdll_pg_U_DL_P_NO_pg ( buf_Q , D_delayed , gate , notifier , vpwr , vgnd ) ; 
`endif

  buf ( Q , buf_Q ) ; 

`ifdef functional
`else
  wire AWAKE;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
	specify
    if (GATEN==1'b0) (D +=> Q)=(0:0:0, 0:0:0);
    if (D==1'b1) (negedge GATEN => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0) (negedge GATEN => (Q +: 1'b1))=(0:0:0, 0:0:0);
    
		$width ( negedge GATEN &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    
    $setuphold ( posedge GATEN , posedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATEN_delayed , D_delayed ) ; 
    $setuphold ( posedge GATEN , negedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATEN_delayed , D_delayed ) ; 
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dlxtn_4  (
output Q,

input D,
input GATEN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire gate;
  wire buf_Q;

`ifdef functional
    not ( gate , GATEN ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_NO_pg  ( buf_Q , D , gate ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P  ( buf_Q , D , gate ) ;
`endif 
`else
  wire GATEN_delayed;
  wire D_delayed;
  reg notifier ; 
  not ( gate , GATEN_delayed ) ; 
scs8hdll_pg_U_DL_P_NO_pg ( buf_Q , D_delayed , gate , notifier , vpwr , vgnd ) ; 
`endif

  buf ( Q , buf_Q ) ; 

`ifdef functional
`else
  wire AWAKE;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
	specify
    if (GATEN==1'b0) (D +=> Q)=(0:0:0, 0:0:0);
    if (D==1'b1) (negedge GATEN => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0) (negedge GATEN => (Q +: 1'b1))=(0:0:0, 0:0:0);
    
		$width ( negedge GATEN &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    
    $setuphold ( posedge GATEN , posedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATEN_delayed , D_delayed ) ; 
    $setuphold ( posedge GATEN , negedge D , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , GATEN_delayed , D_delayed ) ; 
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_dlygate4sd1_1  (
output X,
input A


`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

// modification by BNB, based on SPR13943.  need to have
// the reg and specify gone when using a functional model.
`ifdef functional
`else
	specify
		(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
	endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

module scs8hdll_dlygate4sd2_1  (
output X,
input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

// modification by BNB, based on SPR13943.  need to have
// the reg and specify gone when using a functional model.
`ifdef functional
`else
	specify
		(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
	endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

module scs8hdll_dlygate4sd3_1  (
output X,
input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

// modification by BNB, based on SPR13943.  need to have
// the reg and specify gone when using a functional model.
`ifdef functional
`else
	specify
		(A +=> X ) = (0:0:0,0:0:0);  // delays are tris,tfall
	endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_ebufn_1  (
output Z,

input A,
input TEB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TEB, TEB, vpwr, vgnd) ;
bufif0 (Z,UDP_OUT_A,UDP_OUT_TEB);

  `else
    bufif0 ( Z , A , TEB ) ;
  `endif
`ifdef functional
`else
	specify
    if (TEB==1'b0) (A +=> Z)=(0:0:0, 0:0:0);
    if (A==1'b1) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b0) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_ebufn_2  (
output Z,

input A,
input TEB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TEB, TEB, vpwr, vgnd) ;
bufif0 (Z,UDP_OUT_A,UDP_OUT_TEB);

  `else
    bufif0 ( Z , A , TEB ) ;
  `endif
`ifdef functional
`else
	specify
    if (TEB==1'b0) (A +=> Z)=(0:0:0, 0:0:0);
    if (A==1'b1) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b0) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_ebufn_4  (
output Z,

input A,
input TEB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TEB, TEB, vpwr, vgnd) ;
bufif0 (Z,UDP_OUT_A,UDP_OUT_TEB);

  `else
    bufif0 ( Z , A , TEB ) ;
  `endif
`ifdef functional
`else
	specify
    if (TEB==1'b0) (A +=> Z)=(0:0:0, 0:0:0);
    if (A==1'b1) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b0) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_ebufn_8  (
output Z,

input A,
input TEB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TEB, TEB, vpwr, vgnd) ;
bufif0 (Z,UDP_OUT_A,UDP_OUT_TEB);

  `else
    bufif0 ( Z , A , TEB ) ;
  `endif
`ifdef functional
`else
	specify
    if (TEB==1'b0) (A +=> Z)=(0:0:0, 0:0:0);
    if (A==1'b1) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b0) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_einvn_1  (
output Z,

input A,
input TEB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TEB, TEB, vpwr, vgnd) ;
notif0 (Z,UDP_OUT_A,UDP_OUT_TEB);

  `else
    notif0 ( Z , A , TEB ) ;
  `endif
`ifdef functional
`else
	specify
    if (TEB==1'b0) (A -=> Z)=(0:0:0, 0:0:0);
    if (A==1'b0) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b1) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_einvn_2  (
output Z,

input A,
input TEB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TEB, TEB, vpwr, vgnd) ;
notif0 (Z,UDP_OUT_A,UDP_OUT_TEB);

  `else
    notif0 ( Z , A , TEB ) ;
  `endif
`ifdef functional
`else
	specify
    if (TEB==1'b0) (A -=> Z)=(0:0:0, 0:0:0);
    if (A==1'b0) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b1) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_einvn_4  (
output Z,

input A,
input TEB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TEB, TEB, vpwr, vgnd) ;
notif0 (Z,UDP_OUT_A,UDP_OUT_TEB);

  `else
    notif0 ( Z , A , TEB ) ;
  `endif
`ifdef functional
`else
	specify
    if (TEB==1'b0) (A -=> Z)=(0:0:0, 0:0:0);
    if (A==1'b0) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b1) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_einvn_8  (
output Z,

input A,
input TEB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TEB, TEB, vpwr, vgnd) ;
notif0 (Z,UDP_OUT_A,UDP_OUT_TEB);

  `else
    notif0 ( Z , A , TEB ) ;
  `endif
`ifdef functional
`else
	specify
    if (TEB==1'b0) (A -=> Z)=(0:0:0, 0:0:0);
    if (A==1'b0) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b1) (TEB => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_einvp_1  (
output Z,

input A,
input TE

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TE, TE, vpwr, vgnd) ;
notif1 (Z,UDP_OUT_A,UDP_OUT_TE);

  `else
    notif1 ( Z , A , TE ) ;
  `endif
`ifdef functional
`else
	specify
    if (TE==1'b1) (A -=> Z)=(0:0:0, 0:0:0);
    if (A==1'b0) (TE => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b1) (TE => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_einvp_2  (
output Z,

input A,
input TE

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TE, TE, vpwr, vgnd) ;
notif1 (Z,UDP_OUT_A,UDP_OUT_TE);

  `else
    notif1 ( Z , A , TE ) ;
  `endif
`ifdef functional
`else
	specify
    if (TE==1'b1) (A -=> Z)=(0:0:0, 0:0:0);
    if (A==1'b0) (TE => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b1) (TE => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_einvp_4  (
output Z,

input A,
input TE

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TE, TE, vpwr, vgnd) ;
notif1 (Z,UDP_OUT_A,UDP_OUT_TE);

  `else
    notif1 ( Z , A , TE ) ;
  `endif
`ifdef functional
`else
	specify
    if (TE==1'b1) (A -=> Z)=(0:0:0, 0:0:0);
    if (A==1'b0) (TE => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b1) (TE => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_einvp_8  (
output Z,

input A,
input TE

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_A, A, vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_TE, TE, vpwr, vgnd) ;
notif1 (Z,UDP_OUT_A,UDP_OUT_TE);

  `else
    notif1 ( Z , A , TE ) ;
  `endif
`ifdef functional
`else
	specify
    if (TE==1'b1) (A -=> Z)=(0:0:0, 0:0:0);
    if (A==1'b0) (TE => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
    if (A==1'b1) (TE => Z)=(0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_inv_12  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
		(A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
	endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_inv_16  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
		(A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
	endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_inv_1  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
		(A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
	endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_inv_2  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
		(A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
	endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_inv_4  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
		(A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
	endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_inv_6  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
		(A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
	endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_inv_8  (
output Y,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
		(A -=> Y ) = (0:0:0,0:0:0);  // delays are tris,tfall
	endspecify
`endif

  not  ( UDP_IN_Y , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_mux2_1  (
output X,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1 (UDP_IN_X, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_mux2_2  (
output X,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1 (UDP_IN_X, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_mux2_4  (
output X,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1 (UDP_IN_X, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_mux2_8  (
output X,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1 (UDP_IN_X, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_mux2_12 (
output X,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1 (UDP_IN_X, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_mux2_16 (
output X,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S +=> X)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1 (UDP_IN_X, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_mux2i_1  (
output Y,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif
   
  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1_INV (UDP_IN_Y, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
   
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_mux2i_2  (
output Y,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif
   
  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1_INV (UDP_IN_Y, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
   
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_mux2i_4  (
output Y,

input A0,
input A1,
input S

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (A1==1'b0&&S==1'b0) (A0 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&S==1'b0) (A0 -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b0&&S==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b1&&S==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b0&&A1==1'b1) (S -=> Y)=(0:0:0, 0:0:0);
    if (A0==1'b1&&A1==1'b0) (S +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif
   
  // aug27,2003 - bnb changed to udp model for muxs
   
  scs8hdll_pg_U_MUX_2_1_INV (UDP_IN_Y, A0, A1, S);
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
   
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`timescale 1ns / 1ps
`celldefine
module scs8hdll_muxb4to1_1  (
output Z,
input [3:0]D,
input [3:0]S
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
  `ifdef SC_USE_PG_PIN
  `else
    supply1 vpwr;
    supply0 vgnd;
    supply1 vpb;
    supply0 vnb;
  `endif
`endif

`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d0, D[0], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s0, S[0], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d0, UDP_OUT_s0) ;
`else
  bufif1 (Z, !D[0], S[0]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d1, D[1], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s1, S[1], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d1, UDP_OUT_s1) ;
`else
  bufif1 (Z, !D[1], S[1]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d2, D[2], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s2, S[2], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d2, UDP_OUT_s2) ;
`else
  bufif1 (Z, !D[2], S[2]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d3, D[3], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s3, S[3], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d3, UDP_OUT_s3) ;
`else
  bufif1 (Z, !D[3], S[3]) ;
`endif

`ifdef functional
`else
specify
(D[0] -=> Z)=(0:0:0, 0:0:0);
(D[1] -=> Z)=(0:0:0, 0:0:0);
(D[2] -=> Z)=(0:0:0, 0:0:0);
(D[3] -=> Z)=(0:0:0, 0:0:0);
(S[0] +=> Z)=(0:0:0, 0:0:0);
(S[1] +=> Z)=(0:0:0, 0:0:0);
(S[2] +=> Z)=(0:0:0, 0:0:0);
(S[3] -=> Z)=(0:0:0, 0:0:0);
endspecify
`endif

endmodule
`endcelldefine

`timescale 1ns / 1ps
`celldefine
module scs8hdll_muxb4to1_2  (
output Z,
input [3:0]D,
input [3:0]S
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
  `ifdef SC_USE_PG_PIN
  `else
    supply1 vpwr;
    supply0 vgnd;
    supply1 vpb;
    supply0 vnb;
  `endif
`endif

`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d0, D[0], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s0, S[0], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d0, UDP_OUT_s0) ;
`else
  bufif1 (Z, !D[0], S[0]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d1, D[1], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s1, S[1], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d1, UDP_OUT_s1) ;
`else
  bufif1 (Z, !D[1], S[1]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d2, D[2], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s2, S[2], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d2, UDP_OUT_s2) ;
`else
  bufif1 (Z, !D[2], S[2]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d3, D[3], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s3, S[3], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d3, UDP_OUT_s3) ;
`else
  bufif1 (Z, !D[3], S[3]) ;
`endif

`ifdef functional
`else
specify
(D[0] -=> Z)=(0:0:0, 0:0:0);
(D[1] -=> Z)=(0:0:0, 0:0:0);
(D[2] -=> Z)=(0:0:0, 0:0:0);
(D[3] -=> Z)=(0:0:0, 0:0:0);
(S[0] +=> Z)=(0:0:0, 0:0:0);
(S[1] +=> Z)=(0:0:0, 0:0:0);
(S[2] +=> Z)=(0:0:0, 0:0:0);
(S[3] -=> Z)=(0:0:0, 0:0:0);
endspecify
`endif

endmodule
`endcelldefine

`timescale 1ns / 1ps
`celldefine
module scs8hdll_muxb4to1_4  (
output Z,
input [3:0]D,
input [3:0]S
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
  `ifdef SC_USE_PG_PIN
  `else
    supply1 vpwr;
    supply0 vgnd;
    supply1 vpb;
    supply0 vnb;
  `endif
`endif

`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d0, D[0], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s0, S[0], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d0, UDP_OUT_s0) ;
`else
  bufif1 (Z, !D[0], S[0]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d1, D[1], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s1, S[1], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d1, UDP_OUT_s1) ;
`else
  bufif1 (Z, !D[1], S[1]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d2, D[2], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s2, S[2], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d2, UDP_OUT_s2) ;
`else
  bufif1 (Z, !D[2], S[2]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d3, D[3], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s3, S[3], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d3, UDP_OUT_s3) ;
`else
  bufif1 (Z, !D[3], S[3]) ;
`endif

`ifdef functional
`else
specify
(D[0] -=> Z)=(0:0:0, 0:0:0);
(D[1] -=> Z)=(0:0:0, 0:0:0);
(D[2] -=> Z)=(0:0:0, 0:0:0);
(D[3] -=> Z)=(0:0:0, 0:0:0);
(S[0] +=> Z)=(0:0:0, 0:0:0);
(S[1] +=> Z)=(0:0:0, 0:0:0);
(S[2] +=> Z)=(0:0:0, 0:0:0);
(S[3] -=> Z)=(0:0:0, 0:0:0);
endspecify
`endif

endmodule
`endcelldefine

`timescale 1ns / 1ps
`celldefine
module scs8hdll_muxb8to1_1  (
output Z,
input [7:0]D,
input [7:0]S
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
  `ifdef SC_USE_PG_PIN
  `else
    supply1 vpwr;
    supply0 vgnd;
    supply1 vpb;
    supply0 vnb;
  `endif
`endif

`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d0, D[0], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s0, S[0], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d0, UDP_OUT_s0) ;
`else
  bufif1 (Z, !D[0], S[0]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d1, D[1], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s1, S[1], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d1, UDP_OUT_s1) ;
`else
  bufif1 (Z, !D[1], S[1]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d2, D[2], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s2, S[2], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d2, UDP_OUT_s2) ;
`else
  bufif1 (Z, !D[2], S[2]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d3, D[3], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s3, S[3], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d3, UDP_OUT_s3) ;
`else
  bufif1 (Z, !D[3], S[3]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d4, D[4], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s4, S[4], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d4, UDP_OUT_s4) ;
`else
  bufif1 (Z, !D[4], S[4]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d5, D[5], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s5, S[5], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d5, UDP_OUT_s5) ;
`else
  bufif1 (Z, !D[5], S[5]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d6, D[6], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s6, S[6], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d6, UDP_OUT_s6) ;
`else
  bufif1 (Z, !D[6], S[6]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d7, D[7], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s7, S[7], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d7, UDP_OUT_s7) ;
`else
  bufif1 (Z, !D[7], S[7]) ;
`endif

`ifdef functional
`else
specify
(D[0] -=> Z)=(0:0:0, 0:0:0);
(D[1] -=> Z)=(0:0:0, 0:0:0);
(D[2] -=> Z)=(0:0:0, 0:0:0);
(D[3] -=> Z)=(0:0:0, 0:0:0);
(D[4] -=> Z)=(0:0:0, 0:0:0);
(D[5] -=> Z)=(0:0:0, 0:0:0);
(D[6] -=> Z)=(0:0:0, 0:0:0);
(D[7] -=> Z)=(0:0:0, 0:0:0);
(S[0] +=> Z)=(0:0:0, 0:0:0);
(S[1] +=> Z)=(0:0:0, 0:0:0);
(S[2] +=> Z)=(0:0:0, 0:0:0);
(S[3] +=> Z)=(0:0:0, 0:0:0);
(S[4] +=> Z)=(0:0:0, 0:0:0);
(S[5] +=> Z)=(0:0:0, 0:0:0);
(S[6] +=> Z)=(0:0:0, 0:0:0);
(S[7] -=> Z)=(0:0:0, 0:0:0);
endspecify
`endif

endmodule
`endcelldefine

`timescale 1ns / 1ps
`celldefine
module scs8hdll_muxb8to1_2  (
output Z,
input [7:0]D,
input [7:0]S
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
  `ifdef SC_USE_PG_PIN
  `else
    supply1 vpwr;
    supply0 vgnd;
    supply1 vpb;
    supply0 vnb;
  `endif
`endif

`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d0, D[0], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s0, S[0], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d0, UDP_OUT_s0) ;
`else
  bufif1 (Z, !D[0], S[0]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d1, D[1], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s1, S[1], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d1, UDP_OUT_s1) ;
`else
  bufif1 (Z, !D[1], S[1]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d2, D[2], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s2, S[2], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d2, UDP_OUT_s2) ;
`else
  bufif1 (Z, !D[2], S[2]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d3, D[3], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s3, S[3], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d3, UDP_OUT_s3) ;
`else
  bufif1 (Z, !D[3], S[3]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d4, D[4], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s4, S[4], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d4, UDP_OUT_s4) ;
`else
  bufif1 (Z, !D[4], S[4]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d5, D[5], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s5, S[5], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d5, UDP_OUT_s5) ;
`else
  bufif1 (Z, !D[5], S[5]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d6, D[6], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s6, S[6], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d6, UDP_OUT_s6) ;
`else
  bufif1 (Z, !D[6], S[6]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d7, D[7], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s7, S[7], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d7, UDP_OUT_s7) ;
`else
  bufif1 (Z, !D[7], S[7]) ;
`endif

`ifdef functional
`else
specify
(D[0] -=> Z)=(0:0:0, 0:0:0);
(D[1] -=> Z)=(0:0:0, 0:0:0);
(D[2] -=> Z)=(0:0:0, 0:0:0);
(D[3] -=> Z)=(0:0:0, 0:0:0);
(D[4] -=> Z)=(0:0:0, 0:0:0);
(D[5] -=> Z)=(0:0:0, 0:0:0);
(D[6] -=> Z)=(0:0:0, 0:0:0);
(D[7] -=> Z)=(0:0:0, 0:0:0);
(S[0] +=> Z)=(0:0:0, 0:0:0);
(S[1] +=> Z)=(0:0:0, 0:0:0);
(S[2] +=> Z)=(0:0:0, 0:0:0);
(S[3] +=> Z)=(0:0:0, 0:0:0);
(S[4] +=> Z)=(0:0:0, 0:0:0);
(S[5] +=> Z)=(0:0:0, 0:0:0);
(S[6] +=> Z)=(0:0:0, 0:0:0);
(S[7] -=> Z)=(0:0:0, 0:0:0);
endspecify
`endif

endmodule
`endcelldefine

`timescale 1ns / 1ps
`celldefine
module scs8hdll_muxb8to1_4  (
output Z,
input [7:0]D,
input [7:0]S
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
  `ifdef SC_USE_PG_PIN
  `else
    supply1 vpwr;
    supply0 vgnd;
    supply1 vpb;
    supply0 vnb;
  `endif
`endif

`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d0, D[0], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s0, S[0], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d0, UDP_OUT_s0) ;
`else
  bufif1 (Z, !D[0], S[0]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d1, D[1], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s1, S[1], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d1, UDP_OUT_s1) ;
`else
  bufif1 (Z, !D[1], S[1]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d2, D[2], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s2, S[2], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d2, UDP_OUT_s2) ;
`else
  bufif1 (Z, !D[2], S[2]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d3, D[3], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s3, S[3], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d3, UDP_OUT_s3) ;
`else
  bufif1 (Z, !D[3], S[3]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d4, D[4], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s4, S[4], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d4, UDP_OUT_s4) ;
`else
  bufif1 (Z, !D[4], S[4]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d5, D[5], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s5, S[5], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d5, UDP_OUT_s5) ;
`else
  bufif1 (Z, !D[5], S[5]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d6, D[6], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s6, S[6], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d6, UDP_OUT_s6) ;
`else
  bufif1 (Z, !D[6], S[6]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d7, D[7], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s7, S[7], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d7, UDP_OUT_s7) ;
`else
  bufif1 (Z, !D[7], S[7]) ;
`endif

`ifdef functional
`else
specify
(D[0] -=> Z)=(0:0:0, 0:0:0);
(D[1] -=> Z)=(0:0:0, 0:0:0);
(D[2] -=> Z)=(0:0:0, 0:0:0);
(D[3] -=> Z)=(0:0:0, 0:0:0);
(D[4] -=> Z)=(0:0:0, 0:0:0);
(D[5] -=> Z)=(0:0:0, 0:0:0);
(D[6] -=> Z)=(0:0:0, 0:0:0);
(D[7] -=> Z)=(0:0:0, 0:0:0);
(S[0] +=> Z)=(0:0:0, 0:0:0);
(S[1] +=> Z)=(0:0:0, 0:0:0);
(S[2] +=> Z)=(0:0:0, 0:0:0);
(S[3] +=> Z)=(0:0:0, 0:0:0);
(S[4] +=> Z)=(0:0:0, 0:0:0);
(S[5] +=> Z)=(0:0:0, 0:0:0);
(S[6] +=> Z)=(0:0:0, 0:0:0);
(S[7] -=> Z)=(0:0:0, 0:0:0);
endspecify
`endif

endmodule
`endcelldefine

`timescale 1ns / 1ps
`celldefine
module scs8hdll_muxb16to1_1 (
output Z,
input [15:0]D,
input [15:0]S
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
  `ifdef SC_USE_PG_PIN
  `else
    supply1 vpwr;
    supply0 vgnd;
    supply1 vpb;
    supply0 vnb;
  `endif
`endif

`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d0, D[0], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s0, S[0], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d0, UDP_OUT_s0) ;
`else
  bufif1 (Z, !D[0], S[0]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d1, D[1], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s1, S[1], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d1, UDP_OUT_s1) ;
`else
  bufif1 (Z, !D[1], S[1]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d2, D[2], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s2, S[2], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d2, UDP_OUT_s2) ;
`else
  bufif1 (Z, !D[2], S[2]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d3, D[3], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s3, S[3], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d3, UDP_OUT_s3) ;
`else
  bufif1 (Z, !D[3], S[3]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d4, D[4], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s4, S[4], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d4, UDP_OUT_s4) ;
`else
  bufif1 (Z, !D[4], S[4]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d5, D[5], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s5, S[5], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d5, UDP_OUT_s5) ;
`else
  bufif1 (Z, !D[5], S[5]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d6, D[6], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s6, S[6], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d6, UDP_OUT_s6) ;
`else
  bufif1 (Z, !D[6], S[6]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d7, D[7], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s7, S[7], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d7, UDP_OUT_s7) ;
`else
  bufif1 (Z, !D[7], S[7]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d8, D[8], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s8, S[8], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d8, UDP_OUT_s8) ;
`else
  bufif1 (Z, !D[8], S[8]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d9, D[9], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s9, S[9], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d9, UDP_OUT_s9) ;
`else
  bufif1 (Z, !D[9], S[9]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d10, D[10], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s10, S[10], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d10, UDP_OUT_s10) ;
`else
  bufif1 (Z, !D[10], S[10]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d11, D[11], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s11, S[11], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d11, UDP_OUT_s11) ;
`else
  bufif1 (Z, !D[11], S[11]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d12, D[12], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s12, S[12], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d12, UDP_OUT_s12) ;
`else
  bufif1 (Z, !D[12], S[12]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d13, D[13], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s13, S[13], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d13, UDP_OUT_s13) ;
`else
  bufif1 (Z, !D[13], S[13]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d14, D[14], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s14, S[14], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d14, UDP_OUT_s14) ;
`else
  bufif1 (Z, !D[14], S[14]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d15, D[15], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s15, S[15], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d15, UDP_OUT_s15) ;
`else
  bufif1 (Z, !D[15], S[15]) ;
`endif

`ifdef functional
`else
specify
(D[0] -=> Z)=(0:0:0, 0:0:0);
(S[10] +=> Z)=(0:0:0, 0:0:0);
(S[9] +=> Z)=(0:0:0, 0:0:0);
(S[8] +=> Z)=(0:0:0, 0:0:0);
(S[1] +=> Z)=(0:0:0, 0:0:0);
(S[2] +=> Z)=(0:0:0, 0:0:0);
(D[10] -=> Z)=(0:0:0, 0:0:0);
(D[11] -=> Z)=(0:0:0, 0:0:0);
(D[12] -=> Z)=(0:0:0, 0:0:0);
(D[13] -=> Z)=(0:0:0, 0:0:0);
(D[14] -=> Z)=(0:0:0, 0:0:0);
(D[15] -=> Z)=(0:0:0, 0:0:0);
(D[9] -=> Z)=(0:0:0, 0:0:0);
(D[8] -=> Z)=(0:0:0, 0:0:0);
(D[1] -=> Z)=(0:0:0, 0:0:0);
(D[2] -=> Z)=(0:0:0, 0:0:0);
(D[3] -=> Z)=(0:0:0, 0:0:0);
(D[4] -=> Z)=(0:0:0, 0:0:0);
(D[5] -=> Z)=(0:0:0, 0:0:0);
(D[6] -=> Z)=(0:0:0, 0:0:0);
(D[7] -=> Z)=(0:0:0, 0:0:0);
(S[0] +=> Z)=(0:0:0, 0:0:0);
(S[3] +=> Z)=(0:0:0, 0:0:0);
(S[4] +=> Z)=(0:0:0, 0:0:0);
(S[5] +=> Z)=(0:0:0, 0:0:0);
(S[6] +=> Z)=(0:0:0, 0:0:0);
(S[11] +=> Z)=(0:0:0, 0:0:0);
(S[12] +=> Z)=(0:0:0, 0:0:0);
(S[13] +=> Z)=(0:0:0, 0:0:0);
(S[14] +=> Z)=(0:0:0, 0:0:0);
(S[15] +=> Z)=(0:0:0, 0:0:0);
(S[7] -=> Z)=(0:0:0, 0:0:0);
endspecify
`endif

endmodule
`endcelldefine

`timescale 1ns / 1ps
`celldefine
module scs8hdll_muxb16to1_2 (
output Z,
input [15:0]D,
input [15:0]S
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
  `ifdef SC_USE_PG_PIN
  `else
    supply1 vpwr;
    supply0 vgnd;
    supply1 vpb;
    supply0 vnb;
  `endif
`endif

`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d0, D[0], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s0, S[0], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d0, UDP_OUT_s0) ;
`else
  bufif1 (Z, !D[0], S[0]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d1, D[1], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s1, S[1], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d1, UDP_OUT_s1) ;
`else
  bufif1 (Z, !D[1], S[1]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d2, D[2], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s2, S[2], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d2, UDP_OUT_s2) ;
`else
  bufif1 (Z, !D[2], S[2]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d3, D[3], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s3, S[3], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d3, UDP_OUT_s3) ;
`else
  bufif1 (Z, !D[3], S[3]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d4, D[4], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s4, S[4], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d4, UDP_OUT_s4) ;
`else
  bufif1 (Z, !D[4], S[4]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d5, D[5], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s5, S[5], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d5, UDP_OUT_s5) ;
`else
  bufif1 (Z, !D[5], S[5]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d6, D[6], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s6, S[6], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d6, UDP_OUT_s6) ;
`else
  bufif1 (Z, !D[6], S[6]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d7, D[7], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s7, S[7], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d7, UDP_OUT_s7) ;
`else
  bufif1 (Z, !D[7], S[7]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d8, D[8], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s8, S[8], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d8, UDP_OUT_s8) ;
`else
  bufif1 (Z, !D[8], S[8]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d9, D[9], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s9, S[9], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d9, UDP_OUT_s9) ;
`else
  bufif1 (Z, !D[9], S[9]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d10, D[10], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s10, S[10], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d10, UDP_OUT_s10) ;
`else
  bufif1 (Z, !D[10], S[10]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d11, D[11], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s11, S[11], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d11, UDP_OUT_s11) ;
`else
  bufif1 (Z, !D[11], S[11]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d12, D[12], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s12, S[12], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d12, UDP_OUT_s12) ;
`else
  bufif1 (Z, !D[12], S[12]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d13, D[13], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s13, S[13], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d13, UDP_OUT_s13) ;
`else
  bufif1 (Z, !D[13], S[13]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d14, D[14], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s14, S[14], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d14, UDP_OUT_s14) ;
`else
  bufif1 (Z, !D[14], S[14]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d15, D[15], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s15, S[15], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d15, UDP_OUT_s15) ;
`else
  bufif1 (Z, !D[15], S[15]) ;
`endif

`ifdef functional
`else
specify
(D[0] -=> Z)=(0:0:0, 0:0:0);
(S[10] +=> Z)=(0:0:0, 0:0:0);
(S[9] +=> Z)=(0:0:0, 0:0:0);
(S[8] +=> Z)=(0:0:0, 0:0:0);
(S[1] +=> Z)=(0:0:0, 0:0:0);
(S[2] +=> Z)=(0:0:0, 0:0:0);
(D[10] -=> Z)=(0:0:0, 0:0:0);
(D[11] -=> Z)=(0:0:0, 0:0:0);
(D[12] -=> Z)=(0:0:0, 0:0:0);
(D[13] -=> Z)=(0:0:0, 0:0:0);
(D[14] -=> Z)=(0:0:0, 0:0:0);
(D[15] -=> Z)=(0:0:0, 0:0:0);
(D[9] -=> Z)=(0:0:0, 0:0:0);
(D[8] -=> Z)=(0:0:0, 0:0:0);
(D[1] -=> Z)=(0:0:0, 0:0:0);
(D[2] -=> Z)=(0:0:0, 0:0:0);
(D[3] -=> Z)=(0:0:0, 0:0:0);
(D[4] -=> Z)=(0:0:0, 0:0:0);
(D[5] -=> Z)=(0:0:0, 0:0:0);
(D[6] -=> Z)=(0:0:0, 0:0:0);
(D[7] -=> Z)=(0:0:0, 0:0:0);
(S[0] +=> Z)=(0:0:0, 0:0:0);
(S[3] +=> Z)=(0:0:0, 0:0:0);
(S[4] +=> Z)=(0:0:0, 0:0:0);
(S[5] +=> Z)=(0:0:0, 0:0:0);
(S[6] +=> Z)=(0:0:0, 0:0:0);
(S[11] +=> Z)=(0:0:0, 0:0:0);
(S[12] +=> Z)=(0:0:0, 0:0:0);
(S[13] +=> Z)=(0:0:0, 0:0:0);
(S[14] +=> Z)=(0:0:0, 0:0:0);
(S[15] +=> Z)=(0:0:0, 0:0:0);
(S[7] -=> Z)=(0:0:0, 0:0:0);
endspecify
`endif

endmodule
`endcelldefine

`timescale 1ns / 1ps
`celldefine
module scs8hdll_muxb16to1_4 (
output Z,
input [15:0]D,
input [15:0]S
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
  `ifdef SC_USE_PG_PIN
  `else
    supply1 vpwr;
    supply0 vgnd;
    supply1 vpb;
    supply0 vnb;
  `endif
`endif

`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d0, D[0], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s0, S[0], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d0, UDP_OUT_s0) ;
`else
  bufif1 (Z, !D[0], S[0]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d1, D[1], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s1, S[1], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d1, UDP_OUT_s1) ;
`else
  bufif1 (Z, !D[1], S[1]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d2, D[2], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s2, S[2], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d2, UDP_OUT_s2) ;
`else
  bufif1 (Z, !D[2], S[2]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d3, D[3], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s3, S[3], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d3, UDP_OUT_s3) ;
`else
  bufif1 (Z, !D[3], S[3]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d4, D[4], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s4, S[4], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d4, UDP_OUT_s4) ;
`else
  bufif1 (Z, !D[4], S[4]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d5, D[5], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s5, S[5], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d5, UDP_OUT_s5) ;
`else
  bufif1 (Z, !D[5], S[5]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d6, D[6], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s6, S[6], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d6, UDP_OUT_s6) ;
`else
  bufif1 (Z, !D[6], S[6]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d7, D[7], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s7, S[7], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d7, UDP_OUT_s7) ;
`else
  bufif1 (Z, !D[7], S[7]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d8, D[8], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s8, S[8], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d8, UDP_OUT_s8) ;
`else
  bufif1 (Z, !D[8], S[8]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d9, D[9], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s9, S[9], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d9, UDP_OUT_s9) ;
`else
  bufif1 (Z, !D[9], S[9]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d10, D[10], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s10, S[10], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d10, UDP_OUT_s10) ;
`else
  bufif1 (Z, !D[10], S[10]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d11, D[11], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s11, S[11], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d11, UDP_OUT_s11) ;
`else
  bufif1 (Z, !D[11], S[11]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d12, D[12], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s12, S[12], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d12, UDP_OUT_s12) ;
`else
  bufif1 (Z, !D[12], S[12]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d13, D[13], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s13, S[13], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d13, UDP_OUT_s13) ;
`else
  bufif1 (Z, !D[13], S[13]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d14, D[14], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s14, S[14], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d14, UDP_OUT_s14) ;
`else
  bufif1 (Z, !D[14], S[14]) ;
`endif
`ifdef SC_USE_PG_PIN
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_d15, D[15], vpwr, vgnd) ;
  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_s15, S[15], vpwr, vgnd) ;
  bufif1 (Z, !UDP_OUT_d15, UDP_OUT_s15) ;
`else
  bufif1 (Z, !D[15], S[15]) ;
`endif

`ifdef functional
`else
specify
(D[0] -=> Z)=(0:0:0, 0:0:0);
(S[10] +=> Z)=(0:0:0, 0:0:0);
(S[9] +=> Z)=(0:0:0, 0:0:0);
(S[8] +=> Z)=(0:0:0, 0:0:0);
(S[1] +=> Z)=(0:0:0, 0:0:0);
(S[2] +=> Z)=(0:0:0, 0:0:0);
(D[10] -=> Z)=(0:0:0, 0:0:0);
(D[11] -=> Z)=(0:0:0, 0:0:0);
(D[12] -=> Z)=(0:0:0, 0:0:0);
(D[13] -=> Z)=(0:0:0, 0:0:0);
(D[14] -=> Z)=(0:0:0, 0:0:0);
(D[15] -=> Z)=(0:0:0, 0:0:0);
(D[9] -=> Z)=(0:0:0, 0:0:0);
(D[8] -=> Z)=(0:0:0, 0:0:0);
(D[1] -=> Z)=(0:0:0, 0:0:0);
(D[2] -=> Z)=(0:0:0, 0:0:0);
(D[3] -=> Z)=(0:0:0, 0:0:0);
(D[4] -=> Z)=(0:0:0, 0:0:0);
(D[5] -=> Z)=(0:0:0, 0:0:0);
(D[6] -=> Z)=(0:0:0, 0:0:0);
(D[7] -=> Z)=(0:0:0, 0:0:0);
(S[0] +=> Z)=(0:0:0, 0:0:0);
(S[3] +=> Z)=(0:0:0, 0:0:0);
(S[4] +=> Z)=(0:0:0, 0:0:0);
(S[5] +=> Z)=(0:0:0, 0:0:0);
(S[6] +=> Z)=(0:0:0, 0:0:0);
(S[11] +=> Z)=(0:0:0, 0:0:0);
(S[12] +=> Z)=(0:0:0, 0:0:0);
(S[13] +=> Z)=(0:0:0, 0:0:0);
(S[14] +=> Z)=(0:0:0, 0:0:0);
(S[15] +=> Z)=(0:0:0, 0:0:0);
(S[7] -=> Z)=(0:0:0, 0:0:0);
endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand2_1  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand2_2  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


`ifdef functional
`else
	specify
    if (B==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand2_4  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand2_6  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand2_8  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand2_12 (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand2_16 (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand2b_1  (
output Y,

input AN,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (B==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , B ) ;
  or  ( UDP_IN_Y , csi_opt_276 , AN ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand2b_2  (
output Y,

input AN,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (B==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , B ) ;
  or  ( UDP_IN_Y , csi_opt_276 , AN ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand2b_4  (
output Y,

input AN,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (B==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , B ) ;
  or  ( UDP_IN_Y , csi_opt_276 , AN ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand3_1  (
output Y,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , B , A , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand3_2  (
output Y,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , B , A , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand3_4  (
output Y,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , B , A , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand3b_1  (
output Y,

input AN,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_281;

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_281 , AN ) ;
  nand  ( UDP_IN_Y , B , csi_opt_281 , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand3b_2  (
output Y,

input AN,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_281;

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_281 , AN ) ;
  nand  ( UDP_IN_Y , B , csi_opt_281 , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand3b_4  (
output Y,

input AN,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_281;

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_281 , AN ) ;
  nand  ( UDP_IN_Y , B , csi_opt_281 , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand4_1  (
output Y,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1&&D==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&D==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&C==1'b1) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , D , C , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand4_2  (
output Y,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1&&D==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&D==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&C==1'b1) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , D , C , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand4_4  (
output Y,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1&&D==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&D==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1&&C==1'b1) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand  ( UDP_IN_Y , D , C , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand4b_1  (
output Y,

input AN,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_285;

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&D==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&C==1'b1) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_285 , AN ) ;
  nand  ( UDP_IN_Y , D , C , B , csi_opt_285 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand4b_2  (
output Y,

input AN,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_285;

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&D==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&C==1'b1) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_285 , AN ) ;
  nand  ( UDP_IN_Y , D , C , B , csi_opt_285 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand4b_4  (
output Y,

input AN,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_285;

`ifdef functional
`else
	specify
    if (B==1'b1&&C==1'b1&&D==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&D==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&B==1'b1&&C==1'b1) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_285 , AN ) ;
  nand  ( UDP_IN_Y , D , C , B , csi_opt_285 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand4bb_1  (
output Y,

input AN,
input BN,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_283;

`ifdef functional
`else
	specify
    if (BN==1'b0&&C==1'b1&&D==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (BN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&D==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&C==1'b1) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_283 , D , C ) ;
  or  ( UDP_IN_Y , BN , AN , csi_opt_283 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand4bb_2  (
output Y,

input AN,
input BN,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_283;

`ifdef functional
`else
	specify
    if (BN==1'b0&&C==1'b1&&D==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (BN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&D==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&C==1'b1) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_283 , D , C ) ;
  or  ( UDP_IN_Y , BN , AN , csi_opt_283 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nand4bb_4  (
output Y,

input AN,
input BN,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_283;

`ifdef functional
`else
	specify
    if (BN==1'b0&&C==1'b1&&D==1'b1) (AN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&C==1'b1&&D==1'b1) (BN +=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&D==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (AN==1'b0&&BN==1'b0&&C==1'b1) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_283 , D , C ) ;
  or  ( UDP_IN_Y , BN , AN , csi_opt_283 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor2_1  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor2_2  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor2_4  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor2_8  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor2b_1  (
output Y,

input A,
input BN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (BN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0) (BN +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , A ) ;
  and  ( UDP_IN_Y , csi_opt_276 , BN ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor2b_2  (
output Y,

input A,
input BN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (BN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0) (BN +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , A ) ;
  and  ( UDP_IN_Y , csi_opt_276 , BN ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor2b_4  (
output Y,

input A,
input BN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (BN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0) (BN +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , A ) ;
  and  ( UDP_IN_Y , csi_opt_276 , BN ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor3_1  (
output Y,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , C , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor3_2  (
output Y,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , C , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor3_4  (
output Y,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , C , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor3b_1  (
output Y,

input A,
input B,
input CN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
  specify
    if (B==1'b0&&CN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (CN +=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  nor ( csi_opt_276 , A , B ) ;
  and  ( UDP_IN_Y , CN , csi_opt_276 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor3b_2  (
output Y,

input A,
input B,
input CN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
  specify
    if (B==1'b0&&CN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (CN +=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  nor ( csi_opt_276 , A , B ) ;
  and  ( UDP_IN_Y , CN , csi_opt_276 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor3b_4  (
output Y,

input A,
input B,
input CN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
  specify
    if (B==1'b0&&CN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (CN +=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

  nor ( csi_opt_276 , A , B ) ;
  and  ( UDP_IN_Y , CN , csi_opt_276 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4_1  (
output Y,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&D==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&D==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&D==1'b0) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , A , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4_2  (
output Y,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&D==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&D==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&D==1'b0) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , A , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4_4  (
output Y,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&D==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&D==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&D==1'b0) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , A , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4_6  (
output Y,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&D==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&D==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&D==1'b0) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , A , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4_8  (
output Y,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&D==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&D==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&D==1'b0) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (D -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor  ( UDP_IN_Y , A , B , C , D ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4b_1  (
output Y,

input A,
input B,
input C,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_280;

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&DN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&DN==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (DN +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_280 , DN ) ;
  nor  ( UDP_IN_Y , A , B , C , csi_opt_280 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4b_2  (
output Y,

input A,
input B,
input C,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_280;

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&DN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&DN==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (DN +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_280 , DN ) ;
  nor  ( UDP_IN_Y , A , B , C , csi_opt_280 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4b_4  (
output Y,

input A,
input B,
input C,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_280;

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&DN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&DN==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (C -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (DN +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_280 , DN ) ;
  nor  ( UDP_IN_Y , A , B , C , csi_opt_280 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4bb_1  (
output Y,

input A,
input B,
input CN,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_278;

`ifdef functional
`else
	specify
    if (B==1'b0&&CN==1'b1&&DN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1&&DN==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (CN +=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&CN==1'b1) (DN +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_278 , A , B ) ;
  and  ( UDP_IN_Y , csi_opt_278 , CN , DN ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4bb_2  (
output Y,

input A,
input B,
input CN,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_278;

`ifdef functional
`else
	specify
    if (B==1'b0&&CN==1'b1&&DN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1&&DN==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (CN +=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&CN==1'b1) (DN +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_278 , A , B ) ;
  and  ( UDP_IN_Y , csi_opt_278 , CN , DN ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_nor4bb_4  (
output Y,

input A,
input B,
input CN,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_278;

`ifdef functional
`else
	specify
    if (B==1'b0&&CN==1'b1&&DN==1'b1) (A -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1&&DN==1'b1) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (CN +=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&CN==1'b1) (DN +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_278 , A , B ) ;
  and  ( UDP_IN_Y , csi_opt_278 , CN , DN ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o211a_1  (
output X,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_294 , A2 , A1 ) ;
  and  ( UDP_IN_X , csi_opt_294 , B1 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o211a_2  (
output X,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_294 , A2 , A1 ) ;
  and  ( UDP_IN_X , csi_opt_294 , B1 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o211a_4  (
output X,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_294 , A2 , A1 ) ;
  and  ( UDP_IN_X , csi_opt_294 , B1 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o211ai_1  (
output Y,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_294 , A2 , A1 ) ;
  nand  ( UDP_IN_Y , C1 , csi_opt_294 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o211ai_2  (
output Y,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_294 , A2 , A1 ) ;
  nand  ( UDP_IN_Y , C1 , csi_opt_294 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o211ai_4  (
output Y,

input A1,
input A2,
input B1,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_294 , A2 , A1 ) ;
  nand  ( UDP_IN_Y , C1 , csi_opt_294 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21a_1  (
output X,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_287;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_287 , A2 , A1 ) ;
  and  ( UDP_IN_X , csi_opt_287 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21a_2  (
output X,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_287;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_287 , A2 , A1 ) ;
  and  ( UDP_IN_X , csi_opt_287 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21a_4  (
output X,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_287;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_287 , A2 , A1 ) ;
  and  ( UDP_IN_X , csi_opt_287 , B1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21ai_1  (
output Y,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_287;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_287 , A2 , A1 ) ;
  nand  ( UDP_IN_Y , B1 , csi_opt_287 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21ai_2  (
output Y,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_287;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_287 , A2 , A1 ) ;
  nand  ( UDP_IN_Y , B1 , csi_opt_287 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21ai_4  (
output Y,

input A1,
input A2,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_287;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_287 , A2 , A1 ) ;
  nand  ( UDP_IN_Y , B1 , csi_opt_287 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21ba_1  (
output X,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire csi_opt_273;

`ifdef functional
`else
reg csi_notifier;

	specify
    if (A2==1'b0&&B1N==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1N==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1N -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_273 , A1 , A2 ) ;
  nor  ( UDP_IN_X , B1N , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21ba_2  (
output X,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1N==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1N==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1N -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_273 , A1 , A2 ) ;
  nor  ( UDP_IN_X , B1N , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21ba_4  (
output X,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1N==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1N==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N -=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1N -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_273 , A1 , A2 ) ;
  nor  ( UDP_IN_X , B1N , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21bai_1  (
output Y,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire b;
   
   not (b,B1N);
   or ( csi_opt_287 , A2 , A1 ) ;
   nand  ( UDP_IN_Y , b , csi_opt_287 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
`ifdef functional
`else
  specify
    if (A2==1'b0&&B1N==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1N==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1N +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21bai_2  (
output Y,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire b;
   
   not (b,B1N);
   or ( csi_opt_287 , A2 , A1 ) ;
   nand  ( UDP_IN_Y , b , csi_opt_287 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
`ifdef functional
`else
  specify
    if (A2==1'b0&&B1N==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1N==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1N +=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o21bai_4  (
output Y,

input A1,
input A2,
input B1N

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire b;
   
   not (b,B1N);
   or ( csi_opt_287 , A2 , A1 ) ;
   nand  ( UDP_IN_Y , b , csi_opt_287 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
`ifdef functional
`else
  specify
    if (A2==1'b0&&B1N==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1N==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0) (B1N +=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1) (B1N +=> Y)=(0:0:0, 0:0:0);
  endspecify
`endif

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o221a_1  (
output X,

input A1,
input A2,
input B1,
input B2,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_299;
  wire csi_opt_301;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&C1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_299 , B2 , B1 ) ;
  or ( csi_opt_301 , A2 , A1 ) ;
  and  ( UDP_IN_X , csi_opt_299 , csi_opt_301 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o221a_2  (
output X,

input A1,
input A2,
input B1,
input B2,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_299;
  wire csi_opt_301;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&C1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_299 , B2 , B1 ) ;
  or ( csi_opt_301 , A2 , A1 ) ;
  and  ( UDP_IN_X , csi_opt_299 , csi_opt_301 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o221a_4  (
output X,

input A1,
input A2,
input B1,
input B2,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_299;
  wire csi_opt_301;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&C1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_299 , B2 , B1 ) ;
  or ( csi_opt_301 , A2 , A1 ) ;
  and  ( UDP_IN_X , csi_opt_299 , csi_opt_301 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o221ai_1  (
output Y,

input A1,
input A2,
input B1,
input B2,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_297;
  wire csi_opt_299;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&C1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_297 , B2 , B1 ) ;
  or ( csi_opt_299 , A2 , A1 ) ;
  nand  ( UDP_IN_Y , csi_opt_299 , csi_opt_297 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o221ai_2  (
output Y,

input A1,
input A2,
input B1,
input B2,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_297;
  wire csi_opt_299;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&C1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_297 , B2 , B1 ) ;
  or ( csi_opt_299 , A2 , A1 ) ;
  nand  ( UDP_IN_Y , csi_opt_299 , csi_opt_297 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o221ai_4  (
output Y,

input A1,
input A2,
input B1,
input B2,
input C1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_297;
  wire csi_opt_299;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1&&C1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0&&C1==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&C1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&C1==1'b1) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b1&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b0) (C1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b1&&B2==1'b1) (C1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_297 , B2 , B1 ) ;
  or ( csi_opt_299 , A2 , A1 ) ;
  nand  ( UDP_IN_Y , csi_opt_299 , csi_opt_297 , C1 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o22a_1  (
output X,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_294;
  wire csi_opt_292;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_294 , A2 , A1 ) ;
  or ( csi_opt_292 , B2 , B1 ) ;
  and  ( UDP_IN_X , csi_opt_294 , csi_opt_292 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o22a_2  (
output X,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_294;
  wire csi_opt_292;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_294 , A2 , A1 ) ;
  or ( csi_opt_292 , B2 , B1 ) ;
  and  ( UDP_IN_X , csi_opt_294 , csi_opt_292 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o22a_4  (
output X,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_294;
  wire csi_opt_292;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1) (A1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1) (A2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_294 , A2 , A1 ) ;
  or ( csi_opt_292 , B2 , B1 ) ;
  and  ( UDP_IN_X , csi_opt_294 , csi_opt_292 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o22ai_1  (
output Y,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_273 , B1 , B2 ) ;
  nor ( csi_opt_274 , A1 , A2 ) ;
  or  ( UDP_IN_Y , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o22ai_2  (
output Y,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_273 , B1 , B2 ) ;
  nor ( csi_opt_274 , A1 , A2 ) ;
  or  ( UDP_IN_Y , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o22ai_4  (
output Y,

input A1,
input A2,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
	specify
    if (A2==1'b0&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&B1==1'b1&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&B1==1'b1&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_273 , B1 , B2 ) ;
  nor ( csi_opt_274 , A1 , A2 ) ;
  or  ( UDP_IN_Y , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o2bb2a_1  (
output X,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_296;
  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2N==1'b1&&B1==1'b0&&B2==1'b1) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b0) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b1) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b0&&B2==1'b1) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b0) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b1) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_296 , A2N , A1N ) ;
  or ( csi_opt_294 , B2 , B1 ) ;
  and  ( UDP_IN_X , csi_opt_296 , csi_opt_294 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o2bb2a_2  (
output X,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_296;
  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2N==1'b1&&B1==1'b0&&B2==1'b1) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b0) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b1) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b0&&B2==1'b1) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b0) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b1) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_296 , A2N , A1N ) ;
  or ( csi_opt_294 , B2 , B1 ) ;
  and  ( UDP_IN_X , csi_opt_296 , csi_opt_294 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o2bb2a_4  (
output X,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_296;
  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2N==1'b1&&B1==1'b0&&B2==1'b1) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b0) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b1) (A1N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b0&&B2==1'b1) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b0) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b1) (A2N -=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b0) (B1 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b0) (B2 +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_296 , A2N , A1N ) ;
  or ( csi_opt_294 , B2 , B1 ) ;
  and  ( UDP_IN_X , csi_opt_296 , csi_opt_294 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o2bb2ai_1  (
output Y,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_296;
  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2N==1'b1&&B1==1'b0&&B2==1'b1) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b0) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b1) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b0&&B2==1'b1) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b0) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b1) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_296 , A2N , A1N ) ;
  or ( csi_opt_294 , B2 , B1 ) ;
  nand  ( UDP_IN_Y , csi_opt_296 , csi_opt_294 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o2bb2ai_2  (
output Y,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_296;
  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2N==1'b1&&B1==1'b0&&B2==1'b1) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b0) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b1) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b0&&B2==1'b1) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b0) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b1) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_296 , A2N , A1N ) ;
  or ( csi_opt_294 , B2 , B1 ) ;
  nand  ( UDP_IN_Y , csi_opt_296 , csi_opt_294 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o2bb2ai_4  (
output Y,

input A1N,
input A2N,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_296;
  wire csi_opt_294;

`ifdef functional
`else
	specify
    if (A2N==1'b1&&B1==1'b0&&B2==1'b1) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b0) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A2N==1'b1&&B1==1'b1&&B2==1'b1) (A1N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b0&&B2==1'b1) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b0) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&B1==1'b1&&B2==1'b1) (A2N +=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b0&&A2N==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1N==1'b1&&A2N==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_296 , A2N , A1N ) ;
  or ( csi_opt_294 , B2 , B1 ) ;
  nand  ( UDP_IN_Y , csi_opt_296 , csi_opt_294 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o31ai_1  (
output Y,

input A1,
input A2,
input A3,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_292;

`ifdef functional
`else
	specify
    if (A2==1'b0&&A3==1'b0&&B1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_292 , A2 , A1 , A3 ) ;
  nand  ( UDP_IN_Y , B1 , csi_opt_292 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o31ai_2  (
output Y,

input A1,
input A2,
input A3,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_292;

`ifdef functional
`else
	specify
    if (A2==1'b0&&A3==1'b0&&B1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_292 , A2 , A1 , A3 ) ;
  nand  ( UDP_IN_Y , B1 , csi_opt_292 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o31ai_4  (
output Y,

input A1,
input A2,
input A3,
input B1

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_292;

`ifdef functional
`else
	specify
    if (A2==1'b0&&A3==1'b0&&B1==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b1) (B1 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  or ( csi_opt_292 , A2 , A1 , A3 ) ;
  nand  ( UDP_IN_Y , B1 , csi_opt_292 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o32ai_1  (
output Y,

input A1,
input A2,
input A3,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
	specify
    if (A2==1'b0&&A3==1'b0&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_273 , A3 , A1 , A2 ) ;
  nor ( csi_opt_274 , B1 , B2 ) ;
  or  ( UDP_IN_Y , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o32ai_2  (
output Y,

input A1,
input A2,
input A3,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
	specify
    if (A2==1'b0&&A3==1'b0&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_273 , A3 , A1 , A2 ) ;
  nor ( csi_opt_274 , B1 , B2 ) ;
  or  ( UDP_IN_Y , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_o32ai_4  (
output Y,

input A1,
input A2,
input A3,
input B1,
input B2

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_273;
  wire csi_opt_274;

`ifdef functional
`else
	specify
    if (A2==1'b0&&A3==1'b0&&B1==1'b0&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b0) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A2==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b1) (A1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b0&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b0) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A3==1'b0&&B1==1'b1&&B2==1'b1) (A2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b0&&B2==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b0) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&B1==1'b1&&B2==1'b1) (A3 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b1&&B2==1'b0) (B1 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b0&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b0&&A2==1'b1&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b0&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b0&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
    if (A1==1'b1&&A2==1'b1&&A3==1'b1&&B1==1'b0) (B2 -=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  nor ( csi_opt_273 , A3 , A1 , A2 ) ;
  nor ( csi_opt_274 , B1 , B2 ) ;
  or  ( UDP_IN_Y , csi_opt_274 , csi_opt_273 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or2_1  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (B +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or  ( UDP_IN_X , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or2_2  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (B +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or  ( UDP_IN_X , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or2_4  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (B +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or  ( UDP_IN_X , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_or2_6  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (B +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or  ( UDP_IN_X , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_or2_8  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (B +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or  ( UDP_IN_X , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_or2b_1  (
output X,

input A,
input BN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (BN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (BN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , BN ) ;
  or  ( UDP_IN_X , csi_opt_276 , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or2b_2  (
output X,

input A,
input BN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (BN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (BN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , BN ) ;
  or  ( UDP_IN_X , csi_opt_276 , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or2b_4  (
output X,

input A,
input BN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (BN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (BN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , BN ) ;
  or  ( UDP_IN_X , csi_opt_276 , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or3_1  (
output X,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b0&&C==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  or  ( UDP_IN_X , B , A , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or3_2  (
output X,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b0&&C==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  or  ( UDP_IN_X , B , A , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or3_4  (
output X,

input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    if (B==1'b0&&C==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  or  ( UDP_IN_X , B , A , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or3b_1  (
output X,

input A,
input B,
input CN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_278;

`ifdef functional
`else
	specify
    if (B==1'b0&&CN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (CN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_278 , CN ) ;
  or  ( UDP_IN_X , B , A , csi_opt_278 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or3b_2  (
output X,

input A,
input B,
input CN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_278;

`ifdef functional
`else
	specify
    if (B==1'b0&&CN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (CN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_278 , CN ) ;
  or  ( UDP_IN_X , B , A , csi_opt_278 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or3b_4  (
output X,

input A,
input B,
input CN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_278;

`ifdef functional
`else
	specify
    if (B==1'b0&&CN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (CN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_278 , CN ) ;
  or  ( UDP_IN_X , B , A , csi_opt_278 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or4_1  (
output X,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&D==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&D==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&D==1'b0) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (D +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or  ( UDP_IN_X , D , C , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or4_2  (
output X,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&D==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&D==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&D==1'b0) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (D +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or  ( UDP_IN_X , D , C , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or4_4  (
output X,

input A,
input B,
input C,
input D

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&D==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&D==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&D==1'b0) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (D +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  or  ( UDP_IN_X , D , C , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or4b_1  (
output X,

input A,
input B,
input C,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_281;

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&DN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&DN==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (DN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_281 , DN ) ;
  or  ( UDP_IN_X , csi_opt_281 , C , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or4b_2  (
output X,

input A,
input B,
input C,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_281;

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&DN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&DN==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (DN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_281 , DN ) ;
  or  ( UDP_IN_X , csi_opt_281 , C , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or4b_4  (
output X,

input A,
input B,
input C,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_281;

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0&&DN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0&&DN==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&C==1'b0) (DN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_281 , DN ) ;
  or  ( UDP_IN_X , csi_opt_281 , C , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or4bb_1  (
output X,

input A,
input B,
input CN,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_283;

`ifdef functional
`else
	specify
    if (B==1'b0&&CN==1'b1&&DN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1&&DN==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (CN -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&CN==1'b1) (DN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_283 , DN , CN ) ;
  or  ( UDP_IN_X , B , A , csi_opt_283 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or4bb_2  (
output X,

input A,
input B,
input CN,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_283;

`ifdef functional
`else
	specify
    if (B==1'b0&&CN==1'b1&&DN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1&&DN==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (CN -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&CN==1'b1) (DN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_283 , DN , CN ) ;
  or  ( UDP_IN_X , B , A , csi_opt_283 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_or4bb_4  (
output X,

input A,
input B,
input CN,
input DN

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_283;

`ifdef functional
`else
	specify
    if (B==1'b0&&CN==1'b1&&DN==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&CN==1'b1&&DN==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&DN==1'b1) (CN -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0&&CN==1'b1) (DN -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  nand ( csi_opt_283 , DN , CN ) ;
  or  ( UDP_IN_X , B , A , csi_opt_283 ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_probe_s8p_8 (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_probec_s8p_8 (
output X,

input A

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
  specify
    (A +=> X)=(0:0:0, 0:0:0);
  endspecify
`endif

  buf  ( UDP_IN_X , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfbbp_1  (
output Q,
output QN,
input D,
input SCD,
input SCE,
input CLK,
input SETB,
input RESETB
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire reset;
  wire set;
  wire buf_Q;
`ifdef functional
    not ( reset , RESETB ) ;
    not ( set , SETB ) ;
    scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ;
    `ifdef SC_USE_PG_PIN
     scs8hdll_pg_U_DFB_SETDOM_NO_pg #0.001 ( buf_Q , set , reset , CLK , mux_out ,  , vpwr , vgnd ) ;
    `else
     scs8hdll_pg_U_DFB_SETDOM #0.001 ( buf_Q , set , reset , CLK , mux_out ) ;
    `endif
`else
    reg notifier ;

  wire clk;
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire CLK_delayed;
  wire SETB_delayed;
  wire RESETB_delayed;

    not ( reset , RESETB_delayed ) ; 
    not ( set , SETB_delayed ) ; 
    scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
    scs8hdll_pg_U_DFB_SETDOM_NO_pg ( buf_Q , set , reset , CLK_delayed , mux_out , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire CONDB;
  wire COND_D;
  wire COND_SCD;
  wire COND_SCE;
    assign AWAKE = ( vpwr === 1'b1 ) ; 
    assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
    assign COND1 = ( AWAKE && ( SETB_delayed === 1'b1 ) ) ; 
    assign CONDB = ( COND0 & COND1 ) ; 
    assign COND_D = ( ( SCE_delayed === 1'b0 ) && CONDB ) ; 
    assign COND_SCD = ( ( SCE_delayed === 1'b1 ) && CONDB ) ; 
    assign COND_SCE = ( ( D_delayed !== SCD_delayed ) && CONDB ) ; 
	specify
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);

    $recrem ( posedge SETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , COND0 , COND0 , SETB_delayed , CLK_delayed ) ; 
    $recrem ( posedge RESETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , RESETB_delayed , CLK_delayed ) ; 
	   
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND_D , COND_D , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND_D , COND_D , CLK_delayed , D_delayed ) ; 
	   
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND_SCD , COND_SCD , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND_SCD , COND_SCD , CLK_delayed , SCD_delayed ) ; 
	   
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND_SCE , COND_SCE , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND_SCE , COND_SCE , CLK_delayed , SCE_delayed ) ; 

    $setuphold ( posedge SETB , posedge RESETB , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , RESETB_delayed  ) ;
    $setuphold ( posedge RESETB , posedge SETB , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed  , SETB_delayed ) ; 

		$width ( negedge CLK &&& CONDB , 1.0:1.0:1.0 , 0 , notifier ) ; 
		$width ( posedge CLK &&& CONDB , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 

	endspecify

`endif
  buf ( Q , buf_Q ) ; 
  not ( QN , buf_Q ) ; 
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfrbp_1  (
output Q,
output QN,

input CLK,
input D,
input SCD,
input SCE,
input RESETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire reset;
  wire mux_out;

`ifdef functional
  not ( reset , RESETB ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_R_NO_pg #0.001 ( buf_Q , mux_out , CLK , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_R #0.001 ( buf_Q , mux_out , CLK , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire RESETB_delayed;
  wire CLK_delayed;
  not ( reset , RESETB_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_R_NO_pg ( buf_Q , mux_out , CLK_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( RESETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( RESETB === 1'b1 ) && AWAKE ) ; 
  specify
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    
    $recrem ( posedge RESETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 
not ( QN , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfrbp_2  (
output Q,
output QN,

input CLK,
input D,
input SCD,
input SCE,
input RESETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire reset;
  wire mux_out;

`ifdef functional
  not ( reset , RESETB ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_R_NO_pg #0.001 ( buf_Q , mux_out , CLK , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_R #0.001 ( buf_Q , mux_out , CLK , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire RESETB_delayed;
  wire CLK_delayed;
  not ( reset , RESETB_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_R_NO_pg ( buf_Q , mux_out , CLK_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( RESETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( RESETB === 1'b1 ) && AWAKE ) ; 
  specify
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    
    $recrem ( posedge RESETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 
not ( QN , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfrtn_1  (
output Q,

input CLKN,
input D,
input SCD,
input SCE,
input RESETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire reset;
  wire intclk;
  wire mux_out;

`ifdef functional
  not ( reset , RESETB ) ; 
  not ( intclk , CLKN ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_R_NO_pg #0.001 ( buf_Q , mux_out , intclk , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_R #0.001 ( buf_Q , mux_out , intclk , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire RESETB_delayed;
  wire CLKN_delayed;
  not ( reset , RESETB_delayed ) ; 
  not ( intclk , CLKN_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_R_NO_pg ( buf_Q , mux_out , intclk , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( AWAKE && ( RESETB_delayed === 1'b1 ) ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( AWAKE && ( RESETB === 1'b1 ) ) ; 
  specify
    if (CLKN==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLKN==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge CLKN => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge CLKN => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge CLKN => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge CLKN => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge CLKN => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge CLKN => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge CLKN => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge CLKN => (Q +: 1'b1))=(0:0:0, 0:0:0);

    $recrem ( posedge RESETB , negedge CLKN , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLKN_delayed ) ; 
    $setuphold ( negedge CLKN , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLKN_delayed , D_delayed ) ; 
    $setuphold ( negedge CLKN , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLKN_delayed , D_delayed ) ; 
    $setuphold ( negedge CLKN , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLKN_delayed , SCD_delayed ) ; 
    $setuphold ( negedge CLKN , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLKN_delayed , SCD_delayed ) ; 
    $setuphold ( negedge CLKN , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLKN_delayed , SCE_delayed ) ; 
    $setuphold ( negedge CLKN , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLKN_delayed , SCE_delayed ) ; 
    $width ( posedge CLKN &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLKN &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfrtp_1  (
output Q,

input CLK,
input D,
input SCD,
input SCE,
input RESETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire reset;
  wire mux_out;

`ifdef functional
  not ( reset , RESETB ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_R_NO_pg #0.001 ( buf_Q , mux_out , CLK , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_R #0.001 ( buf_Q , mux_out , CLK , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire RESETB_delayed;
  wire CLK_delayed;
  not ( reset , RESETB_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_R_NO_pg ( buf_Q , mux_out , CLK_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( RESETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( RESETB === 1'b1 ) && AWAKE ) ; 
  specify
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);

    $recrem ( posedge RESETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfrtp_2  (
output Q,

input CLK,
input D,
input SCD,
input SCE,
input RESETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire reset;
  wire mux_out;

`ifdef functional
  not ( reset , RESETB ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_R_NO_pg #0.001 ( buf_Q , mux_out , CLK , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_R #0.001 ( buf_Q , mux_out , CLK , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire RESETB_delayed;
  wire CLK_delayed;
  not ( reset , RESETB_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_R_NO_pg ( buf_Q , mux_out , CLK_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( RESETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( RESETB === 1'b1 ) && AWAKE ) ; 
  specify
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);

    $recrem ( posedge RESETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfrtp_4  (
output Q,

input CLK,
input D,
input SCD,
input SCE,
input RESETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire reset;
  wire mux_out;

`ifdef functional
  not ( reset , RESETB ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_R_NO_pg #0.001 ( buf_Q , mux_out , CLK , reset ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_R #0.001 ( buf_Q , mux_out , CLK , reset ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire RESETB_delayed;
  wire CLK_delayed;
  not ( reset , RESETB_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_R_NO_pg ( buf_Q , mux_out , CLK_delayed , reset , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( RESETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( RESETB === 1'b1 ) && AWAKE ) ; 
  specify
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge RESETB => (Q +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&RESETB==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&RESETB==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);

    $recrem ( posedge RESETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , RESETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge RESETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfsbp_1  (
output Q,
output QN,

input CLK,
input D,
input SCD,
input SCE,
input SETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire set;
  wire mux_out;

`ifdef functional
  not ( set , SETB ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_S_NO_pg #0.001 ( buf_Q , mux_out , CLK , set ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_S #0.001 ( buf_Q , mux_out , CLK , set ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire SETB_delayed;
  wire CLK_delayed;
  not ( set , SETB_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_S_NO_pg ( buf_Q , mux_out , CLK_delayed , set , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( SETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( SETB === 1'b1 ) && AWAKE ) ; 
  specify
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    
    $recrem ( posedge SETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 
not ( QN , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfsbp_2  (
output Q,
output QN,

input CLK,
input D,
input SCD,
input SCE,
input SETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire set;
  wire mux_out;

`ifdef functional
  not ( set , SETB ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_S_NO_pg #0.001 ( buf_Q , mux_out , CLK , set ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_S #0.001 ( buf_Q , mux_out , CLK , set ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire SETB_delayed;
  wire CLK_delayed;
  not ( set , SETB_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_S_NO_pg ( buf_Q , mux_out , CLK_delayed , set , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( SETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( SETB === 1'b1 ) && AWAKE ) ; 
  specify
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (QN +: 1'b0))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    
    $recrem ( posedge SETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 
not ( QN , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfstp_1  (
output Q,

input CLK,
input D,
input SCD,
input SCE,
input SETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire set;
  wire mux_out;

`ifdef functional
  not ( set , SETB ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_S_NO_pg #0.001 ( buf_Q , mux_out , CLK , set ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_S #0.001 ( buf_Q , mux_out , CLK , set ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire SETB_delayed;
  wire CLK_delayed;
  not ( set , SETB_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_S_NO_pg ( buf_Q , mux_out , CLK_delayed , set , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( SETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( SETB === 1'b1 ) && AWAKE ) ; 
  specify
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    
    $recrem ( posedge SETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfstp_2  (
output Q,

input CLK,
input D,
input SCD,
input SCE,
input SETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire set;
  wire mux_out;

`ifdef functional
  not ( set , SETB ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_S_NO_pg #0.001 ( buf_Q , mux_out , CLK , set ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_S #0.001 ( buf_Q , mux_out , CLK , set ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire SETB_delayed;
  wire CLK_delayed;
  not ( set , SETB_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_S_NO_pg ( buf_Q , mux_out , CLK_delayed , set , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( SETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( SETB === 1'b1 ) && AWAKE ) ; 
  specify
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    
    $recrem ( posedge SETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfstp_4  (
output Q,

input CLK,
input D,
input SCD,
input SCE,
input SETB

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire set;
  wire mux_out;

`ifdef functional
  not ( set , SETB ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_S_NO_pg #0.001 ( buf_Q , mux_out , CLK , set ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P_S #0.001 ( buf_Q , mux_out , CLK , set ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire SETB_delayed;
  wire CLK_delayed;
  not ( set , SETB_delayed ) ; 
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_S_NO_pg ( buf_Q , mux_out , CLK_delayed , set , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND0;
  wire COND1;
  wire COND2;
  wire COND3;
  wire COND4;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND0 = ( ( SETB_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && COND0 ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && COND0 ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && COND0 ) ; 
  assign COND4 = ( ( SETB === 1'b1 ) && AWAKE ) ; 
  specify
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b0&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b0&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b0&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b0) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (CLK==1'b1&&D==1'b1&&SCD==1'b1&&SCE==1'b1) (negedge SETB => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1&&SETB==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    
    $recrem ( posedge SETB , posedge CLK , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , SETB_delayed , CLK_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& COND4 , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge SETB &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfxbp_1  (
output Q,
output QN,

input CLK,
input D,
input SCD,
input SCE

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire mux_out;

`ifdef functional
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_NO_pg #0.001 ( buf_Q , mux_out , CLK ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P #0.001 ( buf_Q , mux_out , CLK ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire CLK_delayed;
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_NO_pg ( buf_Q , mux_out , CLK_delayed , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND1;
  wire COND2;
  wire COND3;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && AWAKE ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && AWAKE ) ; 
  specify
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);

    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 
not ( QN , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfxbp_2  (
output Q,
output QN,

input CLK,
input D,
input SCD,
input SCE

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire mux_out;

`ifdef functional
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_NO_pg #0.001 ( buf_Q , mux_out , CLK ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P #0.001 ( buf_Q , mux_out , CLK ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire CLK_delayed;
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_NO_pg ( buf_Q , mux_out , CLK_delayed , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND1;
  wire COND2;
  wire COND3;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && AWAKE ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && AWAKE ) ; 
  specify
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);

    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 
not ( QN , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfxtp_1  (
output Q,

input CLK,
input D,
input SCD,
input SCE

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire mux_out;

`ifdef functional
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_NO_pg #0.001 ( buf_Q , mux_out , CLK ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P #0.001 ( buf_Q , mux_out , CLK ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire CLK_delayed;
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_NO_pg ( buf_Q , mux_out , CLK_delayed , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND1;
  wire COND2;
  wire COND3;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && AWAKE ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && AWAKE ) ; 
  specify
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);

    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfxtp_2  (
output Q,

input CLK,
input D,
input SCD,
input SCE

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire mux_out;

`ifdef functional
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_NO_pg #0.001 ( buf_Q , mux_out , CLK ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P #0.001 ( buf_Q , mux_out , CLK ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire CLK_delayed;
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_NO_pg ( buf_Q , mux_out , CLK_delayed , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND1;
  wire COND2;
  wire COND3;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && AWAKE ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && AWAKE ) ; 
  specify
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);

    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdfxtp_4  (
output Q,

input CLK,
input D,
input SCD,
input SCE

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;
  wire mux_out;

`ifdef functional
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D , SCD , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DF_P_NO_pg #0.001 ( buf_Q , mux_out , CLK ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DF_P #0.001 ( buf_Q , mux_out , CLK ) ;
`endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire CLK_delayed;
  scs8hdll_pg_U_MUX_2_1 ( mux_out , D_delayed , SCD_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DF_P_NO_pg ( buf_Q , mux_out , CLK_delayed , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND1;
  wire COND2;
  wire COND3;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND1 = ( ( SCE_delayed === 1'b0 ) && AWAKE ) ; 
  assign COND2 = ( ( SCE_delayed === 1'b1 ) && AWAKE ) ; 
  assign COND3 = ( ( D_delayed !== SCD_delayed ) && AWAKE ) ; 
  specify
    if (D==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);

    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdlclkp_1  (
output GCLK,

input SCE,
input GATE,
input CLK

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire m0;
  wire m0n;
  wire clkn;
  not ( m0n , m0 ) ; 

`ifdef functional

  not ( clkn , CLK ) ; 
  nor ( SCE_GATE , GATE , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_NO_pg  ( m0 , SCE_GATE , clkn ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P  ( m0 , SCE_GATE , clkn ) ;
`endif 
  and ( GCLK , m0n , CLK ) ; 
`else
  wire CLK_delayed;
  wire SCE_delayed;
  wire GATE_delayed;
  wire SCE_GATE_delayed;
  reg notifier ; 
  not ( clkn , CLK_delayed ) ; 
  nor ( SCE_GATE_delayed , GATE_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DL_P_NO_pg ( m0 , SCE_GATE_delayed , clkn , notifier , vpwr , vgnd ) ; 
  and ( GCLK , m0n , CLK_delayed ) ; 

  wire AWAKE;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  wire SCE_AWAKE;
  assign SCE_AWAKE = (AWAKE&(GATE_delayed === 1'b0));
  wire GATE_AWAKE;
  assign GATE_AWAKE = (AWAKE&(SCE_delayed === 1'b0));
  specify
    if (GATE==1'b0&&SCE==1'b1) (CLK +=> GCLK)=(0:0:0, 0:0:0);
    if (GATE==1'b1&&SCE==1'b0) (CLK +=> GCLK)=(0:0:0, 0:0:0);
    if (GATE==1'b1&&SCE==1'b1) (CLK +=> GCLK)=(0:0:0, 0:0:0);
    if (GATE==1'b0&&SCE==1'b0) (CLK +=> GCLK)=(0:0:0, 0:0:0);

    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , posedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ; 
    $setuphold ( posedge CLK , negedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif


endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdlclkp_2  (
output GCLK,

input SCE,
input GATE,
input CLK

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire m0;
  wire m0n;
  wire clkn;
  not ( m0n , m0 ) ; 

`ifdef functional

  not ( clkn , CLK ) ; 
  nor ( SCE_GATE , GATE , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_NO_pg  ( m0 , SCE_GATE , clkn ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P  ( m0 , SCE_GATE , clkn ) ;
`endif 
  and ( GCLK , m0n , CLK ) ; 
`else
  wire CLK_delayed;
  wire SCE_delayed;
  wire GATE_delayed;
  wire SCE_GATE_delayed;
  reg notifier ; 
  not ( clkn , CLK_delayed ) ; 
  nor ( SCE_GATE_delayed , GATE_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DL_P_NO_pg ( m0 , SCE_GATE_delayed , clkn , notifier , vpwr , vgnd ) ; 
  and ( GCLK , m0n , CLK_delayed ) ; 

  wire AWAKE;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  wire SCE_AWAKE;
  assign SCE_AWAKE = (AWAKE&(GATE_delayed === 1'b0));
  wire GATE_AWAKE;
  assign GATE_AWAKE = (AWAKE&(SCE_delayed === 1'b0));
  specify
    if (GATE==1'b0&&SCE==1'b1) (CLK +=> GCLK)=(0:0:0, 0:0:0);
    if (GATE==1'b1&&SCE==1'b0) (CLK +=> GCLK)=(0:0:0, 0:0:0);
    if (GATE==1'b1&&SCE==1'b1) (CLK +=> GCLK)=(0:0:0, 0:0:0);
    if (GATE==1'b0&&SCE==1'b0) (CLK +=> GCLK)=(0:0:0, 0:0:0);

    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , posedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ; 
    $setuphold ( posedge CLK , negedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif


endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sdlclkp_4  (
output GCLK,

input SCE,
input GATE,
input CLK

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire m0;
  wire m0n;
  wire clkn;
  not ( m0n , m0 ) ; 

`ifdef functional

  not ( clkn , CLK ) ; 
  nor ( SCE_GATE , GATE , SCE ) ; 
`ifdef SC_USE_PG_PIN
 scs8hdll_pg_U_DL_P_NO_pg  ( m0 , SCE_GATE , clkn ,  , vpwr , vgnd ) ;
`else
 scs8hdll_pg_U_DL_P  ( m0 , SCE_GATE , clkn ) ;
`endif 
  and ( GCLK , m0n , CLK ) ; 
`else
  wire CLK_delayed;
  wire SCE_delayed;
  wire GATE_delayed;
  wire SCE_GATE_delayed;
  reg notifier ; 
  not ( clkn , CLK_delayed ) ; 
  nor ( SCE_GATE_delayed , GATE_delayed , SCE_delayed ) ; 
scs8hdll_pg_U_DL_P_NO_pg ( m0 , SCE_GATE_delayed , clkn , notifier , vpwr , vgnd ) ; 
  and ( GCLK , m0n , CLK_delayed ) ; 

  wire AWAKE;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  wire SCE_AWAKE;
  assign SCE_AWAKE = (AWAKE&(GATE_delayed === 1'b0));
  wire GATE_AWAKE;
  assign GATE_AWAKE = (AWAKE&(SCE_delayed === 1'b0));
  specify
    if (GATE==1'b0&&SCE==1'b1) (CLK +=> GCLK)=(0:0:0, 0:0:0);
    if (GATE==1'b1&&SCE==1'b0) (CLK +=> GCLK)=(0:0:0, 0:0:0);
    if (GATE==1'b1&&SCE==1'b1) (CLK +=> GCLK)=(0:0:0, 0:0:0);
    if (GATE==1'b0&&SCE==1'b0) (CLK +=> GCLK)=(0:0:0, 0:0:0);

    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , SCE_AWAKE , SCE_AWAKE , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , posedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ; 
    $setuphold ( posedge CLK , negedge GATE , 0:0:0 , 0:0:0 , notifier , GATE_AWAKE , GATE_AWAKE , CLK_delayed , GATE_delayed ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_sedfxbp_1  (
output Q,
output QN,
input CLK,
input D,
input DE,
input SCD,
input SCE


`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire buf_Q;

`ifdef functional
  scs8hdll_pg_U_MUX_2_1 ( mux_out , DE$D , SCD , SCE ) , ( DE$D , buf_Q , D , DE ) ; 
  `ifdef SC_USE_PG_PIN
   scs8hdll_pg_U_DF_P_NO_pg #0.001 ( buf_Q , mux_out , CLK ,  , vpwr , vgnd ) ;
  `else
   scs8hdll_pg_U_DF_P #0.001 ( buf_Q , mux_out , CLK ) ;
  `endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire DE_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire CLK_delayed;
  scs8hdll_pg_U_MUX_2_1 ( mux_out , DE$D , SCD_delayed , SCE_delayed ) , ( DE$D , buf_Q , D_delayed , DE_delayed ) ; 
  scs8hdll_pg_U_DF_P_NO_pg ( buf_Q , mux_out , CLK_delayed , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND1;
  wire COND2;
  wire COND3;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND1 = ( AWAKE && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) ) ; 
  assign COND2 = ( AWAKE && ( SCE_delayed === 1'b1 ) ) ; 
  assign COND3 = ( AWAKE && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) ) ; 
  specify
    if (D==1'b0&&DE==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);

    $setuphold ( posedge CLK , posedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ; 
    $setuphold ( posedge CLK , negedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 
not ( QN , buf_Q ) ; 

endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_sedfxbp_2  (
output Q,
output QN,
input CLK,
input D,
input DE,
input SCD,
input SCE


`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


  wire buf_Q;

`ifdef functional
  scs8hdll_pg_U_MUX_2_1 ( mux_out , DE$D , SCD , SCE ) , ( DE$D , buf_Q , D , DE ) ; 
  `ifdef SC_USE_PG_PIN
   scs8hdll_pg_U_DF_P_NO_pg #0.001 ( buf_Q , mux_out , CLK ,  , vpwr , vgnd ) ;
  `else
   scs8hdll_pg_U_DF_P #0.001 ( buf_Q , mux_out , CLK ) ;
  `endif 
`else
  reg notifier ; 
  wire D_delayed;
  wire DE_delayed;
  wire SCD_delayed;
  wire SCE_delayed;
  wire CLK_delayed;
  scs8hdll_pg_U_MUX_2_1 ( mux_out , DE$D , SCD_delayed , SCE_delayed ) , ( DE$D , buf_Q , D_delayed , DE_delayed ) ; 
  scs8hdll_pg_U_DF_P_NO_pg ( buf_Q , mux_out , CLK_delayed , notifier , vpwr , vgnd ) ; 

  wire AWAKE;
  wire COND1;
  wire COND2;
  wire COND3;
  assign AWAKE = ( vpwr === 1'b1 ) ; 
  assign COND1 = ( AWAKE && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) ) ; 
  assign COND2 = ( AWAKE && ( SCE_delayed === 1'b1 ) ) ; 
  assign COND3 = ( AWAKE && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) ) ; 
  specify
    if (D==1'b0&&DE==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (Q +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (Q -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b0&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b0&&SCE==1'b1) (posedge CLK => (QN +: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b0&&DE==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b0&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b0&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b1&&SCE==1'b0) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);
    if (D==1'b1&&DE==1'b1&&SCD==1'b1&&SCE==1'b1) (posedge CLK => (QN -: 1'b1))=(0:0:0, 0:0:0);

    $setuphold ( posedge CLK , posedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ; 
    $setuphold ( posedge CLK , negedge DE , 0:0:0 , 0:0:0 , notifier , AWAKE , AWAKE , CLK_delayed , DE_delayed ) ; 
    $setuphold ( posedge CLK , posedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , negedge D , 0:0:0 , 0:0:0 , notifier , COND1 , COND1 , CLK_delayed , D_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCD , 0:0:0 , 0:0:0 , notifier , COND2 , COND2 , CLK_delayed , SCD_delayed ) ; 
    $setuphold ( posedge CLK , posedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $setuphold ( posedge CLK , negedge SCE , 0:0:0 , 0:0:0 , notifier , COND3 , COND3 , CLK_delayed , SCE_delayed ) ; 
    $width ( posedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
    $width ( negedge CLK &&& AWAKE , 1.0:1.0:1.0 , 0 , notifier ) ; 
  endspecify
`endif

buf ( Q , buf_Q ) ; 
not ( QN , buf_Q ) ; 

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_tap_1  (

`ifdef SC_USE_PG_PIN
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_xnor2_1  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (B==1'b1) (A +=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1) (B +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  xnor  ( UDP_IN_Y , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_xnor2_2  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (B==1'b1) (A +=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1) (B +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  xnor  ( UDP_IN_Y , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_xnor2_4  (
output Y,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A -=> Y)=(0:0:0, 0:0:0);
    if (B==1'b1) (A +=> Y)=(0:0:0, 0:0:0);
    if (A==1'b0) (B -=> Y)=(0:0:0, 0:0:0);
    if (A==1'b1) (B +=> Y)=(0:0:0, 0:0:0);
	endspecify
`endif

  xnor  ( UDP_IN_Y , A , B ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_Y, UDP_IN_Y, vpwr, vgnd) ;
  buf  (Y, UDP_OUT_Y) ;
  `else
    buf ( Y , UDP_IN_Y ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_xnor3_1  (
output X,
input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0) (A -=> X)=(0:0:0, 0:0:0);
    if (B==1'b0&&C==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b1) (A -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b0) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  xnor ( UDP_IN_X , A , B , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_xnor3_2  (
output X,
input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0) (A -=> X)=(0:0:0, 0:0:0);
    if (B==1'b0&&C==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b1) (A -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b0) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  xnor ( UDP_IN_X , A , B , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_xnor3_4  (
output X,
input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
reg csi_notifier;

	specify
    if (B==1'b0&&C==1'b0) (A -=> X)=(0:0:0, 0:0:0);
    if (B==1'b0&&C==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b1) (A -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b0) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  xnor ( UDP_IN_X , A , B , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_xor2_1  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b1) (A -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (B -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  xor  ( UDP_IN_X , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_xor2_2  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b1) (A -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (B -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  xor  ( UDP_IN_X , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_xor2_4  (
output X,

input A,
input B

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b1) (A -=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (B -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  xor  ( UDP_IN_X , B , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;
  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_xor3_1  (
output X,
input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b0&&C==1'b1) (A -=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b0) (A -=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b1) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b0) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b1) (C -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b0) (C -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  xor ( UDP_IN_X , A , B , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_xor3_2  (
output X,
input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b0&&C==1'b1) (A -=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b0) (A -=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b1) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b0) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b1) (C -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b0) (C -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  xor ( UDP_IN_X , A , B , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine


`celldefine
`timescale 1ns / 1ps
module scs8hdll_xor3_4  (
output X,
input A,
input B,
input C

`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (B==1'b0&&C==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (B==1'b0&&C==1'b1) (A -=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b0) (A -=> X)=(0:0:0, 0:0:0);
    if (B==1'b1&&C==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b0) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&C==1'b1) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b0) (B -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&C==1'b1) (B +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b0) (C +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0&&B==1'b1) (C -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b0) (C -=> X)=(0:0:0, 0:0:0);
    if (A==1'b1&&B==1'b1) (C +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  xor ( UDP_IN_X , A , B , C ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND (UDP_OUT_X, UDP_IN_X, vpwr, vgnd) ;
  buf  (X, UDP_OUT_X) ;

  `else
    buf ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

//Copying iso cells (9 cells) from s8- CDT 265747 - vjsk
`celldefine
`timescale 1ns / 1ps
module scs8hdll_inputiso0n_1  (

output X,
input A,
input sleepb

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif


`ifdef functional
`else
	specify
    if (sleepb==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (sleepb +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif
  `ifdef SC_USE_PG_PIN


  and ( UDP_IN_X , A , sleepb );
  scs8hdll_pg_U_VPWR_VGND  (X, UDP_IN_X, vpwr, vgnd) ;

 
`else
    and ( X , A , sleepb ) ;
  `endif
endmodule
`endcelldefine


`celldefine


`timescale 1ns / 1ps
module scs8hdll_inputiso0p_1  (

output X,
input A,
input sleep

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif
  
  wire sleepn;

`ifdef functional
`else
	specify
    if (sleep==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (sleep -=> X)=(0:0:0, 0:0:0);
	endspecify

`endif

  not ( sleepn ,  sleep );
  `ifdef SC_USE_PG_PIN

  and ( UDP_IN_X , A , sleepn );
  scs8hdll_pg_U_VPWR_VGND  (X, UDP_IN_X, vpwr, vgnd) ;

`else
    and ( X , A , sleepn ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_inputiso1n_1  (

output X,
input A,
input sleepb

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire sleep;
 
`ifdef functional
`else
	specify
    if (sleepb==1'b1) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (sleepb -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( sleep ,  sleepb );
  `ifdef SC_USE_PG_PIN

  or ( UDP_IN_X ,  A , sleep );
  scs8hdll_pg_U_VPWR_VGND  (X, UDP_IN_X, vpwr, vgnd) ;

`else
    or ( X , A , sleep ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_inputiso1p_1  (

output X,
input A,
input sleep

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

`ifdef functional
`else
	specify
    if (sleep==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b0) (sleep +=> X)=(0:0:0, 0:0:0);
	endspecify
`endif
  `ifdef SC_USE_PG_PIN

  or ( UDP_IN_X ,  A , sleep );
  scs8hdll_pg_U_VPWR_VGND  (X, UDP_IN_X, vpwr, vgnd) ;

`else
    or ( X , A , sleep ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_isobufsrc_1  (

output X,
input SLEEP,
input A

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (SLEEP==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (SLEEP -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , SLEEP ) ;
  and  ( UDP_IN_X , csi_opt_276 , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND_SLEEP (UDP_OUT_X, UDP_IN_X, vpwr, vgnd, SLEEP) ;
  buf  (X, UDP_OUT_X) ;
 
`else
    buf  ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_isobufsrc_16  (

output X,
input SLEEP,
input A

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (SLEEP==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (SLEEP -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , SLEEP ) ;
  and  ( UDP_IN_X , csi_opt_276 , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND_SLEEP (UDP_OUT_X, UDP_IN_X, vpwr, vgnd, SLEEP) ;
  buf  (X, UDP_OUT_X) ;
 
`else
    buf  ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_isobufsrc_2  (

output X,
input SLEEP,
input A

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (SLEEP==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (SLEEP -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , SLEEP ) ;
  and  ( UDP_IN_X , csi_opt_276 , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND_SLEEP (UDP_OUT_X, UDP_IN_X, vpwr, vgnd, SLEEP) ;
  buf  (X, UDP_OUT_X) ;
 
`else
    buf  ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_isobufsrc_4  (

output X,
input SLEEP,
input A

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (SLEEP==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (SLEEP -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , SLEEP ) ;
  and  ( UDP_IN_X , csi_opt_276 , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND_SLEEP (UDP_OUT_X, UDP_IN_X, vpwr, vgnd, SLEEP) ;
  buf  (X, UDP_OUT_X) ;
 
`else
    buf  ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
`timescale 1ns / 1ps
module scs8hdll_isobufsrc_8  (

output X,
input SLEEP,
input A

`ifdef SC_USE_PG_PIN
,
input vpwr,
input vgnd,
input vpb,
input vnb
`endif

);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif

  wire csi_opt_276;

`ifdef functional
`else
	specify
    if (SLEEP==1'b0) (A +=> X)=(0:0:0, 0:0:0);
    if (A==1'b1) (SLEEP -=> X)=(0:0:0, 0:0:0);
	endspecify
`endif

  not ( csi_opt_276 , SLEEP ) ;
  and  ( UDP_IN_X , csi_opt_276 , A ) ;
  `ifdef SC_USE_PG_PIN

  scs8hdll_pg_U_VPWR_VGND_SLEEP (UDP_OUT_X, UDP_IN_X, vpwr, vgnd, SLEEP) ;
  buf  (X, UDP_OUT_X) ;
 
`else
    buf  ( X , UDP_IN_X ) ;
  `endif
endmodule
`endcelldefine

`celldefine
module scs8hdll_diode_2 (
input DIODE
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif
endmodule
`endcelldefine

`celldefine
module scs8hdll_diode_4 (
input DIODE
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif
endmodule
`endcelldefine

`celldefine
module scs8hdll_diode_6 (
input DIODE
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif
endmodule
`endcelldefine

`celldefine
module scs8hdll_diode_8 (
input DIODE
`ifdef SC_USE_PG_PIN
, input vpwr
, input vgnd
, input vpb
, input vnb
`endif
);

`ifdef functional
`else
`ifdef SC_USE_PG_PIN
`else
supply1 vpwr;
supply0 vgnd;
supply1 vpb;
supply0 vnb;
`endif
`endif
endmodule
`endcelldefine

primitive scs8hdll_pg_U_DFB_SETDOM (Q, S, R, CK, D);
   // same as scs8hdll_U_DFB udp but the set line is dominant.
output Q;
input  S, R, CK, D;
reg    Q;
  table
    0  1   ?    ?  :  ?  :  0; // Asserting reset
    0  *   ?    ?  :  0  :  0; // Changing reset
    1  ?   ?    ?  :  ?  :  1; // Asserting set (dominates reset)
    *  0   ?    ?  :  1  :  1; // Changing set
    0  ?   (01) 0  :  ?  :  0; // rising clock
    ?  0   (01) 1  :  ?  :  1; // rising clock 
    0  ?   p    0  :  0  :  0; // potential rising clock
    ?  0   p    1  :  1  :  1; // potential rising clock
    0  0   n    ?  :  ?  :  -; // Clock falling register output does not change
    0  0   ?    *  :  ?  :  -; // Changing Data
 
  endtable
endprimitive
// bnb mar4,2003 - this is a modification of the verplex FF udp
// that was edited to work with tetramax and compiles
// with verilog-xl with no warnings
primitive scs8hdll_pg_U_DFB_SETDOM_NO_pg (Q, S, R, CK, D, NOTIFIER, VPWR, VGND);
   // same as scs8hdll_pg_U_DFB udp but the set line is dominant.
output Q;
input  S, R, CK, D, NOTIFIER, VPWR, VGND;
reg    Q;
  table
    0  1   b    ?  ?  1  0  :  ?  :  0; // Asserting reset
    0  *   ?    ?  ?  1  0  :  0  :  0; // Changing reset
    1  ?   b    ?  ?  1  0  :  ?  :  1; // Asserting set  (dominates reset)
    *  0   ?    ?  ?  1  0  :  1  :  1; // Changing set
    1  ?   n    ?  ?  1  0  :  1  :  1; // JCWR
    ?  1   n    ?  ?  1  0  :  0  :  0; // JCWR
    x  ?   n    ?  ?  1  0  :  1  :  1; // JCWR
    ?  x   n    ?  ?  1  0  :  0  :  0; // JCWR
    0  ?   (01) 0  ?  1  0  :  ?  :  0; // rising clock
    ?  0   (01) 1  ?  1  0  :  ?  :  1; // rising clock 
    0  ?   p    0  ?  1  0  :  0  :  0; // potential rising clock
    ?  0   p    1  ?  1  0  :  1  :  1; // potential rising clock
    0  ?   x    0  ?  1  0  :  1  :  x; // JCWR
    ?  0   x    1  ?  1  0  :  0  :  x; // JCWR
    0  0   n    ?  ?  1  0  :  ?  :  -; // Clock falling register output does not change
    0  0   ?    *  ?  1  0  :  ?  :  -; // Changing Data
`ifdef functional
    ?  ?   ?    ?  *  1  0  :  ?  :  -; // go to - on notify
`else
    ?  ?   ?    ?  *  1  0  :  ?  :  X; // go to X on notify
`endif
    ?  ?   ?    ?  ?  *  0  :  ?  :  X; // any change on vpwr
    ?  ?   ?    ?  ?  ?  *  :  ?  :  X; // any change on vgnd

  endtable
endprimitive
primitive scs8hdll_pg_U_DF_P (Q, D, CP);
    output Q;  
    input  D, CP;
    reg    Q;  
// FUNCTION :  POSITIVE EDGE TRIGGERED D FLIP-FLOP ( Q OUTPUT UDP ).
    table
//      D   CP        :   Qt  :   Qt+1

        1   (01)      :   ?   :   1;  // clocked data
        0   (01)      :   ?   :   0;

        1   (x1)      :   1   :   1;  // reducing pessimism
        0   (x1)      :   0   :   0;                          
        1   (0x)      :   1   :   1;  
        0   (0x)      :   0   :   0; 

        ?   (1x)      :   ?   :   -;  // no change on falling edge 
        ?   (?0)      :   ?   :   -;  

        *    ?        :   ?   :   -;  // ignore edges on data
    endtable
endprimitive
primitive scs8hdll_pg_U_DF_P_NO_pg (Q, D, CP , NOTIFIER, VPWR, VGND);    
    output Q;  
    input  D, CP, NOTIFIER, VPWR, VGND;
    reg    Q;  

// FUNCTION :  POSITIVE EDGE TRIGGERED D FLIP-FLOP ( Q OUTPUT UDP ).


    table
 
    //  D   CP           NOTIFIER VPWR VGND :   Qt  :   Qt+1

        1   (01)            ?      1    0   :   ?   :   1;  // clocked data
        0   (01)            ?      1    0   :   ?   :   0;
                                                           
        1   (x1)            ?      1    0   :   1   :   1;  // reducing pessimism
        0   (x1)            ?      1    0   :   0   :   0;                          
        1   (0x)            ?      1    0   :   1   :   1;  
        0   (0x)            ?      1    0   :   0   :   0; 
        
        0    x              ?      1    0   :   0   :   0; // Hold when CLK=X and D=Q
        1    x              ?      1    0   :   1   :   1; // Hold when CLK=X and D=Q
        ?   (?0)            ?      1    0   :   ?   :   -;  

        *    b              ?      1    0   :   ?   :   -;  // ignore edges on data

`ifdef functional
        ?    ?              *      1    0   :   ?   :   -;
`else
        ?    ?              *      1    0   :   ?   :   x;
`endif

        ?    ?              ?      *    ?   :   ?   :   x;  // any change on vpwr
        ?    ?              ?      ?    *   :   ?   :   x;  // any change on vgnd
    endtable
endprimitive
primitive scs8hdll_pg_U_DF_P_R (Q, D, CP, R);
    output Q;  
    input  D, CP, R;
    reg    Q; 
    
// FUNCTION :  POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
//             ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ).

    table
 
    //  D  CP   R    : Qt : Qt+1
        *  b    0    : ?  :  -  ; // data event, hold unless CP==x

        ?  (?0) 0    : ?  :  -  ; // CP => 0, hold

        ?  b    (?0) : ?  :  -  ; // R => 0, hold unless CP==x
        ?  ?    1    : ?  :  0  ; // async reset

        0  r    ?    : ?  :  0  ; // clock data on CP
        1  r    0    : ?  :  1  ; // clock data on CP

        0  (x1) ?    : 0  :  0  ; // possible CP, hold when D==Q==0
        1  (x1) 0    : 1  :  1  ; // possible CP, hold when D==Q==1

        0  x    ?    : 0  :  0  ; // unkown CP, hold when D==Q==0
        1  x    0    : 1  :  1  ; // unkown CP, hold when D==Q==1

        ?  b    (?x) : 0  :  0  ; // R=>x, hold when Q==0 unless CP==x

    endtable
endprimitive
primitive scs8hdll_pg_U_DF_P_R_NO_pg (Q, D, CP, R, NOTIFIER, VPWR, VGND);
    output Q;  
    input  D, CP, R, NOTIFIER, VPWR, VGND;
    reg    Q; 
    
// FUNCTION :  POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
//             ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ).

    table
 
    //  D  CP   R    NOTIFIER  VPWR VGND : Qt : Qt+1
        *  b    0     ?     1    0  : ?  :  -  ; // data event, hold unless CP==x

        ?  (?0) 0     ?     1    0  : ?  :  -  ; // CP => 0, hold

        ?  b    (?0)  ?     1    0  : ?  :  -  ; // R => 0, hold unless CP==x
        ?  ?    1     ?     1    0  : ?  :  0  ; // async reset

        0  r    ?     ?     1    0  : ?  :  0  ; // clock data on CP
        1  r    0     ?     1    0  : ?  :  1  ; // clock data on CP

        0  (x1) ?     ?     1    0  : 0  :  0  ; // possible CP, hold when D==Q==0
        1  (x1) 0     ?     1    0  : 1  :  1  ; // possible CP, hold when D==Q==1

        0  x    ?     ?     1    0  : 0  :  0  ; // unkown CP, hold when D==Q==0
        1  x    0     ?     1    0  : 1  :  1  ; // unkown CP, hold when D==Q==1

        ?  b    (?x)  ?     1    0  : 0  :  0  ; // R=>x, hold when Q==0 unless CP==x

        ?  (?0) x     ?     1    0  : 0  :  0  ; //JCWR

`ifdef functional
        ?  ?    ?     *     1    0  : ?  :  -  ; // Q => - on any change on notifier
`else
        ?  ?    ?     *     1    0  : ?  :  x  ; // Q => X on any change on notifier
`endif

        ?  ?    ?     ?     *    ?  : ?  :  x  ; // Q => X on any change on vpwr
        ?  ?    ?     ?     ?    *  : ?  :  x  ; // Q => X on any change on vgnd

    endtable
endprimitive
primitive scs8hdll_pg_U_DF_P_S (Q, D, CP, S);
    output Q;  
    input  D, CP, S;
    reg    Q; 
    
// FUNCTION :  POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
//             ASYNCHRONOUS SET ( Q OUTPUT UDP ).

    table
 
    //  D  CP   S    : Qt : Qt+1
        *  b    0    : ?  :  -  ; // data event, hold unless CP==x

        ?  (?0) 0    : ?  :  -  ; // CP => 0, hold

        ?  b    (?0) : ?  :  -  ; // S => 0, hold unless CP==x
        ?  ?    1    : ?  :  1  ; // async set

        0  r    0    : ?  :  0  ; // clock data on CP
        1  r    ?    : ?  :  1  ; // clock data on CP

        0  (x1) 0    : 0  :  0  ; // possible CP, hold when D==Q==0
        1  (x1) ?    : 1  :  1  ; // possible CP, hold when D==Q==1

        0  x    0    : 0  :  0  ; // unkown CP, hold when D==Q==0
        1  x    ?    : 1  :  1  ; // unkown CP, hold when D==Q==1

        ?  b    (?x) : 1  :  1  ; // S=>x, hold when Q==1 unless CP==x

    endtable
endprimitive
primitive scs8hdll_pg_U_DF_P_S_NO_pg (Q, D, CP, S, NOTIFIER, VPWR, VGND);
    output Q;  
    input  D, CP, S, NOTIFIER, VPWR, VGND;
    reg    Q; 
    
// FUNCTION :  POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE HIGH
//             ASYNCHRONOUS SET ( Q OUTPUT UDP ).

    table
 
    //  D  CP   S     NOTIFIER  VPWR VGND : Qt : Qt+1
        *  b    0      ?     1    0  : ?  :  -  ; // data event, hold unless CP==x

        ?  (?0) 0      ?     1    0  : ?  :  -  ; // CP => 0, hold

        ?  b    (?0)   ?     1    0  : ?  :  -  ; // S => 0, hold unless CP==x
        ?  ?    1      ?     1    0  : ?  :  1  ; // async set

        0  r    0      ?     1    0  : ?  :  0  ; // clock data on CP
        1  r    ?      ?     1    0  : ?  :  1  ; // clock data on CP

        0  (x1) 0      ?     1    0  : 0  :  0  ; // possible CP, hold when D==Q==0
        1  (x1) ?      ?     1    0  : 1  :  1  ; // possible CP, hold when D==Q==1

        0  x    0      ?     1    0  : 0  :  0  ; // unkown CP, hold when D==Q==0
        1  x    ?      ?     1    0  : 1  :  1  ; // unkown CP, hold when D==Q==1

        ?  b    (?x)   ?     1    0  : 1  :  1  ; // S=>x, hold when Q==1 unless CP==x

        ?  (?0) x      ?     1    0  : 1  :  1  ; //JCWR

`ifdef functional
        ?  ?    ?      *     1    0  : ?  :  -  ; // Q => - on any change on notifier
`else
        ?  ?    ?      *     1    0  : ?  :  x  ; // Q => X on any change on notifier
`endif

        ?  ?    ?      ?     *    ?  : ?  :  x  ; // Q => X on any change on vpwr
        ?  ?    ?      ?     ?    *  : ?  :  x  ; // Q => X on any change on vgnd
    endtable
endprimitive
primitive scs8hdll_pg_U_DL_P (Q, D, G);
//
// FUNCTION : DLATCH, GATED  STANDARD DRIVE / ACTIVE HIGH ( Q OUTPUT UDP )
//

    output Q; 
    reg    Q;                               
    input  D, G;

   table
     //  D      G    : Qt  :   Qt+1

         ?      0    :  ?  :    -   ;  // hold

         0      1    :  ?  :    0   ;  // pass 0
         1      1    :  ?  :    1   ;  // pass 1

         0      x    :  0  :    0   ;  // reduce pessimism
         1      x    :  1  :    1   ;  // reduce pessimism
                                       
   endtable

endprimitive
primitive scs8hdll_pg_U_DL_P_NO_pg (Q, D, G, NOTIFIER, VPWR, VGND);    
    output Q; 
    reg    Q;                               
    input  D, G, NOTIFIER, VPWR, VGND;       
// FUNCTION : DLATCH, GATED  STANDARD DRIVE / ACTIVE HIGH ( Q OUTPUT UDP )
//
// removing duplicated lines, allow JCWR changes


   table
     //  D       G    NOTIFIER  VPWR VGND  : Qtn :   Qtn+1

         *       0      ?         1    0   :  ?  :    -   ;

         ?      (?0)    ?         1    0   :  ?  :    -   ;
         ?      (1x)    ?         1    0   :  ?  :    -   ;

         0      (0x)    ?         1    0   :  0  :    0   ;
         1      (0x)    ?         1    0   :  1  :    1   ;
         0      (x1)    ?         1    0   :  ?  :    0   ;
         1      (x1)    ?         1    0   :  ?  :    1   ;

        (?0)     1      ?         1    0   :  ?  :    0   ;
        (?1)     1      ?         1    0   :  ?  :    1   ; 
         0      (01)    ?         1    0   :  ?  :    0   ;
         1      (01)    ?         1    0   :  ?  :    1   ; 

        (?1)     x      ?         1    0   :  1  :    1   ;    // Reducing pessimism.
        (?0)     x      ?         1    0   :  0  :    0   ; 
         
`ifdef functional
         ?       ?      *         1    0   :  ?  :    -   ;
`else
         ?       ?      *         1    0   :  ?  :    x   ;
`endif

         0       1      ?       (?1)   0   :  ?  :    0   ;  //JCWR
         1       1      ?       (?1)   0   :  ?  :    1   ;  //JCWR

         0       1      ?         1  (?0)  :  ?  :    0   ;  //JCWR
         1       1      ?         1  (?0)  :  ?  :    1   ;  //JCWR
   endtable

endprimitive
primitive scs8hdll_pg_U_DL_P_R (Q, D, G, R);
//
// FUNCTION : D-LATCH, GATED  CLEAR DIRECT /GATE ACTIVE HIGH ( Q OUTPUT UDP ) 
//

    output Q; 
    reg    Q;                               
    input  D,
           G,          // Gate- active high
           R;          // Clear-active high

    table
     //  D      G      R       : Qt  :   Qt+1

         ?      0      0       :  ?  :    -   ;     // hold

         0      1      0       :  ?  :    0   ;     // pass 0
         1      1      0       :  ?  :    1   ;     // pass 1

         ?      ?      1       :  ?  :    0   ;     // async reset

         0      1      ?       :  ?  :    0   ;     // reduce pessimism
         0      x      0       :  0  :    0   ;     // reduce pessimism
         1      x      0       :  1  :    1   ;     // reduce pessimism
         ?      0      x       :  0  :    0   ;     // reduce pessimism
         0      x      x       :  0  :    0   ;     // reduce pessimism
       
      endtable

endprimitive
primitive scs8hdll_pg_U_DL_P_R_NO_pg (Q, D, G, R, NOTIFIER, VPWR, VGND);    
    output Q; 
    reg    Q;                               
    input  D, G, R, NOTIFIER, VPWR, VGND;
// FUNCTION : D-LATCH, GATED  CLEAR DIRECT /GATE ACTIVE HIGH ( Q OUTPUT UDP ) 
//
// remove duplicated lines, allow JCWR edits
//
   table
     //  D       G      R     NOTIFIER  VPWR, VGND  : Qt  :   Qt+1
         *       0      0      ?          1     0   :  ?  :    -   ;

         ?       ?      1      ?          1     0   :  ?  :    0   ; // asynchro clear

         ?      (?0)    0      ?          1     0   :  ?  :    -   ; // Changed R=? to R=0 ; jek 08/14/06/
         ?      (1x)    0      ?          1     0   :  ?  :    -   ; // Changed R=? to R=0 ; jek 08/14/06

         0      (0x)    0      ?          1     0   :  0  :    0   ;
         1      (0x)    0      ?          1     0   :  1  :    1   ;
         0      (x1)    0      ?          1     0   :  ?  :    0   ;
         1      (x1)    0      ?          1     0   :  ?  :    1   ;

        (?0)     1      0      ?          1     0   :  ?  :    0   ;
        (?1)     1      0      ?          1     0   :  ?  :    1   ; 
         0      (01)    0      ?          1     0   :  ?  :    0   ;
         1      (01)    0      ?          1     0   :  ?  :    1   ; 

         ?       0     (?x)    ?          1     0   :  0  :    0   ;   // Reducing pessimism.//AB
         *       0      x      ?          1     0   :  0  :    0   ;   // Reducing pessimism//AB

         0      (?1)    x      ?          1     0   :  ?  :    0   ;   // Reducing pessimism.
        (?0)     1      x      ?          1     0   :  ?  :    0   ;   // Reducing pessimism.
         0       1     (?x)    ?          1     0   :  ?  :    0   ;   // Reducing pessimism.//AB

         ?       0     (?0)    ?          1     0   :  ?  :    -   ;   // ignore edge on clear
         0       1     (?0)    ?          1     0   :  ?  :    0   ;   // pessimism .
         1       1     (?0)    ?          1     0   :  ?  :    1   ;  

        (?1)     x      0      ?          1     0   :  1  :    1   ;   // Reducing pessimism.
        (?0)     x      0      ?          1     0   :  0  :    0   ;   // Reducing pessimism.
         
`ifdef functional
         ?       ?      ?      *          1     0   :  ?  :    -   ;
`else
         ?       ?      ?      *          1     0   :  ?  :    x   ;
`endif

         0       1      0      ?        (?1)    0   :  ?  :    0   ;  //JCWR
         1       1      0      ?        (?1)    0   :  ?  :    1   ;  //JCWR

         0       1      0      ?          1   (?0)  :  ?  :    0   ;  //JCWR
         1       1      0      ?          1   (?0)  :  ?  :    1   ;  //JCWR

   endtable

endprimitive
primitive scs8hdll_pg_U_MUX_2_1  (X, A0, A1, S);
    output X;
    input A0, A1, S;

// FUNCTION :  TWO TO ONE MULTIPLEXER

    table
    //  A0  A1  S   :   X
        0   0   ?   :   0 ;
        1   1   ?   :   1 ;
        
        0   ?   0   :   0 ;
        1   ?   0   :   1 ;

        ?   0   1   :   0 ;
        ?   1   1   :   1 ;
        
    endtable
endprimitive    
primitive scs8hdll_pg_U_MUX_2_1_INV  (Y, A0, A1, S);

    input A0, A1, S;
    output Y;
   
// FUNCTION :  TWO TO ONE MULTIPLEXER  WITH INVERTING OUTPUT

    table
//   A0  A1  S  : Y
  
     0   ?   0  : 1 ;
     1   ?   0  : 0 ;

     ?   0   1  : 1 ;
     ?   1   1  : 0 ;

     0   0   ?  : 1 ;
     1   1   ?  : 0 ;

     endtable
endprimitive
primitive scs8hdll_pg_U_MUX_4_2  (X, A0, A1, A2, A3, S0, S1);

    input A0, A1, A2, A3, S0, S1;
    output X;
   
// FUNCTION :  FOUR TO ONE MULTIPLEXER WITH 2 SELECT CONTROLS

    table

//   A0  A1  A2 A3  S0  S1 : X
                       
     0   ?   ?  ?    0  0  : 0 ; 
     1   ?   ?  ?    0  0  : 1 ; 
                                 
     ?   0   ?  ?    1  0  : 0 ; 
     ?   1   ?  ?    1  0  : 1 ; 
                                 
     ?   ?   0  ?    0  1  : 0 ; 
     ?   ?   1  ?    0  1  : 1 ; 
                                 
     ?   ?   ?  0    1  1  : 0 ; 
     ?   ?   ?  1    1  1  : 1 ; 
                                 

     0   0   0   0   ?  ?  : 0 ; 
                     
     1   1   1   1   ?  ?  : 1 ;

     0   0   ?   ?   ?  0  : 0 ;    
     1   1   ?   ?   ?  0  : 1 ; 

     ?   ?   0   0   ?  1  : 0 ; 
     ?   ?   1   1   ?  1  : 1 ; 

     0   ?   0   ?   0  ?  : 0 ; 
     1   ?   1   ?   0  ?  : 1 ; 

     ?   0   ?   0   1  ?  : 0 ; 
     ?   1   ?   1   1  ?  : 1 ; 

     endtable
endprimitive
primitive scs8hdll_pg_U_VGND ( UDP_OUT, UDP_IN, VGND );
  output UDP_OUT;
  input UDP_IN, VGND;

// UDP_OUT:=x when VPWR!=1
// UDP_OUT:=UDP_IN when VPWR==1

  table
//  X_int VPWR : X
      0    0   : 0 ;
      1    0   : 1 ;
      ?    1   : x ;
      ?    x   : x ;
  endtable
endprimitive
primitive scs8hdll_pg_U_VPWR ( UDP_OUT, UDP_IN, VPWR );
  output UDP_OUT;
  input UDP_IN, VPWR;

// UDP_OUT:=x when VPWR!=1
// UDP_OUT:=UDP_IN when VPWR==1

  table
//  X_int VPWR : X
      0    1   : 0 ;
      1    1   : 1 ;
      ?    0   : x ;
      ?    x   : x ;
  endtable
endprimitive
primitive scs8hdll_pg_U_VPWR_VGND ( UDP_OUT, UDP_IN, VPWR, VGND);
  output UDP_OUT;
  input UDP_IN, VPWR, VGND;

// UDP_OUT:=x when VPWR!=1 or VGND!=0
// UDP_OUT:=UDP_IN when VPWR==1 and VGND==0

  table
//   in  VPWR VGND  : out
      0    1    0   : 0 ;
      1    1    0   : 1 ;
      x    1    0   : x ;
      ?    0    0   : x ;
      ?    1    1   : x ;
      ?    x    0   : x ;
      ?    1    x   : x ;
  endtable
endprimitive
primitive scs8hdll_pg_U_VPWR_VGND_SLEEP ( UDP_OUT, UDP_IN, VPWR, VGND, SLEEP);
  output UDP_OUT;
  input UDP_IN, VPWR, VGND, SLEEP;

// UDP_OUT:=x when VPWR!=1 or VGND!=0
// UDP_OUT:=UDP_IN when VPWR==1 and VGND==0

  table
//   in  VPWR VGND  SLEEP   : out
      0    1    0     ?     : 0 ;
      1    1    0     0     : 1 ;
      x    1    0     0     : x ;
      ?    0    0     0     : x ;
      ?    1    1     0     : x ;
      ?    x    0     0     : x ;
      ?    1    x     0     : x ;
      ?    ?    0     1     : 0 ;
      ?    ?    1     1     : x ;
      ?    ?    x     1     : x ;
  endtable
endprimitive