// Verilog HDL for "s8iom0s8", "s8iom0s8_top_gpio" "behavioral"

// ===============================================
// Copyright 2011, Cypress Semiconductor Corporation.
//
// This software is owned by Cypress Semiconductor Corporation (Cypress)
// and is protected by United States copyright laws and international
// treaty provisions. Therefore, you must treat this software like any
// other copyrighted material (e.g., book, or musical recording), with
// the exception that one copy may be made for personal use or
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// written permission of Cypress.
//
// Disclaimer: Cypress makes no warranty of any kind, express or implied,
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// implied warranties of merchantability and fitness for a particular
// purpose. Cypress reserves the right to make changes without further
// notice to the materials described herein. Cypress does not assume any
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// circuit described herein. Cypress' products described herein are
// not authorized for use as components in life-support devices.
//
// This software is protected by and subject to worldwide patent
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//
// ===============================================
// File     :$File: //depot/icm/proj/s8iom0s8/icmrel/ipVault/opus/s8iom0s8/s8iom0s8_top_gpio/behavioral/verilog.v $
// Author   : GURU
// Date     : Jan 25, 2012
// $Revision: 1 $
// ===============================================
// Description : General Purpose I/0

`timescale 1ns / 1ps

module s8iom0s8_top_gpio (in_h, pad_a_noesd_h,pad_a_esd_0_h,pad_a_esd_1_h,
    pad, dm, hld_h_n, in, inp_dis, enable_h, enable_vdda_h, enable_inp_h, oe_n, 
    tie_hi_esd, tie_lo_esd, slow, vtrip_sel, hld_ovr, analog_en, analog_sel, 
    analog_pol, out, amuxbus_a, amuxbus_b 
`ifdef USE_PG_PIN    
    ,vssa, vdda, vswitch, vddio_q, vcchib, vddio, vccd, vssio,
    vssd, vssio_q 
`endif
    );


input out;  		
input oe_n;  		
input hld_h_n;		
input enable_h;
input enable_inp_h;	
input enable_vdda_h;	
input inp_dis;		
input vtrip_sel;	
input slow;		
input hld_ovr;		
input analog_en;	
input analog_sel;	
input analog_pol;	
input [2:0] dm;		


`ifdef USE_PG_PIN
	inout vddio;	
	inout vddio_q;	
	inout vdda;
	inout vccd;
	inout vswitch;
	inout vcchib;
	inout vssa;
	inout vssd;
	inout vssio_q;
	inout vssio;
	
`else

	supply1 vddio;
	supply1 vddio_q;
	supply1 vdda;
	supply1 vccd;
	supply1 vswitch;
	supply1 vcchib;
	supply1 vpb;
	supply1 vpbhib;
	supply0 vssd;
	supply0 vssio;
	supply0 vssio_q;
	supply0 vssa;
	
`endif

inout pad;
inout pad_a_noesd_h,pad_a_esd_0_h,pad_a_esd_1_h;
inout amuxbus_a;
inout amuxbus_b;

output in;
output in_h;
output tie_hi_esd, tie_lo_esd;

reg [2:0] dm_final;
reg slow_final, vtrip_sel_final, inp_dis_final, out_final, oe_n_final, hld_ovr_final, analog_en_final;

reg notifier_dm, notifier_slow, notifier_oe_n, notifier_out, notifier_vtrip_sel, notifier_hld_ovr, notifier_inp_dis;
reg notifier_enable_h;


`ifdef functional

`else

specify
 
     (inp_dis => in) = (0:0:0,0:0:0) ; //(2.777::2.833 , 3.614::3.687))
     (inp_dis => in_h) = (0:0:0,0:0:0) ; //(2.438::2.487 , 1.789::1.825))
   
    if ( dm[2] == 1'b0 & dm[1] == 1'b1 & dm[0] == 1'b1 & slow == 1'b1 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b1 & dm[0] == 1'b1 & slow == 1'b1 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b0 & dm[1] == 1'b1 & dm[0] == 1'b1 & slow == 1'b0 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b0 & dm[1] == 1'b1 & dm[0] == 1'b0 & slow == 1'b0 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b1 & dm[0] == 1'b0 & slow == 1'b1 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( vtrip_sel == 1'b1 ) ( pad => in) =  (0:0:0 , 0:0:0); 
    if ( vtrip_sel == 1'b1 ) ( pad => in_h) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b0 & dm[0] == 1'b0 & slow == 1'b0 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( vtrip_sel == 1'b0 ) ( pad => in) = (0:0:0 , 0:0:0); 
    if ( vtrip_sel == 1'b0 ) ( pad => in_h) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b0 & dm[0] == 1'b1 & slow == 1'b0 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b0 & dm[1] == 1'b1 & dm[0] == 1'b0 & slow == 1'b1 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b0 & dm[0] == 1'b0 & slow == 1'b1 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b1 & dm[0] == 1'b0 & slow == 1'b0 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b0 & dm[0] == 1'b1 & slow == 1'b1 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b1 & dm[0] == 1'b1 & slow == 1'b0 &  oe_n == 1'b0 ) ( out => pad) = (0:0:0 , 0:0:0); 

    if ( dm[2] == 1'b0 & dm[1] == 1'b1 & dm[0] == 1'b0 & slow == 1'b1 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b0 & dm[0] == 1'b0 & slow == 1'b0 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b0 & dm[1] == 1'b1 & dm[0] == 1'b1 & slow == 1'b1 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b0 & dm[1] == 1'b1 & dm[0] == 1'b1 & slow == 1'b0 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b0 & dm[0] == 1'b1 & slow == 1'b1 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b0 & dm[0] == 1'b1 & slow == 1'b0 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b0 & dm[1] == 1'b1 & dm[0] == 1'b0 & slow == 1'b0 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b0 & dm[0] == 1'b0 & slow == 1'b1 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b1 & dm[0] == 1'b0 & slow == 1'b0 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b1 & dm[0] == 1'b1 & slow == 1'b0 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b1 & dm[0] == 1'b1 & slow == 1'b1 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    if ( dm[2] == 1'b1 & dm[1] == 1'b1 & dm[0] == 1'b0 & slow == 1'b1 ) ( oe_n => pad) = (0:0:0 , 0:0:0, 0:0:0, 0:0:0, 0:0:0, 0:0:0); 
    
    
    $width  (negedge hld_h_n,	      (15.500:0:15.500));
    $width  (posedge hld_h_n,	      (15.500:0:15.500));
    $width  (negedge hld_ovr,	      (15.500:0:15.500));
    $width  (posedge hld_ovr,	      (15.500:0:15.500));
 
    specparam tsetup = 5;
    specparam thold = 5;

    $setuphold (negedge enable_h,    posedge hld_h_n,    tsetup, thold,  notifier_enable_h); 
    $setuphold (negedge enable_h,    negedge hld_h_n,    tsetup, thold,  notifier_enable_h); 
    $setuphold (posedge enable_h,    posedge hld_h_n,    tsetup, thold,  notifier_enable_h); 
    $setuphold (posedge enable_h,    negedge hld_h_n,    tsetup, thold,  notifier_enable_h); 
    
    $setuphold (negedge hld_h_n, posedge hld_ovr,    tsetup, thold,  notifier_hld_ovr,   enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, negedge hld_ovr,    tsetup, thold,  notifier_hld_ovr,   enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, posedge dm[2],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, negedge dm[2],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, posedge dm[1],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, negedge dm[1],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, posedge dm[0],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, negedge dm[0],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, posedge inp_dis,    tsetup, thold,  notifier_inp_dis,   enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, negedge inp_dis,    tsetup, thold,  notifier_inp_dis,   enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, posedge vtrip_sel,  tsetup, thold,  notifier_vtrip_sel, enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, negedge vtrip_sel,  tsetup, thold,  notifier_vtrip_sel, enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, posedge slow,       tsetup, thold,  notifier_slow,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, negedge slow,       tsetup, thold,  notifier_slow,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, posedge oe_n,       tsetup, thold,  notifier_oe_n,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, negedge oe_n,       tsetup, thold,  notifier_oe_n,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, posedge out,        tsetup, thold,  notifier_out,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (negedge hld_h_n, negedge out,        tsetup, thold,  notifier_out,	 enable_h==1'b1, enable_h==1'b1); 
   
   
    $setuphold (posedge hld_h_n, posedge hld_ovr,    tsetup, thold,  notifier_hld_ovr,   enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, negedge hld_ovr,    tsetup, thold,  notifier_hld_ovr,   enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, posedge dm[2],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, negedge dm[2],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, posedge dm[1],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, negedge dm[1],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, posedge dm[0],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, negedge dm[0],      tsetup, thold,  notifier_dm,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, posedge inp_dis,    tsetup, thold,  notifier_inp_dis,   enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, negedge inp_dis,    tsetup, thold,  notifier_inp_dis,   enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, posedge vtrip_sel,  tsetup, thold,  notifier_vtrip_sel, enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, negedge vtrip_sel,  tsetup, thold,  notifier_vtrip_sel, enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, posedge slow,       tsetup, thold,  notifier_slow,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, negedge slow,       tsetup, thold,  notifier_slow,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, posedge oe_n,       tsetup, thold,  notifier_oe_n,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, negedge oe_n,       tsetup, thold,  notifier_oe_n,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, posedge out,        tsetup, thold,  notifier_out,	 enable_h==1'b1, enable_h==1'b1); 
    $setuphold (posedge hld_h_n, negedge out,        tsetup, thold,  notifier_out,	 enable_h==1'b1, enable_h==1'b1); 


endspecify

`endif


// POWER GOOD LOGIC


`ifdef USE_PG_PIN

	wire  pwr_good_amux_1	      = ((hld_h_n===0 || enable_vdda_h===0) ? 1:(vccd===1)) && (vdda===1) && (vswitch===1) && (vssd===0) && (vssa===0);
	
	wire  pwr_good_amux_2	      = ((hld_h_n===0 || enable_vdda_h===0) ? 1:(vccd===1)) && (vdda===1) && (vswitch===1) && (vssd===0) && (vssa===0) && (vddio_q===1);
	
	wire  pwr_good_hold_ovr_mode  = (vddio_q===1) && (vddio===1)  && (vssd===0)    && (vcchib===1);
	
	wire  pwr_good_active_mode    = (vddio_q===1) && (vddio===1)  && (vssd===0)    && (vccd===1);
	
	wire  pwr_good_hold_mode      = (vddio_q===1) && (vddio===1)  && (vssd===0);  
	
	wire  pwr_good_active_mode_vdda = (vdda===1)  && (vssd===0)   && (vccd===1);
	
	wire  pwr_good_hold_mode_vdda = (vdda===1)    && (vssd===0);  
	
	wire  pwr_good_inpbuff_hv     = (vddio_q===1) && (vssd===0)   && (vddio===1)   && (vssio===0);
	
	wire  pwr_good_inpbuff_lv     = (vddio_q===1) && (vssd===0)   && (vcchib===1)  && (vddio===1) && (vssio===0);
	
	wire  pwr_good_output_driver  = (vddio===1)   && (vddio_q===1)&& (vssio===0)   && (vssd===0)  && (vdda===1) && (vswitch===1) && (vssa===0) ;


`else
	wire  pwr_good_amux_1	      	= 1;
	wire  pwr_good_amux_2	      	= 1;
        wire  pwr_good_inpbuff_hv      	= 1;
	wire  pwr_good_inpbuff_lv       = 1; 
	wire  pwr_good_output_driver  	= 1;
	wire  pwr_good_hold_mode	= 1;
	wire  pwr_good_hold_ovr_mode	= 1;
	wire  pwr_good_active_mode      = 1;
	wire  pwr_good_hold_mode_vdda	= 1;
	wire  pwr_good_active_mode_vdda	= 1;
`endif


//===============================================FEATURES - 1, 2, 7, 8=============================================================


// OUTPUT DRIVER

// Feature - 1 & 2 & 7: Drive-modes (dm[2:0]), inp_dis, and oe_n, and enable_h


wire pad_tristate = oe_n_final === 1 || dm_final === 3'b000 || dm_final === 3'b001;

wire x_on_pad  =  !pwr_good_output_driver 
		  
		  || (dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'bx) 
		  
		  || (^dm_final[2:0] === 1'bx && oe_n_final===1'b0) 
		  
		  || (slow_final===1'bx && dm_final !== 3'b000 && dm_final !== 3'b001 && oe_n_final===1'b0);   
		  

// For dm_final = 000 and 001, out_final = Z
// bufif1 is being used to ensure drive strength resolution

bufif1 (pull1, strong0)   dm2 (pad, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b010));
bufif1 (strong1, pull0)   dm3 (pad, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b011));
bufif1 (highz1, strong0)  dm4 (pad, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b100));
bufif1 (strong1, highz0)  dm5 (pad, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b101));
bufif1 (strong1, strong0) dm6 (pad, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b110));
bufif1 (pull1, pull0)     dm7 (pad, out_final, x_on_pad===1 ? 1'bx : (pad_tristate===0 && dm_final===3'b111));


tran pad_esd_1 (pad,pad_a_noesd_h);
tran pad_esd_2 (pad,pad_a_esd_0_h);
tran pad_esd_3 (pad,pad_a_esd_1_h);

//=========================================================================================================


// INPUT BUFFER

// Effect of dm, inp_dis, dm_000, enable_h, and fault_GPIO on INPUT Buffer. 
// Also if pad is floating or corrupted, input buffer outputs an X.


wire x_on_in  =  (enable_h===0  && ^enable_inp_h===1'bx)

		 || (inp_dis_final===1'bx    && dm_final !== 3'b000      && analog_en_final===0)
		 
		 || (inp_dis_final===0 	     && ^dm_final[2:0] === 1'bx  && analog_en_final===0)
		 
		 || (inp_dis_final===0 	     && dm_final !== 3'b000      && analog_en_final===1'bx)

		 || (vtrip_sel_final===1'bx  && inp_dis_final===0        && dm_final !== 3'b000     && analog_en_final===0) ;
  

wire disable_inp_buff = enable_h===1 ? ((dm_final===3'b000 || inp_dis_final===1 || analog_en_final===1)) : enable_inp_h===0;

assign in_h = (x_on_in===1 || pwr_good_inpbuff_hv===0) ? 1'bx : (disable_inp_buff===1 ? 0 : (^pad===1'bx ? 1'bx : pad));

assign in   = pwr_good_inpbuff_lv===1 ? in_h : 1'bx;

//=============================================================================================================


// Other outputs

assign tie_hi_esd = vddio===1'b1 ? 1'b1 : 1'bx;
assign tie_lo_esd = vssio===1'b0 ? 1'b0 : 1'bx;


//========================================================================================================================================


//======================================= FEATURE - 6,9 ===================================================

// Hold state mode (latch previous state) and Hold over-ride
// Latching onto current inputs and controls when hld_h_n = 0
// All latches are made transparent when when hld_h_n = 1 else, they will be assigned to their latched values.
// Exception : When hld_ovr is asserted, out and oe_n will be taken from corresponding inputs and not from the latched values, even if hld_h_n=0

// Corrupting / Reseting the latches when pwr_good or enable_h toggles
// When brown-out occurs i.e.pwr_good = 0, latch states are corrupted
// and when enable_h asserts, the latches are reset to 0.


always @(*)
begin : LATCH_dm
	
	
	if (^enable_h===1'bx || !pwr_good_hold_mode || (enable_h===1 && ^hld_h_n===1'bx))
		dm_final 	<= 3'bxxx;
	else if (enable_h===0)
		dm_final 	<= 3'b000;
	else if (hld_h_n===1)
		dm_final 	<= (^dm[2:0]	=== 1'bx	|| !pwr_good_active_mode) ? 3'bxxx : dm;
end

always @(notifier_enable_h or notifier_dm)
begin
     disable LATCH_dm; dm_final <= 3'bxxx;
end


always @(*)
begin : LATCH_inp_dis	
	
	
	if (^enable_h===1'bx || !pwr_good_hold_mode || (enable_h===1 && ^hld_h_n===1'bx))
		inp_dis_final 	<= 1'bx;
	else if (enable_h===0)
		inp_dis_final 	<= 1'b0;
	else if (hld_h_n===1)
		inp_dis_final 	<= (^inp_dis === 1'bx	|| !pwr_good_active_mode) ? 1'bx : inp_dis;
end

always @(notifier_enable_h or notifier_inp_dis)
begin
     disable LATCH_inp_dis; inp_dis_final <= 1'bx;
end


always @(*)
begin : LATCH_vtrip_sel	

	
	if (^enable_h===1'bx || !pwr_good_hold_mode || (enable_h===1 && ^hld_h_n===1'bx))
		vtrip_sel_final 	<= 1'bx;
	else if (enable_h===0)
		vtrip_sel_final 	<= 1'b0;
	else if (hld_h_n===1)
		vtrip_sel_final 	<= (^vtrip_sel === 1'bx	|| !pwr_good_active_mode) ? 1'bx : vtrip_sel;
end

always @(notifier_enable_h or notifier_vtrip_sel)
begin
     disable LATCH_vtrip_sel; vtrip_sel_final <= 1'bx;
end


always @(*)
begin : LATCH_slow	

	
	if (^enable_h===1'bx || !pwr_good_hold_mode || (enable_h===1 && ^hld_h_n===1'bx))
		slow_final 	<= 1'bx;
	else if (enable_h===0)
		slow_final 	<= 1'b0;
	else if (hld_h_n===1)
		slow_final 	<= (^slow === 1'bx	|| !pwr_good_active_mode) ? 1'bx : slow;
end
always @(notifier_enable_h or notifier_slow)
begin
     disable LATCH_slow; slow_final <= 1'bx;
end


always @(*)
begin : LATCH_hld_ovr	
	
	
	if (^enable_h===1'bx || !pwr_good_hold_mode || (enable_h===1 && ^hld_h_n===1'bx))
		hld_ovr_final 	<= 1'bx;
	else if (enable_h===0)
		hld_ovr_final 	<= 1'b0;
	else if (hld_h_n===1)
		hld_ovr_final 	<= (^hld_ovr === 1'bx	|| !pwr_good_active_mode) ? 1'bx : hld_ovr;
end
always @(notifier_enable_h or notifier_hld_ovr)
begin
     disable LATCH_hld_ovr; hld_ovr_final <= 1'bx;
end


always @(*)
begin : LATCH_oe_n

		
	if (^enable_h===1'bx || !pwr_good_hold_mode || (enable_h===1 && (^hld_h_n===1'bx || (hld_h_n===0 && hld_ovr_final===1'bx))))
	        oe_n_final 	<= 1'bx;
	else if (enable_h===0)
		oe_n_final 	<= 1'b0;
	else if (hld_h_n===1 || hld_ovr_final===1)
		oe_n_final  	<= (^oe_n  === 1'bx  || !pwr_good_hold_ovr_mode) ? 1'bx   : oe_n;
end		

always @(notifier_enable_h or notifier_oe_n)
begin
     disable LATCH_oe_n; oe_n_final <= 1'bx;
end


always @(*)
begin : LATCH_out

		
	if (^enable_h===1'bx || !pwr_good_hold_mode || (enable_h===1 && (^hld_h_n===1'bx ||(hld_h_n===0 &&  hld_ovr_final===1'bx))))
	        out_final 	<= 1'bx;
	else if (enable_h===0)
		out_final 	<= 1'b0;
	else if (hld_h_n===1 || hld_ovr_final===1)
		out_final  	<= (^out  === 1'bx  || !pwr_good_hold_ovr_mode) ? 1'bx   : out;
end	

always @(notifier_enable_h or notifier_out)
begin
     disable LATCH_out; out_final <= 1'bx;
end


// Level-shifting Latch for analog_en, but without a hold-state mode
// When enable_h=1 or hld_h_n=0, this latch is reset
		
always @(*)
begin
	if (^enable_vdda_h===1'bx || !pwr_good_hold_mode_vdda || (enable_h===1 && ^hld_h_n===1'bx) || (^enable_h===1'bx && hld_h_n===1'b1))
	
		analog_en_final 	= 1'bx;
	
	else if (enable_vdda_h===0 || hld_h_n===0 || enable_h===0)
	
		analog_en_final 	= 1'b0;
	
	else 
		analog_en_final 	= (^analog_en===1'bx || !pwr_good_active_mode_vdda) ? 1'bx   : analog_en;
end


//==================================================================================================================


//=============================================FEATURE - 10 ========================================================

// GPIO Analog Mux (AMUX) Connectivity modes

wire [2:0] amux_select = {analog_sel, analog_pol, out};


wire invalid_controls_amux_1 = 	!pwr_good_amux_1 
				
				|| (analog_en_final===1'bx)
				
				|| (analog_en_final===1 && ^amux_select[2:0] === 1'bx);


wire invalid_controls_amux_2 = 	!pwr_good_amux_2 
				
				|| (^enable_h===1'bx && analog_en_final===1)
				
				|| (analog_en_final===1'bx && enable_h===1)
				
				|| (analog_en_final===1 && enable_h===1 && ^amux_select[2:0] === 1'bx);


wire enable_pad_amuxbus_a = invalid_controls_amux_1  ? 1'bx : (amux_select===3'b001 || amux_select===3'b010) && (analog_en_final===1);
wire enable_pad_amuxbus_b = invalid_controls_amux_1  ? 1'bx : (amux_select===3'b101 || amux_select===3'b110) && (analog_en_final===1);
wire enable_pad_vssio_q   = invalid_controls_amux_1  ? 1'bx : (amux_select===3'b100 || amux_select===3'b000) && (analog_en_final===1);
wire enable_pad_vddio_q   = invalid_controls_amux_2  ? 1'bx : (amux_select===3'b011 || amux_select===3'b111) && (analog_en_final===1 && enable_h===1);


tranif1 pad_amuxbus_a 	(pad, amuxbus_a, enable_pad_amuxbus_a);
tranif1 pad_amuxbus_b 	(pad, amuxbus_b, enable_pad_amuxbus_b);
bufif1 pad_vddio_q	(pad, vddio_q,   enable_pad_vddio_q);
bufif1 pad_vssio_q   	(pad, vssio_q,   enable_pad_vssio_q);


endmodule