verilog/sky130_osu_sc_invx4.v

// type: INV 
`timescale 1ns/10ps
`celldefine
module sky130_osu_sc_INVX4 (Y, A);
	output Y;
	input A;

	// Function
	not (Y, A);

	// Timing
	specify
		(A => Y) = 0;
	endspecify
endmodule
`endcelldefine