diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P56_-40C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P56_-40C.ccs.v
new file mode 100644
index 0000000..62d0e12
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P56_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_ff_1P56_-40C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 17:03:28 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P76_-40C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P76_-40C.ccs.v
new file mode 100644
index 0000000..ce71c60
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P76_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_ff_1P76_-40C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 17:40:54 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P95_-40C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P95_-40C.ccs.v
new file mode 100644
index 0000000..34fa0c8
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P95_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_ff_1P95_-40C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 18:20:06 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P95_100C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P95_100C.ccs.v
new file mode 100644
index 0000000..f920793
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P95_100C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_ff_1P95_100C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 18:59:28 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P95_150C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P95_150C.ccs.v
new file mode 100644
index 0000000..4f85fbd
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_ff_1P95_150C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_ff_1P95_150C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 19:36:37 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P28_-40C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P28_-40C.ccs.v
new file mode 100644
index 0000000..c468de8
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P28_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_ss_1P28_-40C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 20:15:17 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P44_-40C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P44_-40C.ccs.v
new file mode 100644
index 0000000..1af51f4
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P44_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_ss_1P44_-40C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 20:53:58 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P60_-40C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P60_-40C.ccs.v
new file mode 100644
index 0000000..4929c30
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P60_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_ss_1P60_-40C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 21:31:49 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P60_100C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P60_100C.ccs.v
new file mode 100644
index 0000000..7878b9f
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P60_100C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_ss_1P60_100C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 22:09:48 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P60_150C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P60_150C.ccs.v
new file mode 100644
index 0000000..1bcc954
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_ss_1P60_150C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_ss_1P60_150C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 22:48:24 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P20_25C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P20_25C.ccs.v
new file mode 100644
index 0000000..4ed2bca
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P20_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_1P20_25C.ccs created by Liberate 19.2.1.215 on Thu Feb 18 23:27:22 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P35_25C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P35_25C.ccs.v
new file mode 100644
index 0000000..019154a
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P35_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_1P35_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 00:06:57 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P44_25C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P44_25C.ccs.v
new file mode 100644
index 0000000..77c4d40
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P44_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_1P44_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 00:46:41 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P50_25C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P50_25C.ccs.v
new file mode 100644
index 0000000..5777503
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P50_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_1P50_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 01:23:54 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P62_25C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P62_25C.ccs.v
new file mode 100644
index 0000000..48d2e64
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P62_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_1P62_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 02:02:50 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P68_25C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P68_25C.ccs.v
new file mode 100644
index 0000000..f3d08a6
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P68_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_1P68_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 02:42:40 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P80_100C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P80_100C.ccs.v
new file mode 100644
index 0000000..58bdf9e
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P80_100C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_1P80_100C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 03:21:05 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P80_150C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P80_150C.ccs.v
new file mode 100644
index 0000000..2b5d2fe
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P80_150C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_1P80_150C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 04:00:58 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P80_25C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P80_25C.ccs.v
new file mode 100644
index 0000000..d4a8feb
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P80_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_1P80_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 04:41:56 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P89_25C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P89_25C.ccs.v
new file mode 100644
index 0000000..644cf98
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_1P89_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_1P89_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 05:19:57 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_2P10_25C.ccs.v b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_2P10_25C.ccs.v
new file mode 100644
index 0000000..dd6be06
--- /dev/null
+++ b/18T_hs/verilog/sky130_osu_sc_18T_hs_tt_2P10_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_hs_tt_2P10_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 05:59:16 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_hs__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_hs__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P56_-40C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P56_-40C.ccs.v
new file mode 100644
index 0000000..143dd67
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P56_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_ff_1P56_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 19:56:46 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P76_-40C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P76_-40C.ccs.v
new file mode 100644
index 0000000..132fb38
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P76_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_ff_1P76_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 20:34:19 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P95_-40C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P95_-40C.ccs.v
new file mode 100644
index 0000000..8491004
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P95_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_ff_1P95_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 21:11:17 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P95_100C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P95_100C.ccs.v
new file mode 100644
index 0000000..a0fa2b0
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P95_100C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_ff_1P95_100C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 21:49:21 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P95_150C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P95_150C.ccs.v
new file mode 100644
index 0000000..73f1658
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_ff_1P95_150C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_ff_1P95_150C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 22:26:51 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P28_-40C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P28_-40C.ccs.v
new file mode 100644
index 0000000..217f9b9
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P28_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_ss_1P28_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 23:04:36 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P44_-40C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P44_-40C.ccs.v
new file mode 100644
index 0000000..8760c4e
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P44_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_ss_1P44_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 23:42:14 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P60_-40C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P60_-40C.ccs.v
new file mode 100644
index 0000000..634ffdc
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P60_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_ss_1P60_-40C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 00:18:12 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P60_100C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P60_100C.ccs.v
new file mode 100644
index 0000000..ccda147
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P60_100C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_ss_1P60_100C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 00:55:31 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P60_150C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P60_150C.ccs.v
new file mode 100644
index 0000000..71c4321
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_ss_1P60_150C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_ss_1P60_150C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 01:32:56 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P20_25C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P20_25C.ccs.v
new file mode 100644
index 0000000..dc36024
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P20_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_1P20_25C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 02:08:21 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P35_25C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P35_25C.ccs.v
new file mode 100644
index 0000000..f7f3116
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P35_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_1P35_25C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 02:45:12 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P44_25C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P44_25C.ccs.v
new file mode 100644
index 0000000..a9c532d
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P44_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_1P44_25C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 03:21:05 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P50_25C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P50_25C.ccs.v
new file mode 100644
index 0000000..a599fa6
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P50_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_1P50_25C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 03:58:01 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P62_25C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P62_25C.ccs.v
new file mode 100644
index 0000000..ea9542d
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P62_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_1P62_25C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 04:34:40 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P68_25C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P68_25C.ccs.v
new file mode 100644
index 0000000..d0d8623
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P68_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_1P68_25C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 05:10:02 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P80_100C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P80_100C.ccs.v
new file mode 100644
index 0000000..dc769bb
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P80_100C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_1P80_100C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 05:47:09 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P80_150C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P80_150C.ccs.v
new file mode 100644
index 0000000..037e847
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P80_150C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_1P80_150C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 06:24:40 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P80_25C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P80_25C.ccs.v
new file mode 100644
index 0000000..7042078
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P80_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_1P80_25C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 07:01:49 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P89_25C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P89_25C.ccs.v
new file mode 100644
index 0000000..33f0529
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_1P89_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_1P89_25C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 07:39:44 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_2P10_25C.ccs.v b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_2P10_25C.ccs.v
new file mode 100644
index 0000000..f8a36be
--- /dev/null
+++ b/18T_ls/verilog/sky130_osu_sc_18T_ls_tt_2P10_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ls_tt_2P10_25C.ccs created by Liberate 19.2.1.215 on Sat Feb 20 08:17:42 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ls__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ls__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P56_-40C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P56_-40C.ccs.v
new file mode 100644
index 0000000..ad7e00f
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P56_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_ff_1P56_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 06:37:47 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P76_-40C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P76_-40C.ccs.v
new file mode 100644
index 0000000..d5b39fa
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P76_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_ff_1P76_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 07:15:10 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P95_-40C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P95_-40C.ccs.v
new file mode 100644
index 0000000..ef75f6f
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P95_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_ff_1P95_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 07:52:10 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P95_100C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P95_100C.ccs.v
new file mode 100644
index 0000000..0d4f1fa
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P95_100C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_ff_1P95_100C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 08:30:56 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P95_150C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P95_150C.ccs.v
new file mode 100644
index 0000000..419f1c4
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_ff_1P95_150C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_ff_1P95_150C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 09:07:46 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P28_-40C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P28_-40C.ccs.v
new file mode 100644
index 0000000..d5d743b
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P28_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_ss_1P28_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 09:46:10 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P44_-40C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P44_-40C.ccs.v
new file mode 100644
index 0000000..178234e
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P44_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_ss_1P44_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 10:26:30 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P60_-40C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P60_-40C.ccs.v
new file mode 100644
index 0000000..3e19e9b
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P60_-40C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_ss_1P60_-40C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 11:05:17 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P60_100C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P60_100C.ccs.v
new file mode 100644
index 0000000..194a160
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P60_100C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_ss_1P60_100C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 11:43:53 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P60_150C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P60_150C.ccs.v
new file mode 100644
index 0000000..a1f4eb6
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_ss_1P60_150C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_ss_1P60_150C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 12:22:44 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P20_25C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P20_25C.ccs.v
new file mode 100644
index 0000000..26e2882
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P20_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_1P20_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 13:00:39 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P35_25C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P35_25C.ccs.v
new file mode 100644
index 0000000..ddeae80
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P35_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_1P35_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 13:38:03 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P44_25C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P44_25C.ccs.v
new file mode 100644
index 0000000..c177eae
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P44_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_1P44_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 14:15:32 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P50_25C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P50_25C.ccs.v
new file mode 100644
index 0000000..703ae69
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P50_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_1P50_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 14:53:03 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P62_25C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P62_25C.ccs.v
new file mode 100644
index 0000000..9d2d8d4
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P62_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_1P62_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 15:31:14 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P68_25C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P68_25C.ccs.v
new file mode 100644
index 0000000..c81a5ad
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P68_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_1P68_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 16:09:11 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P80_100C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P80_100C.ccs.v
new file mode 100644
index 0000000..eee3fbc
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P80_100C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_1P80_100C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 16:47:03 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P80_150C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P80_150C.ccs.v
new file mode 100644
index 0000000..c1b15f4
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P80_150C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_1P80_150C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 17:26:19 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P80_25C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P80_25C.ccs.v
new file mode 100644
index 0000000..efe9c71
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P80_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_1P80_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 18:04:16 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P89_25C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P89_25C.ccs.v
new file mode 100644
index 0000000..8525d41
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_1P89_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_1P89_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 18:42:12 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_2P10_25C.ccs.v b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_2P10_25C.ccs.v
new file mode 100644
index 0000000..6f5cd78
--- /dev/null
+++ b/18T_ms/verilog/sky130_osu_sc_18T_ms_tt_2P10_25C.ccs.v
@@ -0,0 +1,2143 @@
+// Verilog for library /import/okita1/hlusk/CellRechar/test/osugooglelib/char/liberate/VERILOG/sky130_osu_sc_18T_ms_tt_2P10_25C.ccs created by Liberate 19.2.1.215 on Fri Feb 19 19:20:10 CST 2021 for SDF version 2.1
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_1 (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addf_l (CO, CON, S, A, B, CI);
+	output CO, CON, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6, int_fwire_7, int_fwire_8;
+	wire int_fwire_9;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (CI__bar, CI);
+	not (B__bar, B);
+	and (int_fwire_3, B__bar, CI__bar);
+	not (A__bar, A);
+	and (int_fwire_4, A__bar, CI__bar);
+	and (int_fwire_5, A__bar, B__bar);
+	or (CON, int_fwire_5, int_fwire_4, int_fwire_3);
+	and (int_fwire_6, A__bar, B__bar, CI);
+	and (int_fwire_7, A__bar, B, CI__bar);
+	and (int_fwire_8, A, B__bar, CI__bar);
+	and (int_fwire_9, A, B, CI);
+	or (S, int_fwire_9, int_fwire_8, int_fwire_7, int_fwire_6);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & ~CI))
+			(A => CON) = 0;
+		if ((~B & CI))
+			(A => CON) = 0;
+		ifnone (A => CON) = 0;
+		if ((A & ~CI))
+			(B => CON) = 0;
+		if ((~A & CI))
+			(B => CON) = 0;
+		ifnone (B => CON) = 0;
+		if ((A & ~B))
+			(CI => CON) = 0;
+		if ((~A & B))
+			(CI => CON) = 0;
+		ifnone (CI => CON) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_1 (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__addh 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__addh_l (CO, CON, S, A, B);
+	output CO, CON, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1, int_fwire_2;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	or (CON, CO, int_fwire_0);
+	and (int_fwire_1, A__bar, B);
+	and (int_fwire_2, A, B__bar);
+	or (S, int_fwire_2, int_fwire_1);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (B)
+			(A => CON) = 0;
+		if (~B)
+			(A => CON) = 0;
+		if (A)
+			(B => CON) = 0;
+		if (~A)
+			(B => CON) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_6 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__and2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__and2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__ant (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__aoi22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__aoi22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+	wire int_fwire_2, int_fwire_3;
+
+	not (B1__bar, B1);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B1__bar);
+	not (B0__bar, B0);
+	and (int_fwire_1, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_2, A0__bar, B1__bar);
+	and (int_fwire_3, A0__bar, B0__bar);
+	or (Y, int_fwire_3, int_fwire_2, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		if ((A1 & ~B0 & ~B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		if ((A0 & ~B0 & ~B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & B1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1 & B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & B0))
+			(B1 => Y) = 0;
+		if ((~A0 & ~A1 & B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__buf 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__buf_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_1 (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dff 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dff_l (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	altos_dff_err (xcr_0, delayed_CK, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:D)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_1 (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffr_l (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_1 (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffs 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffs_l (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_1 (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__dffsr 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__dffsr_l (Q, QN, D, RN, SN, CK);
+	output Q, QN;
+	input D, RN, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_RN, delayed_SN, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire int_fwire_s, xcr_0;
+
+	not (int_fwire_s, delayed_SN);
+	not (int_fwire_r, delayed_RN);
+	altos_dff_sr_err (xcr_0, delayed_CK, delayed_D, int_fwire_s, int_fwire_r);
+	altos_dff_sr_0 (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, adacond2;
+	wire adacond3, adacond4, adacond5;
+	wire adacond6, adacond7, adacond8;
+	wire CK__bar, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, RN, SN);
+	and (adacond1, D, SN);
+	and (adacond2, CK, SN);
+	not (CK__bar, CK);
+	and (adacond3, CK__bar, SN);
+	not (D__bar, D);
+	and (adacond4, D__bar, RN);
+	and (adacond5, CK, RN);
+	and (adacond6, CK__bar, RN);
+	and (adacond7, D, RN, SN);
+	and (adacond8, D__bar, RN, SN);
+
+	specify
+		if ((CK & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (Q+:1'b1)) = 0;
+		ifnone (posedge RN => (Q+:1'b1)) = 0;
+		if ((CK & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if ((CK & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & ~SN))
+			(posedge RN => (QN-:1'b1)) = 0;
+		ifnone (posedge RN => (QN-:1'b1)) = 0;
+		if ((CK & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D & ~SN))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		if ((CK & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D & RN))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& adacond0, posedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& adacond0, negedge D &&& adacond0, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge SN &&& CK, posedge RN &&& CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN &&& ~CK, posedge RN &&& ~CK, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$setuphold (posedge SN, posedge RN, 0, 0, notifier,,, delayed_SN, delayed_RN);
+		$recovery (posedge RN &&& adacond1, posedge CK &&& adacond1, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond1, posedge RN &&& adacond1, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$recovery (posedge SN &&& adacond4, posedge CK &&& adacond4, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& adacond4, posedge SN &&& adacond4, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge RN &&& adacond2, 0, 0, notifier);
+		$width (negedge RN &&& adacond3, 0, 0, notifier);
+		$width (negedge SN &&& adacond5, 0, 0, notifier);
+		$width (negedge SN &&& adacond6, 0, 0, notifier);
+		$width (posedge CK &&& adacond7, 0, 0, notifier);
+		$width (negedge CK &&& adacond7, 0, 0, notifier);
+		$width (posedge CK &&& adacond8, 0, 0, notifier);
+		$width (negedge CK &&& adacond8, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__inv 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__inv_l (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__mux2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__mux2_1 (Y, A0, A1, S0);
+	output Y;
+	input A0, A1, S0;
+
+	// Function
+	wire int_fwire_0, int_fwire_1, S0__bar;
+
+	and (int_fwire_0, A1, S0);
+	not (S0__bar, S0);
+	and (int_fwire_1, A0, S0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((~A0 & A1))
+			(S0 => Y) = 0;
+		if ((A0 & ~A1))
+			(S0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nand2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nand2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__nor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__nor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai21_l (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__oai22 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__oai22_l (Y, A0, A1, B0, B1);
+	output Y;
+	input A0, A1, B0, B1;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire B1__bar, int_fwire_0, int_fwire_1;
+
+	not (B1__bar, B1);
+	not (B0__bar, B0);
+	and (int_fwire_0, B0__bar, B1__bar);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, A1__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if ((~A1 & B0 & B1))
+			(A0 => Y) = 0;
+		if ((~A1 & B0 & ~B1))
+			(A0 => Y) = 0;
+		if ((~A1 & ~B0 & B1))
+			(A0 => Y) = 0;
+		ifnone (A0 => Y) = 0;
+		if ((~A0 & B0 & B1))
+			(A1 => Y) = 0;
+		if ((~A0 & B0 & ~B1))
+			(A1 => Y) = 0;
+		if ((~A0 & ~B0 & B1))
+			(A1 => Y) = 0;
+		ifnone (A1 => Y) = 0;
+		if ((A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1 & ~B1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1 & ~B1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+		if ((A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((A0 & ~A1 & ~B0))
+			(B1 => Y) = 0;
+		if ((~A0 & A1 & ~B0))
+			(B1 => Y) = 0;
+		ifnone (B1 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__or2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__or2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif1 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tiehi (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms_ 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tielo (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_1 (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__tnbufi 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__tnbufi_l (Y, A, OE);
+	output Y;
+	input A, OE;
+
+	// Function
+	notif0 (Y, A, OE);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(OE => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xnor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xnor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: sky130_osu_sc_18T_ms__xor2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_18T_ms__xor2_l (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (~B)
+			(A => Y) = 0;
+		if (B)
+			(A => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif