blob: 4038e6cfa1fc303a7dae07b1f00d7167bbce4dab [file] [log] [blame]
// type: DFFN
`timescale 1ns/10ps
`celldefine
module sky130_osu_sc_DFFNXL (Q, QN, D, CK);
output Q, QN;
input D, CK;
reg notifier;
wire delayed_D, delayed_CK;
// Function
wire int_fwire_clk, int_fwire_IQ, int_fwire_IQN;
wire xcr_0;
not (int_fwire_clk, delayed_CK);
altos_dff_err (xcr_0, int_fwire_clk, delayed_D);
altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0);
buf (Q, int_fwire_IQ);
not (int_fwire_IQN, int_fwire_IQ);
buf (QN, int_fwire_IQN);
// Timing
specify
(negedge CK => (Q+:D)) = 0;
(negedge CK => (QN-:D)) = 0;
$setuphold (negedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
$setuphold (negedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
$width (posedge CK &&& D, 0, 0, notifier);
$width (negedge CK &&& D, 0, 0, notifier);
$width (posedge CK &&& ~D, 0, 0, notifier);
$width (negedge CK &&& ~D, 0, 0, notifier);
endspecify
endmodule
`endcelldefine