{ | |
"description": "2-2 counter (half-adder) cell.", | |
"equation": "", | |
"file_prefix": "sky130_osu_sc_ADDFXL", | |
"library": "sky130_osu_sc", | |
"name": "ADDFXL", | |
"parameters": [], | |
"ports": [ | |
[ | |
"signal", | |
"A", | |
"input", | |
"" | |
], | |
[ | |
"signal", | |
"B", | |
"input", | |
"" | |
], | |
[ | |
"signal", | |
"S", | |
"output", | |
"" | |
], | |
[ | |
"signal", | |
"CO", | |
"output", | |
"" | |
], | |
[ | |
"power", | |
"VDD", | |
"input", | |
"supply1" | |
], | |
[ | |
"power", | |
"GND", | |
"input", | |
"supply0" | |
], | |
], | |
"type": "cell", | |
"verilog_name": "sky130_osu_sc_ADDFXL" | |
} |