verilog/s8_osu130_tbufxl.v

// type: TBUF 
`timescale 1ns/10ps
`celldefine
module TBUFXL (Y, A);
	output Y;
	input A;

	// Function
	bufif1 (Y, 1'b1, A);

	// Timing
	specify
		(A => Y) = 0;
		(negedge A => (Y:1)) = 0;
	endspecify
endmodule
`endcelldefine