blob: 6d100ae097ff902cd00dcb8df24a84cdabfee759 [file] [log] [blame]
// type: DFFR
`timescale 1ns/10ps
`celldefine
module sky130_osu_sc_DFFRXL (Q, QN, D, RN, CK);
output Q, QN;
input D, RN, CK;
reg notifier;
wire delayed_D, delayed_CK;
// Function
wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
wire xcr_0;
not (int_fwire_r, RN);
altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
buf (Q, int_fwire_IQ);
not (int_fwire_IQN, int_fwire_IQ);
buf (QN, int_fwire_IQN);
// Timing
// Additional timing wires
wire adacond0, adacond1, D__bar;
// Additional timing gates
and (adacond0, D, RN);
not (D__bar, D);
and (adacond1, D__bar, RN);
specify
if (CK)
(negedge RN => (Q+:1'b0)) = 0;
if ((~CK & D))
(negedge RN => (Q+:1'b0)) = 0;
if ((~CK & ~D))
(negedge RN => (Q+:1'b0)) = 0;
ifnone (negedge RN => (Q+:1'b0)) = 0;
(posedge CK => (Q+:D)) = 0;
if (CK)
(negedge RN => (QN-:1'b0)) = 0;
if ((~CK & D))
(negedge RN => (QN-:1'b0)) = 0;
if ((~CK & ~D))
(negedge RN => (QN-:1'b0)) = 0;
ifnone (negedge RN => (QN-:1'b0)) = 0;
(posedge CK => (QN-:D)) = 0;
$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
$recovery (posedge RN, posedge CK, 0, notifier);
$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
$hold (posedge CK, posedge RN, 0, notifier);
$width (negedge RN &&& CK, 0, 0, notifier);
$width (negedge RN &&& ~CK, 0, 0, notifier);
$width (posedge CK &&& adacond0, 0, 0, notifier);
$width (negedge CK &&& adacond0, 0, 0, notifier);
$width (posedge CK &&& adacond1, 0, 0, notifier);
$width (negedge CK &&& adacond1, 0, 0, notifier);
endspecify
endmodule
`endcelldefine