verilog/sky130_osu_sc_addhx1.v

// type: ADDH 
`timescale 1ns/10ps
`celldefine
module sky130_osu_sc_ADDHX1 (CO, S, A, B);
	output CO, S;
	input A, B;

	// Function
	wire A__bar, B__bar;

	and (CO, A, B);
	not (B__bar, B);
	not (A__bar, A);
	or (S, A__bar, B__bar);

	// Timing
	specify
		(A => CO) = 0;
		(B => CO) = 0;
		ifnone (posedge A => (S+:1'b1)) = 0;
		(A => S) = 0;
		ifnone (posedge B => (S+:1'b1)) = 0;
		(B => S) = 0;
	endspecify
endmodule
`endcelldefine