Repurposing repository to hold the raw design flow used to create, extract, characterize, and test the OSU standard cells.
sky130_osu_18T_hs and sky130_osu_12T_hs are next on the list to be fully implemented, as variants of sky130_osu_18T_ms and sky130_osu_12T_ms.
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..f710d17
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,41 @@
+SHELL:=csh
+
+PROD_PATH:="PATH_TO_PROD_REPO"
+VARIANT:="18T_ms"
+
+.PHONY: all do clean_char clean_design clean char design push_prod
+
+all: do
+
+do: char design
+
+char:
+	-@cd lib && make magic pex VARIANT=${VARIANT}
+	-@cd char && make VARIANT=${VARIANT}
+
+design:
+	@cd flow/synth_snps && make synth VARIANT=${VARIANT}
+	@cd flow/pnr && make all VARIANT=${VARIANT}
+	@cp flow/pnr/final.gds outputs/
+	@cp flow/pnr/final.gds lib/gds/
+
+clean: clean_char clean_design
+
+clean_char:
+	-@cd char && make clean
+
+clean_design:
+	-@cd flow/synth_snps && make clean
+	-@cd flow/pnr && make clean && ./clean_me.csh
+
+push_prod:
+	@mkdir -p $(PROD_PATH)
+	@cp -r Makefile $(PROD_PATH)
+	@cp -r sourceme $(PROD_PATH)
+	@cp -r char $(PROD_PATH)
+	@cp -r lib $(PROD_PATH)
+	@cp -r outputs $(PROD_PATH)
+	@mkdir -p $(PROD_PATH)/flow
+	@cp -r flow/pnr $(PROD_PATH)/flow/pnr
+	@cp -r flow/synth_snps $(PROD_PATH)/flow/synth_snps
+	@rm -rf $(PROD_PATH)/flow/synth_snps/hdl/*
diff --git a/OSU Brand_Primary_021.pdf b/OSU Brand_Primary_021.pdf
deleted file mode 100644
index c3013c8..0000000
--- a/OSU Brand_Primary_021.pdf
+++ /dev/null
Binary files differ
diff --git a/README.rst b/README.rst
index 19b50cc..bed5c2b 100644
--- a/README.rst
+++ b/README.rst
@@ -1,5 +1,44 @@
-:lib:`sky130_osu_sc` - SKY130 Digital Standard Cells (Oklahoma State University Provided)
-=========================================================================================
+# OSU_130_PDK
 
-Initial empty repository creation.
+System on Chip Design Flow including standard cells for SkyWater 130nm process
 
+# VLSI Computer Architecture Research Group
+
+ * James E. Stine, Jr.
+ * Teo Ene
+ * Landon Burleson
+ * Ryan Swann
+ * Ryan Ridley
+ * Brett Mathis
+ * Alex Underwood
+ * S. Ross Thompson
+ * Peter Tikalsky
+ * Brandon Ong
+ * Hunter Lusk
+
+Thanks to the following for help, guidance and support!
+
+ * Tim 'mithro' Ansell \<tansell@google.com\> (Google)
+ * Tim Edwards \<tim@efabless.com\> (eFabless)
+ * Mohamed Kassem \<mkk@efabless.com\> (eFabless)
+
+# License
+
+This repository is released under the Apache 2.0 license. The full license text
+can be found in the [`LICENSE`](LICENSE) file.
+
+```
+Copyright 2020  Board of Regents for the Oklahoma Agricultural and Mechanical Colleges
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License
+```
diff --git a/calibre/README b/calibre/README
new file mode 100644
index 0000000..ff3d308
--- /dev/null
+++ b/calibre/README
@@ -0,0 +1,8 @@
+Running the DRC script:
+
+1. To use the DRC script, source sourceme
+2. Then, the "run_calibreDRC" script can either be executed on one gds layout file or the entire gds catalog found in "../lib/gds" directory.
+
+Example, to run DRC on all gds files use this nomenclature for the command "./run_calibreDRC". 
+Example 2, If a specific cell is desired, run the following nomenclature "./run_calibreDRC cell_name.gds"
+*Note: The gds layout file must be in the "../lib/gds" script in order to work.*
diff --git a/calibre/clean b/calibre/clean
new file mode 100755
index 0000000..d24157f
--- /dev/null
+++ b/calibre/clean
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+rm -rf ./output
+rm -rf ./log
+
diff --git a/calibre/run_calibreDRC b/calibre/run_calibreDRC
new file mode 100755
index 0000000..ce3c73b
--- /dev/null
+++ b/calibre/run_calibreDRC
@@ -0,0 +1,72 @@
+#!/bin/bash
+
+export RUNSET_DIR=./V1.3.0/DRC/Calibre
+export LOG
+export JOB_NAME  
+export JOB_HOME
+
+#Sets the LOG variable and creates the log directory if it doesn't exist.
+if [ ! -d ./log ]; then
+	mkdir log
+	LOG=./log
+else
+	LOG=./log
+fi
+
+#Removes the outputs if the script is run again. Otherwise it creates the output directory and all of its subdirectories
+if [ ! -d "./output/" ]; then 	
+	echo "Making output directory...."
+	mkdir -p output/{summary,results,db,rdb}
+else 
+	echo "Building Directories...." 
+	mkdir -p output/{summary,results,db,rdb}
+fi
+
+
+#If the gds files weren't generated, this if statement extracts all of the gds files from the cells within the lib folder. 
+if [ ! -d "../lib/gds" ]; then
+	cd ../lib/magic
+	./extract_all
+	cd -
+fi 
+
+
+cd ../lib/gds
+JOB_HOME=$PWD 
+cd -
+
+
+if [ ! -z "$1" ]; then
+	export i=$(echo $1 | cut -f 1 -d '.') #i is used as the input variable 
+else 
+	export i="$(basename -s .gds $(ls $JOB_HOME/*.gds))" #i is used s the input variable
+fi
+
+#Loops through the input gds files. If no user input is supplied, all gds files are put through the DRC process. 
+for JOB_NAME in $i ; do 
+
+#Checks to make sure the file supplied exists. If not, then it exits the bash script.
+if [ ! -e $JOB_HOME/$JOB_NAME.gds ]; then 	echo "Did not find '$JOB_HOME/$JOB_NAME.gds'"
+	exit 1
+fi
+
+echo -e "\nexport JOB_HOME='$JOB_HOME'"
+echo -e "export JOB_NAME='$JOB_NAME'"
+echo -e "====================================="
+
+set -x #Turns on debugging
+
+calibre -gui -drc -runset $RUNSET_DIR/s8_drc_runset     -batch > $LOG/s8_drc_runset.log     2>&1
+
+set +x #Turns off debugging
+
+done #End of the loop
+
+echo "Moving output files to ./output"
+mv -v *.results ./output/results/
+mv -v *.summary ./output/summary/
+mv -v *.rdb ./output/rdb/
+mv -v *.db ./output/db/
+mv -v *s8_* ./output/
+
+exit 0
diff --git a/calibre/run_calibreLATCH b/calibre/run_calibreLATCH
new file mode 100755
index 0000000..0215969
--- /dev/null
+++ b/calibre/run_calibreLATCH
@@ -0,0 +1,76 @@
+#!/bin/bash
+
+export RUNSET_DIR=$(cd ./V1.3.0/DRC/Calibre; pwd)
+export PWK_HOME=$(cd ./V1.3.0; pwd)
+export LOG
+export JOB_NAME  
+export JOB_HOME
+
+
+#Sets the LOG variable and creates the log directory if it doesn't exist.
+if [ ! -d ./log ]; then
+	mkdir log
+	LOG=./log
+else
+	LOG=./log
+fi
+
+
+#Removes the outputs if the script is run again. Otherwise it creates the output directory and all of its subdirectories
+if [ ! -d "./output/" ]; then 	
+	echo "Making output directory...."
+	mkdir -p output/{summary,results,db,rdb}
+else 
+	echo "Building directories...."
+	mkdir -p output/{summary,results,db,rdb}
+fi
+
+
+#If the gds files weren't generated, this if statement extracts all of the gds files from the cells within the lib folder. 
+if [ ! -d "../lib/gds" ]; then
+	cd ../lib/magic
+	./extract_all
+	cd -
+fi 
+
+
+cd ../lib/gds
+JOB_HOME=$PWD 
+cd -
+
+
+if [ ! -z "$1" ]; then
+	export i=$(echo $1 | cut -f 1 -d '.') #i is used as the input variable 
+else 
+	export i="$(basename -s .gds $(ls $JOB_HOME/*.gds))" #i is used s the input variable
+fi
+
+
+#Loops through the input gds files. If no user input is supplied, all gds files are put through the DRC process. 
+for JOB_NAME in $i ; do 
+
+#Checks to make sure the file supplied exists. If not, then it exits the bash script.
+if [ ! -e $JOB_HOME/$JOB_NAME.gds ]; then 	echo "Did not find '$JOB_HOME/$JOB_NAME.gds'"
+	exit 1
+fi
+
+echo -e "\nexport JOB_HOME='$JOB_HOME'"
+echo -e "export JOB_NAME='$JOB_NAME'"
+echo -e "====================================="
+
+set -x #Turns on debugging
+
+calibre -gui -drc -runset $RUNSET_DIR/s8_latchup_runset   -batch > $LOG/s8_latch_runset.log   2>&1
+
+set +x #Turns off debugging
+
+done #End of the loop
+
+echo "Moving output files to ./output"
+mv -v *.results ./output/results/
+mv -v *.summary ./output/summary/
+mv -v *.rdb ./output/rdb/
+mv -v *.db ./output/db/
+mv -v *_s8* ./output/
+
+exit 0
diff --git a/calibre/run_calibrePEX b/calibre/run_calibrePEX
new file mode 100755
index 0000000..d393e1b
--- /dev/null
+++ b/calibre/run_calibrePEX
@@ -0,0 +1,79 @@
+#!/bin/bash
+
+export RUNSET_DIR=$(cd ./V1.3.0/PEX/xRC; pwd)
+export PDK_HOME=$(cd ./V1.3.0; pwd)
+export LOG
+export JOB_NAME  
+export JOB_HOME
+
+#Sets the LOG variable and creates the log directory if it doesn't exist.
+if [ ! -d ./log ]; then
+	mkdir log
+	LOG=./log
+else
+	LOG=./log
+fi
+
+#Removes the outputs if the script is run again. Otherwise it creates the output directory and all of its subdirectories
+if [ ! -d "./output/" ]; then 	
+	echo "Making output directory...."
+	mkdir -p output/{report,ext,pex,spice,pxi}
+else 
+	echo "Building Directories...."
+	mkdir -p output/{report,ext,pex,spice,pxi}
+fi
+
+
+#If the gds files weren't generated, this if statement extracts all of the gds files from the cells within the lib folder. 
+if [ ! -d "../lib/gds" ]; then
+	cd ../lib/magic
+	./extract_all
+	cd -
+fi 
+
+
+cd ../lib/gds
+JOB_HOME=$PWD 
+cd -
+
+
+if [ ! -z "$1" ]; then
+	export i=$(echo $1 | cut -f 1 -d '.') #i is used as the input variable 
+else 
+	export i="$(basename -s .gds $(ls $JOB_HOME/*.gds))" #i is used as the input variable
+fi
+
+#Loops through the input gds files. If no user input is supplied, all gds files are put through the DRC process. 
+for JOB_NAME in $i ; do 
+
+#Checks to make sure the file supplied exists. If not, then it exits the bash script.
+if [ ! -e $JOB_HOME/$JOB_NAME.gds ]; then 	echo "Did not find '$JOB_HOME/$JOB_NAME.gds'"
+	exit 1
+fi
+
+echo -e "\nexport JOB_HOME='$JOB_HOME'"
+echo -e "export JOB_NAME='$JOB_NAME'"
+echo -e "====================================="
+
+set -x #Turns on debugging
+
+echo $PDK_HOME
+
+calibre -gui -pex -runset $RUNSET_DIR/s8_xRC_runset     -batch > $LOG/s8_pex_runset.log     2>&1
+
+set +x #Turns off debugging
+
+done #End of the loop
+
+echo "Moving output files to ./output"
+mv -v *.report ./output/report/
+mv -v *.pex ./output/pex/
+mv -v *.spice ./output/spice/
+mv -v *.pxi ./output/pxi/
+mv -v *.ext ./output/ext/
+mv -v *erc* ./output/
+mv -v  _xrcControlFile_s8_ ./output/
+mv -v svdb/ ./output/
+mv -v *bat* ./output/
+
+exit 0
diff --git a/calibre/sourceme b/calibre/sourceme
new file mode 100644
index 0000000..ff481d5
--- /dev/null
+++ b/calibre/sourceme
@@ -0,0 +1,2 @@
+source ../scripts/mentor_x64.cshrc
+source ../scripts/magic.cshrc
diff --git a/cdl/ADDFX1.cdl b/cdl/ADDFX1.cdl
deleted file mode 100644
index 1f1d673..0000000
--- a/cdl/ADDFX1.cdl
+++ /dev/null
@@ -1,211 +0,0 @@
-* SPICE3 file created from ADDFX1.ext - technology: EFS8A
-
-.subckt ADDFX1 CO A CI B S
-M1000 gnd A.t0 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.160556p pd=1.43222u as=0.181667p ps=1.69667u
-M1001 CO.t0 a_247_115# gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.160556p ps=1.43222u
-M1002 a_835_725# CI.t0 a_749_115# vdd pshort w=3u l=0.15u
-+  ad=0.39p pd=3.26u as=0.42p ps=3.28u
-M1003 a_333_115# B.t0 a_247_115# gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.14p ps=1.28u
-M1004 gnd B.t1 a_491_115# gnd nshort w=1u l=0.15u
-+  ad=0.160556p pd=1.43222u as=0.14p ps=1.28u
-M1005 a_247_115# CI.t1 a_n8_725.t0 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1006 a_491_725.t1 A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.481667p ps=3.65444u
-M1007 S.t1 a_749_115# vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.481667p ps=3.65444u
-M1008 a_835_115# CI.t2 a_749_115# gnd nshort w=1u l=0.15u
-+  ad=0.13p pd=1.26u as=0.14p ps=1.28u
-M1009 a_247_115# CI.t3 a_n8_115.t2 gnd nshort w=1u l=0.15u
-+  ad=0.42p pd=3.28u as=0.42p ps=3.28u
-M1010 vdd A.t2 a_917_725.t0 vdd pshort w=3u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1011 a_491_115# A.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.481667p pd=3.65444u as=0.39p ps=3.26u
-M1012 a_n8_725.t2 B.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.14p pd=1.28u as=0.160556p ps=1.43222u
-M1013 S.t0 a_749_115# gnd gnd nshort w=1u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.481667p ps=3.65444u
-M1014 vdd A.t4 a_333_725.t0 vdd pshort w=3u l=0.15u
-+  ad=0.265p pd=2.53u as=0.160556p ps=1.43222u
-M1015 a_749_115# a_247_115# a_491_115# gnd nshort w=1u l=0.15u
-+  ad=0.481667p pd=3.65444u as=0.315p ps=3.21u
-M1016 a_491_725.t0 CI.t4 vdd vdd pshort w=3u l=0.15u
-+  ad=0.14p pd=1.28u as=0.14p ps=1.28u
-M1017 gnd A.t5 a_917_115# gnd nshort w=1u l=0.15u
-+  ad=0.42p pd=3.28u as=0.481667p ps=3.65444u
-M1018 a_n8_115.t0 B.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.160556p pd=1.43222u as=0.13p ps=1.26u
-M1019 gnd A.t6 a_333_115# gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.160556p ps=1.43222u
-M1020 CO.t1 a_247_115# vdd vdd pshort w=3u l=0.15u
-+  ad=0.160556p pd=1.43222u as=0.105p ps=1.21u
-M1021 a_491_115# CI.t5 gnd gnd nshort w=1u l=0.15u
-+  ad=0.39p pd=3.26u as=0.39p ps=3.26u
-M1022 vdd B.t6 a_491_725.t3 vdd pshort w=3u l=0.15u
-+  ad=0.481667p pd=3.65444u as=0.545p ps=4.36333u
-M1023 a_917_115# B.t7 a_835_115# gnd nshort w=1u l=0.15u
-+  ad=0.795p pd=6.53u as=0.481667p ps=3.65444u
-C0 a_247_115# m1_n35_0# 0.059210fF
-C1 vdd a_247_115# 0.000975fF
-C2 A B 3.068600fF
-C3 m1_n35_1379# S 0.029254fF
-C4 m1_n35_1379# m1_n35_0# 0.241432fF
-C5 S CO 0.848968fF
-C6 m1_n35_0# CO 0.083169fF
-C7 a_749_115# S 2.331530fF
-C8 a_247_115# A 0.547304fF
-C9 a_749_115# m1_n35_0# 0.120102fF
-C10 vdd CO 0.001293fF
-C11 vdd a_749_115# 0.000974fF
-C12 CI S 0.023978fF
-C13 m1_n35_0# CI 0.122809fF
-C14 a_247_115# B 0.761193fF
-C15 a_749_115# A 0.429055fF
-C16 m1_n35_0# S 0.083169fF
-C17 A CI 1.338590fF
-C18 a_749_115# B 0.284826fF
-C19 vdd S 0.001086fF
-C20 a_247_115# m1_n35_1379# 0.029642fF
-C21 a_247_115# CO 0.143821fF
-C22 a_247_115# a_749_115# 0.810829fF
-C23 B CI 2.962560fF
-C24 m1_n35_1379# CO 0.029254fF
-C25 a_247_115# CI 1.554230fF
-C26 a_749_115# m1_n35_1379# 0.053451fF
-C27 a_749_115# CO 1.236090fF
-C28 m1_n35_1379# CI 0.059259fF
-C29 CI CO 0.017469fF
-C30 a_247_115# S 0.148248fF
-C31 a_749_115# CI 0.304585fF
-R0 A.t1 A.t4 1150.37
-R1 A.n2 A.t2 937.95
-R2 A.n4 A.t7 824.755
-R3 A.n1 A.t1 803.331
-R4 A.n0 A.t6 475.572
-R5 A.n4 A.t0 429.514
-R6 A.n0 A.t3 413.447
-R7 A.n2 A.t5 300.981
-R8 A.n3 A.n2 194.805
-R9 A.n5 A.n3 160.752
-R10 A.n3 A.n1 27.147
-R11 A.n1 A.n0 16.066
-R12 A A.n5 10.764
-R13 A.n5 A.n4 7.5
-R14 a_n8_115.n0 a_n8_115.t1 131.551
-R15 a_n8_115.n0 a_n8_115.t2 16.8
-R16 a_n8_115.t0 a_n8_115.n0 16.8
-R17 CO CO.t1 762.097
-R18 CO CO.t0 230.961
-R19 CI.n3 CI.t1 824.755
-R20 CI.n1 CI.t4 824.755
-R21 CI.n0 CI.t0 824.755
-R22 CI.n3 CI.t3 429.514
-R23 CI.n1 CI.t5 429.514
-R24 CI.n0 CI.t2 429.514
-R25 CI.n4 CI.n2 242.265
-R26 CI CI.n4 87.193
-R27 CI.n2 CI.n0 68.5
-R28 CI.n2 CI.n1 7.5
-R29 CI.n4 CI.n3 7.5
-R30 B.n1 B.t4 696.221
-R31 B.n0 B.t5 696.221
-R32 B.n5 B.t3 686.581
-R33 B.n2 B.t1 686.581
-R34 B.n5 B.t2 567.688
-R35 B.n2 B.t6 567.688
-R36 B.n1 B.t7 558.047
-R37 B.n0 B.t0 558.047
-R38 B.n3 B.n1 149.849
-R39 B.n4 B.n3 82.529
-R40 B.n6 B.n4 66.741
-R41 B B.n6 39.47
-R42 B.n4 B.n0 27.1
-R43 B.n3 B.n2 7.5
-R44 B.n6 B.n5 7.5
-R45 a_n8_725.n1 a_n8_725.n0 255.992
-R46 a_n8_725.t0 a_n8_725.n1 9.193
-R47 a_n8_725.n1 a_n8_725.t2 9.193
-R48 a_491_725.n9 a_491_725.n8 671.93
-R49 a_491_725.n12 a_491_725.n4 118.017
-R50 a_491_725.n9 a_491_725.n7 118.017
-R51 a_491_725.n13 a_491_725.n2 105.817
-R52 a_491_725.n11 a_491_725.n10 105.817
-R53 a_491_725.n11 a_491_725.n9 84.4
-R54 a_491_725.n13 a_491_725.n12 66
-R55 a_491_725.n12 a_491_725.n11 34.4
-R56 a_491_725.n14 a_491_725.n13 14
-R57 a_491_725.n7 a_491_725.n5 13.133
-R58 a_491_725.n2 a_491_725.n0 9.193
-R59 a_491_725.n2 a_491_725.n1 9.193
-R60 a_491_725.n4 a_491_725.t1 9.193
-R61 a_491_725.n4 a_491_725.n3 9.193
-R62 a_491_725.n7 a_491_725.n6 9.193
-R63 a_491_725.n10 a_491_725.t0 9.193
-R64 a_491_725.n10 a_491_725.t3 9.193
-R65 S S.t1 761.936
-R66 S S.t0 231.123
-R67 a_917_725.n12 a_917_725.n9 671.93
-R68 a_917_725.n14 a_917_725.n5 118.017
-R69 a_917_725.n12 a_917_725.n11 118.017
-R70 a_917_725.n15 a_917_725.n2 105.817
-R71 a_917_725.n13 a_917_725.n8 105.817
-R72 a_917_725.n13 a_917_725.n12 84.4
-R73 a_917_725.n15 a_917_725.n14 66
-R74 a_917_725.n14 a_917_725.n13 34.4
-R75 a_917_725.n16 a_917_725.n15 14
-R76 a_917_725.n11 a_917_725.n10 13.133
-R77 a_917_725.n2 a_917_725.n0 9.193
-R78 a_917_725.n2 a_917_725.n1 9.193
-R79 a_917_725.n5 a_917_725.n3 9.193
-R80 a_917_725.n5 a_917_725.n4 9.193
-R81 a_917_725.n8 a_917_725.n6 9.193
-R82 a_917_725.n8 a_917_725.n7 9.193
-R83 a_917_725.n11 a_917_725.t0 9.193
-R84 a_333_725.n10 a_333_725.n9 671.93
-R85 a_333_725.n10 a_333_725.n8 118.017
-R86 a_333_725.n14 a_333_725.n13 118.017
-R87 a_333_725.n15 a_333_725.n2 105.817
-R88 a_333_725.n11 a_333_725.n5 105.817
-R89 a_333_725.n11 a_333_725.n10 84.4
-R90 a_333_725.n15 a_333_725.n14 66
-R91 a_333_725.n14 a_333_725.n11 34.4
-R92 a_333_725.n16 a_333_725.n15 14
-R93 a_333_725.n8 a_333_725.n6 13.133
-R94 a_333_725.n2 a_333_725.n0 9.193
-R95 a_333_725.n2 a_333_725.n1 9.193
-R96 a_333_725.n5 a_333_725.n3 9.193
-R97 a_333_725.n5 a_333_725.n4 9.193
-R98 a_333_725.n8 a_333_725.n7 9.193
-R99 a_333_725.n13 a_333_725.n12 9.193
-R100 a_333_725.n13 a_333_725.t0 9.193
-C32 a_749_115# gnd 0.209560fF
-C33 a_247_115# gnd 0.257493fF
-C34 vdd gnd 3.292320fF
-C35 S.t1 gnd 1.061540fF
-C36 S.t0 gnd 0.434515fF
-C37 B.t0 gnd 0.279017fF
-C38 B.t7 gnd 0.279017fF
-C39 B.t6 gnd 0.519059fF
-C40 B.t1 gnd 0.324949fF
-C41 B.t2 gnd 0.521367fF
-C42 B.t3 gnd 0.324949fF
-C43 CI.t0 gnd 0.668692fF
-C44 CI.t2 gnd 0.255243fF
-C45 CI.t4 gnd 0.668692fF
-C46 CI.t5 gnd 0.255243fF
-C47 CI.t1 gnd 0.668692fF
-C48 CI.t3 gnd 0.255243fF
-C49 CO.t1 gnd 0.725604fF
-C50 CO.t0 gnd 0.296567fF
-C51 A.t4 gnd 0.578637fF
-C52 A.t1 gnd 0.566972fF
-C53 A.t6 gnd 0.194413fF
-C54 A.t3 gnd 0.175262fF
-C55 A.t2 gnd 0.513205fF
-C56 A.t5 gnd 0.145488fF
-C57 A.t0 gnd 0.179829fF
-.ends
diff --git a/cdl/ADDFXL.cdl b/cdl/ADDFXL.cdl
deleted file mode 100644
index f1e9e66..0000000
--- a/cdl/ADDFXL.cdl
+++ /dev/null
@@ -1,172 +0,0 @@
-* SPICE3 file created from ADDFXL.ext - technology: EFS8A
-
-.subckt ADDFXL CO S A CI B
-M1000 gnd A.t0 a_n8_115.t2 gnd nshort w=1u l=0.15u
-+  ad=0.159734p pd=1.46981u as=0.181667p ps=1.69667u
-M1001 CO.t0 a_247_115# gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.10223p ps=0.940676u
-M1002 a_835_725# CI.t0 a_749_115# vdd pshort w=3u l=0.15u
-+  ad=0.39p pd=3.26u as=0.42p ps=3.28u
-M1003 a_333_115# B.t0 a_247_115# gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.14p ps=1.28u
-M1004 gnd B.t1 a_491_115# gnd nshort w=1u l=0.15u
-+  ad=0.159734p pd=1.46981u as=0.14p ps=1.28u
-M1005 a_247_115# CI.t1 a_n8_725.t0 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1006 a_491_725# A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.478519p ps=3.72716u
-M1007 S.t1 a_749_115# vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.263185p ps=2.04994u
-M1008 a_835_115# CI.t2 a_749_115# gnd nshort w=1u l=0.15u
-+  ad=0.13p pd=1.26u as=0.14p ps=1.28u
-M1009 a_749_115# a_247_115# a_491_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.42p ps=3.28u
-M1010 a_247_115# CI.t3 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1011 vdd A.t2 a_917_725# vdd pshort w=3u l=0.15u
-+  ad=0.478519p pd=3.72716u as=0.39p ps=3.26u
-M1012 a_491_115# A.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.159734p ps=1.46981u
-M1013 a_n8_725.t2 B.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.478519p ps=3.72716u
-M1014 S.t0 a_749_115# gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.10223p ps=0.940676u
-M1015 vdd A.t4 a_333_725# vdd pshort w=3u l=0.15u
-+  ad=0.478519p pd=3.72716u as=0.315p ps=3.21u
-M1016 a_749_115# a_247_115# a_491_115# gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.14p ps=1.28u
-M1017 a_491_725# CI.t4 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.478519p ps=3.72716u
-M1018 gnd A.t5 a_917_115# gnd nshort w=1u l=0.15u
-+  ad=0.159734p pd=1.46981u as=0.13p ps=1.26u
-M1019 a_n8_115.t0 B.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.159734p ps=1.46981u
-M1020 gnd A.t6 a_333_115# gnd nshort w=1u l=0.15u
-+  ad=0.159734p pd=1.46981u as=0.105p ps=1.21u
-M1021 a_917_725# B.t4 a_835_725# vdd pshort w=3u l=0.15u
-+  ad=0.39p pd=3.26u as=0.39p ps=3.26u
-M1022 vdd A.t7 a_n8_725.t1 vdd pshort w=3u l=0.15u
-+  ad=0.478519p pd=3.72716u as=0.545p ps=4.36333u
-M1023 CO.t1 a_247_115# vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.263185p ps=2.04994u
-M1024 a_491_115# CI.t5 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.159734p ps=1.46981u
-M1025 a_333_725# B.t5 a_247_115# vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.28u
-M1026 vdd B.t6 a_491_725# vdd pshort w=3u l=0.15u
-+  ad=0.478519p pd=3.72716u as=0.42p ps=3.28u
-M1027 a_917_115# B.t7 a_835_115# gnd nshort w=1u l=0.15u
-+  ad=0.13p pd=1.26u as=0.13p ps=1.26u
-C0 CI S 0.023458fF
-C1 m1_n35_1379# S 0.029254fF
-C2 m1_n35_0# CI 0.122809fF
-C3 A B 2.930410fF
-C4 m1_n35_1379# m1_n35_0# 0.241432fF
-C5 a_749_115# S 2.679750fF
-C6 a_749_115# m1_n35_0# 0.120102fF
-C7 CI CO 0.017469fF
-C8 m1_n35_0# S 0.083169fF
-C9 m1_n35_1379# CO 0.029254fF
-C10 A CI 1.316500fF
-C11 a_749_115# CO 1.300610fF
-C12 a_247_115# B 0.758314fF
-C13 a_749_115# A 0.628610fF
-C14 vdd a_749_115# 0.000974fF
-C15 S CO 0.902156fF
-C16 m1_n35_0# CO 0.083169fF
-C17 A S 0.005456fF
-C18 a_247_115# CI 1.552100fF
-C19 vdd S 0.002411fF
-C20 a_247_115# m1_n35_1379# 0.029642fF
-C21 a_247_115# a_749_115# 1.050010fF
-C22 B CI 2.962560fF
-C23 a_247_115# S 0.146258fF
-C24 vdd CO 0.003532fF
-C25 a_749_115# B 0.252381fF
-C26 a_247_115# m1_n35_0# 0.059210fF
-C27 m1_n35_1379# CI 0.059259fF
-C28 a_247_115# CO 0.175861fF
-C29 a_749_115# CI 0.285392fF
-C30 a_247_115# A 0.583907fF
-C31 a_749_115# m1_n35_1379# 0.053451fF
-C32 vdd a_247_115# 0.000975fF
-R0 A.t1 A.t4 1150.37
-R1 A.n2 A.t2 994.526
-R2 A.n4 A.t7 824.755
-R3 A.n1 A.t1 803.331
-R4 A.n2 A.t5 480.392
-R5 A.n0 A.t6 475.572
-R6 A.n4 A.t0 429.514
-R7 A.n0 A.t3 413.447
-R8 A.n3 A.n2 312.486
-R9 A.n5 A.n3 160.752
-R10 A.n3 A.n1 27.147
-R11 A.n1 A.n0 16.066
-R12 A A.n5 10.764
-R13 A.n5 A.n4 7.5
-R14 a_n8_115.n0 a_n8_115.t2 131.551
-R15 a_n8_115.n0 a_n8_115.t1 16.8
-R16 a_n8_115.t0 a_n8_115.n0 16.8
-R17 CO CO.t1 228.699
-R18 CO CO.t0 144.004
-R19 CI.n3 CI.t1 824.755
-R20 CI.n1 CI.t4 824.755
-R21 CI.n0 CI.t0 824.755
-R22 CI.n3 CI.t3 429.514
-R23 CI.n1 CI.t5 429.514
-R24 CI.n0 CI.t2 429.514
-R25 CI.n4 CI.n2 242.265
-R26 CI CI.n4 87.193
-R27 CI.n2 CI.n0 68.5
-R28 CI.n2 CI.n1 7.5
-R29 CI.n4 CI.n3 7.5
-R30 B.n1 B.t4 696.221
-R31 B.n0 B.t5 696.221
-R32 B.n5 B.t3 686.581
-R33 B.n2 B.t1 686.581
-R34 B.n5 B.t2 567.688
-R35 B.n2 B.t6 567.688
-R36 B.n1 B.t7 558.047
-R37 B.n0 B.t0 558.047
-R38 B.n3 B.n1 149.849
-R39 B.n4 B.n3 82.529
-R40 B.n6 B.n4 66.741
-R41 B B.n6 39.47
-R42 B.n4 B.n0 27.1
-R43 B.n3 B.n2 7.5
-R44 B.n6 B.n5 7.5
-R45 a_n8_725.n0 a_n8_725.t1 255.992
-R46 a_n8_725.t0 a_n8_725.n0 9.193
-R47 a_n8_725.n0 a_n8_725.t2 9.193
-R48 S S.t1 228.538
-R49 S S.t0 144.166
-C33 a_749_115# gnd 0.283111fF
-C34 a_247_115# gnd 0.328373fF
-C35 vdd gnd 3.292320fF
-C36 S.t1 gnd 1.605390fF
-C37 S.t0 gnd 0.535417fF
-C38 B.t5 gnd 0.570833fF
-C39 B.t0 gnd 0.281898fF
-C40 B.t4 gnd 0.570833fF
-C41 B.t7 gnd 0.281898fF
-C42 B.t6 gnd 0.524420fF
-C43 B.t1 gnd 0.328305fF
-C44 B.t2 gnd 0.526752fF
-C45 B.t3 gnd 0.328305fF
-C46 CI.t0 gnd 0.692327fF
-C47 CI.t2 gnd 0.264265fF
-C48 CI.t4 gnd 0.692327fF
-C49 CI.t5 gnd 0.264265fF
-C50 CI.t1 gnd 0.692327fF
-C51 CI.t3 gnd 0.264265fF
-C52 CO.t1 gnd 1.044440fF
-C53 CO.t0 gnd 0.347512fF
-C54 A.t4 gnd 0.589698fF
-C55 A.t1 gnd 0.577811fF
-C56 A.t6 gnd 0.198129fF
-C57 A.t3 gnd 0.178613fF
-C58 A.t2 gnd 0.541484fF
-C59 A.t5 gnd 0.201167fF
-C60 A.t7 gnd 0.484336fF
-C61 A.t0 gnd 0.183267fF
-.ends
diff --git a/cdl/ADDHX1.cdl b/cdl/ADDHX1.cdl
deleted file mode 100644
index a61875c..0000000
--- a/cdl/ADDHX1.cdl
+++ /dev/null
@@ -1,99 +0,0 @@
-* SPICE3 file created from ADDHX1.ext - technology: EFS8A
-
-.subckt ADDHX1 B A S CO
-M1000 gnd a_8_624.t4 S.t0 gnd nshort w=1u l=0.15u
-+  ad=0.8175p pd=6.545u as=0.315p ps=3.21u
-M1001 a_535_115# A.t1 a_8_624.t2 gnd nshort w=1u l=0.15u
-+  ad=0.17p pd=1.34u as=0.265p ps=2.53u
-M1002 vdd A.t2 a_173_725.t1 vdd pshort w=3u l=0.15u
-+  ad=0.17p pd=1.34u as=0.265p ps=2.53u
-M1003 a_633_725.t0 B.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.48p ps=3.32u
-M1004 a_8_624.t1 B.t1 a_535_115# gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1005 a_173_725.t0 B.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.48p pd=3.32u as=0.42p ps=3.28u
-M1006 vdd a_8_624.t5 S.t1 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.48p ps=3.32u
-M1007 a_173_115# B.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.105p ps=1.21u
-C0 a_535_115# A 0.008320fF
-C1 B A 1.375520fF
-C2 a_535_115# m1_n35_0# 0.154952fF
-C3 a_535_115# S 0.025070fF
-C4 vdd S 0.001278fF
-C5 m1_n35_1379# m1_n35_0# 0.143351fF
-C6 m1_n35_1379# S 0.030096fF
-C7 a_535_115# CO 0.090850fF
-C8 vdd CO 0.001139fF
-C9 m1_n35_1379# CO 0.030096fF
-C10 m1_n35_0# S 0.046763fF
-C11 m1_n35_0# CO 0.046763fF
-C12 a_535_115# B 0.008320fF
-C13 S CO 0.311647fF
-C14 a_535_115# m1_n35_1379# 0.055183fF
-R0 A.n1 A.t2 696.221
-R1 A.n0 A.t1 686.581
-R2 A.n0 A.t0 567.688
-R3 A.n1 A.t3 558.047
-R4 A A.n0 189.062
-R5 A A.n1 7.5
-R6 a_633_725.n8 a_633_725.n7 175.617
-R7 a_633_725.n9 a_633_725.n2 118.017
-R8 a_633_725.n8 a_633_725.n5 118.017
-R9 a_633_725.n9 a_633_725.n8 34.4
-R10 a_633_725.n10 a_633_725.n9 16.4
-R11 a_633_725.n2 a_633_725.n1 13.133
-R12 a_633_725.n5 a_633_725.n3 13.133
-R13 a_633_725.n2 a_633_725.n0 9.193
-R14 a_633_725.n5 a_633_725.n4 9.193
-R15 a_633_725.n7 a_633_725.t0 9.193
-R16 a_633_725.n7 a_633_725.n6 9.193
-R17 a_8_624.n2 a_8_624.t4 680.866
-R18 a_8_624.n2 a_8_624.t5 561.973
-R19 a_8_624.n3 a_8_624.n2 211.258
-R20 a_8_624.n1 a_8_624.n0 191.507
-R21 a_8_624.n1 a_8_624.t3 120.329
-R22 a_8_624.t0 a_8_624.n3 70.702
-R23 a_8_624.n3 a_8_624.n1 49.905
-R24 a_8_624.n0 a_8_624.t2 16.8
-R25 a_8_624.n0 a_8_624.t1 16.8
-R26 S S.t0 179.467
-R27 S S.t1 120.864
-R28 a_173_725.n5 a_173_725.n4 175.617
-R29 a_173_725.n5 a_173_725.n1 118.017
-R30 a_173_725.n8 a_173_725.n7 118.017
-R31 a_173_725.n8 a_173_725.n5 34.4
-R32 a_173_725.n9 a_173_725.n8 16.4
-R33 a_173_725.n1 a_173_725.n0 13.133
-R34 a_173_725.n7 a_173_725.n6 13.133
-R35 a_173_725.n1 a_173_725.t1 9.193
-R36 a_173_725.n4 a_173_725.n2 9.193
-R37 a_173_725.n4 a_173_725.n3 9.193
-R38 a_173_725.n7 a_173_725.t0 9.193
-R39 CO CO.t0 179.406
-R40 CO CO.t1 120.566
-R41 B.n1 B.t2 824.755
-R42 B.n0 B.t0 696.221
-R43 B.n0 B.t1 558.047
-R44 B.n1 B.t3 429.514
-R45 B B.n0 189.063
-R46 B B.n1 7.5
-C15 a_535_115# gnd 0.016740fF
-C16 vdd gnd 1.928880fF
-C17 B.t0 gnd 0.428815fF
-C18 B.t1 gnd 0.217010fF
-C19 B.t2 gnd 0.463593fF
-C20 B.t3 gnd 0.182397fF
-C21 a_173_725.t1 gnd 0.136589fF
-C22 a_173_725.t0 gnd 0.136589fF
-C23 S.t1 gnd 0.587702fF
-C24 S.t0 gnd 0.234423fF
-C25 a_8_624.t2 gnd 0.037599fF
-C26 a_8_624.t1 gnd 0.037599fF
-C27 a_8_624.t5 gnd 0.181333fF
-C28 a_8_624.t4 gnd 0.115582fF
-C29 a_633_725.t0 gnd 0.000715fF
-C30 A.t1 gnd 0.226769fF
-C31 A.t2 gnd 0.386296fF
-.ends
diff --git a/cdl/ADDHXL.cdl b/cdl/ADDHXL.cdl
deleted file mode 100644
index 75e5d9e..0000000
--- a/cdl/ADDHXL.cdl
+++ /dev/null
@@ -1,101 +0,0 @@
-* SPICE3 file created from ADDHXL.ext - technology: EFS8A
-
-.subckt ADDHXL B A S CO
-M1000 a_8_704.t3 A.t0 a_633_725# vdd pshort w=3u l=0.15u
-+  ad=0.8175p pd=6.545u as=0.315p ps=3.21u
-M1001 gnd a_8_704.t4 S.t0 gnd nshort w=0.64u l=0.15u
-+  ad=0.122146p pd=1.04585u as=0.1696p ps=1.81u
-M1002 gnd a_173_725# CO.t0 gnd nshort w=0.64u l=0.15u
-+  ad=0.122146p pd=1.04585u as=0.1696p ps=1.81u
-M1003 CO.t1 a_173_725# vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.28875p ps=2.14824u
-M1004 a_535_115# A.t1 a_8_704.t2 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1005 vdd A.t2 a_173_725# vdd pshort w=3u l=0.15u
-+  ad=0.525p pd=3.90588u as=0.42p ps=3.28u
-M1006 a_633_725# B.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.525p ps=3.90588u
-M1007 a_173_725# A.t3 a_173_115# gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.105p ps=1.21u
-M1008 a_8_704.t1 B.t1 a_535_115# gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1009 a_173_725# B.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.525p ps=3.90588u
-M1010 vdd a_173_725# a_8_704.t0 vdd pshort w=3u l=0.15u
-+  ad=0.525p pd=3.90588u as=0.8175p ps=6.545u
-M1011 vdd a_8_704.t5 S.t1 vdd pshort w=1.65u l=0.15u
-+  ad=0.28875p pd=2.14824u as=0.43725p ps=3.83u
-M1012 a_173_115# B.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.190854p ps=1.63415u
-M1013 a_535_115# a_173_725# gnd gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.190854p ps=1.63415u
-C0 a_535_115# A 0.008320fF
-C1 CO a_173_725# 1.256810fF
-C2 m1_n35_1379# a_173_725# 0.057254fF
-C3 vdd a_173_725# 0.000975fF
-C4 a_535_115# S 0.025070fF
-C5 m1_n35_0# a_173_725# 0.079894fF
-C6 S CO 0.311647fF
-C7 a_535_115# CO 0.090850fF
-C8 m1_n35_1379# S 0.030096fF
-C9 S vdd 0.002694fF
-C10 a_535_115# m1_n35_1379# 0.055183fF
-C11 B a_173_725# 0.672510fF
-C12 B A 1.375520fF
-C13 m1_n35_1379# CO 0.030096fF
-C14 m1_n35_0# S 0.046763fF
-C15 CO vdd 0.003394fF
-C16 A a_173_725# 0.688393fF
-C17 a_535_115# m1_n35_0# 0.154952fF
-C18 m1_n35_0# CO 0.046763fF
-C19 m1_n35_1379# m1_n35_0# 0.143351fF
-C20 a_535_115# B 0.008320fF
-C21 S a_173_725# 0.579602fF
-C22 a_535_115# a_173_725# 0.055817fF
-R0 A.n1 A.t2 696.221
-R1 A.n0 A.t1 686.581
-R2 A.n0 A.t0 567.688
-R3 A.n1 A.t3 558.047
-R4 A A.n0 189.062
-R5 A A.n1 7.5
-R6 a_8_704.n2 a_8_704.t4 867.239
-R7 a_8_704.n2 a_8_704.t5 650.34
-R8 a_8_704.n3 a_8_704.n2 194.753
-R9 a_8_704.n1 a_8_704.n0 191.507
-R10 a_8_704.n1 a_8_704.t3 120.329
-R11 a_8_704.t0 a_8_704.n3 70.702
-R12 a_8_704.n3 a_8_704.n1 49.905
-R13 a_8_704.n0 a_8_704.t2 16.8
-R14 a_8_704.n0 a_8_704.t1 16.8
-R15 S S.t1 228.769
-R16 S S.t0 201.117
-R17 CO CO.t1 228.471
-R18 CO CO.t0 201.056
-R19 B.n1 B.t2 824.755
-R20 B.n0 B.t0 696.221
-R21 B.n0 B.t1 558.047
-R22 B.n1 B.t3 429.514
-R23 B B.n0 189.063
-R24 B B.n1 7.5
-C23 a_535_115# gnd 0.016740fF
-C24 a_173_725# gnd 0.178832fF
-C25 vdd gnd 1.928880fF
-C26 B.t0 gnd 0.428815fF
-C27 B.t1 gnd 0.217010fF
-C28 B.t2 gnd 0.463593fF
-C29 B.t3 gnd 0.182397fF
-C30 CO.t1 gnd 0.952274fF
-C31 CO.t0 gnd 0.429649fF
-C32 S.t1 gnd 0.491342fF
-C33 S.t0 gnd 0.221053fF
-C34 a_8_704.t2 gnd 0.040167fF
-C35 a_8_704.t1 gnd 0.040167fF
-C36 a_8_704.t3 gnd 0.648042fF
-C37 a_8_704.t5 gnd 0.147383fF
-C38 a_8_704.t4 gnd 0.132850fF
-C39 a_8_704.t0 gnd 0.562209fF
-C40 A.t0 gnd 0.355015fF
-C41 A.t1 gnd 0.226769fF
-C42 A.t2 gnd 0.386296fF
-C43 A.t3 gnd 0.195492fF
-.ends
diff --git a/cdl/AND2X1.cdl b/cdl/AND2X1.cdl
deleted file mode 100644
index 7f2b53b..0000000
--- a/cdl/AND2X1.cdl
+++ /dev/null
@@ -1,48 +0,0 @@
-* SPICE3 file created from AND2X1.ext - technology: EFS8A
-
-.subckt AND2X1 A B Y
-M1000 a_75_115# A.t0 a_n8_115.t0 gnd nshort w=2u l=0.15u
-+  ad=0.21p pd=2.21u as=0.53p ps=4.53u
-M1001 Y.t0 a_n8_115.t3 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.545p ps=4.36333u
-M1002 Y.t1 a_n8_115.t4 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.201667p ps=1.56u
-M1003 vdd B.t0 a_n8_115.t2 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-M1004 gnd B.t1 a_75_115# gnd nshort w=2u l=0.15u
-+  ad=0.403333p pd=3.12u as=0.21p ps=2.21u
-M1005 a_n8_115.t1 A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-C0 A B 0.340125fF
-C1 m1_n35_0# Y 0.047670fF
-C2 Y vdd 0.001338fF
-C3 m1_n35_0# m1_n35_1379# 0.064131fF
-C4 Y m1_n35_1379# 0.026952fF
-R0 A.n0 A.t1 567.688
-R1 A.n0 A.t0 525.914
-R2 A A.n0 8.054
-R3 a_n8_115.n0 a_n8_115.t3 858.741
-R4 a_n8_115.n0 a_n8_115.t4 423.799
-R5 a_n8_115.n2 a_n8_115.n1 241.858
-R6 a_n8_115.n1 a_n8_115.n0 117.249
-R7 a_n8_115.n1 a_n8_115.t0 53.043
-R8 a_n8_115.n2 a_n8_115.t2 9.193
-R9 a_n8_115.t1 a_n8_115.n2 9.193
-R10 Y Y.t0 200.833
-R11 Y Y.t1 179.134
-R12 B.n0 B.t0 696.221
-R13 B.n0 B.t1 397.381
-R14 B B.n0 7.684
-C5 vdd gnd 0.873240fF
-C6 B.t0 gnd 0.277045fF
-C7 B.t1 gnd 0.168632fF
-C8 Y.t0 gnd 0.393765fF
-C9 Y.t1 gnd 0.147077fF
-C10 a_n8_115.t2 gnd 0.076136fF
-C11 a_n8_115.t3 gnd 0.147186fF
-C12 a_n8_115.t4 gnd 0.056432fF
-C13 a_n8_115.t0 gnd 0.221324fF
-C14 a_n8_115.t1 gnd 0.076136fF
-C15 A.t1 gnd 0.186946fF
-C16 A.t0 gnd 0.140217fF
-.ends
diff --git a/cdl/AND2X2.cdl b/cdl/AND2X2.cdl
deleted file mode 100644
index 5a754a2..0000000
--- a/cdl/AND2X2.cdl
+++ /dev/null
@@ -1,64 +0,0 @@
-* SPICE3 file created from AND2X2.ext - technology: EFS8A
-
-.subckt AND2X2 A B Y
-M1000 a_75_115# A.t0 a_n8_115.t1 gnd nshort w=2u l=0.15u
-+  ad=0.21p pd=2.21u as=0.53p ps=4.53u
-M1001 gnd a_n8_115.t3 Y.t1 gnd nshort w=1u l=0.15u
-+  ad=0.2175p pd=1.8025u as=0.14p ps=1.28u
-M1002 Y.t3 a_n8_115.t4 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.6075p ps=4.905u
-M1003 Y.t0 a_n8_115.t5 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.2175p ps=1.8025u
-M1004 vdd B.t0 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.6075p pd=4.905u as=0.42p ps=3.28u
-M1005 gnd B.t1 a_75_115# gnd nshort w=2u l=0.15u
-+  ad=0.435p pd=3.605u as=0.21p ps=2.21u
-M1006 a_n8_115.t2 A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.6075p ps=4.905u
-M1007 vdd a_n8_115.t6 Y.t2 vdd pshort w=3u l=0.15u
-+  ad=0.6075p pd=4.905u as=0.42p ps=3.28u
-C0 m1_n35_0# m1_n35_1379# 0.079220fF
-C1 Y vdd 0.000538fF
-C2 Y m1_n35_1379# 0.026974fF
-C3 A B 0.340125fF
-C4 m1_n35_0# Y 0.047670fF
-R0 A.n0 A.t1 567.688
-R1 A.n0 A.t0 525.914
-R2 A A.n0 8.054
-R3 a_n8_115.n0 a_n8_115.t6 644.273
-R4 a_n8_115.n0 a_n8_115.t4 506.1
-R5 a_n8_115.n1 a_n8_115.t3 454.685
-R6 a_n8_115.n1 a_n8_115.t5 410.85
-R7 a_n8_115.n2 a_n8_115.n0 264.74
-R8 a_n8_115.n4 a_n8_115.n3 241.858
-R9 a_n8_115.n3 a_n8_115.n2 117.249
-R10 a_n8_115.n3 a_n8_115.t1 53.043
-R11 a_n8_115.n2 a_n8_115.n1 12.949
-R12 a_n8_115.t0 a_n8_115.n4 9.193
-R13 a_n8_115.n4 a_n8_115.t2 9.193
-R14 Y Y.n0 191.64
-R15 Y Y.n1 162.325
-R16 Y.n1 Y.t1 16.8
-R17 Y.n1 Y.t0 16.8
-R18 Y.n0 Y.t2 9.193
-R19 Y.n0 Y.t3 9.193
-R20 B.n0 B.t0 696.221
-R21 B.n0 B.t1 397.381
-R22 B B.n0 7.684
-C5 vdd gnd 1.073880fF
-C6 B.t0 gnd 0.288219fF
-C7 B.t1 gnd 0.175433fF
-C8 Y.t2 gnd 0.070269fF
-C9 Y.t3 gnd 0.070269fF
-C10 Y.t1 gnd 0.023423fF
-C11 Y.t0 gnd 0.023423fF
-C12 a_n8_115.t4 gnd 0.107326fF
-C13 a_n8_115.t6 gnd 0.118821fF
-C14 a_n8_115.t3 gnd 0.054049fF
-C15 a_n8_115.t5 gnd 0.050295fF
-C16 a_n8_115.t1 gnd 0.202452fF
-C17 a_n8_115.t2 gnd 0.069644fF
-C18 a_n8_115.t0 gnd 0.069644fF
-C19 A.t1 gnd 0.193507fF
-C20 A.t0 gnd 0.145138fF
-.ends
diff --git a/cdl/AND2X4.cdl b/cdl/AND2X4.cdl
deleted file mode 100644
index 9eb06c0..0000000
--- a/cdl/AND2X4.cdl
+++ /dev/null
@@ -1,98 +0,0 @@
-* SPICE3 file created from AND2X4.ext - technology: EFS8A
-
-.subckt AND2X4 A B Y
-M1000 a_75_115# A.t0 a_n8_115.t0 gnd nshort w=2u l=0.15u
-+  ad=0.21p pd=2.21u as=0.53p ps=4.53u
-M1001 gnd a_n8_115.t3 Y.t7 gnd nshort w=1u l=0.15u
-+  ad=0.191667p pd=1.62833u as=0.14p ps=1.28u
-M1002 Y.t3 a_n8_115.t4 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1003 vdd a_n8_115.t5 Y.t2 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-M1004 Y.t6 a_n8_115.t6 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.191667p ps=1.62833u
-M1005 vdd B.t0 a_n8_115.t2 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-M1006 gnd a_n8_115.t7 Y.t5 gnd nshort w=1u l=0.15u
-+  ad=0.191667p pd=1.62833u as=0.14p ps=1.28u
-M1007 gnd B.t1 a_75_115# gnd nshort w=2u l=0.15u
-+  ad=0.383333p pd=3.25667u as=0.21p ps=2.21u
-M1008 Y.t1 a_n8_115.t8 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1009 a_n8_115.t1 A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1010 Y.t4 a_n8_115.t9 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.191667p ps=1.62833u
-M1011 vdd a_n8_115.t10 Y.t0 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-C0 m1_n35_1379# Y 0.122412fF
-C1 m1_n35_0# Y 0.210435fF
-C2 vdd Y 0.005614fF
-C3 m1_n35_1379# m1_n35_0# 0.109399fF
-C4 A B 0.340125fF
-R0 A.n0 A.t1 567.688
-R1 A.n0 A.t0 525.914
-R2 A A.n0 8.054
-R3 a_n8_115.n0 a_n8_115.t5 644.273
-R4 a_n8_115.n3 a_n8_115.t7 538.232
-R5 a_n8_115.n2 a_n8_115.t4 506.1
-R6 a_n8_115.n0 a_n8_115.t8 506.1
-R7 a_n8_115.n1 a_n8_115.t10 506.1
-R8 a_n8_115.n5 a_n8_115.t6 410.85
-R9 a_n8_115.n4 a_n8_115.t3 400.059
-R10 a_n8_115.n3 a_n8_115.t9 400.059
-R11 a_n8_115.n6 a_n8_115.n2 264.74
-R12 a_n8_115.n8 a_n8_115.n7 241.858
-R13 a_n8_115.n4 a_n8_115.n3 138.173
-R14 a_n8_115.n1 a_n8_115.n0 138.173
-R15 a_n8_115.n2 a_n8_115.n1 138.173
-R16 a_n8_115.n7 a_n8_115.n6 117.249
-R17 a_n8_115.n5 a_n8_115.n4 54.626
-R18 a_n8_115.n7 a_n8_115.t0 53.043
-R19 a_n8_115.n6 a_n8_115.n5 12.949
-R20 a_n8_115.n8 a_n8_115.t2 9.193
-R21 a_n8_115.t1 a_n8_115.n8 9.193
-R22 Y.n1 Y.n0 191.147
-R23 Y.n3 Y.n2 191.147
-R24 Y.n7 Y.n6 161.725
-R25 Y.n5 Y.n4 161.723
-R26 Y.n6 Y.t7 16.8
-R27 Y.n6 Y.t6 16.8
-R28 Y.n4 Y.t5 16.8
-R29 Y.n4 Y.t4 16.8
-R30 Y.n0 Y.t2 9.193
-R31 Y.n0 Y.t1 9.193
-R32 Y.n2 Y.t0 9.193
-R33 Y.n2 Y.t3 9.193
-R34 Y.n3 Y.n1 0.575
-R35 Y.n7 Y.n5 0.573
-R36 Y Y.n7 0.553
-R37 Y Y.n3 0.444
-R38 B.n0 B.t0 696.221
-R39 B.n0 B.t1 397.381
-R40 B B.n0 7.684
-C5 vdd gnd 1.475160fF
-C6 B.t0 gnd 0.300226fF
-C7 B.t1 gnd 0.182742fF
-C8 Y.t2 gnd 0.058727fF
-C9 Y.t1 gnd 0.058727fF
-C10 Y.t0 gnd 0.058727fF
-C11 Y.t3 gnd 0.058727fF
-C12 Y.t5 gnd 0.019576fF
-C13 Y.t4 gnd 0.019576fF
-C14 Y.t7 gnd 0.019576fF
-C15 Y.t6 gnd 0.019576fF
-C16 a_n8_115.t2 gnd 0.067822fF
-C17 a_n8_115.t4 gnd 0.104518fF
-C18 a_n8_115.t10 gnd 0.104518fF
-C19 a_n8_115.t8 gnd 0.104518fF
-C20 a_n8_115.t5 gnd 0.115713fF
-C21 a_n8_115.t3 gnd 0.048081fF
-C22 a_n8_115.t9 gnd 0.048081fF
-C23 a_n8_115.t7 gnd 0.059429fF
-C24 a_n8_115.t6 gnd 0.048979fF
-C25 a_n8_115.t0 gnd 0.197156fF
-C26 a_n8_115.t1 gnd 0.067822fF
-C27 A.t1 gnd 0.201957fF
-C28 A.t0 gnd 0.151476fF
-.ends
diff --git a/cdl/AND2X8.cdl b/cdl/AND2X8.cdl
deleted file mode 100644
index 4fae085..0000000
--- a/cdl/AND2X8.cdl
+++ /dev/null
@@ -1,165 +0,0 @@
-* SPICE3 file created from AND2X8.ext - technology: EFS8A
-
-.subckt AND2X8 A B Y
-M1000 a_75_115# A.t0 a_n8_115.t1 gnd nshort w=2u l=0.15u
-+  ad=0.21p pd=2.21u as=0.53p ps=4.53u
-M1001 Y.t7 a_n8_115.t3 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1002 gnd a_n8_115.t4 Y.t15 gnd nshort w=1u l=0.15u
-+  ad=0.171p pd=1.489u as=0.14p ps=1.28u
-M1003 Y.t6 a_n8_115.t5 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1004 vdd a_n8_115.t6 Y.t5 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1005 Y.t14 a_n8_115.t7 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.171p ps=1.489u
-M1006 vdd a_n8_115.t8 Y.t4 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1007 Y.t13 a_n8_115.t9 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.171p ps=1.489u
-M1008 gnd a_n8_115.t10 Y.t12 gnd nshort w=1u l=0.15u
-+  ad=0.171p pd=1.489u as=0.14p ps=1.28u
-M1009 vdd B.t0 a_n8_115.t2 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1010 Y.t3 a_n8_115.t11 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1011 gnd a_n8_115.t12 Y.t11 gnd nshort w=1u l=0.15u
-+  ad=0.171p pd=1.489u as=0.14p ps=1.28u
-M1012 gnd B.t1 a_75_115# gnd nshort w=2u l=0.15u
-+  ad=0.342p pd=2.978u as=0.21p ps=2.21u
-M1013 Y.t2 a_n8_115.t13 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1014 Y.t10 a_n8_115.t14 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.171p ps=1.489u
-M1015 a_n8_115.t0 A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1016 vdd a_n8_115.t15 Y.t1 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1017 Y.t9 a_n8_115.t16 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.171p ps=1.489u
-M1018 vdd a_n8_115.t17 Y.t0 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1019 gnd a_n8_115.t18 Y.t8 gnd nshort w=1u l=0.15u
-+  ad=0.171p pd=1.489u as=0.14p ps=1.28u
-C0 A B 0.340125fF
-C1 vdd Y 0.015766fF
-C2 m1_n35_1379# Y 0.313289fF
-C3 m1_n35_0# Y 0.535965fF
-C4 m1_n35_1379# m1_n35_0# 0.165985fF
-R0 A.n0 A.t1 567.688
-R1 A.n0 A.t0 525.914
-R2 A A.n0 8.054
-R3 a_n8_115.n6 a_n8_115.t6 644.273
-R4 a_n8_115.n4 a_n8_115.t10 538.232
-R5 a_n8_115.n3 a_n8_115.t5 506.1
-R6 a_n8_115.n6 a_n8_115.t11 506.1
-R7 a_n8_115.n7 a_n8_115.t15 506.1
-R8 a_n8_115.n8 a_n8_115.t3 506.1
-R9 a_n8_115.n0 a_n8_115.t8 506.1
-R10 a_n8_115.n1 a_n8_115.t13 506.1
-R11 a_n8_115.n2 a_n8_115.t17 506.1
-R12 a_n8_115.n14 a_n8_115.t9 410.85
-R13 a_n8_115.n13 a_n8_115.t4 400.059
-R14 a_n8_115.n12 a_n8_115.t16 400.059
-R15 a_n8_115.n11 a_n8_115.t12 400.059
-R16 a_n8_115.n10 a_n8_115.t7 400.059
-R17 a_n8_115.n5 a_n8_115.t18 400.059
-R18 a_n8_115.n4 a_n8_115.t14 400.059
-R19 a_n8_115.n9 a_n8_115.n8 298.84
-R20 a_n8_115.n15 a_n8_115.n3 264.74
-R21 a_n8_115.n17 a_n8_115.n16 241.858
-R22 a_n8_115.n5 a_n8_115.n4 138.173
-R23 a_n8_115.n11 a_n8_115.n10 138.173
-R24 a_n8_115.n12 a_n8_115.n11 138.173
-R25 a_n8_115.n13 a_n8_115.n12 138.173
-R26 a_n8_115.n7 a_n8_115.n6 138.173
-R27 a_n8_115.n8 a_n8_115.n7 138.173
-R28 a_n8_115.n1 a_n8_115.n0 138.173
-R29 a_n8_115.n2 a_n8_115.n1 138.173
-R30 a_n8_115.n3 a_n8_115.n2 138.173
-R31 a_n8_115.n9 a_n8_115.n5 134.96
-R32 a_n8_115.n16 a_n8_115.n15 117.249
-R33 a_n8_115.n14 a_n8_115.n13 54.626
-R34 a_n8_115.n16 a_n8_115.t1 53.043
-R35 a_n8_115.n15 a_n8_115.n14 12.949
-R36 a_n8_115.n17 a_n8_115.t2 9.193
-R37 a_n8_115.t0 a_n8_115.n17 9.193
-R38 a_n8_115.n10 a_n8_115.n9 3.213
-R39 Y.n5 Y.n4 191.147
-R40 Y.n7 Y.n6 191.147
-R41 Y.n3 Y.n2 191.147
-R42 Y.n1 Y.n0 191.147
-R43 Y.n17 Y.n16 161.725
-R44 Y.n15 Y.n14 161.723
-R45 Y.n9 Y.n8 161.723
-R46 Y.n12 Y.n11 161.723
-R47 Y.n16 Y.t15 16.8
-R48 Y.n16 Y.t13 16.8
-R49 Y.n14 Y.t11 16.8
-R50 Y.n14 Y.t9 16.8
-R51 Y.n8 Y.t12 16.8
-R52 Y.n8 Y.t10 16.8
-R53 Y.n11 Y.t8 16.8
-R54 Y.n11 Y.t14 16.8
-R55 Y.n4 Y.t4 9.193
-R56 Y.n4 Y.t2 9.193
-R57 Y.n6 Y.t0 9.193
-R58 Y.n6 Y.t6 9.193
-R59 Y.n2 Y.t1 9.193
-R60 Y.n2 Y.t7 9.193
-R61 Y.n0 Y.t5 9.193
-R62 Y.n0 Y.t3 9.193
-R63 Y.n7 Y.n5 0.575
-R64 Y.n3 Y.n1 0.575
-R65 Y.n5 Y.n3 0.575
-R66 Y.n17 Y.n15 0.573
-R67 Y.n13 Y.n12 0.57
-R68 Y.n10 Y.n9 0.57
-R69 Y Y.n17 0.553
-R70 Y Y.n7 0.444
-R71 Y.n12 Y.n10 0.005
-R72 Y.n15 Y.n13 0.005
-R73 B.n0 B.t0 696.221
-R74 B.n0 B.t1 397.381
-R75 B B.n0 7.684
-C5 vdd gnd 2.238960fF
-C6 B.t0 gnd 0.322718fF
-C7 B.t1 gnd 0.196432fF
-C8 Y.t5 gnd 0.049063fF
-C9 Y.t3 gnd 0.049063fF
-C10 Y.t1 gnd 0.049063fF
-C11 Y.t7 gnd 0.049063fF
-C12 Y.t4 gnd 0.049063fF
-C13 Y.t2 gnd 0.049063fF
-C14 Y.t0 gnd 0.049063fF
-C15 Y.t6 gnd 0.049063fF
-C16 Y.t12 gnd 0.016354fF
-C17 Y.t10 gnd 0.016354fF
-C18 Y.t8 gnd 0.016354fF
-C19 Y.t14 gnd 0.016354fF
-C20 Y.t11 gnd 0.016354fF
-C21 Y.t9 gnd 0.016354fF
-C22 Y.t15 gnd 0.016354fF
-C23 Y.t13 gnd 0.016354fF
-C24 a_n8_115.t2 gnd 0.061514fF
-C25 a_n8_115.t5 gnd 0.094797fF
-C26 a_n8_115.t17 gnd 0.094797fF
-C27 a_n8_115.t13 gnd 0.094797fF
-C28 a_n8_115.t8 gnd 0.094797fF
-C29 a_n8_115.t4 gnd 0.043609fF
-C30 a_n8_115.t16 gnd 0.043609fF
-C31 a_n8_115.t12 gnd 0.043609fF
-C32 a_n8_115.t7 gnd 0.043609fF
-C33 a_n8_115.t18 gnd 0.043609fF
-C34 a_n8_115.t14 gnd 0.043609fF
-C35 a_n8_115.t10 gnd 0.053902fF
-C36 a_n8_115.t3 gnd 0.094797fF
-C37 a_n8_115.t15 gnd 0.094797fF
-C38 a_n8_115.t11 gnd 0.094797fF
-C39 a_n8_115.t6 gnd 0.104951fF
-C40 a_n8_115.t9 gnd 0.044424fF
-C41 a_n8_115.t1 gnd 0.178819fF
-C42 a_n8_115.t0 gnd 0.061514fF
-C43 A.t1 gnd 0.219378fF
-C44 A.t0 gnd 0.164542fF
-.ends
diff --git a/cdl/AND2XL.cdl b/cdl/AND2XL.cdl
deleted file mode 100644
index 5059a00..0000000
--- a/cdl/AND2XL.cdl
+++ /dev/null
@@ -1,48 +0,0 @@
-* SPICE3 file created from AND2XL.ext - technology: EFS8A
-
-.subckt AND2XL B A Y
-M1000 a_75_115# A.t0 a_n8_115.t0 gnd nshort w=1.26u l=0.15u
-+  ad=0.1323p pd=1.47u as=0.3339p ps=3.05u
-M1001 Y.t0 a_n8_115.t3 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.29975p ps=2.56333u
-M1002 Y.t1 a_n8_115.t4 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.12864p ps=1.07789u
-M1003 vdd B.t0 a_n8_115.t2 vdd pshort w=1.65u l=0.15u
-+  ad=0.29975p pd=2.56333u as=0.231p ps=1.93u
-M1004 gnd B.t1 a_75_115# gnd nshort w=1.26u l=0.15u
-+  ad=0.25326p pd=2.12211u as=0.1323p ps=1.47u
-M1005 a_n8_115.t1 A.t1 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.231p pd=1.93u as=0.29975p ps=2.56333u
-C0 m1_n35_0# m1_n35_1379# 0.064131fF
-C1 Y vdd 0.001954fF
-C2 Y m1_n35_1379# 0.026952fF
-C3 A B 0.865875fF
-C4 m1_n35_0# Y 0.047670fF
-R0 A.n0 A.t1 784.588
-R1 A.n0 A.t0 644.808
-R2 A A.n0 8.054
-R3 a_n8_115.n0 a_n8_115.t3 1041.66
-R4 a_n8_115.n0 a_n8_115.t4 487.354
-R5 a_n8_115.n2 a_n8_115.n1 317.018
-R6 a_n8_115.n1 a_n8_115.t0 109.462
-R7 a_n8_115.n1 a_n8_115.n0 88.235
-R8 a_n8_115.n2 a_n8_115.t2 16.715
-R9 a_n8_115.t1 a_n8_115.n2 16.715
-R10 Y Y.t0 257.155
-R11 Y Y.t1 200.784
-R12 B.n0 B.t0 913.121
-R13 B.n0 B.t1 516.275
-R14 B B.n0 7.684
-C5 vdd gnd 0.873945fF
-C6 B.t0 gnd 0.583515fF
-C7 B.t1 gnd 0.360491fF
-C8 Y.t0 gnd 0.264592fF
-C9 Y.t1 gnd 0.112846fF
-C10 a_n8_115.t2 gnd 0.070264fF
-C11 a_n8_115.t0 gnd 0.286032fF
-C12 a_n8_115.t3 gnd 0.211589fF
-C13 a_n8_115.t4 gnd 0.087104fF
-C14 a_n8_115.t1 gnd 0.070264fF
-C15 A.t1 gnd 0.397116fF
-C16 A.t0 gnd 0.311957fF
-.ends
diff --git a/cdl/AND3XL.cdl b/cdl/AND3XL.cdl
deleted file mode 100644
index 100f0ea..0000000
--- a/cdl/AND3XL.cdl
+++ /dev/null
@@ -1,67 +0,0 @@
-* SPICE3 file created from AND3XL.ext - technology: EFS8A
-
-.subckt AND3XL C Y B A
-M1000 a_75_115# A.t0 Y.t2 gnd nshort w=2u l=0.15u
-+  ad=0.21p pd=2.21u as=0.53p ps=4.53u
-M1001 a_317_115# Y.t4 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.140121p ps=1.13455u
-M1002 vdd C.t0 Y.t1 vdd pshort w=1.65u l=0.15u
-+  ad=0.231p pd=1.93u as=0.29975p ps=2.56333u
-M1003 gnd C.t1 a_147_115# gnd nshort w=2u l=0.15u
-+  ad=0.437879p pd=3.54545u as=0.21p ps=2.21u
-M1004 Y.t0 B.t0 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.29975p pd=2.56333u as=0.231p ps=1.93u
-M1005 a_147_115# B.t1 a_75_115# gnd nshort w=2u l=0.15u
-+  ad=0.21p pd=2.21u as=0.21p ps=2.21u
-M1006 vdd A.t1 Y.t3 vdd pshort w=1.65u l=0.15u
-+  ad=0.231p pd=1.93u as=0.29975p ps=2.56333u
-M1007 a_317_115# Y.t5 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.231p ps=1.93u
-C0 A Y 0.161239fF
-C1 B C 0.638866fF
-C2 vdd a_317_115# 0.001954fF
-C3 B Y 0.231578fF
-C4 Y vdd 0.001942fF
-C5 C Y 0.585110fF
-C6 Y a_317_115# 0.287882fF
-C7 m1_n35_1379# a_317_115# 0.027915fF
-C8 m1_n35_1379# Y 0.026952fF
-C9 A B 0.703875fF
-C10 m1_n35_0# a_317_115# 0.050384fF
-C11 m1_n35_0# Y 0.047670fF
-C12 A C 0.249213fF
-C13 m1_n35_1379# m1_n35_0# 0.079220fF
-R0 A.n0 A.t1 784.588
-R1 A.n0 A.t0 525.914
-R2 A A.n0 8.054
-R3 Y.n2 Y.t5 1035.94
-R4 Y.n2 Y.t4 481.639
-R5 Y.n1 Y.n0 190.858
-R6 Y.n1 Y.t3 145.856
-R7 Y.n3 Y.n2 143.083
-R8 Y Y.n1 99.345
-R9 Y.n3 Y.t2 53.044
-R10 Y Y.n3 49.714
-R11 Y.n0 Y.t1 16.715
-R12 Y.n0 Y.t0 16.715
-R13 C.n0 C.t0 911.09
-R14 C.n0 C.t1 395.35
-R15 C C.n0 7.5
-R16 B.n0 B.t0 656.055
-R17 B.n0 B.t1 654.448
-R18 B B.n0 7.684
-C14 a_317_115# gnd 0.034885fF
-C15 vdd gnd 1.073880fF
-C16 B.t0 gnd 0.453854fF
-C17 B.t1 gnd 0.499363fF
-C18 C.t0 gnd 0.521735fF
-C19 C.t1 gnd 0.368159fF
-C20 Y.t3 gnd 0.194301fF
-C21 Y.t1 gnd 0.035719fF
-C22 Y.t0 gnd 0.035719fF
-C23 Y.t2 gnd 0.188790fF
-C24 Y.t5 gnd 0.107172fF
-C25 Y.t4 gnd 0.043916fF
-C26 A.t1 gnd 0.369041fF
-C27 A.t0 gnd 0.325670fF
-.ends
diff --git a/cdl/ANT.cdl b/cdl/ANT.cdl
deleted file mode 100644
index e67802b..0000000
--- a/cdl/ANT.cdl
+++ /dev/null
@@ -1,22 +0,0 @@
-* SPICE3 file created from ANT.ext - technology: EFS8A
-
-.subckt ANT A
-M1000 A.t2 A.t0 A.t1 gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.265p ps=2.53u
-M1001 vdd A.t3 A.t4 vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.795p ps=6.53u
-C0 m1_n35_1379# m1_n35_0# 0.033951fF
-R0 A.n1 A.t0 678.334
-R1 A.n1 A.t3 559.441
-R2 A A.t4 150.087
-R3 A.n0 A.t1 127.281
-R4 A.n0 A.t2 96.423
-R5 A A.n0 77.059
-R6 A A.n1 7.5
-C1 vdd gnd 0.474240fF
-C2 A.t4 gnd 0.003567fF
-C3 A.t2 gnd 0.001112fF
-C4 A.t1 gnd 0.001274fF
-C5 A.t3 gnd 0.001076fF
-C6 A.t0 gnd 0.000685fF
-.ends
diff --git a/cdl/AOI21XL.cdl b/cdl/AOI21XL.cdl
deleted file mode 100644
index 4c77627..0000000
--- a/cdl/AOI21XL.cdl
+++ /dev/null
@@ -1,51 +0,0 @@
-* SPICE3 file created from AOI21XL.ext - technology: EFS8A
-
-.subckt AOI21XL Y A0 A1 B0
-M1000 a_75_115# A0.t0 gnd gnd nshort w=1.26u l=0.15u
-+  ad=0.1323p pd=1.47u as=0.3339p ps=3.22295u
-M1001 Y.t2 B0.t0 a_n8_725.t2 vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.545p ps=4.36333u
-M1002 gnd B0.t1 Y.t1 gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.63705u as=0.12864p ps=1.07789u
-M1003 a_n8_725.t0 A1.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-M1004 Y.t0 A1.t1 a_75_115# gnd nshort w=1.26u l=0.15u
-+  ad=0.25326p pd=2.12211u as=0.1323p ps=1.47u
-M1005 vdd A0.t1 a_n8_725.t1 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-C0 Y m1_n35_1379# 0.049089fF
-C1 A0 B0 0.170267fF
-C2 Y m1_n35_0# 0.135998fF
-C3 A1 B0 0.373951fF
-C4 A1 Y 0.004853fF
-C5 m1_n35_1379# m1_n35_0# 0.064131fF
-C6 Y vdd 0.001080fF
-C7 B0 Y 0.040279fF
-C8 A0 A1 0.562125fF
-R0 A0.n0 A0.t0 644.711
-R1 A0.n0 A0.t1 567.591
-R2 A0 A0.n0 7.5
-R3 B0.n0 B0.t0 801.923
-R4 B0.n0 B0.t1 520.547
-R5 B0 B0.n0 7.5
-R6 a_n8_725.n0 a_n8_725.t1 313.404
-R7 a_n8_725.n0 a_n8_725.t2 9.193
-R8 a_n8_725.t0 a_n8_725.n0 9.193
-R9 Y Y.t2 121.015
-R10 Y Y.n0 86.535
-R11 Y.n0 Y.t1 37.898
-R12 Y.n0 Y.t0 13.841
-R13 A1.n0 A1.t0 692.42
-R14 A1.n0 A1.t1 512.474
-R15 A1 A1.n0 7.5
-C9 vdd gnd 0.873240fF
-C10 A1.t0 gnd 0.390737fF
-C11 A1.t1 gnd 0.207769fF
-C12 Y.t2 gnd 0.120135fF
-C13 Y.t1 gnd 0.007264fF
-C14 Y.t0 gnd 0.010979fF
-C15 B0.t0 gnd 0.285279fF
-C16 B0.t1 gnd 0.107195fF
-C17 A0.t1 gnd 0.287067fF
-C18 A0.t0 gnd 0.191624fF
-.ends
diff --git a/cdl/BUFX1.cdl b/cdl/BUFX1.cdl
deleted file mode 100644
index c81fbca..0000000
--- a/cdl/BUFX1.cdl
+++ /dev/null
@@ -1,37 +0,0 @@
-* SPICE3 file created from BUFX1.ext - technology: EFS8A
-
-.subckt BUFX1 A Y
-M1000 gnd A.t0 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.265p ps=2.53u
-M1001 Y.t0 a_n8_115.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.28u
-M1002 Y.t1 a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.14p ps=1.28u
-M1003 vdd A.t1 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-C0 m1_n35_1379# m1_n35_0# 0.049041fF
-C1 vdd Y 0.001326fF
-C2 m1_n35_1379# Y 0.026952fF
-C3 m1_n35_0# Y 0.047670fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 558.047
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n0 a_n8_115.t3 686.581
-R6 a_n8_115.n0 a_n8_115.t2 567.688
-R7 a_n8_115.n1 a_n8_115.t1 255.638
-R8 a_n8_115.t0 a_n8_115.n1 179.239
-R9 a_n8_115.n1 a_n8_115.n0 25.8
-R10 Y Y.t0 200.995
-R11 Y Y.t1 178.972
-C4 vdd gnd 0.677160fF
-C5 Y.t0 gnd 0.845700fF
-C6 Y.t1 gnd 0.315624fF
-C7 a_n8_115.t2 gnd 0.236188fF
-C8 a_n8_115.t3 gnd 0.150867fF
-C9 a_n8_115.t1 gnd 0.400275fF
-C10 a_n8_115.t0 gnd 0.811599fF
-C11 A.t1 gnd 0.241886fF
-C12 A.t0 gnd 0.122411fF
-.ends
diff --git a/cdl/BUFX2.cdl b/cdl/BUFX2.cdl
deleted file mode 100644
index a66bc02..0000000
--- a/cdl/BUFX2.cdl
+++ /dev/null
@@ -1,53 +0,0 @@
-* SPICE3 file created from BUFX2.ext - technology: EFS8A
-
-.subckt BUFX2 A Y
-M1000 gnd A.t0 a_n8_115.t0 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.265p ps=2.53u
-M1001 vdd a_n8_115.t2 Y.t3 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-M1002 gnd a_n8_115.t3 Y.t1 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1003 Y.t2 a_n8_115.t4 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1004 Y.t0 a_n8_115.t5 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1005 vdd A.t1 a_n8_115.t1 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.795p ps=6.53u
-C0 m1_n35_0# Y 0.047670fF
-C1 m1_n35_1379# m1_n35_0# 0.064131fF
-C2 m1_n35_1379# Y 0.026952fF
-C3 Y vdd 0.001167fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 558.047
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n0 a_n8_115.t2 613.746
-R6 a_n8_115.n0 a_n8_115.t4 551.621
-R7 a_n8_115.n1 a_n8_115.t3 483.605
-R8 a_n8_115.n1 a_n8_115.t5 345.432
-R9 a_n8_115.n2 a_n8_115.n1 292.948
-R10 a_n8_115.n3 a_n8_115.t0 255.638
-R11 a_n8_115.t1 a_n8_115.n3 179.239
-R12 a_n8_115.n3 a_n8_115.n2 25.8
-R13 a_n8_115.n2 a_n8_115.n0 16.066
-R14 Y Y.n0 191.718
-R15 Y Y.n1 162.257
-R16 Y.n1 Y.t1 16.8
-R17 Y.n1 Y.t0 16.8
-R18 Y.n0 Y.t3 9.193
-R19 Y.n0 Y.t2 9.193
-C4 vdd gnd 0.875520fF
-C5 Y.t3 gnd 0.149657fF
-C6 Y.t2 gnd 0.149657fF
-C7 Y.t1 gnd 0.049886fF
-C8 Y.t0 gnd 0.049886fF
-C9 a_n8_115.t2 gnd 0.213046fF
-C10 a_n8_115.t4 gnd 0.203484fF
-C11 a_n8_115.t5 gnd 0.082828fF
-C12 a_n8_115.t3 gnd 0.104407fF
-C13 a_n8_115.t0 gnd 0.349367fF
-C14 a_n8_115.t1 gnd 0.708377fF
-C15 A.t1 gnd 0.276151fF
-C16 A.t0 gnd 0.139751fF
-.ends
diff --git a/cdl/BUFX4.cdl b/cdl/BUFX4.cdl
deleted file mode 100644
index a5bb09c..0000000
--- a/cdl/BUFX4.cdl
+++ /dev/null
@@ -1,87 +0,0 @@
-* SPICE3 file created from BUFX4.ext - technology: EFS8A
-
-.subckt BUFX4 A Y
-M1000 gnd A.t0 a_n8_115.t0 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.265p ps=2.53u
-M1001 Y.t3 a_n8_115.t2 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.165p ps=1.53u
-M1002 vdd a_n8_115.t3 Y.t7 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1003 gnd a_n8_115.t4 Y.t2 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.14p ps=1.28u
-M1004 Y.t6 a_n8_115.t5 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1005 vdd a_n8_115.t6 Y.t5 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1006 Y.t1 a_n8_115.t7 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.165p ps=1.53u
-M1007 vdd A.t1 a_n8_115.t1 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.795p ps=6.53u
-M1008 gnd a_n8_115.t8 Y.t0 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.14p ps=1.28u
-M1009 Y.t4 a_n8_115.t9 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-C0 m1_n35_0# Y 0.210441fF
-C1 m1_n35_1379# m1_n35_0# 0.094310fF
-C2 vdd Y 0.006872fF
-C3 m1_n35_1379# Y 0.122398fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 558.047
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n0 a_n8_115.t6 676.406
-R6 a_n8_115.n2 a_n8_115.t5 551.621
-R7 a_n8_115.n0 a_n8_115.t9 538.233
-R8 a_n8_115.n1 a_n8_115.t3 538.233
-R9 a_n8_115.n3 a_n8_115.t8 483.605
-R10 a_n8_115.n5 a_n8_115.t7 345.432
-R11 a_n8_115.n4 a_n8_115.t4 345.432
-R12 a_n8_115.n3 a_n8_115.t2 345.432
-R13 a_n8_115.n6 a_n8_115.n5 292.948
-R14 a_n8_115.n7 a_n8_115.t0 255.638
-R15 a_n8_115.t1 a_n8_115.n7 179.239
-R16 a_n8_115.n1 a_n8_115.n0 138.173
-R17 a_n8_115.n4 a_n8_115.n3 138.173
-R18 a_n8_115.n5 a_n8_115.n4 138.173
-R19 a_n8_115.n2 a_n8_115.n1 75.513
-R20 a_n8_115.n7 a_n8_115.n6 25.8
-R21 a_n8_115.n6 a_n8_115.n2 16.066
-R22 Y.n1 Y.n0 191.147
-R23 Y.n3 Y.n2 191.147
-R24 Y.n7 Y.n6 161.723
-R25 Y.n5 Y.n4 161.723
-R26 Y.n6 Y.t0 16.8
-R27 Y.n6 Y.t3 16.8
-R28 Y.n4 Y.t2 16.8
-R29 Y.n4 Y.t1 16.8
-R30 Y.n0 Y.t7 9.193
-R31 Y.n0 Y.t6 9.193
-R32 Y.n2 Y.t5 9.193
-R33 Y.n2 Y.t4 9.193
-R34 Y.n7 Y.n5 0.575
-R35 Y.n3 Y.n1 0.573
-R36 Y Y.n7 0.569
-R37 Y Y.n3 0.437
-C4 vdd gnd 1.279080fF
-C5 Y.t7 gnd 0.098917fF
-C6 Y.t6 gnd 0.098917fF
-C7 Y.t5 gnd 0.098917fF
-C8 Y.t4 gnd 0.098917fF
-C9 Y.t2 gnd 0.032972fF
-C10 Y.t1 gnd 0.032972fF
-C11 Y.t0 gnd 0.032972fF
-C12 Y.t3 gnd 0.032972fF
-C13 a_n8_115.t3 gnd 0.177941fF
-C14 a_n8_115.t9 gnd 0.177941fF
-C15 a_n8_115.t6 gnd 0.196507fF
-C16 a_n8_115.t5 gnd 0.179712fF
-C17 a_n8_115.t7 gnd 0.073151fF
-C18 a_n8_115.t4 gnd 0.073151fF
-C19 a_n8_115.t2 gnd 0.073151fF
-C20 a_n8_115.t8 gnd 0.092209fF
-C21 a_n8_115.t0 gnd 0.308552fF
-C22 a_n8_115.t1 gnd 0.625620fF
-C23 A.t1 gnd 0.312987fF
-C24 A.t0 gnd 0.158393fF
-.ends
diff --git a/cdl/BUFX6.cdl b/cdl/BUFX6.cdl
deleted file mode 100644
index e9c9712..0000000
--- a/cdl/BUFX6.cdl
+++ /dev/null
@@ -1,119 +0,0 @@
-* SPICE3 file created from BUFX6.ext - technology: EFS8A
-
-.subckt BUFX6 A Y
-M1000 gnd A.t0 a_n8_115.t0 gnd nshort w=1u l=0.15u
-+  ad=0.157857p pd=1.45857u as=0.265p ps=2.53u
-M1001 vdd a_n8_115.t2 Y.t11 vdd pshort w=3u l=0.15u
-+  ad=0.473571p pd=3.74429u as=0.42p ps=3.28u
-M1002 Y.t5 a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.157857p ps=1.45857u
-M1003 vdd a_n8_115.t4 Y.t10 vdd pshort w=3u l=0.15u
-+  ad=0.473571p pd=3.74429u as=0.42p ps=3.28u
-M1004 gnd a_n8_115.t5 Y.t4 gnd nshort w=1u l=0.15u
-+  ad=0.157857p pd=1.45857u as=0.14p ps=1.28u
-M1005 Y.t9 a_n8_115.t6 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.473571p ps=3.74429u
-M1006 gnd a_n8_115.t7 Y.t3 gnd nshort w=1u l=0.15u
-+  ad=0.157857p pd=1.45857u as=0.14p ps=1.28u
-M1007 Y.t8 a_n8_115.t8 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.473571p ps=3.74429u
-M1008 Y.t2 a_n8_115.t9 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.157857p ps=1.45857u
-M1009 vdd a_n8_115.t10 Y.t7 vdd pshort w=3u l=0.15u
-+  ad=0.473571p pd=3.74429u as=0.42p ps=3.28u
-M1010 Y.t1 a_n8_115.t11 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.157857p ps=1.45857u
-M1011 vdd A.t1 a_n8_115.t1 vdd pshort w=3u l=0.15u
-+  ad=0.473571p pd=3.74429u as=0.795p ps=6.53u
-M1012 gnd a_n8_115.t12 Y.t0 gnd nshort w=1u l=0.15u
-+  ad=0.157857p pd=1.45857u as=0.14p ps=1.28u
-M1013 Y.t6 a_n8_115.t13 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.473571p ps=3.74429u
-C0 m1_n35_1379# Y 0.217843fF
-C1 m1_n35_0# Y 0.373213fF
-C2 m1_n35_1379# m1_n35_0# 0.124489fF
-C3 vdd Y 0.012577fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 558.047
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n1 a_n8_115.t2 676.406
-R6 a_n8_115.n5 a_n8_115.t8 551.621
-R7 a_n8_115.n1 a_n8_115.t6 538.233
-R8 a_n8_115.n2 a_n8_115.t10 538.233
-R9 a_n8_115.n3 a_n8_115.t13 538.233
-R10 a_n8_115.n4 a_n8_115.t4 538.233
-R11 a_n8_115.n0 a_n8_115.t5 483.605
-R12 a_n8_115.n9 a_n8_115.t11 345.432
-R13 a_n8_115.n0 a_n8_115.t9 345.432
-R14 a_n8_115.n8 a_n8_115.t7 345.432
-R15 a_n8_115.n7 a_n8_115.t3 345.432
-R16 a_n8_115.n6 a_n8_115.t12 345.432
-R17 a_n8_115.n1 a_n8_115.n0 321.333
-R18 a_n8_115.n10 a_n8_115.n9 292.948
-R19 a_n8_115.n11 a_n8_115.t0 255.638
-R20 a_n8_115.t1 a_n8_115.n11 179.239
-R21 a_n8_115.n2 a_n8_115.n1 138.173
-R22 a_n8_115.n3 a_n8_115.n2 138.173
-R23 a_n8_115.n4 a_n8_115.n3 138.173
-R24 a_n8_115.n7 a_n8_115.n6 138.173
-R25 a_n8_115.n8 a_n8_115.n7 138.173
-R26 a_n8_115.n9 a_n8_115.n8 138.173
-R27 a_n8_115.n5 a_n8_115.n4 75.513
-R28 a_n8_115.n11 a_n8_115.n10 25.8
-R29 a_n8_115.n10 a_n8_115.n5 16.066
-R30 Y.n2 Y.n1 191.147
-R31 Y.n3 Y.n0 191.147
-R32 Y.n5 Y.n4 191.147
-R33 Y.n11 Y.n10 161.723
-R34 Y.n9 Y.n6 161.723
-R35 Y.n8 Y.n7 161.723
-R36 Y.n10 Y.t4 16.8
-R37 Y.n10 Y.t2 16.8
-R38 Y.n6 Y.t0 16.8
-R39 Y.n6 Y.t5 16.8
-R40 Y.n7 Y.t3 16.8
-R41 Y.n7 Y.t1 16.8
-R42 Y.n1 Y.t10 9.193
-R43 Y.n1 Y.t8 9.193
-R44 Y.n0 Y.t7 9.193
-R45 Y.n0 Y.t6 9.193
-R46 Y.n4 Y.t11 9.193
-R47 Y.n4 Y.t9 9.193
-R48 Y.n9 Y.n8 0.575
-R49 Y.n11 Y.n9 0.575
-R50 Y.n5 Y.n3 0.573
-R51 Y.n3 Y.n2 0.573
-R52 Y Y.n11 0.569
-R53 Y Y.n5 0.437
-C4 vdd gnd 1.680360fF
-C5 Y.t7 gnd 0.079518fF
-C6 Y.t6 gnd 0.079518fF
-C7 Y.t10 gnd 0.079518fF
-C8 Y.t8 gnd 0.079518fF
-C9 Y.t11 gnd 0.079518fF
-C10 Y.t9 gnd 0.079518fF
-C11 Y.t0 gnd 0.026506fF
-C12 Y.t5 gnd 0.026506fF
-C13 Y.t3 gnd 0.026506fF
-C14 Y.t1 gnd 0.026506fF
-C15 Y.t4 gnd 0.026506fF
-C16 Y.t2 gnd 0.026506fF
-C17 a_n8_115.t4 gnd 0.157573fF
-C18 a_n8_115.t13 gnd 0.157573fF
-C19 a_n8_115.t10 gnd 0.157573fF
-C20 a_n8_115.t6 gnd 0.157573fF
-C21 a_n8_115.t2 gnd 0.174014fF
-C22 a_n8_115.t9 gnd 0.064778fF
-C23 a_n8_115.t5 gnd 0.081655fF
-C24 a_n8_115.t8 gnd 0.159141fF
-C25 a_n8_115.t11 gnd 0.064778fF
-C26 a_n8_115.t7 gnd 0.064778fF
-C27 a_n8_115.t3 gnd 0.064778fF
-C28 a_n8_115.t12 gnd 0.064778fF
-C29 a_n8_115.t0 gnd 0.273234fF
-C30 a_n8_115.t1 gnd 0.554009fF
-C31 A.t1 gnd 0.347207fF
-C32 A.t0 gnd 0.175710fF
-.ends
diff --git a/cdl/BUFX8.cdl b/cdl/BUFX8.cdl
deleted file mode 100644
index 090e2a0..0000000
--- a/cdl/BUFX8.cdl
+++ /dev/null
@@ -1,151 +0,0 @@
-* SPICE3 file created from BUFX8.ext - technology: EFS8A
-
-.subckt BUFX8 A Y
-M1000 gnd A.t0 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.158333p pd=1.42778u as=0.265p ps=2.53u
-M1001 vdd a_n8_115.t2 Y.t7 vdd pshort w=3u l=0.15u
-+  ad=0.475p pd=3.65u as=0.42p ps=3.28u
-M1002 Y.t15 a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.158333p ps=1.42778u
-M1003 Y.t14 a_n8_115.t4 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.158333p ps=1.42778u
-M1004 vdd a_n8_115.t5 Y.t6 vdd pshort w=3u l=0.15u
-+  ad=0.475p pd=3.65u as=0.42p ps=3.28u
-M1005 gnd a_n8_115.t6 Y.t13 gnd nshort w=1u l=0.15u
-+  ad=0.158333p pd=1.42778u as=0.14p ps=1.28u
-M1006 Y.t5 a_n8_115.t7 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.475p ps=3.65u
-M1007 gnd a_n8_115.t8 Y.t12 gnd nshort w=1u l=0.15u
-+  ad=0.158333p pd=1.42778u as=0.14p ps=1.28u
-M1008 Y.t4 a_n8_115.t9 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.475p ps=3.65u
-M1009 vdd a_n8_115.t10 Y.t3 vdd pshort w=3u l=0.15u
-+  ad=0.475p pd=3.65u as=0.42p ps=3.28u
-M1010 Y.t11 a_n8_115.t11 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.158333p ps=1.42778u
-M1011 vdd a_n8_115.t12 Y.t2 vdd pshort w=3u l=0.15u
-+  ad=0.475p pd=3.65u as=0.42p ps=3.28u
-M1012 Y.t10 a_n8_115.t13 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.158333p ps=1.42778u
-M1013 gnd a_n8_115.t14 Y.t9 gnd nshort w=1u l=0.15u
-+  ad=0.158333p pd=1.42778u as=0.14p ps=1.28u
-M1014 vdd A.t1 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.475p pd=3.65u as=0.795p ps=6.53u
-M1015 Y.t1 a_n8_115.t15 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.475p ps=3.65u
-M1016 gnd a_n8_115.t16 Y.t8 gnd nshort w=1u l=0.15u
-+  ad=0.158333p pd=1.42778u as=0.14p ps=1.28u
-M1017 Y.t0 a_n8_115.t17 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.475p ps=3.65u
-C0 m1_n35_0# Y 0.544061fF
-C1 vdd Y 0.019608fF
-C2 m1_n35_1379# m1_n35_0# 0.154668fF
-C3 m1_n35_1379# Y 0.318095fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 558.047
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n0 a_n8_115.t10 676.406
-R6 a_n8_115.n9 a_n8_115.t9 551.621
-R7 a_n8_115.n5 a_n8_115.t7 538.233
-R8 a_n8_115.n0 a_n8_115.t15 538.233
-R9 a_n8_115.n1 a_n8_115.t2 538.233
-R10 a_n8_115.n6 a_n8_115.t12 538.233
-R11 a_n8_115.n7 a_n8_115.t17 538.233
-R12 a_n8_115.n8 a_n8_115.t5 538.233
-R13 a_n8_115.n2 a_n8_115.t14 483.605
-R14 a_n8_115.n13 a_n8_115.t13 345.432
-R15 a_n8_115.n4 a_n8_115.t11 345.432
-R16 a_n8_115.n12 a_n8_115.t8 345.432
-R17 a_n8_115.n11 a_n8_115.t4 345.432
-R18 a_n8_115.n10 a_n8_115.t16 345.432
-R19 a_n8_115.n3 a_n8_115.t6 345.432
-R20 a_n8_115.n2 a_n8_115.t3 345.432
-R21 a_n8_115.n5 a_n8_115.n4 321.333
-R22 a_n8_115.n14 a_n8_115.n13 292.948
-R23 a_n8_115.n15 a_n8_115.t1 255.638
-R24 a_n8_115.t0 a_n8_115.n15 179.239
-R25 a_n8_115.n1 a_n8_115.n0 151.026
-R26 a_n8_115.n3 a_n8_115.n2 151.026
-R27 a_n8_115.n5 a_n8_115.n1 138.173
-R28 a_n8_115.n6 a_n8_115.n5 138.173
-R29 a_n8_115.n7 a_n8_115.n6 138.173
-R30 a_n8_115.n8 a_n8_115.n7 138.173
-R31 a_n8_115.n4 a_n8_115.n3 138.173
-R32 a_n8_115.n11 a_n8_115.n10 138.173
-R33 a_n8_115.n12 a_n8_115.n11 138.173
-R34 a_n8_115.n13 a_n8_115.n12 138.173
-R35 a_n8_115.n9 a_n8_115.n8 75.513
-R36 a_n8_115.n15 a_n8_115.n14 25.8
-R37 a_n8_115.n14 a_n8_115.n9 16.066
-R38 Y.n3 Y.n2 191.147
-R39 Y.n4 Y.n1 191.147
-R40 Y.n5 Y.n0 191.147
-R41 Y.n7 Y.n6 191.147
-R42 Y.n15 Y.n14 161.723
-R43 Y.n13 Y.n8 161.723
-R44 Y.n12 Y.n9 161.723
-R45 Y.n11 Y.n10 161.723
-R46 Y.n14 Y.t9 16.8
-R47 Y.n14 Y.t15 16.8
-R48 Y.n8 Y.t13 16.8
-R49 Y.n8 Y.t11 16.8
-R50 Y.n9 Y.t8 16.8
-R51 Y.n9 Y.t14 16.8
-R52 Y.n10 Y.t12 16.8
-R53 Y.n10 Y.t10 16.8
-R54 Y.n2 Y.t6 9.193
-R55 Y.n2 Y.t4 9.193
-R56 Y.n1 Y.t2 9.193
-R57 Y.n1 Y.t0 9.193
-R58 Y.n0 Y.t7 9.193
-R59 Y.n0 Y.t5 9.193
-R60 Y.n6 Y.t3 9.193
-R61 Y.n6 Y.t1 9.193
-R62 Y.n15 Y.n13 0.604
-R63 Y.n7 Y.n5 0.603
-R64 Y Y.n15 0.584
-R65 Y.n12 Y.n11 0.575
-R66 Y.n13 Y.n12 0.575
-R67 Y.n5 Y.n4 0.573
-R68 Y.n4 Y.n3 0.573
-R69 Y Y.n7 0.422
-C4 vdd gnd 2.081640fF
-C5 Y.t7 gnd 0.069243fF
-C6 Y.t5 gnd 0.069243fF
-C7 Y.t2 gnd 0.069243fF
-C8 Y.t0 gnd 0.069243fF
-C9 Y.t6 gnd 0.069243fF
-C10 Y.t4 gnd 0.069243fF
-C11 Y.t3 gnd 0.069243fF
-C12 Y.t1 gnd 0.069243fF
-C13 Y.t13 gnd 0.023081fF
-C14 Y.t11 gnd 0.023081fF
-C15 Y.t8 gnd 0.023081fF
-C16 Y.t14 gnd 0.023081fF
-C17 Y.t12 gnd 0.023081fF
-C18 Y.t10 gnd 0.023081fF
-C19 Y.t9 gnd 0.023081fF
-C20 Y.t15 gnd 0.023081fF
-C21 a_n8_115.t5 gnd 0.142504fF
-C22 a_n8_115.t17 gnd 0.142504fF
-C23 a_n8_115.t12 gnd 0.142504fF
-C24 a_n8_115.t7 gnd 0.142504fF
-C25 a_n8_115.t2 gnd 0.142504fF
-C26 a_n8_115.t15 gnd 0.142504fF
-C27 a_n8_115.t10 gnd 0.157373fF
-C28 a_n8_115.t11 gnd 0.058583fF
-C29 a_n8_115.t6 gnd 0.058583fF
-C30 a_n8_115.t3 gnd 0.058583fF
-C31 a_n8_115.t14 gnd 0.073846fF
-C32 a_n8_115.t9 gnd 0.143922fF
-C33 a_n8_115.t13 gnd 0.058583fF
-C34 a_n8_115.t8 gnd 0.058583fF
-C35 a_n8_115.t4 gnd 0.058583fF
-C36 a_n8_115.t16 gnd 0.058583fF
-C37 a_n8_115.t1 gnd 0.247104fF
-C38 a_n8_115.t0 gnd 0.501028fF
-C39 A.t1 gnd 0.362901fF
-C40 A.t0 gnd 0.183653fF
-.ends
diff --git a/cdl/BUFXL.cdl b/cdl/BUFXL.cdl
deleted file mode 100644
index 9afef1b..0000000
--- a/cdl/BUFXL.cdl
+++ /dev/null
@@ -1,37 +0,0 @@
-* SPICE3 file created from BUFXL.ext - technology: EFS8A
-
-.subckt BUFXL A Y
-M1000 gnd A.t0 a_n8_115.t1 gnd nshort w=0.64u l=0.15u
-+  ad=0.0896p pd=0.92u as=0.1696p ps=1.81u
-M1001 Y.t0 a_n8_115.t2 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.231p ps=1.93u
-M1002 Y.t1 a_n8_115.t3 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.0896p ps=0.92u
-M1003 vdd A.t1 a_n8_115.t0 vdd pshort w=1.65u l=0.15u
-+  ad=0.231p pd=1.93u as=0.43725p ps=3.83u
-C0 m1_n35_1379# Y 0.026952fF
-C1 m1_n35_0# Y 0.047670fF
-C2 m1_n35_1379# m1_n35_0# 0.049041fF
-C3 vdd Y 0.001942fF
-R0 A.n0 A.t1 913.121
-R1 A.n0 A.t0 615.887
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n0 a_n8_115.t2 784.588
-R6 a_n8_115.n0 a_n8_115.t3 744.421
-R7 a_n8_115.n1 a_n8_115.t1 277.288
-R8 a_n8_115.t0 a_n8_115.n1 235.561
-R9 a_n8_115.n1 a_n8_115.n0 25.8
-R10 Y Y.t0 257.317
-R11 Y Y.t1 200.622
-C4 vdd gnd 0.677160fF
-C5 Y.t0 gnd 0.696532fF
-C6 Y.t1 gnd 0.296755fF
-C7 a_n8_115.t2 gnd 0.278230fF
-C8 a_n8_115.t3 gnd 0.196009fF
-C9 a_n8_115.t1 gnd 0.441703fF
-C10 a_n8_115.t0 gnd 0.731352fF
-C11 A.t1 gnd 0.358777fF
-C12 A.t0 gnd 0.195247fF
-.ends
diff --git a/cdl/CLKBUFX1.cdl b/cdl/CLKBUFX1.cdl
deleted file mode 100644
index 26ff1f5..0000000
--- a/cdl/CLKBUFX1.cdl
+++ /dev/null
@@ -1,37 +0,0 @@
-* SPICE3 file created from CLKBUFX1.ext - technology: EFS8A
-
-.subckt CLKBUFX1 A Y
-M1000 gnd A.t0 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.265p ps=2.53u
-M1001 Y.t0 a_n8_115.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.28u
-M1002 Y.t1 a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.14p ps=1.28u
-M1003 vdd A.t1 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-C0 m1_n35_1379# Y 0.026952fF
-C1 m1_n35_0# Y 0.047670fF
-C2 m1_n35_1379# m1_n35_0# 0.049041fF
-C3 vdd Y 0.001326fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 558.047
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n0 a_n8_115.t3 686.581
-R6 a_n8_115.n0 a_n8_115.t2 567.688
-R7 a_n8_115.n1 a_n8_115.t1 255.638
-R8 a_n8_115.t0 a_n8_115.n1 179.239
-R9 a_n8_115.n1 a_n8_115.n0 25.8
-R10 Y Y.t0 200.995
-R11 Y Y.t1 178.972
-C4 vdd gnd 0.677160fF
-C5 Y.t0 gnd 0.845700fF
-C6 Y.t1 gnd 0.315624fF
-C7 a_n8_115.t2 gnd 0.236188fF
-C8 a_n8_115.t3 gnd 0.150867fF
-C9 a_n8_115.t1 gnd 0.400275fF
-C10 a_n8_115.t0 gnd 0.811599fF
-C11 A.t1 gnd 0.241886fF
-C12 A.t0 gnd 0.122411fF
-.ends
diff --git a/cdl/CLKINVX1.cdl b/cdl/CLKINVX1.cdl
deleted file mode 100644
index 2b5062f..0000000
--- a/cdl/CLKINVX1.cdl
+++ /dev/null
@@ -1,23 +0,0 @@
-* SPICE3 file created from CLKINVX1.ext - technology: EFS8A
-
-.subckt CLKINVX1 A Y
-M1000 Y.t1 A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.265p ps=2.53u
-M1001 Y.t0 A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.795p ps=6.53u
-C0 m1_n35_1379# Y 0.026952fF
-C1 m1_n35_0# Y 0.047670fF
-C2 A Y 0.013384fF
-C3 m1_n35_1379# m1_n35_0# 0.033951fF
-C4 vdd Y 0.001338fF
-R0 A.n0 A.t1 824.755
-R1 A.n0 A.t0 429.514
-R2 A A.n0 7.5
-R3 Y Y.t0 200.833
-R4 Y Y.t1 179.134
-C5 vdd gnd 0.474240fF
-C6 Y.t0 gnd 0.064007fF
-C7 Y.t1 gnd 0.023907fF
-C8 A.t1 gnd 0.049713fF
-C9 A.t0 gnd 0.019559fF
-.ends
diff --git a/cdl/CLKINVX2.cdl b/cdl/CLKINVX2.cdl
deleted file mode 100644
index c9f727e..0000000
--- a/cdl/CLKINVX2.cdl
+++ /dev/null
@@ -1,39 +0,0 @@
-* SPICE3 file created from CLKINVX2.ext - technology: EFS8A
-
-.subckt CLKINVX2 A Y
-M1000 Y.t3 A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.265p ps=2.53u
-M1001 vdd A.t1 Y.t1 vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.28u
-M1002 gnd A.t2 Y.t2 gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.14p ps=1.28u
-M1003 Y.t0 A.t3 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-C0 m1_n35_0# Y 0.047670fF
-C1 A Y 0.033891fF
-C2 m1_n35_1379# m1_n35_0# 0.049041fF
-C3 vdd Y 0.000538fF
-C4 m1_n35_1379# Y 0.026952fF
-R0 A.n0 A.t1 644.273
-R1 A.n0 A.t3 506.1
-R2 A.n1 A.t2 475.572
-R3 A.n1 A.t0 413.447
-R4 A.n2 A.n0 270.455
-R5 A.n2 A.n1 16.066
-R6 A A.n2 7.5
-R7 Y Y.n0 191.64
-R8 Y Y.n1 162.334
-R9 Y.n1 Y.t2 16.8
-R10 Y.n1 Y.t3 16.8
-R11 Y.n0 Y.t1 9.193
-R12 Y.n0 Y.t0 9.193
-C5 vdd gnd 0.674880fF
-C6 Y.t1 gnd 0.012331fF
-C7 Y.t0 gnd 0.012331fF
-C8 Y.t2 gnd 0.004110fF
-C9 Y.t3 gnd 0.004110fF
-C10 A.t3 gnd 0.026812fF
-C11 A.t1 gnd 0.029684fF
-C12 A.t2 gnd 0.013943fF
-C13 A.t0 gnd 0.012612fF
-.ends
diff --git a/cdl/CLKINVX4.cdl b/cdl/CLKINVX4.cdl
deleted file mode 100644
index 0a7f948..0000000
--- a/cdl/CLKINVX4.cdl
+++ /dev/null
@@ -1,73 +0,0 @@
-* SPICE3 file created from CLKINVX4.ext - technology: EFS8A
-
-.subckt CLKINVX4 A Y
-M1000 Y.t3 A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.2025p ps=1.905u
-M1001 gnd A.t1 Y.t2 gnd nshort w=1u l=0.15u
-+  ad=0.2025p pd=1.905u as=0.14p ps=1.28u
-M1002 Y.t7 A.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.6075p ps=4.905u
-M1003 Y.t1 A.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.2025p ps=1.905u
-M1004 vdd A.t4 Y.t6 vdd pshort w=3u l=0.15u
-+  ad=0.6075p pd=4.905u as=0.42p ps=3.28u
-M1005 gnd A.t5 Y.t0 gnd nshort w=1u l=0.15u
-+  ad=0.2025p pd=1.905u as=0.14p ps=1.28u
-M1006 Y.t5 A.t6 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.6075p ps=4.905u
-M1007 vdd A.t7 Y.t4 vdd pshort w=3u l=0.15u
-+  ad=0.6075p pd=4.905u as=0.42p ps=3.28u
-C0 m1_n35_1379# m1_n35_0# 0.079220fF
-C1 m1_n35_1379# Y 0.122391fF
-C2 m1_n35_0# Y 0.210435fF
-C3 vdd Y 0.005614fF
-C4 A Y 0.081784fF
-R0 A.n0 A.t7 644.273
-R1 A.n3 A.t1 538.232
-R2 A.n2 A.t6 506.1
-R3 A.n0 A.t2 506.1
-R4 A.n1 A.t4 506.1
-R5 A.n5 A.t0 413.447
-R6 A.n4 A.t5 400.059
-R7 A.n3 A.t3 400.059
-R8 A.n6 A.n2 270.455
-R9 A.n4 A.n3 138.173
-R10 A.n1 A.n0 138.173
-R11 A.n2 A.n1 138.173
-R12 A.n5 A.n4 75.513
-R13 A.n6 A.n5 16.066
-R14 A A.n6 7.5
-R15 Y.n1 Y.n0 191.147
-R16 Y.n3 Y.n2 191.147
-R17 Y.n7 Y.n6 161.723
-R18 Y.n5 Y.n4 161.723
-R19 Y.n6 Y.t0 16.8
-R20 Y.n6 Y.t3 16.8
-R21 Y.n4 Y.t2 16.8
-R22 Y.n4 Y.t1 16.8
-R23 Y.n0 Y.t4 9.193
-R24 Y.n0 Y.t7 9.193
-R25 Y.n2 Y.t6 9.193
-R26 Y.n2 Y.t5 9.193
-R27 Y.n3 Y.n1 0.575
-R28 Y.n7 Y.n5 0.575
-R29 Y Y.n7 0.562
-R30 Y Y.n3 0.444
-C5 vdd gnd 1.076160fF
-C6 Y.t4 gnd 0.021135fF
-C7 Y.t7 gnd 0.021135fF
-C8 Y.t6 gnd 0.021135fF
-C9 Y.t5 gnd 0.021135fF
-C10 Y.t2 gnd 0.007045fF
-C11 Y.t1 gnd 0.007045fF
-C12 Y.t0 gnd 0.007045fF
-C13 Y.t3 gnd 0.007045fF
-C14 A.t6 gnd 0.018512fF
-C15 A.t4 gnd 0.018512fF
-C16 A.t2 gnd 0.018512fF
-C17 A.t7 gnd 0.020495fF
-C18 A.t5 gnd 0.008516fF
-C19 A.t3 gnd 0.008516fF
-C20 A.t1 gnd 0.010526fF
-C21 A.t0 gnd 0.008708fF
-.ends
diff --git a/cdl/DECAPX1.cdl b/cdl/DECAPX1.cdl
deleted file mode 100644
index 1ceacef..0000000
--- a/cdl/DECAPX1.cdl
+++ /dev/null
@@ -1,9 +0,0 @@
-* SPICE3 file created from DECAPX1.ext - technology: EFS8A
-
-M1000 gnd a_45_80# gnd gnd nshort w=2u l=0.15u
-+  ad=0.53p pd=4.53u as=0.53p ps=4.53u
-M1001 vdd a_45_80# vdd vdd pshort w=2u l=0.15u
-+  ad=0.53p pd=4.53u as=0.53p ps=4.53u
-C0 m1_n35_1379# m1_n35_0# 0.033951fF
-C1 a_45_80# gnd 0.102415fF
-C2 vdd gnd 0.474240fF
diff --git a/cdl/DECAPXL.cdl b/cdl/DECAPXL.cdl
deleted file mode 100644
index 55a4373..0000000
--- a/cdl/DECAPXL.cdl
+++ /dev/null
@@ -1,9 +0,0 @@
-* SPICE3 file created from DECAPXL.ext - technology: EFS8A
-
-M1000 gnd a_45_80# gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.265p ps=2.53u
-M1001 vdd a_45_80# vdd vdd pshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.265p ps=2.53u
-C0 m1_n35_1379# m1_n35_0# 0.033951fF
-C1 a_45_80# gnd 0.185315fF
-C2 vdd gnd 0.474240fF
diff --git a/cdl/DFFNX1.cdl b/cdl/DFFNX1.cdl
deleted file mode 100644
index edd3105..0000000
--- a/cdl/DFFNX1.cdl
+++ /dev/null
@@ -1,158 +0,0 @@
-* SPICE3 file created from DFFNX1.ext - technology: EFS8A
-
-.subckt DFFNX1 D Q QN CK
-M1000 a_583_115# CK.t0 a_511_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1001 gnd a_11_624.t4 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.153889p pd=1.41889u as=0.265p ps=2.53u
-M1002 a_353_725# CK.t1 a_11_624.t2 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1003 a_11_624.t1 a_203_619# a_161_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1004 a_745_89# a_583_115# gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.153889p ps=1.41889u
-M1005 Q.t0 QN.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.461667p ps=3.64111u
-M1006 a_703_115# CK.t2 a_583_115# gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1007 a_583_115# a_203_619# a_511_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1008 a_203_619# CK.t3 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.461667p ps=3.64111u
-M1009 a_11_624.t3 CK.t4 a_161_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1010 a_353_115# a_203_619# a_11_624.t0 gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1011 a_511_725# a_n8_115.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.461667p ps=3.64111u
-M1012 Q.t1 QN.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.153889p ps=1.41889u
-M1013 vdd a_745_89# QN.t0 vdd pshort w=3u l=0.15u
-+  ad=0.461667p pd=3.64111u as=0.795p ps=6.53u
-M1014 a_161_725# D.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.461667p ps=3.64111u
-M1015 a_203_619# CK.t5 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.153889p ps=1.41889u
-M1016 vdd a_745_89# a_703_725# vdd pshort w=3u l=0.15u
-+  ad=0.461667p pd=3.64111u as=0.315p ps=3.21u
-M1017 a_511_115# a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.153889p ps=1.41889u
-M1018 gnd a_745_89# QN.t1 gnd nshort w=1u l=0.15u
-+  ad=0.153889p pd=1.41889u as=0.265p ps=2.53u
-M1019 vdd a_n8_115.t4 a_353_725# vdd pshort w=3u l=0.15u
-+  ad=0.461667p pd=3.64111u as=0.315p ps=3.21u
-M1020 a_161_115# D.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.153889p ps=1.41889u
-M1021 vdd a_11_624.t5 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.461667p pd=3.64111u as=0.795p ps=6.53u
-M1022 gnd a_745_89# a_703_115# gnd nshort w=1u l=0.15u
-+  ad=0.153889p pd=1.41889u as=0.105p ps=1.21u
-M1023 a_745_89# a_583_115# vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.461667p ps=3.64111u
-M1024 gnd a_n8_115.t5 a_353_115# gnd nshort w=1u l=0.15u
-+  ad=0.153889p pd=1.41889u as=0.105p ps=1.21u
-M1025 a_703_725# a_203_619# a_583_115# vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-C0 m1_n35_1379# QN 0.043190fF
-C1 a_745_89# CK 1.140550fF
-C2 a_203_619# D 0.307591fF
-C3 a_203_619# a_583_115# 0.652731fF
-C4 QN Q 1.498410fF
-C5 D CK 0.547298fF
-C6 m1_n35_0# QN 0.100829fF
-C7 m1_n35_1379# Q 0.026952fF
-C8 m1_n35_1379# m1_n35_0# 0.248977fF
-C9 a_583_115# CK 0.331428fF
-C10 a_745_89# QN 1.127450fF
-C11 a_745_89# m1_n35_1379# 0.032426fF
-C12 vdd Q 0.001326fF
-C13 vdd a_745_89# 0.001338fF
-C14 m1_n35_0# Q 0.047670fF
-C15 D QN 0.025622fF
-C16 a_583_115# QN 0.231554fF
-C17 a_745_89# Q 0.351014fF
-C18 a_583_115# m1_n35_1379# 0.026111fF
-C19 a_203_619# CK 1.025630fF
-C20 a_745_89# m1_n35_0# 0.097208fF
-C21 vdd a_583_115# 0.001219fF
-C22 a_583_115# Q 0.120162fF
-C23 a_745_89# D 0.077652fF
-C24 a_583_115# m1_n35_0# 0.084075fF
-C25 a_203_619# QN 0.257302fF
-C26 a_203_619# m1_n35_1379# 0.044365fF
-C27 a_745_89# a_583_115# 0.608448fF
-C28 CK QN 0.140632fF
-C29 a_583_115# D 0.033983fF
-C30 a_203_619# Q 0.158003fF
-C31 a_203_619# m1_n35_0# 0.137136fF
-C32 a_203_619# a_745_89# 0.983039fF
-R0 CK.n0 CK.t3 937.411
-R1 CK.n2 CK.t0 803.333
-R2 CK.n1 CK.t1 803.333
-R3 CK.n1 CK.t4 642.666
-R4 CK.n2 CK.n1 369.533
-R5 CK.n3 CK.t2 300.981
-R6 CK.n0 CK.t5 289.129
-R7 CK.n3 CK.n2 255.995
-R8 CK CK.n3 77.47
-R9 CK CK.n0 8.935
-R10 a_11_624.n1 a_11_624.t4 674.53
-R11 a_11_624.n1 a_11_624.t5 558.746
-R12 a_11_624.n3 a_11_624.n2 157.971
-R13 a_11_624.n2 a_11_624.n1 104.241
-R14 a_11_624.n2 a_11_624.n0 54.501
-R15 a_11_624.n0 a_11_624.t0 19.539
-R16 a_11_624.n0 a_11_624.t3 19.011
-R17 a_11_624.n3 a_11_624.t2 14.775
-R18 a_11_624.t1 a_11_624.n3 14.775
-R19 a_n8_115.n0 a_n8_115.t2 592.681
-R20 a_n8_115.n0 a_n8_115.t4 592.681
-R21 a_n8_115.n1 a_n8_115.t5 319.547
-R22 a_n8_115.n1 a_n8_115.t3 319.547
-R23 a_n8_115.t0 a_n8_115.n3 289.939
-R24 a_n8_115.n3 a_n8_115.n2 176.094
-R25 a_n8_115.n2 a_n8_115.n0 166.449
-R26 a_n8_115.n3 a_n8_115.t1 67.717
-R27 a_n8_115.n2 a_n8_115.n1 13.653
-R28 QN.n0 QN.t3 686.581
-R29 QN.n0 QN.t2 567.688
-R30 QN.n1 QN.t1 255.638
-R31 QN.n1 QN.t0 179.239
-R32 QN QN.n0 25.441
-R33 QN QN.n1 0.358
-R34 Q Q.t0 200.877
-R35 Q Q.t1 179.09
-R36 D.n0 D.t0 824.755
-R37 D.n0 D.t1 429.514
-R38 D D.n0 7.5
-C33 a_583_115# gnd 0.150773fF
-C34 a_745_89# gnd 0.258597fF
-C35 a_203_619# gnd 0.207187fF
-C36 vdd gnd 3.331080fF
-C37 D.t0 gnd 0.712394fF
-C38 D.t1 gnd 0.280285fF
-C39 Q.t0 gnd 1.292190fF
-C40 Q.t1 gnd 0.482543fF
-C41 QN.t2 gnd 0.392149fF
-C42 QN.t3 gnd 0.250488fF
-C43 QN.t1 gnd 0.664587fF
-C44 QN.t0 gnd 1.347520fF
-C45 a_n8_115.t1 gnd 0.387465fF
-C46 a_n8_115.t2 gnd 0.454461fF
-C47 a_n8_115.t4 gnd 0.454461fF
-C48 a_n8_115.t3 gnd 0.176994fF
-C49 a_n8_115.t5 gnd 0.176994fF
-C50 a_n8_115.t0 gnd 1.720190fF
-C51 a_11_624.t2 gnd 0.338297fF
-C52 a_11_624.t3 gnd 0.116720fF
-C53 a_11_624.t0 gnd 0.117878fF
-C54 a_11_624.t5 gnd 0.338330fF
-C55 a_11_624.t4 gnd 0.222061fF
-C56 a_11_624.t1 gnd 0.338297fF
-C57 CK.t3 gnd 0.632627fF
-C58 CK.t5 gnd 0.184356fF
-C59 CK.t0 gnd 0.577341fF
-C60 CK.t1 gnd 0.577341fF
-C61 CK.t4 gnd 0.306850fF
-C62 CK.t2 gnd 0.186948fF
-.ends
diff --git a/cdl/DFFNXL.cdl b/cdl/DFFNXL.cdl
deleted file mode 100644
index 9021996..0000000
--- a/cdl/DFFNXL.cdl
+++ /dev/null
@@ -1,158 +0,0 @@
-* SPICE3 file created from DFFNXL.ext - technology: EFS8A
-
-.subckt DFFNXL D Q QN CK
-M1000 a_583_115# CK.t0 a_511_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1001 gnd a_11_624.t4 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.155097p pd=1.45531u as=0.265p ps=2.53u
-M1002 a_353_725# CK.t1 a_11_624.t2 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1003 a_11_624.t1 a_203_619# a_161_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1004 a_745_89# a_583_115# gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.155097p ps=1.45531u
-M1005 Q.t0 QN.t2 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.256463p ps=2.04179u
-M1006 a_703_115# CK.t2 a_583_115# gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1007 a_583_115# a_203_619# a_511_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1008 a_203_619# CK.t3 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.466296p ps=3.71235u
-M1009 a_11_624.t3 CK.t4 a_161_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1010 a_353_115# a_203_619# a_11_624.t0 gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1011 a_511_725# a_n8_115.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.466296p ps=3.71235u
-M1012 Q.t1 QN.t3 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.0992618p ps=0.931401u
-M1013 vdd a_745_89# QN.t0 vdd pshort w=1.65u l=0.15u
-+  ad=0.256463p pd=2.04179u as=0.43725p ps=3.83u
-M1014 a_161_725# D.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.466296p ps=3.71235u
-M1015 a_203_619# CK.t5 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.155097p ps=1.45531u
-M1016 vdd a_745_89# a_703_725# vdd pshort w=3u l=0.15u
-+  ad=0.466296p pd=3.71235u as=0.315p ps=3.21u
-M1017 a_511_115# a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.155097p ps=1.45531u
-M1018 gnd a_745_89# QN.t1 gnd nshort w=0.64u l=0.15u
-+  ad=0.0992618p pd=0.931401u as=0.1696p ps=1.81u
-M1019 vdd a_n8_115.t4 a_353_725# vdd pshort w=3u l=0.15u
-+  ad=0.466296p pd=3.71235u as=0.315p ps=3.21u
-M1020 a_161_115# D.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.155097p ps=1.45531u
-M1021 vdd a_11_624.t5 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.466296p pd=3.71235u as=0.795p ps=6.53u
-M1022 gnd a_745_89# a_703_115# gnd nshort w=1u l=0.15u
-+  ad=0.155097p pd=1.45531u as=0.105p ps=1.21u
-M1023 a_745_89# a_583_115# vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.466296p ps=3.71235u
-M1024 gnd a_n8_115.t5 a_353_115# gnd nshort w=1u l=0.15u
-+  ad=0.155097p pd=1.45531u as=0.105p ps=1.21u
-M1025 a_703_725# a_203_619# a_583_115# vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-C0 m1_n35_0# QN 0.100829fF
-C1 m1_n35_1379# Q 0.026952fF
-C2 D CK 0.547155fF
-C3 a_583_115# D 0.033983fF
-C4 a_745_89# CK 1.121820fF
-C5 a_203_619# Q 0.158003fF
-C6 a_203_619# m1_n35_1379# 0.044365fF
-C7 m1_n35_0# Q 0.047670fF
-C8 D QN 0.025622fF
-C9 m1_n35_1379# m1_n35_0# 0.248977fF
-C10 a_745_89# a_583_115# 0.608448fF
-C11 vdd a_745_89# 0.001338fF
-C12 a_583_115# CK 0.335149fF
-C13 a_745_89# QN 1.512200fF
-C14 a_203_619# m1_n35_0# 0.137136fF
-C15 CK QN 0.141073fF
-C16 vdd a_583_115# 0.001219fF
-C17 a_583_115# QN 0.231554fF
-C18 a_745_89# Q 0.351014fF
-C19 a_745_89# m1_n35_1379# 0.032426fF
-C20 a_203_619# D 0.307591fF
-C21 a_203_619# a_745_89# 0.983039fF
-C22 a_583_115# Q 0.120162fF
-C23 vdd Q 0.001942fF
-C24 a_583_115# m1_n35_1379# 0.026111fF
-C25 a_203_619# CK 1.024570fF
-C26 a_745_89# m1_n35_0# 0.097208fF
-C27 QN Q 1.498410fF
-C28 m1_n35_1379# QN 0.043190fF
-C29 a_203_619# a_583_115# 0.652731fF
-C30 a_745_89# D 0.077652fF
-C31 a_583_115# m1_n35_0# 0.084075fF
-C32 a_203_619# QN 0.257302fF
-R0 CK.n0 CK.t3 932.219
-R1 CK.n2 CK.t0 803.333
-R2 CK.n1 CK.t1 803.333
-R3 CK.n1 CK.t4 642.666
-R4 CK.n2 CK.n1 369.533
-R5 CK.n3 CK.t2 300.981
-R6 CK.n0 CK.t5 293.928
-R7 CK.n3 CK.n2 255.995
-R8 CK CK.n3 77.47
-R9 CK CK.n0 8.935
-R10 a_11_624.n1 a_11_624.t4 674.53
-R11 a_11_624.n1 a_11_624.t5 558.746
-R12 a_11_624.n3 a_11_624.n2 157.971
-R13 a_11_624.n2 a_11_624.n1 104.241
-R14 a_11_624.n2 a_11_624.n0 54.501
-R15 a_11_624.n0 a_11_624.t0 19.539
-R16 a_11_624.n0 a_11_624.t3 19.011
-R17 a_11_624.n3 a_11_624.t2 14.775
-R18 a_11_624.t1 a_11_624.n3 14.775
-R19 a_n8_115.n0 a_n8_115.t2 592.681
-R20 a_n8_115.n0 a_n8_115.t4 592.681
-R21 a_n8_115.n1 a_n8_115.t5 319.547
-R22 a_n8_115.n1 a_n8_115.t3 319.547
-R23 a_n8_115.t0 a_n8_115.n3 289.939
-R24 a_n8_115.n3 a_n8_115.n2 176.094
-R25 a_n8_115.n2 a_n8_115.n0 166.449
-R26 a_n8_115.n3 a_n8_115.t1 67.717
-R27 a_n8_115.n2 a_n8_115.n1 13.653
-R28 QN.n0 QN.t2 784.588
-R29 QN.n0 QN.t3 744.421
-R30 QN.n1 QN.t1 277.288
-R31 QN QN.t0 235.202
-R32 QN.n1 QN.n0 25.8
-R33 QN QN.n1 0.358
-R34 Q Q.t0 257.199
-R35 Q Q.t1 200.74
-R36 D.n0 D.t0 824.755
-R37 D.n0 D.t1 429.514
-R38 D D.n0 7.5
-C33 a_583_115# gnd 0.150773fF
-C34 a_745_89# gnd 0.329477fF
-C35 a_203_619# gnd 0.207234fF
-C36 vdd gnd 3.331080fF
-C37 D.t0 gnd 0.712335fF
-C38 D.t1 gnd 0.280262fF
-C39 Q.t0 gnd 1.063580fF
-C40 Q.t1 gnd 0.453476fF
-C41 QN.t2 gnd 0.431779fF
-C42 QN.t3 gnd 0.304183fF
-C43 QN.t1 gnd 0.685471fF
-C44 QN.t0 gnd 1.134230fF
-C45 a_n8_115.t1 gnd 0.387467fF
-C46 a_n8_115.t2 gnd 0.454463fF
-C47 a_n8_115.t4 gnd 0.454463fF
-C48 a_n8_115.t3 gnd 0.176995fF
-C49 a_n8_115.t5 gnd 0.176995fF
-C50 a_n8_115.t0 gnd 1.720200fF
-C51 a_11_624.t2 gnd 0.338289fF
-C52 a_11_624.t3 gnd 0.116717fF
-C53 a_11_624.t0 gnd 0.117875fF
-C54 a_11_624.t5 gnd 0.338322fF
-C55 a_11_624.t4 gnd 0.222056fF
-C56 a_11_624.t1 gnd 0.338289fF
-C57 CK.t3 gnd 0.631681fF
-C58 CK.t5 gnd 0.184201fF
-C59 CK.t0 gnd 0.574821fF
-C60 CK.t1 gnd 0.574821fF
-C61 CK.t4 gnd 0.305511fF
-C62 CK.t2 gnd 0.186133fF
-.ends
diff --git a/cdl/DFFRX1.cdl b/cdl/DFFRX1.cdl
deleted file mode 100644
index 27fd37b..0000000
--- a/cdl/DFFRX1.cdl
+++ /dev/null
@@ -1,215 +0,0 @@
-* SPICE3 file created from DFFRX1.ext - technology: EFS8A
-
-.subckt DFFRX1 CK Q RN D QN
-M1000 a_843_89# a_21_384.t2 a_1235_725# vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.315p ps=3.21u
-M1001 a_n8_725.t1 a_21_384.t3 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.0896p pd=0.92u as=0.109079p ps=1.0097u
-M1002 a_801_115# a_301_89# a_681_115# gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1003 gnd a_843_89# QN.t1 gnd nshort w=1u l=0.15u
-+  ad=0.170436p pd=1.57765u as=0.265p ps=2.53u
-M1004 a_681_115# CK.t0 a_609_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1005 a_451_115# CK.t1 a_117_624.t1 gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1006 a_301_89# CK.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.28u
-M1007 a_117_624.t3 a_301_89# a_259_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1008 a_609_725# a_n8_725.t3 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.28u
-M1009 a_259_725# D.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.28u
-M1010 a_301_89# CK.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.170436p ps=1.57765u
-M1011 vdd a_843_89# a_801_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.315p ps=3.21u
-M1012 a_1235_725# a_681_115# vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.28u
-M1013 a_609_115# a_n8_725.t4 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.170436p ps=1.57765u
-M1014 gnd a_21_384.t4 a_843_89# gnd nshort w=0.64u l=0.15u
-+  ad=0.109079p pd=1.0097u as=0.0896p ps=0.92u
-M1015 vdd a_n8_725.t5 a_451_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.315p ps=3.21u
-M1016 Q.t0 QN.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.28u
-M1017 a_259_115# D.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.170436p ps=1.57765u
-M1018 gnd a_843_89# a_801_115# gnd nshort w=1u l=0.15u
-+  ad=0.42p pd=3.28u as=0.51p ps=3.34u
-M1019 vdd RN.t0 a_21_384.t1 vdd pshort w=3u l=0.15u
-+  ad=0.170436p pd=1.57765u as=0.105p ps=1.21u
-M1020 gnd a_117_624.t5 a_n8_725.t2 gnd nshort w=0.64u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-M1021 gnd a_n8_725.t6 a_451_115# gnd nshort w=1u l=0.15u
-+  ad=0.109079p pd=1.0097u as=0.0896p ps=0.92u
-M1022 a_843_89# a_681_115# gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.170436p pd=1.57765u as=0.105p ps=1.21u
-M1023 Q.t1 QN.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.0896p pd=0.92u as=0.109079p ps=1.0097u
-M1024 a_75_725.t0 a_21_384.t5 a_n8_725.t0 vdd pshort w=3u l=0.15u
-+  ad=0.265p pd=2.53u as=0.170436p ps=1.57765u
-M1025 vdd a_843_89# QN.t0 vdd pshort w=3u l=0.15u
-+  ad=0.51p pd=3.34u as=0.795p ps=6.53u
-M1026 a_681_115# a_301_89# a_609_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-M1027 a_801_725# CK.t4 a_681_115# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1028 a_117_624.t0 CK.t5 a_259_725# vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1029 a_451_725# a_301_89# a_117_624.t2 vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1030 gnd RN.t1 a_21_384.t0 gnd nshort w=1u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-C0 RN QN 0.320223fF
-C1 CK Q 0.040951fF
-C2 D CK 0.350660fF
-C3 m1_n35_0# RN 0.087082fF
-C4 m1_n35_1379# QN 0.041280fF
-C5 a_681_115# CK 0.391492fF
-C6 a_843_89# RN 0.592553fF
-C7 m1_n35_1379# m1_n35_0# 0.298018fF
-C8 vdd Q 0.001326fF
-C9 a_843_89# m1_n35_1379# 0.032489fF
-C10 vdd a_681_115# 0.001219fF
-C11 RN Q 0.148908fF
-C12 m1_n35_0# QN 0.129338fF
-C13 D RN 0.033983fF
-C14 m1_n35_1379# Q 0.026952fF
-C15 a_681_115# RN 0.771586fF
-C16 a_843_89# QN 0.823317fF
-C17 a_681_115# m1_n35_1379# 0.026111fF
-C18 a_301_89# CK 1.198450fF
-C19 a_843_89# m1_n35_0# 0.050293fF
-C20 vdd a_301_89# 0.001311fF
-C21 QN Q 1.504360fF
-C22 m1_n35_0# Q 0.047670fF
-C23 D QN 0.022050fF
-C24 a_681_115# QN 0.194689fF
-C25 a_843_89# Q 0.244660fF
-C26 a_681_115# m1_n35_0# 0.084075fF
-C27 a_843_89# D 0.073493fF
-C28 a_301_89# RN 0.836447fF
-C29 a_843_89# a_681_115# 0.319529fF
-C30 a_301_89# m1_n35_1379# 0.031888fF
-C31 CK RN 0.353413fF
-C32 a_681_115# Q 0.094815fF
-C33 m1_n35_1379# CK 0.022603fF
-C34 a_681_115# D 0.030745fF
-C35 a_301_89# QN 0.222428fF
-C36 a_301_89# m1_n35_0# 0.100363fF
-C37 a_301_89# a_843_89# 0.740354fF
-C38 CK QN 0.129713fF
-C39 m1_n35_1379# RN 0.018753fF
-C40 m1_n35_0# CK 0.050365fF
-C41 a_301_89# Q 0.135648fF
-C42 a_843_89# CK 0.948925fF
-C43 a_301_89# D 0.504230fF
-C44 a_301_89# a_681_115# 0.641152fF
-C45 vdd a_843_89# 0.001325fF
-R0 a_21_384.n1 a_21_384.t5 953.288
-R1 a_21_384.n0 a_21_384.t4 744.421
-R2 a_21_384.n0 a_21_384.t2 567.563
-R3 a_21_384.n1 a_21_384.t3 358.821
-R4 a_21_384.t1 a_21_384.n3 200.34
-R5 a_21_384.n2 a_21_384.n0 102.537
-R6 a_21_384.n3 a_21_384.t0 93.893
-R7 a_21_384.n2 a_21_384.n1 68.502
-R8 a_21_384.n3 a_21_384.n2 0.196
-R9 a_n8_725.n1 a_n8_725.t3 592.681
-R10 a_n8_725.n1 a_n8_725.t5 592.681
-R11 a_n8_725.n2 a_n8_725.t6 319.547
-R12 a_n8_725.n2 a_n8_725.t4 319.547
-R13 a_n8_725.t0 a_n8_725.n4 302.497
-R14 a_n8_725.n4 a_n8_725.n3 180.399
-R15 a_n8_725.n3 a_n8_725.n1 166.449
-R16 a_n8_725.n4 a_n8_725.n0 63.117
-R17 a_n8_725.n0 a_n8_725.t2 26.25
-R18 a_n8_725.n0 a_n8_725.t1 26.25
-R19 a_n8_725.n3 a_n8_725.n2 13.653
-R20 QN.n0 QN.t3 686.581
-R21 QN.n0 QN.t2 567.688
-R22 QN.n1 QN.t1 227.226
-R23 QN QN.t0 178.88
-R24 QN.n1 QN.n0 25.8
-R25 QN QN.n1 0.358
-R26 CK.n3 CK.t3 670.704
-R27 CK.n0 CK.t5 650.679
-R28 CK.n2 CK.t4 604.032
-R29 CK.n3 CK.t2 561.009
-R30 CK.n0 CK.t1 473.198
-R31 CK.n1 CK.t0 359.792
-R32 CK CK.n2 91.052
-R33 CK.n1 CK.n0 78.941
-R34 CK.n2 CK.n1 34.447
-R35 CK CK.n3 7.5
-R36 a_117_624.n1 a_117_624.t5 743.369
-R37 a_117_624.n1 a_117_624.t4 566.636
-R38 a_117_624.n3 a_117_624.n2 157.971
-R39 a_117_624.n2 a_117_624.n1 101.37
-R40 a_117_624.n2 a_117_624.n0 54.501
-R41 a_117_624.n0 a_117_624.t1 19.539
-R42 a_117_624.n0 a_117_624.t3 19.011
-R43 a_117_624.n3 a_117_624.t2 14.775
-R44 a_117_624.t0 a_117_624.n3 14.775
-R45 D.n0 D.t0 824.755
-R46 D.n0 D.t1 429.514
-R47 D D.n0 7.5
-R48 Q Q.t0 201.083
-R49 Q Q.t1 178.884
-R50 a_75_725.n5 a_75_725.n3 592.681
-R51 a_75_725.n5 a_75_725.n4 592.681
-R52 a_75_725.n8 a_75_725.n7 319.547
-R53 a_75_725.n8 a_75_725.n6 319.547
-R54 a_75_725.t0 a_75_725.n10 302.497
-R55 a_75_725.n10 a_75_725.n9 180.399
-R56 a_75_725.n9 a_75_725.n5 166.449
-R57 a_75_725.n10 a_75_725.n2 63.117
-R58 a_75_725.n2 a_75_725.n0 26.25
-R59 a_75_725.n2 a_75_725.n1 26.25
-R60 a_75_725.n9 a_75_725.n8 13.653
-R61 RN.n0 RN.t1 686.581
-R62 RN.n0 RN.t0 567.688
-R63 RN RN.n0 7.5
-C46 a_681_115# gnd 0.165695fF
-C47 a_843_89# gnd 0.234842fF
-C48 a_301_89# gnd 0.322380fF
-C49 vdd gnd 4.003680fF
-C50 RN.t0 gnd 3.737800fF
-C51 RN.t1 gnd 2.387550fF
-C52 a_75_725.t0 gnd 0.009829fF
-C53 Q.t0 gnd 1.454510fF
-C54 Q.t1 gnd 0.542612fF
-C55 D.t0 gnd 0.807800fF
-C56 D.t1 gnd 0.317822fF
-C57 a_117_624.t2 gnd 0.475682fF
-C58 a_117_624.t3 gnd 0.164120fF
-C59 a_117_624.t1 gnd 0.165749fF
-C60 a_117_624.t5 gnd 0.285598fF
-C61 a_117_624.t0 gnd 0.475682fF
-C62 CK.t4 gnd 0.587051fF
-C63 CK.t0 gnd 0.272431fF
-C64 CK.t1 gnd 0.401982fF
-C65 CK.t5 gnd 0.641090fF
-C66 CK.t2 gnd 0.562318fF
-C67 CK.t3 gnd 0.368133fF
-C68 QN.t2 gnd 0.430383fF
-C69 QN.t3 gnd 0.274911fF
-C70 QN.t1 gnd 0.714336fF
-C71 QN.t0 gnd 1.478200fF
-C72 a_n8_725.t2 gnd 0.091090fF
-C73 a_n8_725.t1 gnd 0.091090fF
-C74 a_n8_725.t3 gnd 0.704407fF
-C75 a_n8_725.t5 gnd 0.704407fF
-C76 a_n8_725.t4 gnd 0.274338fF
-C77 a_n8_725.t6 gnd 0.274338fF
-C78 a_n8_725.t0 gnd 2.770220fF
-C79 a_21_384.t2 gnd 1.019870fF
-C80 a_21_384.t4 gnd 0.610646fF
-C81 a_21_384.t5 gnd 1.289800fF
-C82 a_21_384.t3 gnd 0.341700fF
-C83 a_21_384.t0 gnd 1.002940fF
-C84 a_21_384.t1 gnd 3.501710fF
-.ends
diff --git a/cdl/DFFRXL.cdl b/cdl/DFFRXL.cdl
deleted file mode 100644
index 69e9214..0000000
--- a/cdl/DFFRXL.cdl
+++ /dev/null
@@ -1,215 +0,0 @@
-* SPICE3 file created from DFFRXL.ext - technology: EFS8A
-
-.subckt DFFRXL CK QN Q RN D
-M1000 a_843_89# a_21_384.t2 a_1235_725# vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.315p ps=3.21u
-M1001 a_n8_725.t1 a_21_384.t3 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.0896p pd=0.92u as=0.110504p ps=1.03675u
-M1002 a_801_115# a_301_89# a_681_115# gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1003 gnd a_843_89# QN.t1 gnd nshort w=0.64u l=0.15u
-+  ad=0.110504p pd=1.03675u as=0.1696p ps=1.81u
-M1004 a_681_115# CK.t0 a_609_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1005 a_451_115# CK.t1 a_117_624.t3 gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1006 a_301_89# CK.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.30769u
-M1007 a_117_624.t1 a_301_89# a_259_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1008 a_609_725# a_n8_725.t3 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.30769u
-M1009 a_259_725# D.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.30769u
-M1010 a_301_89# CK.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.172663p ps=1.61992u
-M1011 vdd a_843_89# a_801_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.30769u as=0.315p ps=3.21u
-M1012 a_1235_725# a_681_115# vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.30769u
-M1013 a_609_115# a_n8_725.t4 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.172663p ps=1.61992u
-M1014 gnd a_21_384.t4 a_843_89# gnd nshort w=0.64u l=0.15u
-+  ad=0.110504p pd=1.03675u as=0.0896p ps=0.92u
-M1015 Q.t0 QN.t2 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.231p ps=1.81923u
-M1016 vdd a_n8_725.t5 a_451_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.30769u as=0.315p ps=3.21u
-M1017 a_259_115# D.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.172663p ps=1.61992u
-M1018 gnd a_843_89# a_801_115# gnd nshort w=1u l=0.15u
-+  ad=0.42p pd=3.30769u as=0.51p ps=3.34u
-M1019 vdd RN.t0 a_21_384.t1 vdd pshort w=3u l=0.15u
-+  ad=0.172663p pd=1.61992u as=0.105p ps=1.21u
-M1020 gnd a_117_624.t5 a_n8_725.t2 gnd nshort w=0.64u l=0.15u
-+  ad=0.42p pd=3.30769u as=0.795p ps=6.53u
-M1021 gnd a_n8_725.t6 a_451_115# gnd nshort w=1u l=0.15u
-+  ad=0.110504p pd=1.03675u as=0.0896p ps=0.92u
-M1022 a_843_89# a_681_115# gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.172663p pd=1.61992u as=0.105p ps=1.21u
-M1023 Q.t1 QN.t3 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.0896p pd=0.92u as=0.110504p ps=1.03675u
-M1024 vdd a_843_89# QN.t0 vdd pshort w=1.65u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.110504p ps=1.03675u
-M1025 a_75_725.t0 a_21_384.t5 a_n8_725.t0 vdd pshort w=3u l=0.15u
-+  ad=0.231p pd=1.81923u as=0.43725p ps=3.83u
-M1026 a_681_115# a_301_89# a_609_725# vdd pshort w=3u l=0.15u
-+  ad=0.51p pd=3.34u as=0.795p ps=6.53u
-M1027 a_801_725# CK.t4 a_681_115# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1028 a_117_624.t2 CK.t5 a_259_725# vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1029 a_451_725# a_301_89# a_117_624.t0 vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1030 gnd RN.t1 a_21_384.t0 gnd nshort w=1u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-C0 a_681_115# D 0.030745fF
-C1 a_843_89# CK 0.948925fF
-C2 m1_n35_1379# m1_n35_0# 0.298018fF
-C3 a_301_89# m1_n35_0# 0.100363fF
-C4 CK Q 0.040951fF
-C5 RN QN 0.320223fF
-C6 D CK 0.350660fF
-C7 m1_n35_1379# QN 0.041280fF
-C8 a_843_89# RN 0.592553fF
-C9 a_681_115# CK 0.391492fF
-C10 a_301_89# QN 0.222428fF
-C11 a_843_89# m1_n35_1379# 0.032489fF
-C12 a_301_89# a_843_89# 0.740354fF
-C13 vdd a_301_89# 0.001311fF
-C14 RN Q 0.148908fF
-C15 m1_n35_1379# Q 0.026952fF
-C16 m1_n35_0# QN 0.129338fF
-C17 D RN 0.033983fF
-C18 a_681_115# RN 0.771586fF
-C19 a_301_89# Q 0.135648fF
-C20 a_843_89# m1_n35_0# 0.050293fF
-C21 a_681_115# m1_n35_1379# 0.026111fF
-C22 a_301_89# D 0.504230fF
-C23 a_301_89# a_681_115# 0.641152fF
-C24 m1_n35_0# Q 0.047670fF
-C25 CK RN 0.353413fF
-C26 a_843_89# QN 1.208070fF
-C27 m1_n35_1379# CK 0.022603fF
-C28 a_681_115# m1_n35_0# 0.084075fF
-C29 a_301_89# CK 1.198450fF
-C30 vdd a_843_89# 0.001325fF
-C31 QN Q 1.504360fF
-C32 D QN 0.022050fF
-C33 a_681_115# QN 0.208352fF
-C34 a_843_89# Q 0.244660fF
-C35 m1_n35_1379# RN 0.018753fF
-C36 m1_n35_0# CK 0.050365fF
-C37 a_301_89# RN 0.836447fF
-C38 vdd Q 0.001942fF
-C39 a_843_89# D 0.073493fF
-C40 a_843_89# a_681_115# 0.337968fF
-C41 a_301_89# m1_n35_1379# 0.031888fF
-C42 vdd a_681_115# 0.001219fF
-C43 CK QN 0.129713fF
-C44 a_681_115# Q 0.094815fF
-C45 m1_n35_0# RN 0.087082fF
-R0 a_21_384.n1 a_21_384.t5 953.288
-R1 a_21_384.n0 a_21_384.t4 744.421
-R2 a_21_384.n0 a_21_384.t2 567.563
-R3 a_21_384.n1 a_21_384.t3 358.821
-R4 a_21_384.t1 a_21_384.n3 200.34
-R5 a_21_384.n2 a_21_384.n0 102.537
-R6 a_21_384.n3 a_21_384.t0 93.893
-R7 a_21_384.n2 a_21_384.n1 68.502
-R8 a_21_384.n3 a_21_384.n2 0.196
-R9 a_n8_725.n1 a_n8_725.t3 592.681
-R10 a_n8_725.n1 a_n8_725.t5 592.681
-R11 a_n8_725.n2 a_n8_725.t6 319.547
-R12 a_n8_725.n2 a_n8_725.t4 319.547
-R13 a_n8_725.t0 a_n8_725.n4 302.497
-R14 a_n8_725.n4 a_n8_725.n3 180.399
-R15 a_n8_725.n3 a_n8_725.n1 166.449
-R16 a_n8_725.n4 a_n8_725.n0 63.117
-R17 a_n8_725.n0 a_n8_725.t2 26.25
-R18 a_n8_725.n0 a_n8_725.t1 26.25
-R19 a_n8_725.n3 a_n8_725.n2 13.653
-R20 QN.n0 QN.t2 784.588
-R21 QN.n0 QN.t3 744.421
-R22 QN.n1 QN.t1 248.876
-R23 QN QN.t0 235.202
-R24 QN.n1 QN.n0 25.8
-R25 QN QN.n1 0.358
-R26 CK.n3 CK.t3 670.704
-R27 CK.n0 CK.t5 650.679
-R28 CK.n2 CK.t4 604.032
-R29 CK.n3 CK.t2 561.009
-R30 CK.n0 CK.t1 473.198
-R31 CK.n1 CK.t0 359.792
-R32 CK CK.n2 91.052
-R33 CK.n1 CK.n0 78.941
-R34 CK.n2 CK.n1 34.447
-R35 CK CK.n3 7.5
-R36 a_117_624.n1 a_117_624.t5 743.369
-R37 a_117_624.n1 a_117_624.t4 566.636
-R38 a_117_624.n3 a_117_624.n2 157.971
-R39 a_117_624.n2 a_117_624.n1 101.37
-R40 a_117_624.n2 a_117_624.n0 54.501
-R41 a_117_624.n0 a_117_624.t3 19.539
-R42 a_117_624.n0 a_117_624.t1 19.011
-R43 a_117_624.t0 a_117_624.n3 14.775
-R44 a_117_624.n3 a_117_624.t2 14.775
-R45 D.n0 D.t0 824.755
-R46 D.n0 D.t1 429.514
-R47 D D.n0 7.5
-R48 Q Q.t0 257.405
-R49 Q Q.t1 200.534
-R50 a_75_725.n5 a_75_725.n3 592.681
-R51 a_75_725.n5 a_75_725.n4 592.681
-R52 a_75_725.n8 a_75_725.n7 319.547
-R53 a_75_725.n8 a_75_725.n6 319.547
-R54 a_75_725.t0 a_75_725.n10 302.497
-R55 a_75_725.n10 a_75_725.n9 180.399
-R56 a_75_725.n9 a_75_725.n5 166.449
-R57 a_75_725.n10 a_75_725.n2 63.117
-R58 a_75_725.n2 a_75_725.n0 26.25
-R59 a_75_725.n2 a_75_725.n1 26.25
-R60 a_75_725.n9 a_75_725.n8 13.653
-R61 RN.n0 RN.t1 686.581
-R62 RN.n0 RN.t0 567.688
-R63 RN RN.n0 7.5
-C46 a_681_115# gnd 0.165695fF
-C47 a_843_89# gnd 0.305722fF
-C48 a_301_89# gnd 0.322380fF
-C49 vdd gnd 4.003680fF
-C50 RN.t0 gnd 3.737800fF
-C51 RN.t1 gnd 2.387550fF
-C52 a_75_725.t0 gnd 0.009829fF
-C53 Q.t0 gnd 1.197160fF
-C54 Q.t1 gnd 0.509770fF
-C55 D.t0 gnd 0.807800fF
-C56 D.t1 gnd 0.317822fF
-C57 a_117_624.t1 gnd 0.164284fF
-C58 a_117_624.t3 gnd 0.165914fF
-C59 a_117_624.t5 gnd 0.285882fF
-C60 a_117_624.t2 gnd 0.476155fF
-C61 a_117_624.t0 gnd 0.476155fF
-C62 CK.t4 gnd 0.587051fF
-C63 CK.t0 gnd 0.272431fF
-C64 CK.t1 gnd 0.401982fF
-C65 CK.t5 gnd 0.641090fF
-C66 CK.t2 gnd 0.562318fF
-C67 CK.t3 gnd 0.368133fF
-C68 QN.t2 gnd 0.473429fF
-C69 QN.t3 gnd 0.333525fF
-C70 QN.t1 gnd 0.729750fF
-C71 QN.t0 gnd 1.243640fF
-C72 a_n8_725.t2 gnd 0.091090fF
-C73 a_n8_725.t1 gnd 0.091090fF
-C74 a_n8_725.t3 gnd 0.704407fF
-C75 a_n8_725.t5 gnd 0.704407fF
-C76 a_n8_725.t4 gnd 0.274338fF
-C77 a_n8_725.t6 gnd 0.274338fF
-C78 a_n8_725.t0 gnd 2.770220fF
-C79 a_21_384.t2 gnd 1.022950fF
-C80 a_21_384.t4 gnd 0.612493fF
-C81 a_21_384.t5 gnd 1.293700fF
-C82 a_21_384.t3 gnd 0.342733fF
-C83 a_21_384.t0 gnd 1.005970fF
-C84 a_21_384.t1 gnd 3.512300fF
-.ends
diff --git a/cdl/DFFSX1.cdl b/cdl/DFFSX1.cdl
deleted file mode 100644
index a21d250..0000000
--- a/cdl/DFFSX1.cdl
+++ /dev/null
@@ -1,231 +0,0 @@
-* SPICE3 file created from DFFSX1.ext - technology: EFS8A
-
-.subckt DFFSX1 CK D QN Q SN
-M1000 vdd a_843_89# QN.t1 vdd pshort w=3u l=0.15u
-+  ad=0.516359p pd=4.11413u as=0.795p ps=6.53u
-M1001 a_801_115# a_301_89# a_681_115# gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1002 a_681_115# CK.t0 a_609_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1003 a_1163_115# a_681_115# gnd gnd nshort w=1.26u l=0.15u
-+  ad=0.1323p pd=1.47u as=0.208972p ps=1.84368u
-M1004 a_89_115# SN.t0 a_6_115.t0 gnd nshort w=1.26u l=0.15u
-+  ad=0.1323p pd=1.47u as=0.3339p ps=3.05u
-M1005 a_451_115# CK.t1 a_117_624.t0 gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1006 a_301_89# CK.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.516359p ps=4.11413u
-M1007 a_117_624.t3 a_301_89# a_259_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1008 a_609_725.t0 a_6_115.t3 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.516359p ps=4.11413u
-M1009 gnd a_843_89# QN.t0 gnd nshort w=1u l=0.15u
-+  ad=0.165851p pd=1.46324u as=0.265p ps=2.53u
-M1010 a_259_725# D.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.516359p ps=4.11413u
-M1011 a_301_89# CK.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.165851p ps=1.46324u
-M1012 vdd SN.t1 a_843_89# vdd pshort w=1.65u l=0.15u
-+  ad=0.283997p pd=2.26277u as=0.231p ps=1.93u
-M1013 vdd a_843_89# a_801_725# vdd pshort w=3u l=0.15u
-+  ad=0.516359p pd=4.11413u as=0.315p ps=3.21u
-M1014 a_609_115# a_6_115.t4 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.165851p ps=1.46324u
-M1015 vdd a_117_624.t4 a_6_115.t2 vdd pshort w=1.65u l=0.15u
-+  ad=0.283997p pd=2.26277u as=0.231p ps=1.93u
-M1016 vdd a_6_115.t5 a_451_725.t0 vdd pshort w=3u l=0.15u
-+  ad=0.516359p pd=4.11413u as=0.315p ps=3.21u
-M1017 a_259_115# D.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.165851p ps=1.46324u
-M1018 gnd a_843_89# a_801_115# gnd nshort w=1u l=0.15u
-+  ad=0.165851p pd=1.46324u as=0.105p ps=1.21u
-M1019 a_843_89# SN.t2 a_1163_115# gnd nshort w=1.26u l=0.15u
-+  ad=0.3339p pd=3.05u as=0.1323p ps=1.47u
-M1020 a_843_89# a_681_115# vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.231p pd=1.93u as=0.283997p ps=2.26277u
-M1021 gnd a_117_624.t5 a_89_115# gnd nshort w=1.26u l=0.15u
-+  ad=0.208972p pd=1.84368u as=0.1323p ps=1.47u
-M1022 a_6_115.t1 SN.t3 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.231p pd=1.93u as=0.283997p ps=2.26277u
-M1023 Q.t1 QN.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.516359p ps=4.11413u
-M1024 gnd a_6_115.t6 a_451_115# gnd nshort w=1u l=0.15u
-+  ad=0.165851p pd=1.46324u as=0.105p ps=1.21u
-M1025 a_801_725# CK.t4 a_681_115# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1026 a_117_624.t1 CK.t5 a_259_725# vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1027 Q.t0 QN.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-C0 a_843_89# a_681_115# 0.378213fF
-C1 vdd a_301_89# 0.001311fF
-C2 D QN 0.023779fF
-C3 a_681_115# Q 0.106540fF
-C4 m1_n35_1379# CK 0.022603fF
-C5 a_681_115# SN 1.205880fF
-C6 a_301_89# QN 0.226276fF
-C7 a_843_89# D 0.075494fF
-C8 a_301_89# m1_n35_0# 0.100363fF
-C9 a_301_89# a_843_89# 0.964264fF
-C10 a_801_725# SN 0.012625fF
-C11 m1_n35_1379# QN 0.043190fF
-C12 SN D 0.210830fF
-C13 a_681_115# D 0.030035fF
-C14 a_301_89# Q 0.161004fF
-C15 m1_n35_1379# m1_n35_0# 0.279156fF
-C16 a_301_89# SN 0.591717fF
-C17 a_843_89# m1_n35_1379# 0.046887fF
-C18 a_301_89# a_681_115# 0.645804fF
-C19 CK QN 0.151046fF
-C20 m1_n35_0# CK 0.050365fF
-C21 m1_n35_1379# Q 0.026952fF
-C22 a_843_89# CK 0.975813fF
-C23 a_259_725# SN 0.012625fF
-C24 m1_n35_1379# SN 0.539618fF
-C25 a_681_115# m1_n35_1379# 0.026111fF
-C26 a_301_89# D 0.504230fF
-C27 vdd a_843_89# 0.001911fF
-C28 CK Q 0.044728fF
-C29 m1_n35_0# QN 0.100829fF
-C30 SN CK 0.378938fF
-C31 a_843_89# QN 0.799110fF
-C32 a_681_115# CK 0.444978fF
-C33 vdd Q 0.001326fF
-C34 a_843_89# m1_n35_0# 0.079959fF
-C35 a_301_89# m1_n35_1379# 0.031888fF
-C36 vdd SN 0.039534fF
-C37 vdd a_681_115# 0.001219fF
-C38 QN Q 1.498410fF
-C39 m1_n35_0# Q 0.047670fF
-C40 SN QN 0.122538fF
-C41 D CK 0.350660fF
-C42 a_681_115# QN 0.176779fF
-C43 a_843_89# Q 0.215754fF
-C44 m1_n35_0# SN 0.397855fF
-C45 a_301_89# CK 1.198450fF
-C46 a_681_115# m1_n35_0# 0.084075fF
-C47 a_843_89# SN 0.720868fF
-R0 QN QN.t1 768.6
-R1 QN.n0 QN.t3 686.581
-R2 QN.n0 QN.t2 567.688
-R3 QN.n1 QN.t0 364.245
-R4 QN.n1 QN.n0 25.8
-R5 QN QN.n1 0.358
-R6 CK.n3 CK.t3 670.704
-R7 CK.n0 CK.t5 650.679
-R8 CK.n2 CK.t4 604.032
-R9 CK.n3 CK.t2 561.009
-R10 CK.n0 CK.t1 473.198
-R11 CK.n1 CK.t0 359.792
-R12 CK CK.n2 91.052
-R13 CK.n1 CK.n0 78.941
-R14 CK.n2 CK.n1 34.447
-R15 CK CK.n3 7.5
-R16 SN.n1 SN.t2 891.583
-R17 SN.n0 SN.t0 876.246
-R18 SN.n1 SN.t1 517.229
-R19 SN.n0 SN.t3 517.229
-R20 SN SN.n0 170.161
-R21 SN SN.n1 13.653
-R22 a_6_115.n0 a_6_115.t3 592.681
-R23 a_6_115.n0 a_6_115.t5 592.681
-R24 a_6_115.n4 a_6_115.n3 339.82
-R25 a_6_115.n1 a_6_115.t6 319.547
-R26 a_6_115.n1 a_6_115.t4 319.547
-R27 a_6_115.n3 a_6_115.n2 206.235
-R28 a_6_115.n2 a_6_115.n0 166.449
-R29 a_6_115.n3 a_6_115.t0 52.05
-R30 a_6_115.n4 a_6_115.t2 16.715
-R31 a_6_115.t1 a_6_115.n4 16.715
-R32 a_6_115.n2 a_6_115.n1 13.653
-R33 a_117_624.n1 a_117_624.t4 784.588
-R34 a_117_624.n1 a_117_624.t5 644.808
-R35 a_117_624.n3 a_117_624.n2 157.971
-R36 a_117_624.n2 a_117_624.n1 101.37
-R37 a_117_624.n2 a_117_624.n0 54.501
-R38 a_117_624.n0 a_117_624.t0 19.539
-R39 a_117_624.n0 a_117_624.t3 19.011
-R40 a_117_624.n3 a_117_624.t2 14.775
-R41 a_117_624.t1 a_117_624.n3 14.775
-R42 a_609_725.n11 a_609_725.n10 119.817
-R43 a_609_725.n17 a_609_725.n2 118.017
-R44 a_609_725.n13 a_609_725.n5 118.017
-R45 a_609_725.n16 a_609_725.n15 118.017
-R46 a_609_725.n19 a_609_725.n18 101.332
-R47 a_609_725.n12 a_609_725.n6 98.132
-R48 a_609_725.n11 a_609_725.n7 98.132
-R49 a_609_725.n16 a_609_725.n13 70
-R50 a_609_725.n17 a_609_725.n16 70
-R51 a_609_725.n13 a_609_725.n12 38
-R52 a_609_725.n12 a_609_725.n11 34.4
-R53 a_609_725.n19 a_609_725.n17 33.6
-R54 a_609_725.n2 a_609_725.n1 23.878
-R55 a_609_725.n2 a_609_725.n0 14.679
-R56 a_609_725.n5 a_609_725.n3 9.193
-R57 a_609_725.n5 a_609_725.n4 9.193
-R58 a_609_725.n10 a_609_725.n8 9.193
-R59 a_609_725.n10 a_609_725.n9 9.193
-R60 a_609_725.n15 a_609_725.t0 9.193
-R61 a_609_725.n15 a_609_725.n14 9.193
-R62 D.n0 D.t0 824.755
-R63 D.n0 D.t1 429.514
-R64 D D.n0 7.5
-R65 a_451_725.n11 a_451_725.n10 119.817
-R66 a_451_725.n17 a_451_725.n2 118.017
-R67 a_451_725.n13 a_451_725.n5 118.017
-R68 a_451_725.n16 a_451_725.n15 118.017
-R69 a_451_725.n19 a_451_725.n18 101.332
-R70 a_451_725.n12 a_451_725.n6 98.132
-R71 a_451_725.n11 a_451_725.n7 98.132
-R72 a_451_725.n16 a_451_725.n13 70
-R73 a_451_725.n17 a_451_725.n16 70
-R74 a_451_725.n13 a_451_725.n12 38
-R75 a_451_725.n12 a_451_725.n11 34.4
-R76 a_451_725.n19 a_451_725.n17 33.6
-R77 a_451_725.n2 a_451_725.n1 23.878
-R78 a_451_725.n2 a_451_725.n0 14.679
-R79 a_451_725.n5 a_451_725.n3 9.193
-R80 a_451_725.n5 a_451_725.n4 9.193
-R81 a_451_725.n10 a_451_725.n8 9.193
-R82 a_451_725.n10 a_451_725.n9 9.193
-R83 a_451_725.n15 a_451_725.n14 9.193
-R84 a_451_725.n15 a_451_725.t0 9.193
-R85 Q Q.t1 790.803
-R86 Q Q.t0 287.491
-C48 a_681_115# gnd 0.195954fF
-C49 a_843_89# gnd 0.245130fF
-C50 a_301_89# gnd 0.322380fF
-C51 vdd gnd 3.752880fF
-C52 Q.t1 gnd 0.738180fF
-C53 Q.t0 gnd 0.364431fF
-C54 a_451_725.t0 gnd 0.000249fF
-C55 D.t0 gnd 0.761419fF
-C56 D.t1 gnd 0.299574fF
-C57 a_609_725.t0 gnd 0.000249fF
-C58 a_117_624.t3 gnd 0.147923fF
-C59 a_117_624.t0 gnd 0.149391fF
-C60 a_117_624.t4 gnd 0.365796fF
-C61 a_117_624.t5 gnd 0.287353fF
-C62 a_117_624.t1 gnd 0.428737fF
-C63 a_6_115.t2 gnd 0.164988fF
-C64 a_6_115.t0 gnd 0.504666fF
-C65 a_6_115.t3 gnd 0.494883fF
-C66 a_6_115.t5 gnd 0.494883fF
-C67 a_6_115.t4 gnd 0.192737fF
-C68 a_6_115.t6 gnd 0.192737fF
-C69 a_6_115.t1 gnd 0.164988fF
-C70 SN.t3 gnd 0.483989fF
-C71 SN.t0 gnd 0.625870fF
-C72 SN.t1 gnd 0.483989fF
-C73 SN.t2 gnd 0.607435fF
-C74 CK.t4 gnd 0.560156fF
-C75 CK.t0 gnd 0.259951fF
-C76 CK.t1 gnd 0.383566fF
-C77 CK.t5 gnd 0.611913fF
-C78 CK.t2 gnd 0.536557fF
-C79 CK.t3 gnd 0.351267fF
-C80 QN.t2 gnd 0.360451fF
-C81 QN.t3 gnd 0.230241fF
-C82 QN.t0 gnd 0.491529fF
-C83 QN.t1 gnd 0.729139fF
-.ends
diff --git a/cdl/DFFSXL.cdl b/cdl/DFFSXL.cdl
deleted file mode 100644
index 5a1803f..0000000
--- a/cdl/DFFSXL.cdl
+++ /dev/null
@@ -1,196 +0,0 @@
-* SPICE3 file created from DFFSXL.ext - technology: EFS8A
-
-.subckt DFFSXL CK D QN Q SN
-M1000 a_801_115# a_301_89# a_681_115# gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1001 a_681_115# CK.t0 a_609_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1002 a_1163_115# a_681_115# gnd gnd nshort w=1.26u l=0.15u
-+  ad=0.1323p pd=1.47u as=0.211637p ps=1.89143u
-M1003 a_89_115# SN.t0 a_6_115.t1 gnd nshort w=1.26u l=0.15u
-+  ad=0.1323p pd=1.47u as=0.3339p ps=3.05u
-M1004 a_451_115# CK.t1 a_117_624.t2 gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1005 a_301_89# CK.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.526807p ps=4.23494u
-M1006 a_117_624.t0 a_301_89# a_259_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1007 a_609_725# a_6_115.t3 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.526807p ps=4.23494u
-M1008 gnd a_843_89# QN.t0 gnd nshort w=0.64u l=0.15u
-+  ad=0.107498p pd=0.960727u as=0.1696p ps=1.81u
-M1009 a_259_725# D.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.526807p ps=4.23494u
-M1010 a_301_89# CK.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.167966p ps=1.50114u
-M1011 vdd SN.t1 a_843_89# vdd pshort w=1.65u l=0.15u
-+  ad=0.289744p pd=2.32922u as=0.231p ps=1.93u
-M1012 vdd a_843_89# a_801_725# vdd pshort w=3u l=0.15u
-+  ad=0.526807p pd=4.23494u as=0.315p ps=3.21u
-M1013 a_609_115# a_6_115.t4 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.167966p ps=1.50114u
-M1014 vdd a_117_624.t4 a_6_115.t2 vdd pshort w=1.65u l=0.15u
-+  ad=0.289744p pd=2.32922u as=0.231p ps=1.93u
-M1015 vdd a_6_115.t5 a_451_725# vdd pshort w=3u l=0.15u
-+  ad=0.526807p pd=4.23494u as=0.315p ps=3.21u
-M1016 a_259_115# D.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.167966p ps=1.50114u
-M1017 gnd a_843_89# a_801_115# gnd nshort w=1u l=0.15u
-+  ad=0.167966p pd=1.50114u as=0.105p ps=1.21u
-M1018 a_843_89# SN.t2 a_1163_115# gnd nshort w=1.26u l=0.15u
-+  ad=0.3339p pd=3.05u as=0.1323p ps=1.47u
-M1019 a_843_89# a_681_115# vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.231p pd=1.93u as=0.289744p ps=2.32922u
-M1020 Q.t1 QN.t2 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.289744p ps=2.32922u
-M1021 gnd a_117_624.t5 a_89_115# gnd nshort w=1.26u l=0.15u
-+  ad=0.211637p pd=1.89143u as=0.1323p ps=1.47u
-M1022 a_6_115.t0 SN.t3 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.231p pd=1.93u as=0.289744p ps=2.32922u
-M1023 gnd a_6_115.t6 a_451_115# gnd nshort w=1u l=0.15u
-+  ad=0.167966p pd=1.50114u as=0.105p ps=1.21u
-M1024 a_681_115# a_301_89# a_609_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1025 a_801_725# CK.t4 a_681_115# vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1026 a_117_624.t3 CK.t5 a_259_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1027 a_451_725# a_301_89# a_117_624.t1 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1028 Q.t0 QN.t3 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.107498p ps=0.960727u
-M1029 vdd a_843_89# QN.t1 vdd pshort w=1.65u l=0.15u
-+  ad=0.289744p pd=2.32922u as=0.43725p ps=3.83u
-C0 a_301_89# a_843_89# 0.964264fF
-C1 SN D 0.210830fF
-C2 m1_n35_0# CK 0.050365fF
-C3 m1_n35_1379# Q 0.026952fF
-C4 m1_n35_0# QN 0.100829fF
-C5 a_801_725# SN 0.012625fF
-C6 a_843_89# SN 0.851215fF
-C7 a_301_89# CK 1.198450fF
-C8 a_681_115# m1_n35_0# 0.084075fF
-C9 a_301_89# QN 0.226276fF
-C10 a_301_89# a_681_115# 0.645804fF
-C11 vdd a_301_89# 0.001311fF
-C12 SN CK 0.378938fF
-C13 m1_n35_0# Q 0.047670fF
-C14 SN QN 0.207765fF
-C15 m1_n35_1379# m1_n35_0# 0.279156fF
-C16 a_843_89# D 0.075494fF
-C17 a_681_115# SN 1.205880fF
-C18 a_301_89# Q 0.161004fF
-C19 a_301_89# m1_n35_1379# 0.031888fF
-C20 vdd SN 0.039534fF
-C21 D CK 0.350660fF
-C22 D QN 0.023779fF
-C23 m1_n35_1379# SN 0.539618fF
-C24 a_259_725# SN 0.012625fF
-C25 a_843_89# CK 0.975813fF
-C26 a_681_115# D 0.030035fF
-C27 a_843_89# QN 1.183860fF
-C28 a_301_89# m1_n35_0# 0.100363fF
-C29 a_843_89# a_681_115# 0.446802fF
-C30 vdd a_843_89# 0.001911fF
-C31 CK QN 0.151046fF
-C32 m1_n35_0# SN 0.397855fF
-C33 a_681_115# CK 0.444978fF
-C34 a_451_725# SN 0.012625fF
-C35 a_843_89# Q 0.215754fF
-C36 a_681_115# QN 0.227708fF
-C37 a_301_89# SN 0.591717fF
-C38 a_843_89# m1_n35_1379# 0.046887fF
-C39 vdd a_681_115# 0.001219fF
-C40 CK Q 0.044728fF
-C41 m1_n35_1379# CK 0.022603fF
-C42 QN Q 1.498410fF
-C43 m1_n35_1379# QN 0.043190fF
-C44 a_609_725# SN 0.012625fF
-C45 a_681_115# Q 0.106540fF
-C46 a_301_89# D 0.504230fF
-C47 a_843_89# m1_n35_0# 0.079959fF
-C48 a_681_115# m1_n35_1379# 0.026111fF
-C49 vdd Q 0.001942fF
-R0 CK.n3 CK.t3 670.704
-R1 CK.n0 CK.t5 650.679
-R2 CK.n2 CK.t4 604.032
-R3 CK.n3 CK.t2 561.009
-R4 CK.n0 CK.t1 473.198
-R5 CK.n1 CK.t0 359.792
-R6 CK CK.n2 91.052
-R7 CK.n1 CK.n0 78.941
-R8 CK.n2 CK.n1 34.447
-R9 CK CK.n3 7.5
-R10 SN.n0 SN.t2 891.583
-R11 SN.n1 SN.t0 876.246
-R12 SN.n1 SN.t3 517.229
-R13 SN.n0 SN.t1 517.229
-R14 SN SN.n1 170.161
-R15 SN SN.n0 13.653
-R16 a_6_115.n0 a_6_115.t3 592.681
-R17 a_6_115.n0 a_6_115.t5 592.681
-R18 a_6_115.n4 a_6_115.n3 339.82
-R19 a_6_115.n1 a_6_115.t6 319.547
-R20 a_6_115.n1 a_6_115.t4 319.547
-R21 a_6_115.n3 a_6_115.n2 206.235
-R22 a_6_115.n2 a_6_115.n0 166.449
-R23 a_6_115.n3 a_6_115.t1 52.05
-R24 a_6_115.n4 a_6_115.t2 16.715
-R25 a_6_115.t0 a_6_115.n4 16.715
-R26 a_6_115.n2 a_6_115.n1 13.653
-R27 a_117_624.n1 a_117_624.t4 784.588
-R28 a_117_624.n1 a_117_624.t5 644.808
-R29 a_117_624.n3 a_117_624.n2 157.971
-R30 a_117_624.n2 a_117_624.n1 101.37
-R31 a_117_624.n2 a_117_624.n0 54.501
-R32 a_117_624.n0 a_117_624.t2 19.539
-R33 a_117_624.n0 a_117_624.t0 19.011
-R34 a_117_624.t1 a_117_624.n3 14.775
-R35 a_117_624.n3 a_117_624.t3 14.775
-R36 QN.n0 QN.t2 784.588
-R37 QN.n0 QN.t3 744.421
-R38 QN.n1 QN.t0 277.288
-R39 QN QN.t1 235.202
-R40 QN.n1 QN.n0 25.8
-R41 QN QN.n1 0.358
-R42 D.n0 D.t0 824.755
-R43 D.n0 D.t1 429.514
-R44 D D.n0 7.5
-R45 Q Q.t1 257.405
-R46 Q Q.t0 200.534
-C50 a_681_115# gnd 0.195954fF
-C51 a_843_89# gnd 0.316010fF
-C52 a_301_89# gnd 0.322380fF
-C53 vdd gnd 3.752880fF
-C54 Q.t1 gnd 1.012310fF
-C55 Q.t0 gnd 0.431057fF
-C56 D.t0 gnd 0.761419fF
-C57 D.t1 gnd 0.299574fF
-C58 QN.t2 gnd 0.415503fF
-C59 QN.t3 gnd 0.292717fF
-C60 QN.t0 gnd 0.659632fF
-C61 QN.t1 gnd 1.091470fF
-C62 a_117_624.t0 gnd 0.148582fF
-C63 a_117_624.t2 gnd 0.150056fF
-C64 a_117_624.t4 gnd 0.367424fF
-C65 a_117_624.t5 gnd 0.288632fF
-C66 a_117_624.t3 gnd 0.430645fF
-C67 a_117_624.t1 gnd 0.430645fF
-C68 a_6_115.t2 gnd 0.164988fF
-C69 a_6_115.t1 gnd 0.504666fF
-C70 a_6_115.t3 gnd 0.494883fF
-C71 a_6_115.t5 gnd 0.494883fF
-C72 a_6_115.t4 gnd 0.192737fF
-C73 a_6_115.t6 gnd 0.192737fF
-C74 a_6_115.t0 gnd 0.164988fF
-C75 SN.t1 gnd 0.499343fF
-C76 SN.t2 gnd 0.626704fF
-C77 SN.t3 gnd 0.499343fF
-C78 SN.t0 gnd 0.645724fF
-C79 CK.t4 gnd 0.560156fF
-C80 CK.t0 gnd 0.259951fF
-C81 CK.t1 gnd 0.383566fF
-C82 CK.t5 gnd 0.611913fF
-C83 CK.t2 gnd 0.536557fF
-C84 CK.t3 gnd 0.351267fF
-.ends
diff --git a/cdl/DFFX1.cdl b/cdl/DFFX1.cdl
deleted file mode 100644
index ad74940..0000000
--- a/cdl/DFFX1.cdl
+++ /dev/null
@@ -1,162 +0,0 @@
-* SPICE3 file created from DFFX1.ext - technology: EFS8A
-
-.subckt DFFX1 CK D QN Q
-M1000 a_583_115# a_203_89# a_511_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1001 gnd a_11_624.t4 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.153889p pd=1.41889u as=0.265p ps=2.53u
-M1002 a_353_725# a_203_89# a_11_624.t2 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1003 a_11_624.t1 CK.t0 a_161_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1004 a_745_89# a_583_115# gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.153889p ps=1.41889u
-M1005 Q.t0 QN.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.461667p ps=3.64111u
-M1006 a_703_115# a_203_89# a_583_115# gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1007 a_583_115# CK.t1 a_511_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1008 a_203_89# CK.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.461667p ps=3.64111u
-M1009 a_11_624.t3 a_203_89# a_161_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1010 a_353_115# CK.t3 a_11_624.t0 gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1011 a_511_725# a_n8_115.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.461667p ps=3.64111u
-M1012 Q.t1 QN.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.153889p ps=1.41889u
-M1013 vdd a_745_89# QN.t0 vdd pshort w=3u l=0.15u
-+  ad=0.461667p pd=3.64111u as=0.795p ps=6.53u
-M1014 a_161_725# D.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.461667p ps=3.64111u
-M1015 a_203_89# CK.t4 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.153889p ps=1.41889u
-M1016 vdd a_745_89# a_703_725# vdd pshort w=3u l=0.15u
-+  ad=0.461667p pd=3.64111u as=0.315p ps=3.21u
-M1017 a_511_115# a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.153889p ps=1.41889u
-M1018 gnd a_745_89# QN.t1 gnd nshort w=1u l=0.15u
-+  ad=0.153889p pd=1.41889u as=0.265p ps=2.53u
-M1019 vdd a_n8_115.t4 a_353_725# vdd pshort w=3u l=0.15u
-+  ad=0.461667p pd=3.64111u as=0.315p ps=3.21u
-M1020 a_161_115# D.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.153889p ps=1.41889u
-M1021 vdd a_11_624.t5 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.461667p pd=3.64111u as=0.795p ps=6.53u
-M1022 gnd a_745_89# a_703_115# gnd nshort w=1u l=0.15u
-+  ad=0.153889p pd=1.41889u as=0.105p ps=1.21u
-M1023 a_745_89# a_583_115# vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.461667p ps=3.64111u
-M1024 gnd a_n8_115.t5 a_353_115# gnd nshort w=1u l=0.15u
-+  ad=0.153889p pd=1.41889u as=0.105p ps=1.21u
-M1025 a_703_725# CK.t5 a_583_115# vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-C0 CK Q 0.048859fF
-C1 m1_n35_1379# CK 0.022603fF
-C2 a_203_89# a_745_89# 1.341820fF
-C3 a_583_115# Q 0.120162fF
-C4 a_745_89# m1_n35_0# 0.097208fF
-C5 vdd Q 0.001326fF
-C6 a_583_115# m1_n35_1379# 0.026111fF
-C7 a_203_89# CK 1.198450fF
-C8 QN Q 1.498410fF
-C9 m1_n35_0# CK 0.050365fF
-C10 m1_n35_1379# QN 0.043190fF
-C11 a_203_89# a_583_115# 0.661477fF
-C12 vdd a_203_89# 0.001311fF
-C13 a_583_115# m1_n35_0# 0.084075fF
-C14 a_203_89# QN 0.278706fF
-C15 a_745_89# D 0.077652fF
-C16 m1_n35_0# QN 0.100829fF
-C17 m1_n35_1379# Q 0.026952fF
-C18 D CK 0.350660fF
-C19 a_203_89# Q 0.194303fF
-C20 a_745_89# CK 1.025610fF
-C21 a_583_115# D 0.033983fF
-C22 a_203_89# m1_n35_1379# 0.031888fF
-C23 D QN 0.025622fF
-C24 m1_n35_0# Q 0.047670fF
-C25 m1_n35_1379# m1_n35_0# 0.248977fF
-C26 a_745_89# a_583_115# 0.608448fF
-C27 vdd a_745_89# 0.001338fF
-C28 a_583_115# CK 0.483573fF
-C29 a_745_89# QN 1.127450fF
-C30 a_203_89# m1_n35_0# 0.100363fF
-C31 CK QN 0.173201fF
-C32 vdd a_583_115# 0.001219fF
-C33 a_745_89# Q 0.351014fF
-C34 a_583_115# QN 0.231554fF
-C35 a_203_89# D 0.504230fF
-C36 a_745_89# m1_n35_1379# 0.032426fF
-R0 a_11_624.n1 a_11_624.t4 674.53
-R1 a_11_624.n1 a_11_624.t5 558.746
-R2 a_11_624.n3 a_11_624.n2 157.971
-R3 a_11_624.n2 a_11_624.n1 104.241
-R4 a_11_624.n2 a_11_624.n0 54.501
-R5 a_11_624.n0 a_11_624.t0 19.539
-R6 a_11_624.n0 a_11_624.t3 19.011
-R7 a_11_624.n3 a_11_624.t2 14.775
-R8 a_11_624.t1 a_11_624.n3 14.775
-R9 a_n8_115.n0 a_n8_115.t2 592.681
-R10 a_n8_115.n0 a_n8_115.t4 592.681
-R11 a_n8_115.n1 a_n8_115.t5 319.547
-R12 a_n8_115.n1 a_n8_115.t3 319.547
-R13 a_n8_115.t0 a_n8_115.n3 289.939
-R14 a_n8_115.n3 a_n8_115.n2 176.094
-R15 a_n8_115.n2 a_n8_115.n0 166.449
-R16 a_n8_115.n3 a_n8_115.t1 67.717
-R17 a_n8_115.n2 a_n8_115.n1 13.653
-R18 CK.n3 CK.t4 670.704
-R19 CK.n0 CK.t0 650.679
-R20 CK.n2 CK.t5 604.032
-R21 CK.n3 CK.t2 561.009
-R22 CK.n0 CK.t3 473.198
-R23 CK.n1 CK.t1 359.792
-R24 CK CK.n2 91.052
-R25 CK.n1 CK.n0 78.941
-R26 CK.n2 CK.n1 34.447
-R27 CK CK.n3 7.5
-R28 QN.n0 QN.t3 686.581
-R29 QN.n0 QN.t2 567.688
-R30 QN.n1 QN.t1 255.638
-R31 QN.n1 QN.t0 179.239
-R32 QN QN.n0 25.441
-R33 QN QN.n1 0.358
-R34 Q Q.t0 201.131
-R35 Q Q.t1 178.836
-R36 D.n0 D.t0 824.755
-R37 D.n0 D.t1 429.514
-R38 D D.n0 7.5
-C37 a_583_115# gnd 0.150773fF
-C38 a_745_89# gnd 0.258106fF
-C39 a_203_89# gnd 0.322380fF
-C40 vdd gnd 3.331080fF
-C41 D.t0 gnd 0.712394fF
-C42 D.t1 gnd 0.280285fF
-C43 Q.t0 gnd 1.337260fF
-C44 Q.t1 gnd 0.498760fF
-C45 QN.t2 gnd 0.397417fF
-C46 QN.t3 gnd 0.253854fF
-C47 QN.t1 gnd 0.673516fF
-C48 QN.t0 gnd 1.365620fF
-C49 CK.t5 gnd 0.542177fF
-C50 CK.t1 gnd 0.251607fF
-C51 CK.t3 gnd 0.371255fF
-C52 CK.t0 gnd 0.600245fF
-C53 CK.t2 gnd 0.519335fF
-C54 CK.t4 gnd 0.339993fF
-C55 a_n8_115.t1 gnd 0.392973fF
-C56 a_n8_115.t2 gnd 0.460922fF
-C57 a_n8_115.t4 gnd 0.460922fF
-C58 a_n8_115.t3 gnd 0.179510fF
-C59 a_n8_115.t5 gnd 0.179510fF
-C60 a_n8_115.t0 gnd 1.744650fF
-C61 a_11_624.t2 gnd 0.343081fF
-C62 a_11_624.t3 gnd 0.118370fF
-C63 a_11_624.t0 gnd 0.119545fF
-C64 a_11_624.t5 gnd 0.343115fF
-C65 a_11_624.t4 gnd 0.225201fF
-C66 a_11_624.t1 gnd 0.343081fF
-.ends
diff --git a/cdl/DFFXL.cdl b/cdl/DFFXL.cdl
deleted file mode 100644
index 90fd1d7..0000000
--- a/cdl/DFFXL.cdl
+++ /dev/null
@@ -1,162 +0,0 @@
-* SPICE3 file created from DFFXL.ext - technology: EFS8A
-
-.subckt DFFXL CK D QN Q
-M1000 a_583_115# a_203_89# a_511_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1001 gnd a_11_624.t4 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.155097p pd=1.45531u as=0.265p ps=2.53u
-M1002 a_353_725# a_203_89# a_11_624.t2 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1003 a_11_624.t1 CK.t0 a_161_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1004 a_745_89# a_583_115# gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.155097p ps=1.45531u
-M1005 Q.t0 QN.t2 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.256463p ps=2.04179u
-M1006 a_703_115# a_203_89# a_583_115# gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1007 a_583_115# CK.t1 a_511_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1008 a_203_89# CK.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.466296p ps=3.71235u
-M1009 a_11_624.t3 a_203_89# a_161_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1010 a_353_115# CK.t3 a_11_624.t0 gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1011 a_511_725# a_n8_115.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.466296p ps=3.71235u
-M1012 Q.t1 QN.t3 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.0992618p ps=0.931401u
-M1013 vdd a_745_89# QN.t0 vdd pshort w=1.65u l=0.15u
-+  ad=0.256463p pd=2.04179u as=0.43725p ps=3.83u
-M1014 a_161_725# D.t0 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.466296p ps=3.71235u
-M1015 a_203_89# CK.t4 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.155097p ps=1.45531u
-M1016 vdd a_745_89# a_703_725# vdd pshort w=3u l=0.15u
-+  ad=0.466296p pd=3.71235u as=0.315p ps=3.21u
-M1017 a_511_115# a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.155097p ps=1.45531u
-M1018 gnd a_745_89# QN.t1 gnd nshort w=0.64u l=0.15u
-+  ad=0.0992618p pd=0.931401u as=0.1696p ps=1.81u
-M1019 vdd a_n8_115.t4 a_353_725# vdd pshort w=3u l=0.15u
-+  ad=0.466296p pd=3.71235u as=0.315p ps=3.21u
-M1020 a_161_115# D.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.155097p ps=1.45531u
-M1021 vdd a_11_624.t5 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.466296p pd=3.71235u as=0.795p ps=6.53u
-M1022 gnd a_745_89# a_703_115# gnd nshort w=1u l=0.15u
-+  ad=0.155097p pd=1.45531u as=0.105p ps=1.21u
-M1023 a_745_89# a_583_115# vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.466296p ps=3.71235u
-M1024 gnd a_n8_115.t5 a_353_115# gnd nshort w=1u l=0.15u
-+  ad=0.155097p pd=1.45531u as=0.105p ps=1.21u
-M1025 a_703_725# CK.t5 a_583_115# vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-C0 vdd Q 0.001942fF
-C1 a_583_115# m1_n35_1379# 0.026111fF
-C2 a_203_89# CK 1.198450fF
-C3 a_745_89# m1_n35_0# 0.097208fF
-C4 QN Q 1.498410fF
-C5 m1_n35_0# CK 0.050365fF
-C6 m1_n35_1379# QN 0.043190fF
-C7 a_203_89# a_583_115# 0.661477fF
-C8 vdd a_203_89# 0.001311fF
-C9 a_203_89# QN 0.278706fF
-C10 a_745_89# D 0.077652fF
-C11 a_583_115# m1_n35_0# 0.084075fF
-C12 m1_n35_0# QN 0.100829fF
-C13 m1_n35_1379# Q 0.026952fF
-C14 D CK 0.350660fF
-C15 a_203_89# Q 0.194303fF
-C16 a_745_89# CK 1.025610fF
-C17 a_583_115# D 0.033983fF
-C18 a_203_89# m1_n35_1379# 0.031888fF
-C19 D QN 0.025622fF
-C20 m1_n35_0# Q 0.047670fF
-C21 m1_n35_1379# m1_n35_0# 0.248977fF
-C22 a_745_89# a_583_115# 0.608448fF
-C23 vdd a_745_89# 0.001338fF
-C24 a_583_115# CK 0.483573fF
-C25 a_745_89# QN 1.512200fF
-C26 a_203_89# m1_n35_0# 0.100363fF
-C27 CK QN 0.173201fF
-C28 vdd a_583_115# 0.001219fF
-C29 a_745_89# Q 0.351014fF
-C30 a_583_115# QN 0.231554fF
-C31 a_745_89# m1_n35_1379# 0.032426fF
-C32 a_203_89# D 0.504230fF
-C33 CK Q 0.048859fF
-C34 m1_n35_1379# CK 0.022603fF
-C35 a_203_89# a_745_89# 1.341820fF
-C36 a_583_115# Q 0.120162fF
-R0 a_11_624.n1 a_11_624.t4 674.53
-R1 a_11_624.n1 a_11_624.t5 558.746
-R2 a_11_624.n3 a_11_624.n2 157.971
-R3 a_11_624.n2 a_11_624.n1 104.241
-R4 a_11_624.n2 a_11_624.n0 54.501
-R5 a_11_624.n0 a_11_624.t0 19.539
-R6 a_11_624.n0 a_11_624.t3 19.011
-R7 a_11_624.n3 a_11_624.t2 14.775
-R8 a_11_624.t1 a_11_624.n3 14.775
-R9 a_n8_115.n0 a_n8_115.t2 592.681
-R10 a_n8_115.n0 a_n8_115.t4 592.681
-R11 a_n8_115.n1 a_n8_115.t5 319.547
-R12 a_n8_115.n1 a_n8_115.t3 319.547
-R13 a_n8_115.t0 a_n8_115.n3 289.939
-R14 a_n8_115.n3 a_n8_115.n2 176.094
-R15 a_n8_115.n2 a_n8_115.n0 166.449
-R16 a_n8_115.n3 a_n8_115.t1 67.717
-R17 a_n8_115.n2 a_n8_115.n1 13.653
-R18 CK.n3 CK.t4 670.704
-R19 CK.n0 CK.t0 650.679
-R20 CK.n2 CK.t5 604.032
-R21 CK.n3 CK.t2 561.009
-R22 CK.n0 CK.t3 473.198
-R23 CK.n1 CK.t1 359.792
-R24 CK CK.n2 91.052
-R25 CK.n1 CK.n0 78.941
-R26 CK.n2 CK.n1 34.447
-R27 CK CK.n3 7.5
-R28 QN.n0 QN.t2 784.588
-R29 QN.n0 QN.t3 744.421
-R30 QN.n1 QN.t1 277.288
-R31 QN QN.t0 235.202
-R32 QN.n1 QN.n0 25.8
-R33 QN QN.n1 0.358
-R34 Q Q.t0 257.413
-R35 Q Q.t1 200.527
-R36 D.n0 D.t0 824.755
-R37 D.n0 D.t1 429.514
-R38 D D.n0 7.5
-C37 a_583_115# gnd 0.150773fF
-C38 a_745_89# gnd 0.328985fF
-C39 a_203_89# gnd 0.322380fF
-C40 vdd gnd 3.331080fF
-C41 D.t0 gnd 0.712394fF
-C42 D.t1 gnd 0.280285fF
-C43 Q.t0 gnd 1.100690fF
-C44 Q.t1 gnd 0.468669fF
-C45 QN.t2 gnd 0.437106fF
-C46 QN.t3 gnd 0.307936fF
-C47 QN.t1 gnd 0.693928fF
-C48 QN.t0 gnd 1.148220fF
-C49 CK.t5 gnd 0.542177fF
-C50 CK.t1 gnd 0.251607fF
-C51 CK.t3 gnd 0.371255fF
-C52 CK.t0 gnd 0.600245fF
-C53 CK.t2 gnd 0.519335fF
-C54 CK.t4 gnd 0.339993fF
-C55 a_n8_115.t1 gnd 0.392973fF
-C56 a_n8_115.t2 gnd 0.460922fF
-C57 a_n8_115.t4 gnd 0.460922fF
-C58 a_n8_115.t3 gnd 0.179510fF
-C59 a_n8_115.t5 gnd 0.179510fF
-C60 a_n8_115.t0 gnd 1.744650fF
-C61 a_11_624.t2 gnd 0.343081fF
-C62 a_11_624.t3 gnd 0.118370fF
-C63 a_11_624.t0 gnd 0.119545fF
-C64 a_11_624.t5 gnd 0.343115fF
-C65 a_11_624.t4 gnd 0.225201fF
-C66 a_11_624.t1 gnd 0.343081fF
-.ends
diff --git a/cdl/DLY1.cdl b/cdl/DLY1.cdl
deleted file mode 100644
index 1119b7f..0000000
--- a/cdl/DLY1.cdl
+++ /dev/null
@@ -1,53 +0,0 @@
-* SPICE3 file created from DLY1.ext - technology: EFS8A
-
-.subckt DLY1 A Y
-M1000 gnd A.t0 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.265p ps=2.53u
-M1001 vdd a_n8_115.t2 Y.t1 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-M1002 gnd a_n8_115.t3 Y.t3 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1003 Y.t0 a_n8_115.t4 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1004 Y.t2 a_n8_115.t5 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1005 vdd A.t1 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.795p ps=6.53u
-C0 m1_n35_1379# Y 0.026952fF
-C1 Y vdd 0.001167fF
-C2 m1_n35_0# Y 0.047670fF
-C3 m1_n35_1379# m1_n35_0# 0.064131fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 558.047
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n0 a_n8_115.t2 613.746
-R6 a_n8_115.n0 a_n8_115.t4 551.621
-R7 a_n8_115.n1 a_n8_115.t3 483.605
-R8 a_n8_115.n1 a_n8_115.t5 345.432
-R9 a_n8_115.n2 a_n8_115.n1 292.948
-R10 a_n8_115.n3 a_n8_115.t1 255.638
-R11 a_n8_115.t0 a_n8_115.n3 179.239
-R12 a_n8_115.n3 a_n8_115.n2 25.8
-R13 a_n8_115.n2 a_n8_115.n0 16.066
-R14 Y Y.n0 191.813
-R15 Y Y.n1 162.161
-R16 Y.n1 Y.t3 16.8
-R17 Y.n1 Y.t2 16.8
-R18 Y.n0 Y.t1 9.193
-R19 Y.n0 Y.t0 9.193
-C4 vdd gnd 0.875520fF
-C5 Y.t1 gnd 0.149657fF
-C6 Y.t0 gnd 0.149657fF
-C7 Y.t3 gnd 0.049886fF
-C8 Y.t2 gnd 0.049886fF
-C9 a_n8_115.t2 gnd 0.213046fF
-C10 a_n8_115.t4 gnd 0.203484fF
-C11 a_n8_115.t5 gnd 0.082828fF
-C12 a_n8_115.t3 gnd 0.104407fF
-C13 a_n8_115.t1 gnd 0.349367fF
-C14 a_n8_115.t0 gnd 0.708377fF
-C15 A.t1 gnd 0.276151fF
-C16 A.t0 gnd 0.139751fF
-.ends
diff --git a/cdl/DLY2.cdl b/cdl/DLY2.cdl
deleted file mode 100644
index 9481dbb..0000000
--- a/cdl/DLY2.cdl
+++ /dev/null
@@ -1,87 +0,0 @@
-* SPICE3 file created from DLY2.ext - technology: EFS8A
-
-.subckt DLY2 A Y
-M1000 gnd A.t0 a_n8_115.t0 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.265p ps=2.53u
-M1001 Y.t3 a_n8_115.t2 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.165p ps=1.53u
-M1002 vdd a_n8_115.t3 Y.t7 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1003 gnd a_n8_115.t4 Y.t2 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.14p ps=1.28u
-M1004 Y.t6 a_n8_115.t5 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1005 vdd a_n8_115.t6 Y.t5 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1006 Y.t1 a_n8_115.t7 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.165p ps=1.53u
-M1007 vdd A.t1 a_n8_115.t1 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.795p ps=6.53u
-M1008 gnd a_n8_115.t8 Y.t0 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.14p ps=1.28u
-M1009 Y.t4 a_n8_115.t9 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-C0 m1_n35_1379# m1_n35_0# 0.094310fF
-C1 vdd Y 0.006872fF
-C2 m1_n35_1379# Y 0.122398fF
-C3 m1_n35_0# Y 0.210441fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 558.047
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n0 a_n8_115.t6 676.406
-R6 a_n8_115.n2 a_n8_115.t5 551.621
-R7 a_n8_115.n0 a_n8_115.t9 538.233
-R8 a_n8_115.n1 a_n8_115.t3 538.233
-R9 a_n8_115.n3 a_n8_115.t8 483.605
-R10 a_n8_115.n5 a_n8_115.t7 345.432
-R11 a_n8_115.n4 a_n8_115.t4 345.432
-R12 a_n8_115.n3 a_n8_115.t2 345.432
-R13 a_n8_115.n6 a_n8_115.n5 292.948
-R14 a_n8_115.n7 a_n8_115.t0 255.638
-R15 a_n8_115.t1 a_n8_115.n7 179.239
-R16 a_n8_115.n1 a_n8_115.n0 138.173
-R17 a_n8_115.n4 a_n8_115.n3 138.173
-R18 a_n8_115.n5 a_n8_115.n4 138.173
-R19 a_n8_115.n2 a_n8_115.n1 75.513
-R20 a_n8_115.n7 a_n8_115.n6 25.8
-R21 a_n8_115.n6 a_n8_115.n2 16.066
-R22 Y.n1 Y.n0 191.147
-R23 Y.n3 Y.n2 191.147
-R24 Y.n7 Y.n6 161.723
-R25 Y.n5 Y.n4 161.723
-R26 Y.n6 Y.t0 16.8
-R27 Y.n6 Y.t3 16.8
-R28 Y.n4 Y.t2 16.8
-R29 Y.n4 Y.t1 16.8
-R30 Y.n0 Y.t7 9.193
-R31 Y.n0 Y.t6 9.193
-R32 Y.n2 Y.t5 9.193
-R33 Y.n2 Y.t4 9.193
-R34 Y.n7 Y.n5 0.575
-R35 Y.n3 Y.n1 0.573
-R36 Y Y.n7 0.536
-R37 Y Y.n3 0.47
-C4 vdd gnd 1.279080fF
-C5 Y.t7 gnd 0.098917fF
-C6 Y.t6 gnd 0.098917fF
-C7 Y.t5 gnd 0.098917fF
-C8 Y.t4 gnd 0.098917fF
-C9 Y.t2 gnd 0.032972fF
-C10 Y.t1 gnd 0.032972fF
-C11 Y.t0 gnd 0.032972fF
-C12 Y.t3 gnd 0.032972fF
-C13 a_n8_115.t3 gnd 0.177941fF
-C14 a_n8_115.t9 gnd 0.177941fF
-C15 a_n8_115.t6 gnd 0.196507fF
-C16 a_n8_115.t5 gnd 0.179712fF
-C17 a_n8_115.t7 gnd 0.073151fF
-C18 a_n8_115.t4 gnd 0.073151fF
-C19 a_n8_115.t2 gnd 0.073151fF
-C20 a_n8_115.t8 gnd 0.092209fF
-C21 a_n8_115.t0 gnd 0.308552fF
-C22 a_n8_115.t1 gnd 0.625620fF
-C23 A.t1 gnd 0.312987fF
-C24 A.t0 gnd 0.158393fF
-.ends
diff --git a/cdl/DLY3.cdl b/cdl/DLY3.cdl
deleted file mode 100644
index 3ef4e16..0000000
--- a/cdl/DLY3.cdl
+++ /dev/null
@@ -1,119 +0,0 @@
-* SPICE3 file created from DLY3.ext - technology: EFS8A
-
-.subckt DLY3 A Y
-M1000 gnd A.t0 a_n8_115.t0 gnd nshort w=1u l=0.15u
-+  ad=0.157857p pd=1.45857u as=0.265p ps=2.53u
-M1001 vdd a_n8_115.t2 Y.t11 vdd pshort w=3u l=0.15u
-+  ad=0.473571p pd=3.74429u as=0.42p ps=3.28u
-M1002 Y.t5 a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.157857p ps=1.45857u
-M1003 vdd a_n8_115.t4 Y.t10 vdd pshort w=3u l=0.15u
-+  ad=0.473571p pd=3.74429u as=0.42p ps=3.28u
-M1004 gnd a_n8_115.t5 Y.t4 gnd nshort w=1u l=0.15u
-+  ad=0.157857p pd=1.45857u as=0.14p ps=1.28u
-M1005 Y.t9 a_n8_115.t6 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.473571p ps=3.74429u
-M1006 gnd a_n8_115.t7 Y.t3 gnd nshort w=1u l=0.15u
-+  ad=0.157857p pd=1.45857u as=0.14p ps=1.28u
-M1007 Y.t8 a_n8_115.t8 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.473571p ps=3.74429u
-M1008 Y.t2 a_n8_115.t9 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.157857p ps=1.45857u
-M1009 vdd a_n8_115.t10 Y.t7 vdd pshort w=3u l=0.15u
-+  ad=0.473571p pd=3.74429u as=0.42p ps=3.28u
-M1010 Y.t1 a_n8_115.t11 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.157857p ps=1.45857u
-M1011 vdd A.t1 a_n8_115.t1 vdd pshort w=3u l=0.15u
-+  ad=0.473571p pd=3.74429u as=0.795p ps=6.53u
-M1012 gnd a_n8_115.t12 Y.t0 gnd nshort w=1u l=0.15u
-+  ad=0.157857p pd=1.45857u as=0.14p ps=1.28u
-M1013 Y.t6 a_n8_115.t13 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.473571p ps=3.74429u
-C0 m1_n35_1379# Y 0.217843fF
-C1 m1_n35_0# Y 0.373213fF
-C2 m1_n35_1379# m1_n35_0# 0.124489fF
-C3 vdd Y 0.012577fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 558.047
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n1 a_n8_115.t2 676.406
-R6 a_n8_115.n5 a_n8_115.t8 551.621
-R7 a_n8_115.n1 a_n8_115.t6 538.233
-R8 a_n8_115.n2 a_n8_115.t10 538.233
-R9 a_n8_115.n3 a_n8_115.t13 538.233
-R10 a_n8_115.n4 a_n8_115.t4 538.233
-R11 a_n8_115.n0 a_n8_115.t5 483.605
-R12 a_n8_115.n9 a_n8_115.t11 345.432
-R13 a_n8_115.n0 a_n8_115.t9 345.432
-R14 a_n8_115.n8 a_n8_115.t7 345.432
-R15 a_n8_115.n7 a_n8_115.t3 345.432
-R16 a_n8_115.n6 a_n8_115.t12 345.432
-R17 a_n8_115.n1 a_n8_115.n0 321.333
-R18 a_n8_115.n10 a_n8_115.n9 292.948
-R19 a_n8_115.n11 a_n8_115.t0 255.638
-R20 a_n8_115.t1 a_n8_115.n11 179.239
-R21 a_n8_115.n2 a_n8_115.n1 138.173
-R22 a_n8_115.n3 a_n8_115.n2 138.173
-R23 a_n8_115.n4 a_n8_115.n3 138.173
-R24 a_n8_115.n7 a_n8_115.n6 138.173
-R25 a_n8_115.n8 a_n8_115.n7 138.173
-R26 a_n8_115.n9 a_n8_115.n8 138.173
-R27 a_n8_115.n5 a_n8_115.n4 75.513
-R28 a_n8_115.n11 a_n8_115.n10 25.8
-R29 a_n8_115.n10 a_n8_115.n5 16.066
-R30 Y.n2 Y.n1 191.147
-R31 Y.n3 Y.n0 191.147
-R32 Y.n5 Y.n4 191.147
-R33 Y.n11 Y.n10 161.723
-R34 Y.n9 Y.n6 161.723
-R35 Y.n8 Y.n7 161.723
-R36 Y.n10 Y.t4 16.8
-R37 Y.n10 Y.t2 16.8
-R38 Y.n6 Y.t0 16.8
-R39 Y.n6 Y.t5 16.8
-R40 Y.n7 Y.t3 16.8
-R41 Y.n7 Y.t1 16.8
-R42 Y.n1 Y.t10 9.193
-R43 Y.n1 Y.t8 9.193
-R44 Y.n0 Y.t7 9.193
-R45 Y.n0 Y.t6 9.193
-R46 Y.n4 Y.t11 9.193
-R47 Y.n4 Y.t9 9.193
-R48 Y.n9 Y.n8 0.575
-R49 Y.n11 Y.n9 0.575
-R50 Y.n5 Y.n3 0.573
-R51 Y.n3 Y.n2 0.573
-R52 Y Y.n11 0.558
-R53 Y Y.n5 0.448
-C4 vdd gnd 1.680360fF
-C5 Y.t7 gnd 0.079518fF
-C6 Y.t6 gnd 0.079518fF
-C7 Y.t10 gnd 0.079518fF
-C8 Y.t8 gnd 0.079518fF
-C9 Y.t11 gnd 0.079518fF
-C10 Y.t9 gnd 0.079518fF
-C11 Y.t0 gnd 0.026506fF
-C12 Y.t5 gnd 0.026506fF
-C13 Y.t3 gnd 0.026506fF
-C14 Y.t1 gnd 0.026506fF
-C15 Y.t4 gnd 0.026506fF
-C16 Y.t2 gnd 0.026506fF
-C17 a_n8_115.t4 gnd 0.157573fF
-C18 a_n8_115.t13 gnd 0.157573fF
-C19 a_n8_115.t10 gnd 0.157573fF
-C20 a_n8_115.t6 gnd 0.157573fF
-C21 a_n8_115.t2 gnd 0.174014fF
-C22 a_n8_115.t9 gnd 0.064778fF
-C23 a_n8_115.t5 gnd 0.081655fF
-C24 a_n8_115.t8 gnd 0.159141fF
-C25 a_n8_115.t11 gnd 0.064778fF
-C26 a_n8_115.t7 gnd 0.064778fF
-C27 a_n8_115.t3 gnd 0.064778fF
-C28 a_n8_115.t12 gnd 0.064778fF
-C29 a_n8_115.t0 gnd 0.273234fF
-C30 a_n8_115.t1 gnd 0.554009fF
-C31 A.t1 gnd 0.347207fF
-C32 A.t0 gnd 0.175710fF
-.ends
diff --git a/cdl/DLY4.cdl b/cdl/DLY4.cdl
deleted file mode 100644
index a164a4d..0000000
--- a/cdl/DLY4.cdl
+++ /dev/null
@@ -1,151 +0,0 @@
-* SPICE3 file created from DLY4.ext - technology: EFS8A
-
-.subckt DLY4 A Y
-M1000 gnd A.t0 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.158333p pd=1.42778u as=0.265p ps=2.53u
-M1001 vdd a_n8_115.t2 Y.t7 vdd pshort w=3u l=0.15u
-+  ad=0.475p pd=3.65u as=0.42p ps=3.28u
-M1002 Y.t15 a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.158333p ps=1.42778u
-M1003 Y.t14 a_n8_115.t4 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.158333p ps=1.42778u
-M1004 vdd a_n8_115.t5 Y.t6 vdd pshort w=3u l=0.15u
-+  ad=0.475p pd=3.65u as=0.42p ps=3.28u
-M1005 gnd a_n8_115.t6 Y.t13 gnd nshort w=1u l=0.15u
-+  ad=0.158333p pd=1.42778u as=0.14p ps=1.28u
-M1006 Y.t5 a_n8_115.t7 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.475p ps=3.65u
-M1007 gnd a_n8_115.t8 Y.t12 gnd nshort w=1u l=0.15u
-+  ad=0.158333p pd=1.42778u as=0.14p ps=1.28u
-M1008 Y.t4 a_n8_115.t9 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.475p ps=3.65u
-M1009 vdd a_n8_115.t10 Y.t3 vdd pshort w=3u l=0.15u
-+  ad=0.475p pd=3.65u as=0.42p ps=3.28u
-M1010 Y.t11 a_n8_115.t11 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.158333p ps=1.42778u
-M1011 vdd a_n8_115.t12 Y.t2 vdd pshort w=3u l=0.15u
-+  ad=0.475p pd=3.65u as=0.42p ps=3.28u
-M1012 Y.t10 a_n8_115.t13 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.158333p ps=1.42778u
-M1013 gnd a_n8_115.t14 Y.t9 gnd nshort w=1u l=0.15u
-+  ad=0.158333p pd=1.42778u as=0.14p ps=1.28u
-M1014 vdd A.t1 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.475p pd=3.65u as=0.795p ps=6.53u
-M1015 Y.t1 a_n8_115.t15 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.475p ps=3.65u
-M1016 gnd a_n8_115.t16 Y.t8 gnd nshort w=1u l=0.15u
-+  ad=0.158333p pd=1.42778u as=0.14p ps=1.28u
-M1017 Y.t0 a_n8_115.t17 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.475p ps=3.65u
-C0 m1_n35_0# Y 0.544061fF
-C1 m1_n35_1379# m1_n35_0# 0.154668fF
-C2 vdd Y 0.019608fF
-C3 m1_n35_1379# Y 0.318095fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 558.047
-R2 A.n1 A.n0 7.5
-R3 A A.n1 3.142
-R4 A.n1 A 3.142
-R5 a_n8_115.n0 a_n8_115.t10 676.406
-R6 a_n8_115.n9 a_n8_115.t9 551.621
-R7 a_n8_115.n5 a_n8_115.t7 538.233
-R8 a_n8_115.n0 a_n8_115.t15 538.233
-R9 a_n8_115.n1 a_n8_115.t2 538.233
-R10 a_n8_115.n6 a_n8_115.t12 538.233
-R11 a_n8_115.n7 a_n8_115.t17 538.233
-R12 a_n8_115.n8 a_n8_115.t5 538.233
-R13 a_n8_115.n2 a_n8_115.t14 483.605
-R14 a_n8_115.n13 a_n8_115.t13 345.432
-R15 a_n8_115.n4 a_n8_115.t11 345.432
-R16 a_n8_115.n12 a_n8_115.t8 345.432
-R17 a_n8_115.n11 a_n8_115.t4 345.432
-R18 a_n8_115.n10 a_n8_115.t16 345.432
-R19 a_n8_115.n3 a_n8_115.t6 345.432
-R20 a_n8_115.n2 a_n8_115.t3 345.432
-R21 a_n8_115.n5 a_n8_115.n4 321.333
-R22 a_n8_115.n14 a_n8_115.n13 292.948
-R23 a_n8_115.n15 a_n8_115.t1 255.638
-R24 a_n8_115.t0 a_n8_115.n15 179.239
-R25 a_n8_115.n1 a_n8_115.n0 151.026
-R26 a_n8_115.n3 a_n8_115.n2 151.026
-R27 a_n8_115.n5 a_n8_115.n1 138.173
-R28 a_n8_115.n6 a_n8_115.n5 138.173
-R29 a_n8_115.n7 a_n8_115.n6 138.173
-R30 a_n8_115.n8 a_n8_115.n7 138.173
-R31 a_n8_115.n4 a_n8_115.n3 138.173
-R32 a_n8_115.n11 a_n8_115.n10 138.173
-R33 a_n8_115.n12 a_n8_115.n11 138.173
-R34 a_n8_115.n13 a_n8_115.n12 138.173
-R35 a_n8_115.n9 a_n8_115.n8 75.513
-R36 a_n8_115.n15 a_n8_115.n14 25.8
-R37 a_n8_115.n14 a_n8_115.n9 16.066
-R38 Y.n3 Y.n2 191.147
-R39 Y.n4 Y.n1 191.147
-R40 Y.n5 Y.n0 191.147
-R41 Y.n7 Y.n6 191.147
-R42 Y.n15 Y.n14 161.723
-R43 Y.n13 Y.n8 161.723
-R44 Y.n12 Y.n9 161.723
-R45 Y.n11 Y.n10 161.723
-R46 Y.n14 Y.t9 16.8
-R47 Y.n14 Y.t15 16.8
-R48 Y.n8 Y.t13 16.8
-R49 Y.n8 Y.t11 16.8
-R50 Y.n9 Y.t8 16.8
-R51 Y.n9 Y.t14 16.8
-R52 Y.n10 Y.t12 16.8
-R53 Y.n10 Y.t10 16.8
-R54 Y.n2 Y.t6 9.193
-R55 Y.n2 Y.t4 9.193
-R56 Y.n1 Y.t2 9.193
-R57 Y.n1 Y.t0 9.193
-R58 Y.n0 Y.t7 9.193
-R59 Y.n0 Y.t5 9.193
-R60 Y.n6 Y.t3 9.193
-R61 Y.n6 Y.t1 9.193
-R62 Y.n15 Y.n13 0.604
-R63 Y.n7 Y.n5 0.603
-R64 Y.n12 Y.n11 0.575
-R65 Y.n13 Y.n12 0.575
-R66 Y.n5 Y.n4 0.573
-R67 Y.n4 Y.n3 0.573
-R68 Y Y.n15 0.536
-R69 Y Y.n7 0.47
-C4 vdd gnd 2.081640fF
-C5 Y.t7 gnd 0.069243fF
-C6 Y.t5 gnd 0.069243fF
-C7 Y.t2 gnd 0.069243fF
-C8 Y.t0 gnd 0.069243fF
-C9 Y.t6 gnd 0.069243fF
-C10 Y.t4 gnd 0.069243fF
-C11 Y.t3 gnd 0.069243fF
-C12 Y.t1 gnd 0.069243fF
-C13 Y.t13 gnd 0.023081fF
-C14 Y.t11 gnd 0.023081fF
-C15 Y.t8 gnd 0.023081fF
-C16 Y.t14 gnd 0.023081fF
-C17 Y.t12 gnd 0.023081fF
-C18 Y.t10 gnd 0.023081fF
-C19 Y.t9 gnd 0.023081fF
-C20 Y.t15 gnd 0.023081fF
-C21 a_n8_115.t5 gnd 0.142504fF
-C22 a_n8_115.t17 gnd 0.142504fF
-C23 a_n8_115.t12 gnd 0.142504fF
-C24 a_n8_115.t7 gnd 0.142504fF
-C25 a_n8_115.t2 gnd 0.142504fF
-C26 a_n8_115.t15 gnd 0.142504fF
-C27 a_n8_115.t10 gnd 0.157373fF
-C28 a_n8_115.t11 gnd 0.058583fF
-C29 a_n8_115.t6 gnd 0.058583fF
-C30 a_n8_115.t3 gnd 0.058583fF
-C31 a_n8_115.t14 gnd 0.073846fF
-C32 a_n8_115.t9 gnd 0.143922fF
-C33 a_n8_115.t13 gnd 0.058583fF
-C34 a_n8_115.t8 gnd 0.058583fF
-C35 a_n8_115.t4 gnd 0.058583fF
-C36 a_n8_115.t16 gnd 0.058583fF
-C37 a_n8_115.t1 gnd 0.247104fF
-C38 a_n8_115.t0 gnd 0.501028fF
-C39 A.t1 gnd 0.362901fF
-C40 A.t0 gnd 0.183653fF
-.ends
diff --git a/cdl/FILLX1.cdl b/cdl/FILLX1.cdl
deleted file mode 100644
index 86a51b0..0000000
--- a/cdl/FILLX1.cdl
+++ /dev/null
@@ -1,3 +0,0 @@
-* SPICE3 file created from FILLX1.ext - technology: EFS8A
-
-C0 m1_n35_1379# m1_n35_0# 0.003772fF
diff --git a/cdl/FILLX16.cdl b/cdl/FILLX16.cdl
deleted file mode 100644
index 1929522..0000000
--- a/cdl/FILLX16.cdl
+++ /dev/null
@@ -1,3 +0,0 @@
-* SPICE3 file created from FILLX16.ext - technology: EFS8A
-
-C0 m1_n35_1379# m1_n35_0# 0.060358fF
diff --git a/cdl/FILLX2.cdl b/cdl/FILLX2.cdl
deleted file mode 100644
index 0226f80..0000000
--- a/cdl/FILLX2.cdl
+++ /dev/null
@@ -1,3 +0,0 @@
-* SPICE3 file created from FILLX2.ext - technology: EFS8A
-
-C0 m1_n35_1379# m1_n35_0# 0.007545fF
diff --git a/cdl/FILLX32.cdl b/cdl/FILLX32.cdl
deleted file mode 100644
index 05e8466..0000000
--- a/cdl/FILLX32.cdl
+++ /dev/null
@@ -1,3 +0,0 @@
-* SPICE3 file created from FILLX32.ext - technology: EFS8A
-
-C0 m1_n35_1379# m1_n35_0# 0.120716fF
diff --git a/cdl/FILLX4.cdl b/cdl/FILLX4.cdl
deleted file mode 100644
index 2502078..0000000
--- a/cdl/FILLX4.cdl
+++ /dev/null
@@ -1,3 +0,0 @@
-* SPICE3 file created from FILLX4.ext - technology: EFS8A
-
-C0 m1_n35_1379# m1_n35_0# 0.015090fF
diff --git a/cdl/FILLX8.cdl b/cdl/FILLX8.cdl
deleted file mode 100644
index 8faff48..0000000
--- a/cdl/FILLX8.cdl
+++ /dev/null
@@ -1,3 +0,0 @@
-* SPICE3 file created from FILLX8.ext - technology: EFS8A
-
-C0 m1_n35_1379# m1_n35_0# 0.030179fF
diff --git a/cdl/INVX1.cdl b/cdl/INVX1.cdl
deleted file mode 100644
index b0796bc..0000000
--- a/cdl/INVX1.cdl
+++ /dev/null
@@ -1,23 +0,0 @@
-* SPICE3 file created from INVX1.ext - technology: EFS8A
-
-.subckt INVX1 A Y
-M1000 Y.t1 A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.265p ps=2.53u
-M1001 Y.t0 A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.795p ps=6.53u
-C0 m1_n35_0# Y 0.047670fF
-C1 A Y 0.013384fF
-C2 m1_n35_1379# m1_n35_0# 0.033951fF
-C3 vdd Y 0.001338fF
-C4 m1_n35_1379# Y 0.026952fF
-R0 A.n0 A.t1 824.755
-R1 A.n0 A.t0 429.514
-R2 A A.n0 7.5
-R3 Y Y.t0 200.833
-R4 Y Y.t1 179.134
-C5 vdd gnd 0.474240fF
-C6 Y.t0 gnd 0.064007fF
-C7 Y.t1 gnd 0.023907fF
-C8 A.t1 gnd 0.049713fF
-C9 A.t0 gnd 0.019559fF
-.ends
diff --git a/cdl/INVX10.cdl b/cdl/INVX10.cdl
deleted file mode 100644
index 45fe914..0000000
--- a/cdl/INVX10.cdl
+++ /dev/null
@@ -1,173 +0,0 @@
-* SPICE3 file created from INVX10.ext - technology: EFS8A
-
-.subckt INVX10 A Y
-M1000 Y.t19 A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.165p ps=1.53u
-M1001 gnd A.t1 Y.t18 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.14p ps=1.28u
-M1002 Y.t9 A.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1003 gnd A.t3 Y.t17 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.14p ps=1.28u
-M1004 Y.t8 A.t4 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1005 vdd A.t5 Y.t7 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1006 Y.t16 A.t6 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.165p ps=1.53u
-M1007 vdd A.t7 Y.t6 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1008 Y.t15 A.t8 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.165p ps=1.53u
-M1009 gnd A.t9 Y.t14 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.14p ps=1.28u
-M1010 vdd A.t10 Y.t5 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1011 Y.t4 A.t11 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1012 gnd A.t12 Y.t13 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.14p ps=1.28u
-M1013 Y.t3 A.t13 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1014 gnd A.t14 Y.t12 gnd nshort w=1u l=0.15u
-+  ad=0.165p pd=1.53u as=0.14p ps=1.28u
-M1015 Y.t11 A.t15 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.165p ps=1.53u
-M1016 Y.t2 A.t16 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.495p ps=3.93u
-M1017 vdd A.t17 Y.t1 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-M1018 Y.t10 A.t18 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.165p ps=1.53u
-M1019 vdd A.t19 Y.t0 vdd pshort w=3u l=0.15u
-+  ad=0.495p pd=3.93u as=0.42p ps=3.28u
-C0 m1_n35_0# Y 0.698731fF
-C1 A Y 0.225464fF
-C2 m1_n35_1379# m1_n35_0# 0.169757fF
-C3 vdd Y 0.020842fF
-C4 m1_n35_1379# Y 0.408706fF
-R0 A.n8 A.t5 644.273
-R1 A.n4 A.t9 538.232
-R2 A.n3 A.t16 506.1
-R3 A.n8 A.t11 506.1
-R4 A.n9 A.t17 506.1
-R5 A.n10 A.t2 506.1
-R6 A.n11 A.t7 506.1
-R7 A.n12 A.t13 506.1
-R8 A.n0 A.t19 506.1
-R9 A.n1 A.t4 506.1
-R10 A.n2 A.t10 506.1
-R11 A.n17 A.t0 413.447
-R12 A.n13 A.t18 400.059
-R13 A.n4 A.t15 400.059
-R14 A.n16 A.t14 400.059
-R15 A.n15 A.t8 400.059
-R16 A.n14 A.t3 400.059
-R17 A.n7 A.t12 400.059
-R18 A.n6 A.t6 400.059
-R19 A.n5 A.t1 400.059
-R20 A.n13 A.n12 298.84
-R21 A.n18 A.n3 270.455
-R22 A.n5 A.n4 138.173
-R23 A.n6 A.n5 138.173
-R24 A.n7 A.n6 138.173
-R25 A.n13 A.n7 138.173
-R26 A.n14 A.n13 138.173
-R27 A.n15 A.n14 138.173
-R28 A.n16 A.n15 138.173
-R29 A.n9 A.n8 138.173
-R30 A.n10 A.n9 138.173
-R31 A.n11 A.n10 138.173
-R32 A.n12 A.n11 138.173
-R33 A.n1 A.n0 138.173
-R34 A.n2 A.n1 138.173
-R35 A.n3 A.n2 138.173
-R36 A.n17 A.n16 75.513
-R37 A.n18 A.n17 16.066
-R38 A A.n18 7.5
-R39 Y.n1 Y.n0 191.149
-R40 Y.n6 Y.n5 191.147
-R41 Y.n9 Y.n8 191.147
-R42 Y.n11 Y.n10 191.147
-R43 Y.n3 Y.n2 191.147
-R44 Y.n13 Y.n12 161.725
-R45 Y.n23 Y.n22 161.723
-R46 Y.n21 Y.n20 161.723
-R47 Y.n18 Y.n17 161.723
-R48 Y.n15 Y.n14 161.723
-R49 Y.n22 Y.t12 16.8
-R50 Y.n22 Y.t19 16.8
-R51 Y.n20 Y.t17 16.8
-R52 Y.n20 Y.t15 16.8
-R53 Y.n17 Y.t13 16.8
-R54 Y.n17 Y.t10 16.8
-R55 Y.n14 Y.t18 16.8
-R56 Y.n14 Y.t16 16.8
-R57 Y.n12 Y.t14 16.8
-R58 Y.n12 Y.t11 16.8
-R59 Y.n5 Y.t6 9.193
-R60 Y.n5 Y.t3 9.193
-R61 Y.n8 Y.t0 9.193
-R62 Y.n8 Y.t8 9.193
-R63 Y.n10 Y.t5 9.193
-R64 Y.n10 Y.t2 9.193
-R65 Y.n2 Y.t1 9.193
-R66 Y.n2 Y.t9 9.193
-R67 Y.n0 Y.t7 9.193
-R68 Y.n0 Y.t4 9.193
-R69 Y.n11 Y.n9 0.575
-R70 Y.n23 Y.n21 0.575
-R71 Y.n9 Y.n7 0.573
-R72 Y.n18 Y.n16 0.573
-R73 Y.n3 Y.n1 0.573
-R74 Y.n15 Y.n13 0.573
-R75 Y.n6 Y.n4 0.573
-R76 Y.n21 Y.n19 0.573
-R77 Y Y.n23 0.562
-R78 Y Y.n11 0.444
-R79 Y.n16 Y.n15 0.002
-R80 Y.n4 Y.n3 0.002
-R81 Y.n7 Y.n6 0.002
-R82 Y.n19 Y.n18 0.002
-C5 vdd gnd 2.277720fF
-C6 Y.t7 gnd 0.026080fF
-C7 Y.t4 gnd 0.026080fF
-C8 Y.t1 gnd 0.026080fF
-C9 Y.t9 gnd 0.026080fF
-C10 Y.t6 gnd 0.026080fF
-C11 Y.t3 gnd 0.026080fF
-C12 Y.t0 gnd 0.026080fF
-C13 Y.t8 gnd 0.026080fF
-C14 Y.t5 gnd 0.026080fF
-C15 Y.t2 gnd 0.026080fF
-C16 Y.t14 gnd 0.008693fF
-C17 Y.t11 gnd 0.008693fF
-C18 Y.t18 gnd 0.008693fF
-C19 Y.t16 gnd 0.008693fF
-C20 Y.t13 gnd 0.008693fF
-C21 Y.t10 gnd 0.008693fF
-C22 Y.t17 gnd 0.008693fF
-C23 Y.t15 gnd 0.008693fF
-C24 Y.t12 gnd 0.008693fF
-C25 Y.t19 gnd 0.008693fF
-C26 A.t16 gnd 0.012780fF
-C27 A.t10 gnd 0.012780fF
-C28 A.t4 gnd 0.012780fF
-C29 A.t19 gnd 0.012780fF
-C30 A.t14 gnd 0.005879fF
-C31 A.t8 gnd 0.005879fF
-C32 A.t3 gnd 0.005879fF
-C33 A.t18 gnd 0.005879fF
-C34 A.t12 gnd 0.005879fF
-C35 A.t6 gnd 0.005879fF
-C36 A.t1 gnd 0.005879fF
-C37 A.t15 gnd 0.005879fF
-C38 A.t9 gnd 0.007266fF
-C39 A.t13 gnd 0.012780fF
-C40 A.t7 gnd 0.012780fF
-C41 A.t2 gnd 0.012780fF
-C42 A.t17 gnd 0.012780fF
-C43 A.t11 gnd 0.012780fF
-C44 A.t5 gnd 0.014148fF
-C45 A.t0 gnd 0.006011fF
-.ends
diff --git a/cdl/INVX2.cdl b/cdl/INVX2.cdl
deleted file mode 100644
index 4a4272f..0000000
--- a/cdl/INVX2.cdl
+++ /dev/null
@@ -1,39 +0,0 @@
-* SPICE3 file created from INVX2.ext - technology: EFS8A
-
-.subckt INVX2 A Y
-M1000 Y.t3 A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.265p ps=2.53u
-M1001 vdd A.t1 Y.t1 vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.28u
-M1002 gnd A.t2 Y.t2 gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.14p ps=1.28u
-M1003 Y.t0 A.t3 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-C0 m1_n35_0# Y 0.047670fF
-C1 A Y 0.033891fF
-C2 m1_n35_1379# m1_n35_0# 0.049041fF
-C3 vdd Y 0.000538fF
-C4 m1_n35_1379# Y 0.026952fF
-R0 A.n0 A.t1 644.273
-R1 A.n0 A.t3 506.1
-R2 A.n1 A.t2 475.572
-R3 A.n1 A.t0 413.447
-R4 A.n2 A.n0 270.455
-R5 A.n2 A.n1 16.066
-R6 A A.n2 7.5
-R7 Y Y.n0 191.64
-R8 Y Y.n1 162.334
-R9 Y.n1 Y.t2 16.8
-R10 Y.n1 Y.t3 16.8
-R11 Y.n0 Y.t1 9.193
-R12 Y.n0 Y.t0 9.193
-C5 vdd gnd 0.674880fF
-C6 Y.t1 gnd 0.012331fF
-C7 Y.t0 gnd 0.012331fF
-C8 Y.t2 gnd 0.004110fF
-C9 Y.t3 gnd 0.004110fF
-C10 A.t3 gnd 0.026812fF
-C11 A.t1 gnd 0.029684fF
-C12 A.t2 gnd 0.013943fF
-C13 A.t0 gnd 0.012612fF
-.ends
diff --git a/cdl/INVX3.cdl b/cdl/INVX3.cdl
deleted file mode 100644
index 187dad6..0000000
--- a/cdl/INVX3.cdl
+++ /dev/null
@@ -1,57 +0,0 @@
-* SPICE3 file created from INVX3.ext - technology: EFS8A
-
-.subckt INVX3 A Y
-M1000 Y.t2 A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.181667p ps=1.69667u
-M1001 Y.t5 A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.545p ps=4.36333u
-M1002 Y.t1 A.t2 gnd gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.181667p ps=1.69667u
-M1003 vdd A.t3 Y.t4 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.545p ps=4.36333u
-M1004 gnd A.t4 Y.t0 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.181667p ps=1.69667u
-M1005 Y.t3 A.t5 vdd vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.545p ps=4.36333u
-C0 m1_n35_1379# Y 0.122391fF
-C1 m1_n35_0# Y 0.210435fF
-C2 m1_n35_1379# m1_n35_0# 0.064131fF
-C3 Y vdd 0.006414fF
-C4 A Y 0.057732fF
-R0 A.n0 A.t1 644.273
-R1 A.n2 A.t2 538.232
-R2 A.n1 A.t5 506.1
-R3 A.n0 A.t3 506.1
-R4 A.n3 A.t0 413.447
-R5 A.n2 A.t4 400.059
-R6 A.n4 A.n1 270.455
-R7 A.n1 A.n0 138.173
-R8 A.n3 A.n2 75.513
-R9 A.n4 A.n3 16.066
-R10 A A.n4 7.5
-R11 Y.n0 Y.t5 200.34
-R12 Y.n2 Y.n1 191.147
-R13 Y.n3 Y.t1 178.523
-R14 Y.n5 Y.n4 161.723
-R15 Y.n4 Y.t0 16.8
-R16 Y.n4 Y.t2 16.8
-R17 Y.n1 Y.t4 9.193
-R18 Y.n1 Y.t3 9.193
-R19 Y.n2 Y.n0 0.575
-R20 Y.n5 Y.n3 0.575
-R21 Y Y.n5 0.562
-R22 Y Y.n2 0.444
-C5 vdd gnd 0.875520fF
-C6 Y.t5 gnd 0.115119fF
-C7 Y.t4 gnd 0.020782fF
-C8 Y.t3 gnd 0.020782fF
-C9 Y.t1 gnd 0.042945fF
-C10 Y.t0 gnd 0.006927fF
-C11 Y.t2 gnd 0.006927fF
-C12 A.t5 gnd 0.021337fF
-C13 A.t3 gnd 0.021337fF
-C14 A.t1 gnd 0.023623fF
-C15 A.t4 gnd 0.009816fF
-C16 A.t2 gnd 0.012132fF
-C17 A.t0 gnd 0.010037fF
-.ends
diff --git a/cdl/INVX4.cdl b/cdl/INVX4.cdl
deleted file mode 100644
index 30a62bc..0000000
--- a/cdl/INVX4.cdl
+++ /dev/null
@@ -1,73 +0,0 @@
-* SPICE3 file created from INVX4.ext - technology: EFS8A
-
-.subckt INVX4 A Y
-M1000 Y.t3 A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.2025p ps=1.905u
-M1001 gnd A.t1 Y.t2 gnd nshort w=1u l=0.15u
-+  ad=0.2025p pd=1.905u as=0.14p ps=1.28u
-M1002 Y.t7 A.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.6075p ps=4.905u
-M1003 Y.t1 A.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.2025p ps=1.905u
-M1004 vdd A.t4 Y.t6 vdd pshort w=3u l=0.15u
-+  ad=0.6075p pd=4.905u as=0.42p ps=3.28u
-M1005 gnd A.t5 Y.t0 gnd nshort w=1u l=0.15u
-+  ad=0.2025p pd=1.905u as=0.14p ps=1.28u
-M1006 Y.t5 A.t6 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.6075p ps=4.905u
-M1007 vdd A.t7 Y.t4 vdd pshort w=3u l=0.15u
-+  ad=0.6075p pd=4.905u as=0.42p ps=3.28u
-C0 m1_n35_1379# Y 0.122391fF
-C1 m1_n35_0# Y 0.210435fF
-C2 vdd Y 0.005614fF
-C3 A Y 0.081784fF
-C4 m1_n35_1379# m1_n35_0# 0.079220fF
-R0 A.n0 A.t7 644.273
-R1 A.n3 A.t1 538.232
-R2 A.n2 A.t6 506.1
-R3 A.n0 A.t2 506.1
-R4 A.n1 A.t4 506.1
-R5 A.n5 A.t0 413.447
-R6 A.n4 A.t5 400.059
-R7 A.n3 A.t3 400.059
-R8 A.n6 A.n2 270.455
-R9 A.n4 A.n3 138.173
-R10 A.n1 A.n0 138.173
-R11 A.n2 A.n1 138.173
-R12 A.n5 A.n4 75.513
-R13 A.n6 A.n5 16.066
-R14 A A.n6 7.5
-R15 Y.n1 Y.n0 191.147
-R16 Y.n3 Y.n2 191.147
-R17 Y.n7 Y.n6 161.723
-R18 Y.n5 Y.n4 161.723
-R19 Y.n6 Y.t0 16.8
-R20 Y.n6 Y.t3 16.8
-R21 Y.n4 Y.t2 16.8
-R22 Y.n4 Y.t1 16.8
-R23 Y.n0 Y.t4 9.193
-R24 Y.n0 Y.t7 9.193
-R25 Y.n2 Y.t6 9.193
-R26 Y.n2 Y.t5 9.193
-R27 Y.n3 Y.n1 0.575
-R28 Y.n7 Y.n5 0.575
-R29 Y Y.n7 0.562
-R30 Y Y.n3 0.444
-C5 vdd gnd 1.076160fF
-C6 Y.t4 gnd 0.021135fF
-C7 Y.t7 gnd 0.021135fF
-C8 Y.t6 gnd 0.021135fF
-C9 Y.t5 gnd 0.021135fF
-C10 Y.t2 gnd 0.007045fF
-C11 Y.t1 gnd 0.007045fF
-C12 Y.t0 gnd 0.007045fF
-C13 Y.t3 gnd 0.007045fF
-C14 A.t6 gnd 0.018512fF
-C15 A.t4 gnd 0.018512fF
-C16 A.t2 gnd 0.018512fF
-C17 A.t7 gnd 0.020495fF
-C18 A.t5 gnd 0.008516fF
-C19 A.t3 gnd 0.008516fF
-C20 A.t1 gnd 0.010526fF
-C21 A.t0 gnd 0.008708fF
-.ends
diff --git a/cdl/INVX6.cdl b/cdl/INVX6.cdl
deleted file mode 100644
index 20540e0..0000000
--- a/cdl/INVX6.cdl
+++ /dev/null
@@ -1,105 +0,0 @@
-* SPICE3 file created from INVX6.ext - technology: EFS8A
-
-.subckt INVX6 A Y
-M1000 Y.t5 A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1001 gnd A.t1 Y.t4 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1002 Y.t11 A.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1003 vdd A.t3 Y.t10 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-M1004 Y.t3 A.t4 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1005 vdd A.t5 Y.t9 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-M1006 gnd A.t6 Y.t2 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1007 Y.t8 A.t7 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1008 gnd A.t8 Y.t1 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1009 Y.t7 A.t9 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1010 Y.t0 A.t10 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1011 vdd A.t11 Y.t6 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-C0 m1_n35_0# Y 0.373200fF
-C1 A Y 0.129677fF
-C2 m1_n35_1379# m1_n35_0# 0.109399fF
-C3 vdd Y 0.010690fF
-C4 m1_n35_1379# Y 0.217829fF
-R0 A.n4 A.t3 644.273
-R1 A.n5 A.t6 538.232
-R2 A.n3 A.t9 506.1
-R3 A.n4 A.t7 506.1
-R4 A.n0 A.t11 506.1
-R5 A.n1 A.t2 506.1
-R6 A.n2 A.t5 506.1
-R7 A.n9 A.t0 413.447
-R8 A.n5 A.t10 400.059
-R9 A.n8 A.t8 400.059
-R10 A.n7 A.t4 400.059
-R11 A.n6 A.t1 400.059
-R12 A.n5 A.n4 298.84
-R13 A.n10 A.n3 270.455
-R14 A.n6 A.n5 138.173
-R15 A.n7 A.n6 138.173
-R16 A.n8 A.n7 138.173
-R17 A.n1 A.n0 138.173
-R18 A.n2 A.n1 138.173
-R19 A.n3 A.n2 138.173
-R20 A.n9 A.n8 75.513
-R21 A.n10 A.n9 16.066
-R22 A A.n10 7.5
-R23 Y.n1 Y.n0 191.149
-R24 Y.n3 Y.n2 191.147
-R25 Y.n5 Y.n4 191.147
-R26 Y.n7 Y.n6 161.725
-R27 Y.n11 Y.n10 161.723
-R28 Y.n9 Y.n8 161.723
-R29 Y.n10 Y.t1 16.8
-R30 Y.n10 Y.t5 16.8
-R31 Y.n8 Y.t4 16.8
-R32 Y.n8 Y.t3 16.8
-R33 Y.n6 Y.t2 16.8
-R34 Y.n6 Y.t0 16.8
-R35 Y.n0 Y.t10 9.193
-R36 Y.n0 Y.t8 9.193
-R37 Y.n2 Y.t6 9.193
-R38 Y.n2 Y.t11 9.193
-R39 Y.n4 Y.t9 9.193
-R40 Y.n4 Y.t7 9.193
-R41 Y.n5 Y.n3 0.575
-R42 Y.n11 Y.n9 0.575
-R43 Y.n3 Y.n1 0.573
-R44 Y.n9 Y.n7 0.573
-R45 Y Y.n11 0.562
-R46 Y Y.n5 0.444
-C5 vdd gnd 1.477440fF
-C6 Y.t10 gnd 0.023912fF
-C7 Y.t8 gnd 0.023912fF
-C8 Y.t6 gnd 0.023912fF
-C9 Y.t11 gnd 0.023912fF
-C10 Y.t9 gnd 0.023912fF
-C11 Y.t7 gnd 0.023912fF
-C12 Y.t2 gnd 0.007971fF
-C13 Y.t0 gnd 0.007971fF
-C14 Y.t4 gnd 0.007971fF
-C15 Y.t3 gnd 0.007971fF
-C16 Y.t1 gnd 0.007971fF
-C17 Y.t5 gnd 0.007971fF
-C18 A.t9 gnd 0.015176fF
-C19 A.t5 gnd 0.015176fF
-C20 A.t2 gnd 0.015176fF
-C21 A.t11 gnd 0.015176fF
-C22 A.t8 gnd 0.006981fF
-C23 A.t4 gnd 0.006981fF
-C24 A.t1 gnd 0.006981fF
-C25 A.t10 gnd 0.006981fF
-C26 A.t6 gnd 0.008629fF
-C27 A.t7 gnd 0.015176fF
-C28 A.t3 gnd 0.016802fF
-C29 A.t0 gnd 0.007138fF
-.ends
diff --git a/cdl/INVX8.cdl b/cdl/INVX8.cdl
deleted file mode 100644
index 6d2dab3..0000000
--- a/cdl/INVX8.cdl
+++ /dev/null
@@ -1,139 +0,0 @@
-* SPICE3 file created from INVX8.ext - technology: EFS8A
-
-.subckt INVX8 A Y
-M1000 Y.t15 A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.17125p ps=1.5925u
-M1001 gnd A.t1 Y.t14 gnd nshort w=1u l=0.15u
-+  ad=0.17125p pd=1.5925u as=0.14p ps=1.28u
-M1002 Y.t7 A.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.51375p ps=4.0925u
-M1003 gnd A.t3 Y.t13 gnd nshort w=1u l=0.15u
-+  ad=0.17125p pd=1.5925u as=0.14p ps=1.28u
-M1004 Y.t6 A.t4 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.51375p ps=4.0925u
-M1005 Y.t12 A.t5 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.17125p ps=1.5925u
-M1006 vdd A.t6 Y.t5 vdd pshort w=3u l=0.15u
-+  ad=0.51375p pd=4.0925u as=0.42p ps=3.28u
-M1007 Y.t11 A.t7 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.17125p ps=1.5925u
-M1008 vdd A.t8 Y.t4 vdd pshort w=3u l=0.15u
-+  ad=0.51375p pd=4.0925u as=0.42p ps=3.28u
-M1009 gnd A.t9 Y.t10 gnd nshort w=1u l=0.15u
-+  ad=0.17125p pd=1.5925u as=0.14p ps=1.28u
-M1010 Y.t3 A.t10 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.51375p ps=4.0925u
-M1011 gnd A.t11 Y.t9 gnd nshort w=1u l=0.15u
-+  ad=0.17125p pd=1.5925u as=0.14p ps=1.28u
-M1012 Y.t2 A.t12 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.51375p ps=4.0925u
-M1013 vdd A.t13 Y.t1 vdd pshort w=3u l=0.15u
-+  ad=0.51375p pd=4.0925u as=0.42p ps=3.28u
-M1014 Y.t8 A.t14 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.17125p ps=1.5925u
-M1015 vdd A.t15 Y.t0 vdd pshort w=3u l=0.15u
-+  ad=0.51375p pd=4.0925u as=0.42p ps=3.28u
-C0 A Y 0.177570fF
-C1 m1_n35_1379# m1_n35_0# 0.139578fF
-C2 vdd Y 0.015766fF
-C3 m1_n35_1379# Y 0.313267fF
-C4 m1_n35_0# Y 0.535965fF
-R0 A.n6 A.t13 644.273
-R1 A.n4 A.t1 538.232
-R2 A.n3 A.t12 506.1
-R3 A.n6 A.t2 506.1
-R4 A.n7 A.t6 506.1
-R5 A.n8 A.t10 506.1
-R6 A.n0 A.t15 506.1
-R7 A.n1 A.t4 506.1
-R8 A.n2 A.t8 506.1
-R9 A.n13 A.t0 413.447
-R10 A.n9 A.t14 400.059
-R11 A.n12 A.t11 400.059
-R12 A.n11 A.t7 400.059
-R13 A.n10 A.t3 400.059
-R14 A.n5 A.t9 400.059
-R15 A.n4 A.t5 400.059
-R16 A.n9 A.n8 298.84
-R17 A.n14 A.n3 270.455
-R18 A.n5 A.n4 138.173
-R19 A.n9 A.n5 138.173
-R20 A.n10 A.n9 138.173
-R21 A.n11 A.n10 138.173
-R22 A.n12 A.n11 138.173
-R23 A.n7 A.n6 138.173
-R24 A.n8 A.n7 138.173
-R25 A.n1 A.n0 138.173
-R26 A.n2 A.n1 138.173
-R27 A.n3 A.n2 138.173
-R28 A.n13 A.n12 75.513
-R29 A.n14 A.n13 16.066
-R30 A A.n14 7.5
-R31 Y.n1 Y.n0 191.149
-R32 Y.n3 Y.n2 191.147
-R33 Y.n6 Y.n5 191.147
-R34 Y.n8 Y.n7 191.147
-R35 Y.n10 Y.n9 161.725
-R36 Y.n17 Y.n16 161.723
-R37 Y.n15 Y.n14 161.723
-R38 Y.n12 Y.n11 161.723
-R39 Y.n16 Y.t9 16.8
-R40 Y.n16 Y.t15 16.8
-R41 Y.n14 Y.t13 16.8
-R42 Y.n14 Y.t11 16.8
-R43 Y.n11 Y.t10 16.8
-R44 Y.n11 Y.t8 16.8
-R45 Y.n9 Y.t14 16.8
-R46 Y.n9 Y.t12 16.8
-R47 Y.n2 Y.t5 9.193
-R48 Y.n2 Y.t3 9.193
-R49 Y.n5 Y.t0 9.193
-R50 Y.n5 Y.t6 9.193
-R51 Y.n7 Y.t4 9.193
-R52 Y.n7 Y.t2 9.193
-R53 Y.n0 Y.t1 9.193
-R54 Y.n0 Y.t7 9.193
-R55 Y.n8 Y.n6 0.575
-R56 Y.n17 Y.n15 0.575
-R57 Y.n6 Y.n4 0.573
-R58 Y.n12 Y.n10 0.573
-R59 Y.n3 Y.n1 0.573
-R60 Y.n15 Y.n13 0.573
-R61 Y Y.n17 0.562
-R62 Y Y.n8 0.444
-R63 Y.n4 Y.n3 0.002
-R64 Y.n13 Y.n12 0.002
-C5 vdd gnd 1.876440fF
-C6 Y.t1 gnd 0.025272fF
-C7 Y.t7 gnd 0.025272fF
-C8 Y.t5 gnd 0.025272fF
-C9 Y.t3 gnd 0.025272fF
-C10 Y.t0 gnd 0.025272fF
-C11 Y.t6 gnd 0.025272fF
-C12 Y.t4 gnd 0.025272fF
-C13 Y.t2 gnd 0.025272fF
-C14 Y.t14 gnd 0.008424fF
-C15 Y.t12 gnd 0.008424fF
-C16 Y.t10 gnd 0.008424fF
-C17 Y.t8 gnd 0.008424fF
-C18 Y.t13 gnd 0.008424fF
-C19 Y.t11 gnd 0.008424fF
-C20 Y.t9 gnd 0.008424fF
-C21 Y.t15 gnd 0.008424fF
-C22 A.t12 gnd 0.013822fF
-C23 A.t8 gnd 0.013822fF
-C24 A.t4 gnd 0.013822fF
-C25 A.t15 gnd 0.013822fF
-C26 A.t11 gnd 0.006358fF
-C27 A.t7 gnd 0.006358fF
-C28 A.t3 gnd 0.006358fF
-C29 A.t14 gnd 0.006358fF
-C30 A.t9 gnd 0.006358fF
-C31 A.t5 gnd 0.006358fF
-C32 A.t1 gnd 0.007859fF
-C33 A.t10 gnd 0.013822fF
-C34 A.t6 gnd 0.013822fF
-C35 A.t2 gnd 0.013822fF
-C36 A.t13 gnd 0.015302fF
-C37 A.t0 gnd 0.006502fF
-.ends
diff --git a/cdl/INVXL.cdl b/cdl/INVXL.cdl
deleted file mode 100644
index cd5aad4..0000000
--- a/cdl/INVXL.cdl
+++ /dev/null
@@ -1,23 +0,0 @@
-* SPICE3 file created from INVXL.ext - technology: EFS8A
-
-.subckt INVXL A Y
-M1000 Y.t1 A.t0 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.1696p ps=1.81u
-M1001 Y.t0 A.t1 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.43725p ps=3.83u
-C0 m1_n35_0# Y 0.047670fF
-C1 A Y 0.013384fF
-C2 m1_n35_1379# m1_n35_0# 0.033951fF
-C3 vdd Y 0.001954fF
-C4 m1_n35_1379# Y 0.026952fF
-R0 A.n0 A.t1 1041.66
-R1 A.n0 A.t0 487.354
-R2 A A.n0 7.5
-R3 Y Y.t0 257.155
-R4 Y Y.t1 200.784
-C5 vdd gnd 0.474240fF
-C6 Y.t0 gnd 0.053807fF
-C7 Y.t1 gnd 0.022948fF
-C8 A.t1 gnd 0.068952fF
-C9 A.t0 gnd 0.028385fF
-.ends
diff --git a/cdl/NAND2X1.cdl b/cdl/NAND2X1.cdl
deleted file mode 100644
index dc1e590..0000000
--- a/cdl/NAND2X1.cdl
+++ /dev/null
@@ -1,38 +0,0 @@
-* SPICE3 file created from NAND2X1.ext - technology: EFS8A
-
-.subckt NAND2X1 B Y A
-M1000 a_75_115# A.t0 Y.t2 gnd nshort w=2u l=0.15u
-+  ad=0.21p pd=2.21u as=0.53p ps=4.53u
-M1001 vdd B.t0 Y.t0 vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.28u
-M1002 gnd B.t1 a_75_115# gnd nshort w=2u l=0.15u
-+  ad=0.53p pd=4.53u as=0.21p ps=2.21u
-M1003 Y.t1 A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-C0 B Y 0.023360fF
-C1 vdd Y 0.001199fF
-C2 a_75_115# Y 0.021635fF
-C3 m1_n35_1379# Y 0.044702fF
-C4 m1_n35_0# Y 0.097003fF
-C5 A B 0.340125fF
-C6 A Y 0.013240fF
-C7 m1_n35_1379# m1_n35_0# 0.049041fF
-R0 A.n0 A.t1 567.688
-R1 A.n0 A.t0 525.914
-R2 A A.n0 8.054
-R3 Y Y.n0 191.887
-R4 Y Y.t2 103.014
-R5 Y.n0 Y.t0 9.193
-R6 Y.n0 Y.t1 9.193
-R7 B.n0 B.t0 696.221
-R8 B.n0 B.t1 397.381
-R9 B B.n0 7.684
-C8 vdd gnd 0.672600fF
-C9 B.t0 gnd 0.163992fF
-C10 B.t1 gnd 0.099819fF
-C11 Y.t0 gnd 0.017814fF
-C12 Y.t1 gnd 0.017814fF
-C13 Y.t2 gnd 0.059698fF
-C14 A.t1 gnd 0.146044fF
-C15 A.t0 gnd 0.109539fF
-.ends
diff --git a/cdl/NAND2XL.cdl b/cdl/NAND2XL.cdl
deleted file mode 100644
index 38d6133..0000000
--- a/cdl/NAND2XL.cdl
+++ /dev/null
@@ -1,37 +0,0 @@
-* SPICE3 file created from NAND2XL.ext - technology: EFS8A
-
-.subckt NAND2XL Y B A
-M1000 a_75_115# A.t0 Y.t2 gnd nshort w=1.26u l=0.15u
-+  ad=0.1323p pd=1.47u as=0.3339p ps=3.05u
-M1001 vdd B.t0 Y.t0 vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.231p ps=1.93u
-M1002 gnd B.t1 a_75_115# gnd nshort w=1.26u l=0.15u
-+  ad=0.3339p pd=3.05u as=0.1323p ps=1.47u
-M1003 Y.t1 A.t1 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.231p pd=1.93u as=0.43725p ps=3.83u
-C0 m1_n35_1379# m1_n35_0# 0.049041fF
-C1 B Y 0.023360fF
-C2 vdd Y 0.001911fF
-C3 m1_n35_1379# Y 0.044702fF
-C4 m1_n35_0# Y 0.097003fF
-C5 A B 0.865875fF
-C6 A Y 0.013240fF
-R0 A.n0 A.t1 784.588
-R1 A.n0 A.t0 644.808
-R2 A A.n0 8.054
-R3 Y Y.n0 240.687
-R4 Y Y.t2 163.481
-R5 Y.n0 Y.t0 16.715
-R6 Y.n0 Y.t1 16.715
-R7 B.n0 B.t0 913.121
-R8 B.n0 B.t1 516.275
-R9 B B.n0 7.684
-C7 vdd gnd 0.672600fF
-C8 B.t0 gnd 0.343289fF
-C9 B.t1 gnd 0.212081fF
-C10 Y.t0 gnd 0.011986fF
-C11 Y.t1 gnd 0.011986fF
-C12 Y.t2 gnd 0.053293fF
-C13 A.t1 gnd 0.307010fF
-C14 A.t0 gnd 0.241174fF
-.ends
diff --git a/cdl/NAND3X1.cdl b/cdl/NAND3X1.cdl
deleted file mode 100644
index 6c3f663..0000000
--- a/cdl/NAND3X1.cdl
+++ /dev/null
@@ -1,109 +0,0 @@
-* SPICE3 file created from NAND3X1.ext - technology: EFS8A
-
-.subckt NAND3X1 A B C Y
-M1000 a_75_115# A.t0 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.18667u as=0.265p ps=2.35333u
-M1001 vdd A.t1 Y.t7 vdd pshort w=1u l=0.15u
-+  ad=0.160556p pd=1.31111u as=0.181667p ps=1.57556u
-M1002 a_161_115# C.t0 Y.t3 gnd nshort w=2u l=0.15u
-+  ad=0.28p pd=2.37333u as=0.403333p ps=3.12u
-M1003 Y.t5 B.t0 vdd vdd pshort w=1u l=0.15u
-+  ad=0.181667p pd=1.57556u as=0.160556p ps=1.31111u
-M1004 Y.t6 A.t2 vdd vdd pshort w=2u l=0.15u
-+  ad=0.363333p pd=3.15111u as=0.321111p ps=2.62222u
-M1005 vdd C.t1 Y.t2 vdd pshort w=1u l=0.15u
-+  ad=0.160556p pd=1.31111u as=0.181667p ps=1.57556u
-M1006 Y.t1 C.t2 a_161_115# gnd nshort w=1u l=0.15u
-+  ad=0.201667p pd=1.56u as=0.14p ps=1.18667u
-M1007 vdd B.t1 Y.t4 vdd pshort w=2u l=0.15u
-+  ad=0.321111p pd=2.62222u as=0.363333p ps=3.15111u
-M1008 gnd A.t3 a_75_115# gnd nshort w=2u l=0.15u
-+  ad=0.53p pd=4.70667u as=0.28p ps=2.37333u
-M1009 a_161_115# B.t2 a_75_115# gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.18667u as=0.14p ps=1.18667u
-M1010 Y.t0 C.t3 vdd vdd pshort w=2u l=0.15u
-+  ad=0.363333p pd=3.15111u as=0.321111p ps=2.62222u
-M1011 a_75_115# B.t3 a_161_115# gnd nshort w=2u l=0.15u
-+  ad=0.28p pd=2.37333u as=0.28p ps=2.37333u
-C0 B C 1.531980fF
-C1 a_161_115# B 0.457543fF
-C2 m1_n35_1379# A 0.168296fF
-C3 a_75_115# C 0.173138fF
-C4 a_75_115# a_161_115# 1.286470fF
-C5 m1_n35_1379# B 0.093536fF
-C6 a_75_115# Y 0.005711fF
-C7 m1_n35_0# A 0.205006fF
-C8 a_161_115# C 0.131721fF
-C9 a_75_115# m1_n35_1379# 0.108378fF
-C10 a_161_115# Y 0.005711fF
-C11 m1_n35_0# B 0.147381fF
-C12 m1_n35_1379# C 0.051912fF
-C13 a_75_115# m1_n35_0# 0.224212fF
-C14 a_161_115# m1_n35_1379# 0.058052fF
-C15 m1_n35_0# C 0.049224fF
-C16 A B 3.393150fF
-C17 a_161_115# m1_n35_0# 0.162727fF
-C18 a_75_115# A 0.763275fF
-C19 A C 1.309810fF
-C20 a_75_115# B 1.720010fF
-C21 m1_n35_1379# m1_n35_0# 0.109399fF
-C22 vdd C 0.001523fF
-C23 a_161_115# A 0.269313fF
-R0 A.n0 A.t1 889.021
-R1 A.n1 A.t2 728.354
-R2 A.n0 A.t0 686.581
-R3 A.n1 A.t3 525.914
-R4 A.n2 A.n1 167.309
-R5 A.n2 A.n0 13.653
-R6 A A.n2 0.554
-R7 Y.n2 Y.t7 214.132
-R8 Y.n3 Y.t6 163.742
-R9 Y Y.n4 162.51
-R10 Y.n2 Y.n1 124.835
-R11 Y.n3 Y.n0 88.235
-R12 Y Y.n3 71.405
-R13 Y.n3 Y.n2 66.023
-R14 Y.n1 Y.t2 27.58
-R15 Y.n1 Y.t5 27.58
-R16 Y.n4 Y.t1 24
-R17 Y.n0 Y.t4 13.79
-R18 Y.n0 Y.t0 13.79
-R19 Y.n4 Y.t3 8.7
-R20 C.n1 C.t2 596.072
-R21 C.n0 C.t1 594.465
-R22 C.n1 C.t0 416.125
-R23 C.n0 C.t3 414.519
-R24 C.n2 C.n1 259.208
-R25 C.n2 C.n0 206.188
-R26 C C.n2 13.653
-R27 B.n0 B.t0 1017.55
-R28 B.n1 B.t1 856.888
-R29 B.n0 B.t2 558.047
-R30 B.n1 B.t3 397.381
-R31 B.n2 B.n1 166.573
-R32 B.n2 B.n0 13.653
-R33 B B.n2 0.184
-C24 a_161_115# gnd 0.011854fF
-C25 a_75_115# gnd 0.013063fF
-C26 vdd gnd 1.482000fF
-C27 B.t0 gnd 0.989728fF
-C28 B.t2 gnd 0.629235fF
-C29 B.t1 gnd 1.116490fF
-C30 B.t3 gnd 0.756822fF
-C31 C.t3 gnd 0.475300fF
-C32 C.t1 gnd 0.406424fF
-C33 C.t0 gnd 0.476063fF
-C34 C.t2 gnd 0.407193fF
-C35 Y.t4 gnd 0.000330fF
-C36 Y.t0 gnd 0.000330fF
-C37 Y.t6 gnd 0.001858fF
-C38 Y.t2 gnd 0.000165fF
-C39 Y.t5 gnd 0.000165fF
-C40 Y.t7 gnd 0.001136fF
-C41 Y.t3 gnd 0.000362fF
-C42 Y.t1 gnd 0.000236fF
-C43 A.t1 gnd 0.691627fF
-C44 A.t0 gnd 0.568006fF
-C45 A.t2 gnd 0.790347fF
-C46 A.t3 gnd 0.666960fF
-.ends
diff --git a/cdl/NAND3XL.cdl b/cdl/NAND3XL.cdl
deleted file mode 100644
index b029458..0000000
--- a/cdl/NAND3XL.cdl
+++ /dev/null
@@ -1,50 +0,0 @@
-* SPICE3 file created from NAND3XL.ext - technology: EFS8A
-
-.subckt NAND3XL C Y B A
-M1000 a_75_115# A.t0 Y.t2 gnd nshort w=2u l=0.15u
-+  ad=0.21p pd=2.21u as=0.53p ps=4.53u
-M1001 vdd C.t0 Y.t1 vdd pshort w=1.65u l=0.15u
-+  ad=0.29975p pd=2.56333u as=0.29975p ps=2.56333u
-M1002 gnd C.t1 a_147_115# gnd nshort w=2u l=0.15u
-+  ad=0.53p pd=4.53u as=0.21p ps=2.21u
-M1003 Y.t0 B.t0 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.29975p pd=2.56333u as=0.29975p ps=2.56333u
-M1004 a_147_115# B.t1 a_75_115# gnd nshort w=2u l=0.15u
-+  ad=0.21p pd=2.21u as=0.21p ps=2.21u
-M1005 vdd A.t1 Y.t3 vdd pshort w=1.65u l=0.15u
-+  ad=0.29975p pd=2.56333u as=0.29975p ps=2.56333u
-C0 m1_n35_1379# m1_n35_0# 0.064131fF
-C1 A Y 0.013384fF
-C2 B C 0.638866fF
-C3 vdd Y 0.001942fF
-C4 A B 0.703875fF
-C5 m1_n35_1379# Y 0.026952fF
-C6 A C 0.249213fF
-C7 m1_n35_0# Y 0.047670fF
-R0 A.n0 A.t1 784.588
-R1 A.n0 A.t0 525.914
-R2 A A.n0 8.054
-R3 Y.n1 Y.n0 190.858
-R4 Y.n1 Y.t3 145.856
-R5 Y Y.t2 102.757
-R6 Y Y.n1 99.345
-R7 Y.n0 Y.t1 16.715
-R8 Y.n0 Y.t0 16.715
-R9 C.n0 C.t0 911.09
-R10 C.n0 C.t1 395.35
-R11 C C.n0 7.5
-R12 B.n0 B.t0 656.055
-R13 B.n0 B.t1 654.448
-R14 B B.n0 7.684
-C8 vdd gnd 0.873240fF
-C9 B.t0 gnd 0.391872fF
-C10 B.t1 gnd 0.431166fF
-C11 C.t0 gnd 0.330418fF
-C12 C.t1 gnd 0.233158fF
-C13 Y.t3 gnd 0.022819fF
-C14 Y.t1 gnd 0.004195fF
-C15 Y.t0 gnd 0.004195fF
-C16 Y.t2 gnd 0.025535fF
-C17 A.t1 gnd 0.324885fF
-C18 A.t0 gnd 0.286704fF
-.ends
diff --git a/cdl/NAND4XL.cdl b/cdl/NAND4XL.cdl
deleted file mode 100644
index e8db014..0000000
--- a/cdl/NAND4XL.cdl
+++ /dev/null
@@ -1,89 +0,0 @@
-* SPICE3 file created from NAND4XL.ext - technology: EFS8A
-
-.subckt NAND4XL Y B D A C
-M1000 a_75_115# D.t0 gnd gnd nshort w=1.5u l=0.15u
-+  ad=0.21p pd=1.78u as=0.3975p ps=3.53u
-M1001 gnd D.t1 a_75_115# gnd nshort w=1.5u l=0.15u
-+  ad=0.3975p pd=3.53u as=0.21p ps=1.78u
-M1002 Y.t4 A.t0 a_247_115# gnd nshort w=1.5u l=0.15u
-+  ad=0.21p pd=1.78u as=0.21p ps=1.78u
-M1003 a_75_115# C.t0 a_161_115.t1 gnd nshort w=1.5u l=0.15u
-+  ad=0.21p pd=1.78u as=0.21p ps=1.78u
-M1004 Y.t2 D.t2 vdd vdd pshort w=1.5u l=0.15u
-+  ad=0.21p pd=1.78u as=0.21p ps=1.78u
-M1005 vdd C.t1 Y.t0 vdd pshort w=1.5u l=0.15u
-+  ad=0.21p pd=1.78u as=0.30375p ps=2.655u
-M1006 a_161_115.t0 C.t2 a_75_115# gnd nshort w=1.5u l=0.15u
-+  ad=0.21p pd=1.78u as=0.21p ps=1.78u
-M1007 Y.t1 B.t2 vdd vdd pshort w=1.5u l=0.15u
-+  ad=0.30375p pd=2.655u as=0.21p ps=1.78u
-M1008 a_247_115# A.t1 Y.t3 gnd nshort w=1.5u l=0.15u
-+  ad=0.21p pd=1.78u as=0.21p ps=1.78u
-M1009 vdd A.t2 Y.t5 vdd pshort w=1.5u l=0.15u
-+  ad=0.21p pd=1.78u as=0.30375p ps=2.655u
-C0 B Y 0.016238fF
-C1 D B 0.440786fF
-C2 m1_n35_0# A 0.032480fF
-C3 m1_n35_1379# m1_n35_0# 0.135806fF
-C4 vdd A 0.006950fF
-C5 A Y 1.260910fF
-C6 D A 0.123924fF
-C7 C B 1.291400fF
-C8 m1_n35_1379# Y 0.046100fF
-C9 C A 0.208744fF
-C10 m1_n35_0# Y 0.054988fF
-C11 vdd Y 0.016791fF
-C12 B A 0.616376fF
-C13 C Y 0.001414fF
-C14 m1_n35_1379# A 0.036835fF
-C15 D C 1.336500fF
-R0 D.n0 D.t2 1209.82
-R1 D D.t1 557.011
-R2 D.n0 D.t0 435.406
-R3 D D.n0 117.3
-R4 A A.t2 529.596
-R5 A.n0 A.t0 351.312
-R6 A.n0 A.t1 351.312
-R7 A A.n0 7.858
-R8 Y.n2 Y.n0 94.334
-R9 Y.n2 Y.n1 94.334
-R10 Y Y.n2 76.431
-R11 Y Y.n3 69.728
-R12 Y.n0 Y.t5 18.386
-R13 Y.n0 Y.t1 18.386
-R14 Y.n1 Y.t0 18.386
-R15 Y.n1 Y.t2 18.386
-R16 Y.n3 Y.t3 11.2
-R17 Y.n3 Y.t4 11.2
-R18 C.n0 C.t1 1013.81
-R19 C C.t0 744.66
-R20 C.n0 C.t2 653.913
-R21 C C.n0 86.441
-R22 a_161_115.n3 a_161_115.n2 273.352
-R23 a_161_115.n2 a_161_115.t0 11.2
-R24 a_161_115.n2 a_161_115.n1 11.2
-R25 a_161_115.n3 a_161_115.n0 11.2
-R26 a_161_115.t1 a_161_115.n3 11.2
-R27 B.n0 B.t2 1092.53
-R28 B.n1 B.t1 733.078
-R29 B.n0 B.t0 549.48
-R30 B.n1 B.n0 183.598
-R31 B B.n1 8.576
-C16 vdd gnd 1.826280fF
-C17 B.t2 gnd 0.435356fF
-C18 C.t0 gnd 0.438698fF
-C19 C.t1 gnd 0.513698fF
-C20 C.t2 gnd 0.371516fF
-C21 Y.t5 gnd 0.056910fF
-C22 Y.t1 gnd 0.056910fF
-C23 Y.t0 gnd 0.056910fF
-C24 Y.t2 gnd 0.056910fF
-C25 Y.t3 gnd 0.056910fF
-C26 Y.t4 gnd 0.056910fF
-C27 A.t2 gnd 0.440368fF
-C28 A.t1 gnd 0.195613fF
-C29 A.t0 gnd 0.195613fF
-C30 D.t1 gnd 0.278375fF
-C31 D.t2 gnd 0.399113fF
-C32 D.t0 gnd 0.200045fF
-.ends
diff --git a/cdl/NOR2X1.cdl b/cdl/NOR2X1.cdl
deleted file mode 100644
index 083911a..0000000
--- a/cdl/NOR2X1.cdl
+++ /dev/null
@@ -1,50 +0,0 @@
-* SPICE3 file created from NOR2X1.ext - technology: EFS8A
-
-.subckt NOR2X1 B Y A
-M1000 gnd B.t0 Y.t3 gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.14p ps=1.28u
-M1001 a_75_725# A.t0 Y.t2 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.42p ps=3.28u
-M1002 Y.t1 A.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.265p ps=2.53u
-M1003 Y.t0 A.t2 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.42p ps=3.28u
-M1004 a_75_725# B.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-M1005 vdd B.t2 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.28u
-C0 B A 0.801698fF
-C1 m1_n35_0# Y 0.073155fF
-C2 B Y 0.008531fF
-C3 m1_n35_1379# m1_n35_0# 0.079220fF
-C4 A Y 0.018093fF
-C5 vdd Y 0.001596fF
-C6 a_75_725# Y 0.006422fF
-C7 m1_n35_1379# Y 0.053711fF
-R0 B B.t1 795.938
-R1 B.n0 B.t2 696.221
-R2 B.n0 B.t0 558.047
-R3 B B.n0 7.858
-R4 Y Y.n0 184.353
-R5 Y Y.n1 162.345
-R6 Y.n1 Y.t3 16.8
-R7 Y.n1 Y.t1 16.8
-R8 Y.n0 Y.t2 9.193
-R9 Y.n0 Y.t0 9.193
-R10 A.n1 A.t1 737.993
-R11 A.n0 A.t0 581.613
-R12 A.n0 A.t2 519.488
-R13 A.n1 A.n0 33.918
-R14 A A.n1 7.858
-C8 vdd gnd 1.073880fF
-C9 A.t0 gnd 0.218114fF
-C10 A.t2 gnd 0.208071fF
-C11 A.t1 gnd 0.150931fF
-C12 Y.t2 gnd 0.017635fF
-C13 Y.t0 gnd 0.017635fF
-C14 Y.t3 gnd 0.005878fF
-C15 Y.t1 gnd 0.005878fF
-C16 B.t2 gnd 0.271237fF
-C17 B.t0 gnd 0.137265fF
-C18 B.t1 gnd 0.273348fF
-.ends
diff --git a/cdl/NOR2XL.cdl b/cdl/NOR2XL.cdl
deleted file mode 100644
index 5c48381..0000000
--- a/cdl/NOR2XL.cdl
+++ /dev/null
@@ -1,38 +0,0 @@
-* SPICE3 file created from NOR2XL.ext - technology: EFS8A
-
-.subckt NOR2XL Y B A
-M1000 Y.t2 A.t0 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.0896p pd=0.92u as=0.1696p ps=1.81u
-M1001 vdd B.t0 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.315p ps=3.21u
-M1002 gnd B.t1 Y.t0 gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.0896p ps=0.92u
-M1003 a_75_725# A.t1 Y.t1 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.795p ps=6.53u
-C0 vdd Y 0.001635fF
-C1 a_75_725# Y 0.006766fF
-C2 m1_n35_1379# Y 0.053711fF
-C3 m1_n35_0# Y 0.073155fF
-C4 A B 0.708375fF
-C5 A Y 0.013240fF
-C6 m1_n35_1379# m1_n35_0# 0.049041fF
-C7 B Y 0.031636fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 615.887
-R2 A A.n0 8.054
-R3 Y Y.t1 201.34
-R4 Y Y.n0 174.288
-R5 Y.n0 Y.t0 26.25
-R6 Y.n0 Y.t2 26.25
-R7 B.n0 B.t0 824.755
-R8 B.n0 B.t1 487.354
-R9 B B.n0 7.684
-C8 vdd gnd 0.672600fF
-C9 B.t0 gnd 0.356230fF
-C10 B.t1 gnd 0.127977fF
-C11 Y.t1 gnd 0.107936fF
-C12 Y.t0 gnd 0.004151fF
-C13 Y.t2 gnd 0.004151fF
-C14 A.t1 gnd 0.321262fF
-C15 A.t0 gnd 0.150749fF
-.ends
diff --git a/cdl/OAI21XL.cdl b/cdl/OAI21XL.cdl
deleted file mode 100644
index 5af56a3..0000000
--- a/cdl/OAI21XL.cdl
+++ /dev/null
@@ -1,53 +0,0 @@
-* SPICE3 file created from OAI21XL.ext - technology: EFS8A
-
-.subckt OAI21XL A0 A1 Y B0
-M1000 gnd A0.t0 a_n8_115.t2 gnd nshort w=1.26u l=0.15u
-+  ad=0.1764p pd=1.54u as=0.2289p ps=2.04333u
-M1001 Y.t1 B0.t0 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.67613u as=0.326008p ps=2.37032u
-M1002 vdd A1.t0 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.592742p pd=4.30968u as=0.315p ps=3.21u
-M1003 Y.t2 B0.t1 a_n8_115.t0 gnd nshort w=1.26u l=0.15u
-+  ad=0.3339p pd=3.05u as=0.2289p ps=2.04333u
-M1004 a_n8_115.t1 A1.t1 gnd gnd nshort w=1.26u l=0.15u
-+  ad=0.2289p pd=2.04333u as=0.1764p ps=1.54u
-M1005 a_75_725# A0.t1 Y.t0 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.795p ps=6.68387u
-C0 A0 A1 0.568875fF
-C1 Y m1_n35_0# 0.135543fF
-C2 A0 B0 0.182389fF
-C3 Y vdd 0.007098fF
-C4 A0 Y 0.008453fF
-C5 A1 B0 0.429705fF
-C6 Y a_75_725# 0.006766fF
-C7 A1 Y 0.007139fF
-C8 B0 Y 0.016985fF
-C9 Y m1_n35_1379# 0.119725fF
-C10 m1_n35_1379# m1_n35_0# 0.064131fF
-R0 A0.n0 A0.t1 696.221
-R1 A0.n0 A0.t0 516.275
-R2 A0 A0.n0 7.5
-R3 a_n8_115.n0 a_n8_115.t2 209.896
-R4 a_n8_115.t0 a_n8_115.n0 13.333
-R5 a_n8_115.n0 a_n8_115.t1 13.333
-R6 B0.n0 B0.t0 784.078
-R7 B0.n0 B0.t1 644.808
-R8 B0 B0.n0 7.5
-R9 Y.n0 Y.t1 256.662
-R10 Y.n0 Y.t0 201.246
-R11 Y Y.t2 163.522
-R12 Y Y.n0 0.394
-R13 A1.n0 A1.t0 824.755
-R14 A1.n0 A1.t1 387.741
-R15 A1 A1.n0 7.5
-C11 vdd gnd 0.873240fF
-C12 A1.t0 gnd 0.455437fF
-C13 A1.t1 gnd 0.190459fF
-C14 Y.t1 gnd 0.075848fF
-C15 Y.t0 gnd 0.116186fF
-C16 Y.t2 gnd 0.051239fF
-C17 B0.t0 gnd 0.233125fF
-C18 B0.t1 gnd 0.183193fF
-C19 A0.t1 gnd 0.326004fF
-C20 A0.t0 gnd 0.173661fF
-.ends
diff --git a/cdl/OR2X1.cdl b/cdl/OR2X1.cdl
deleted file mode 100644
index cc9d9e6..0000000
--- a/cdl/OR2X1.cdl
+++ /dev/null
@@ -1,60 +0,0 @@
-* SPICE3 file created from OR2X1.ext - technology: EFS8A
-
-.subckt OR2X1 Y A B
-M1000 gnd B.t0 a_161_725.t3 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1001 a_75_725# A.t0 a_161_725.t2 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.42p ps=3.28u
-M1002 a_161_725.t1 A.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1003 a_161_725.t0 A.t2 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.42p ps=3.28u
-M1004 Y.t1 a_161_725.t4 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.545p ps=4.36333u
-M1005 a_75_725# B.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1006 Y.t0 a_161_725.t5 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.181667p ps=1.69667u
-M1007 vdd B.t2 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-C0 m1_n35_1379# m1_n35_0# 0.094310fF
-C1 vdd Y 0.001338fF
-C2 m1_n35_1379# Y 0.026952fF
-C3 B A 0.801698fF
-C4 m1_n35_0# Y 0.047670fF
-R0 B B.t1 796.297
-R1 B.n0 B.t2 696.221
-R2 B.n0 B.t0 558.047
-R3 B B.n0 7.5
-R4 a_161_725.n1 a_161_725.t4 824.755
-R5 a_161_725.n1 a_161_725.t5 429.514
-R6 a_161_725.n3 a_161_725.n2 260.633
-R7 a_161_725.n2 a_161_725.n0 108.329
-R8 a_161_725.n2 a_161_725.n1 58.094
-R9 a_161_725.n0 a_161_725.t3 16.8
-R10 a_161_725.n0 a_161_725.t1 16.8
-R11 a_161_725.n3 a_161_725.t2 9.193
-R12 a_161_725.t0 a_161_725.n3 9.193
-R13 A.n1 A.t1 737.993
-R14 A.n0 A.t0 581.613
-R15 A.n0 A.t2 519.488
-R16 A.n1 A.n0 33.918
-R17 A A.n1 7.858
-R18 Y Y.t1 200.833
-R19 Y Y.t0 179.134
-C5 vdd gnd 1.274520fF
-C6 Y.t1 gnd 0.319471fF
-C7 Y.t0 gnd 0.119327fF
-C8 A.t0 gnd 0.260868fF
-C9 A.t2 gnd 0.248856fF
-C10 A.t1 gnd 0.180515fF
-C11 a_161_725.t2 gnd 0.099783fF
-C12 a_161_725.t3 gnd 0.033261fF
-C13 a_161_725.t1 gnd 0.033261fF
-C14 a_161_725.t4 gnd 0.189374fF
-C15 a_161_725.t5 gnd 0.074508fF
-C16 a_161_725.t0 gnd 0.099783fF
-C17 B.t1 gnd 0.428851fF
-C18 B.t2 gnd 0.425468fF
-C19 B.t0 gnd 0.215316fF
-.ends
diff --git a/cdl/OR2X2.cdl b/cdl/OR2X2.cdl
deleted file mode 100644
index 3e73d44..0000000
--- a/cdl/OR2X2.cdl
+++ /dev/null
@@ -1,63 +0,0 @@
-* SPICE3 file created from OR2X2.ext - technology: EFS8A
-
-.subckt OR2X2 A B Y
-M1000 gnd B.t0 a_161_725# gnd nshort w=1u l=0.15u
-+  ad=0.2025p pd=1.905u as=0.14p ps=1.28u
-M1001 a_75_725# A.t0 a_161_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.42p ps=3.28u
-M1002 vdd a_161_725# Y.t3 vdd pshort w=3u l=0.15u
-+  ad=0.6075p pd=4.905u as=0.42p ps=3.28u
-M1003 a_161_725# A.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.2025p ps=1.905u
-M1004 a_161_725# A.t2 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.42p ps=3.28u
-M1005 gnd a_161_725# Y.t1 gnd nshort w=1u l=0.15u
-+  ad=0.2025p pd=1.905u as=0.14p ps=1.28u
-M1006 Y.t2 a_161_725# vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.6075p ps=4.905u
-M1007 a_75_725# B.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.6075p ps=4.905u
-M1008 Y.t0 a_161_725# gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.2025p ps=1.905u
-M1009 vdd B.t2 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.6075p pd=4.905u as=0.42p ps=3.28u
-C0 a_161_725# B 0.747381fF
-C1 A B 0.801698fF
-C2 Y m1_n35_0# 0.047670fF
-C3 vdd a_161_725# 0.001596fF
-C4 m1_n35_1379# m1_n35_0# 0.109399fF
-C5 Y vdd 0.000538fF
-C6 A a_161_725# 0.274494fF
-C7 a_161_725# a_75_725# 0.006422fF
-C8 Y a_161_725# 0.519330fF
-C9 a_161_725# m1_n35_1379# 0.054249fF
-C10 a_161_725# m1_n35_0# 0.065522fF
-C11 Y m1_n35_1379# 0.026952fF
-R0 B B.t1 796.297
-R1 B.n0 B.t2 696.221
-R2 B.n0 B.t0 558.047
-R3 B B.n0 7.5
-R4 A.n1 A.t1 737.993
-R5 A.n0 A.t0 581.613
-R6 A.n0 A.t2 519.488
-R7 A.n1 A.n0 33.918
-R8 A A.n1 7.858
-R9 Y Y.n0 191.64
-R10 Y Y.n1 162.334
-R11 Y.n1 Y.t1 16.8
-R12 Y.n1 Y.t0 16.8
-R13 Y.n0 Y.t3 9.193
-R14 Y.n0 Y.t2 9.193
-C12 a_161_725# gnd 0.137641fF
-C13 vdd gnd 1.475160fF
-C14 Y.t3 gnd 0.057206fF
-C15 Y.t2 gnd 0.057206fF
-C16 Y.t1 gnd 0.019069fF
-C17 Y.t0 gnd 0.019069fF
-C18 A.t0 gnd 0.276271fF
-C19 A.t2 gnd 0.263550fF
-C20 A.t1 gnd 0.191174fF
-C21 B.t1 gnd 0.462171fF
-C22 B.t2 gnd 0.458524fF
-C23 B.t0 gnd 0.232045fF
-.ends
diff --git a/cdl/OR2X4.cdl b/cdl/OR2X4.cdl
deleted file mode 100644
index e136e22..0000000
--- a/cdl/OR2X4.cdl
+++ /dev/null
@@ -1,110 +0,0 @@
-* SPICE3 file created from OR2X4.ext - technology: EFS8A
-
-.subckt OR2X4 A B Y
-M1000 gnd a_161_725.t4 Y.t7 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1001 Y.t3 a_161_725.t5 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1002 gnd B.t0 a_161_725.t0 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1003 a_75_725# A.t0 a_161_725.t3 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.42p ps=3.28u
-M1004 Y.t6 a_161_725.t6 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1005 vdd a_161_725.t7 Y.t2 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-M1006 a_161_725.t2 A.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1007 a_161_725.t1 A.t2 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.42p ps=3.28u
-M1008 gnd a_161_725.t8 Y.t5 gnd nshort w=1u l=0.15u
-+  ad=0.181667p pd=1.69667u as=0.14p ps=1.28u
-M1009 Y.t1 a_161_725.t9 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1010 a_75_725# B.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.545p ps=4.36333u
-M1011 vdd a_161_725.t10 Y.t0 vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-M1012 Y.t4 a_161_725.t11 gnd gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.181667p ps=1.69667u
-M1013 vdd B.t2 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.545p pd=4.36333u as=0.42p ps=3.28u
-C0 m1_n35_1379# m1_n35_0# 0.139578fF
-C1 vdd Y 0.005614fF
-C2 m1_n35_0# Y 0.210435fF
-C3 m1_n35_1379# Y 0.122391fF
-C4 B A 0.801698fF
-R0 a_161_725.n1 a_161_725.t10 644.273
-R1 a_161_725.n4 a_161_725.t4 538.232
-R2 a_161_725.n3 a_161_725.t9 506.1
-R3 a_161_725.n1 a_161_725.t5 506.1
-R4 a_161_725.n2 a_161_725.t7 506.1
-R5 a_161_725.n6 a_161_725.t11 413.447
-R6 a_161_725.n5 a_161_725.t8 400.059
-R7 a_161_725.n4 a_161_725.t6 400.059
-R8 a_161_725.n7 a_161_725.n3 270.455
-R9 a_161_725.n9 a_161_725.n8 260.633
-R10 a_161_725.n5 a_161_725.n4 138.173
-R11 a_161_725.n2 a_161_725.n1 138.173
-R12 a_161_725.n3 a_161_725.n2 138.173
-R13 a_161_725.n8 a_161_725.n0 108.329
-R14 a_161_725.n6 a_161_725.n5 75.513
-R15 a_161_725.n8 a_161_725.n7 58.094
-R16 a_161_725.n0 a_161_725.t0 16.8
-R17 a_161_725.n0 a_161_725.t2 16.8
-R18 a_161_725.n7 a_161_725.n6 16.066
-R19 a_161_725.n9 a_161_725.t3 9.193
-R20 a_161_725.t1 a_161_725.n9 9.193
-R21 Y.n1 Y.n0 191.147
-R22 Y.n3 Y.n2 191.147
-R23 Y.n7 Y.n6 161.723
-R24 Y.n5 Y.n4 161.723
-R25 Y.n6 Y.t5 16.8
-R26 Y.n6 Y.t4 16.8
-R27 Y.n4 Y.t7 16.8
-R28 Y.n4 Y.t6 16.8
-R29 Y.n0 Y.t0 9.193
-R30 Y.n0 Y.t3 9.193
-R31 Y.n2 Y.t2 9.193
-R32 Y.n2 Y.t1 9.193
-R33 Y.n3 Y.n1 0.575
-R34 Y.n7 Y.n5 0.575
-R35 Y Y.n7 0.562
-R36 Y Y.n3 0.444
-R37 B B.t1 796.297
-R38 B.n0 B.t2 696.221
-R39 B.n0 B.t0 558.047
-R40 B B.n0 7.5
-R41 A.n1 A.t1 737.993
-R42 A.n0 A.t0 581.613
-R43 A.n0 A.t2 519.488
-R44 A.n1 A.n0 33.918
-R45 A A.n1 7.858
-C5 vdd gnd 1.876440fF
-C6 A.t0 gnd 0.296487fF
-C7 A.t2 gnd 0.282835fF
-C8 A.t1 gnd 0.205163fF
-C9 B.t1 gnd 0.501896fF
-C10 B.t2 gnd 0.497936fF
-C11 B.t0 gnd 0.251990fF
-C12 Y.t0 gnd 0.050995fF
-C13 Y.t3 gnd 0.050995fF
-C14 Y.t2 gnd 0.050995fF
-C15 Y.t1 gnd 0.050995fF
-C16 Y.t7 gnd 0.016998fF
-C17 Y.t6 gnd 0.016998fF
-C18 Y.t5 gnd 0.016998fF
-C19 Y.t4 gnd 0.016998fF
-C20 a_161_725.t3 gnd 0.083463fF
-C21 a_161_725.t0 gnd 0.027821fF
-C22 a_161_725.t2 gnd 0.027821fF
-C23 a_161_725.t9 gnd 0.128622fF
-C24 a_161_725.t7 gnd 0.128622fF
-C25 a_161_725.t5 gnd 0.128622fF
-C26 a_161_725.t10 gnd 0.142398fF
-C27 a_161_725.t8 gnd 0.059169fF
-C28 a_161_725.t6 gnd 0.059169fF
-C29 a_161_725.t4 gnd 0.073134fF
-C30 a_161_725.t11 gnd 0.060501fF
-C31 a_161_725.t1 gnd 0.083463fF
-.ends
diff --git a/cdl/OR2XL.cdl b/cdl/OR2XL.cdl
deleted file mode 100644
index 0c6776c..0000000
--- a/cdl/OR2XL.cdl
+++ /dev/null
@@ -1,48 +0,0 @@
-* SPICE3 file created from OR2XL.ext - technology: EFS8A
-
-.subckt OR2XL B A Y
-M1000 a_n8_725.t1 A.t0 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.0896p pd=0.92u as=0.116267p ps=1.21667u
-M1001 Y.t0 a_n8_725.t3 vdd vdd pshort w=1.65u l=0.15u
-+  ad=0.43725p pd=3.83u as=0.326008p ps=2.37032u
-M1002 vdd B.t0 a_75_725# vdd pshort w=3u l=0.15u
-+  ad=0.592742p pd=4.30968u as=0.315p ps=3.21u
-M1003 Y.t1 a_n8_725.t4 gnd gnd nshort w=0.64u l=0.15u
-+  ad=0.1696p pd=1.81u as=0.116267p ps=1.21667u
-M1004 gnd B.t1 a_n8_725.t2 gnd nshort w=0.64u l=0.15u
-+  ad=0.116267p pd=1.21667u as=0.0896p ps=0.92u
-M1005 a_75_725# A.t1 a_n8_725.t0 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.795p ps=6.53u
-C0 m1_n35_1379# Y 0.026499fF
-C1 m1_n35_1379# m1_n35_0# 0.064131fF
-C2 vdd Y 0.001954fF
-C3 m1_n35_0# Y 0.060117fF
-C4 A B 0.708375fF
-R0 A.n0 A.t1 696.221
-R1 A.n0 A.t0 615.887
-R2 A A.n0 8.054
-R3 a_n8_725.n1 a_n8_725.t3 1169.68
-R4 a_n8_725.t0 a_n8_725.n2 867.425
-R5 a_n8_725.n1 a_n8_725.t4 358.821
-R6 a_n8_725.n2 a_n8_725.n0 91.823
-R7 a_n8_725.n2 a_n8_725.n1 58.094
-R8 a_n8_725.n0 a_n8_725.t2 26.25
-R9 a_n8_725.n0 a_n8_725.t1 26.25
-R10 Y Y.t0 257.155
-R11 Y Y.t1 172.372
-R12 B.n0 B.t0 824.755
-R13 B.n0 B.t1 487.354
-R14 B B.n0 7.684
-C5 vdd gnd 0.873240fF
-C6 B.t0 gnd 0.593878fF
-C7 B.t1 gnd 0.213353fF
-C8 Y.t0 gnd 0.329576fF
-C9 Y.t1 gnd 0.122785fF
-C10 a_n8_725.t2 gnd 0.025328fF
-C11 a_n8_725.t1 gnd 0.025328fF
-C12 a_n8_725.t3 gnd 0.213515fF
-C13 a_n8_725.t4 gnd 0.064177fF
-C14 a_n8_725.t0 gnd 0.447276fF
-C15 A.t1 gnd 0.412612fF
-C16 A.t0 gnd 0.193615fF
-.ends
diff --git a/cdl/TBUFXL.cdl b/cdl/TBUFXL.cdl
deleted file mode 100644
index 23ca5d3..0000000
--- a/cdl/TBUFXL.cdl
+++ /dev/null
@@ -1,46 +0,0 @@
-* SPICE3 file created from TBUFXL.ext - technology: EFS8A
-
-.subckt TBUFXL OE Y A
-M1000 gnd OE.t0 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.265p ps=2.53u
-M1001 Y.t1 A.t0 a_161_725# vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.315p ps=3.21u
-M1002 Y.t0 A.t1 a_161_115# gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.105p ps=1.21u
-M1003 a_161_725# a_n8_115.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.28u
-M1004 a_161_115# OE.t1 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.14p ps=1.28u
-M1005 vdd OE.t2 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-C0 m1_n35_1379# Y 0.026952fF
-C1 OE A 0.307712fF
-C2 m1_n35_0# Y 0.047670fF
-C3 vdd Y 0.001326fF
-C4 m1_n35_1379# m1_n35_0# 0.064131fF
-C5 A Y 0.013384fF
-R0 OE.n1 OE.t2 681.226
-R1 OE.n1 OE.n0 338.202
-R2 OE.n0 OE.t1 322.939
-R3 OE.n0 OE.t0 184.766
-R4 OE OE.n1 7.5
-R5 a_n8_115.n0 a_n8_115.t2 874.237
-R6 a_n8_115.t0 a_n8_115.n0 277.151
-R7 a_n8_115.n0 a_n8_115.t1 125.129
-R8 A.n0 A.t1 686.581
-R9 A.n0 A.t0 567.688
-R10 A A.n0 7.5
-R11 Y Y.t1 200.833
-R12 Y Y.t0 179.134
-C6 vdd gnd 0.875520fF
-C7 Y.t1 gnd 0.230920fF
-C8 Y.t0 gnd 0.086252fF
-C9 A.t0 gnd 0.301651fF
-C10 A.t1 gnd 0.192682fF
-C11 a_n8_115.t1 gnd 0.167931fF
-C12 a_n8_115.t2 gnd 0.178552fF
-C13 a_n8_115.t0 gnd 0.550084fF
-C14 OE.t2 gnd 0.248598fF
-C15 OE.t0 gnd 0.066580fF
-C16 OE.t1 gnd 0.091601fF
-.ends
diff --git a/cdl/TIEHI.cdl b/cdl/TIEHI.cdl
deleted file mode 100644
index 58d172f..0000000
--- a/cdl/TIEHI.cdl
+++ /dev/null
@@ -1,12 +0,0 @@
-* SPICE3 file created from TIEHI.ext - technology: EFS8A
-
-.subckt TIEHI Y
-M1000 a_45_89# a_45_89# gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.265p ps=2.53u
-M1001 Y.t0 a_45_89# vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.795p ps=6.53u
-C0 m1_n35_1379# m1_n35_0# 0.033951fF
-R0 Y Y.t0 127.569
-C1 a_45_89# gnd 0.106884fF
-C2 vdd gnd 0.474240fF
-.ends
diff --git a/cdl/TIELO.cdl b/cdl/TIELO.cdl
deleted file mode 100644
index 33d3c38..0000000
--- a/cdl/TIELO.cdl
+++ /dev/null
@@ -1,12 +0,0 @@
-* SPICE3 file created from TIELO.ext - technology: EFS8A
-
-.subckt TIELO Y
-M1000 Y.t0 a_45_89# gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.265p ps=2.53u
-M1001 a_45_89# a_45_89# vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.795p ps=6.53u
-C0 m1_n35_1379# m1_n35_0# 0.033951fF
-R0 Y Y.t0 73.458
-C1 a_45_89# gnd 0.106884fF
-C2 vdd gnd 0.474240fF
-.ends
diff --git a/cdl/TNBUFXL.cdl b/cdl/TNBUFXL.cdl
deleted file mode 100644
index b5ce43b..0000000
--- a/cdl/TNBUFXL.cdl
+++ /dev/null
@@ -1,45 +0,0 @@
-* SPICE3 file created from TNBUFXL.ext - technology: EFS8A
-
-.subckt TNBUFXL OE Y A
-M1000 gnd OE.t0 a_n8_115.t1 gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.265p ps=2.53u
-M1001 Y.t0 A.t1 a_161_115# gnd nshort w=1u l=0.15u
-+  ad=0.795p pd=6.53u as=0.315p ps=3.21u
-M1002 a_161_725.t0 OE.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.265p pd=2.53u as=0.105p ps=1.21u
-M1003 a_161_115# a_n8_115.t2 gnd gnd nshort w=1u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.28u
-M1004 vdd OE.t2 a_n8_115.t0 vdd pshort w=3u l=0.15u
-+  ad=0.105p pd=1.21u as=0.14p ps=1.28u
-C0 Y vdd 0.001326fF
-C1 m1_n35_1379# m1_n35_0# 0.064131fF
-C2 OE A 0.307712fF
-C3 m1_n35_0# Y 0.047670fF
-C4 A Y 0.013384fF
-C5 m1_n35_1379# Y 0.026952fF
-R0 OE.n0 OE.t1 644.273
-R1 OE.n1 OE.t0 543.052
-R2 OE.n0 OE.t2 506.1
-R3 OE.n1 OE.n0 155.042
-R4 OE OE.n1 7.5
-R5 a_n8_115.n0 a_n8_115.t2 478.996
-R6 a_n8_115.t0 a_n8_115.n0 277.151
-R7 a_n8_115.n0 a_n8_115.t1 125.129
-R8 A.n0 A.t1 686.581
-R9 A.n0 A.t0 567.688
-R10 A A.n0 7.5
-R11 a_161_725.n2 a_161_725.n1 144.217
-R12 a_161_725.n1 a_161_725.t0 9.193
-R13 a_161_725.n1 a_161_725.n0 9.193
-R14 Y Y.t1 200.833
-R15 Y Y.t0 179.134
-C6 vdd gnd 0.875520fF
-C7 Y.t0 gnd 0.086252fF
-C8 A.t1 gnd 0.177195fF
-C9 a_n8_115.t1 gnd 0.169500fF
-C10 a_n8_115.t2 gnd 0.078429fF
-C11 a_n8_115.t0 gnd 0.555221fF
-C12 OE.t2 gnd 0.162969fF
-C13 OE.t1 gnd 0.180424fF
-C14 OE.t0 gnd 0.096373fF
-.ends
diff --git a/cdl/XNOR2XL.cdl b/cdl/XNOR2XL.cdl
deleted file mode 100644
index 3c39b18..0000000
--- a/cdl/XNOR2XL.cdl
+++ /dev/null
@@ -1,80 +0,0 @@
-* SPICE3 file created from XNOR2XL.ext - technology: EFS8A
-
-.subckt XNOR2XL Y B A
-M1000 gnd A.t0 a_n8_115.t0 gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.265p ps=2.53u
-M1001 a_353_725# B.t0 Y.t3 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1002 Y.t0 a_203_89# a_161_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1003 Y.t1 a_203_89# a_161_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1004 a_353_115# B.t1 Y.t2 gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1005 a_203_89# B.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.28u
-M1006 a_161_725# a_n8_115.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.28u
-M1007 a_203_89# B.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.14p ps=1.28u
-M1008 vdd A.t1 a_353_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.315p ps=3.21u
-M1009 a_161_115# A.t2 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.14p ps=1.28u
-M1010 vdd A.t3 a_n8_115.t1 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-M1011 gnd a_n8_115.t3 a_353_115# gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.105p ps=1.21u
-C0 B a_203_89# 0.490894fF
-C1 a_203_89# m1_n35_1379# 0.026952fF
-C2 Y m1_n35_1379# 0.026111fF
-C3 Y a_203_89# 0.372358fF
-C4 m1_n35_0# m1_n35_1379# 0.109399fF
-C5 m1_n35_0# a_203_89# 0.047670fF
-C6 m1_n35_0# Y 0.084075fF
-C7 A B 0.770915fF
-C8 vdd a_203_89# 0.001312fF
-C9 Y vdd 0.001219fF
-C10 A a_203_89# 0.388212fF
-R0 A A.t1 842.585
-R1 A.n1 A.t3 681.226
-R2 A.n1 A.n0 338.202
-R3 A.n0 A.t2 322.939
-R4 A.n0 A.t0 184.766
-R5 A A.n1 8.576
-R6 a_n8_115.n0 a_n8_115.t2 832.255
-R7 a_n8_115.n0 a_n8_115.t3 456.889
-R8 a_n8_115.t1 a_n8_115.n1 277.151
-R9 a_n8_115.n1 a_n8_115.t0 125.129
-R10 a_n8_115.n1 a_n8_115.n0 41.982
-R11 B.n1 B.t1 686.581
-R12 B.n0 B.t3 671.586
-R13 B.n1 B.t0 563.404
-R14 B.n0 B.t2 556.556
-R15 B B.n1 77.111
-R16 B B.n0 8.935
-R17 Y Y.n0 140.185
-R18 Y Y.n1 54.111
-R19 Y.n1 Y.t2 19.539
-R20 Y.n1 Y.t1 19.011
-R21 Y.n0 Y.t3 14.775
-R22 Y.n0 Y.t0 14.775
-C11 a_203_89# gnd 0.106885fF
-C12 vdd gnd 1.475160fF
-C13 Y.t3 gnd 0.077371fF
-C14 Y.t0 gnd 0.077371fF
-C15 Y.t1 gnd 0.026695fF
-C16 Y.t2 gnd 0.026960fF
-C17 B.t2 gnd 0.311190fF
-C18 B.t3 gnd 0.205138fF
-C19 B.t0 gnd 0.312241fF
-C20 B.t1 gnd 0.199844fF
-C21 a_n8_115.t0 gnd 0.247814fF
-C22 a_n8_115.t3 gnd 0.155251fF
-C23 a_n8_115.t2 gnd 0.253099fF
-C24 a_n8_115.t1 gnd 0.811753fF
-C25 A.t1 gnd 0.385213fF
-C26 A.t3 gnd 0.321238fF
-C27 A.t0 gnd 0.086035fF
-C28 A.t2 gnd 0.118367fF
-.ends
diff --git a/cdl/XOR2XL.cdl b/cdl/XOR2XL.cdl
deleted file mode 100644
index 5daf59b..0000000
--- a/cdl/XOR2XL.cdl
+++ /dev/null
@@ -1,80 +0,0 @@
-* SPICE3 file created from XOR2XL.ext - technology: EFS8A
-
-.subckt XOR2XL A Y B
-M1000 gnd A.t0 a_n8_115.t0 gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.265p ps=2.53u
-M1001 a_353_725# B.t0 Y.t3 vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.675p ps=3.45u
-M1002 Y.t0 a_203_89# a_161_725# vdd pshort w=3u l=0.15u
-+  ad=0.675p pd=3.45u as=0.315p ps=3.21u
-M1003 Y.t1 a_203_89# a_161_115# gnd nshort w=1u l=0.15u
-+  ad=0.225p pd=1.45u as=0.105p ps=1.21u
-M1004 a_353_115# B.t1 Y.t2 gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.225p ps=1.45u
-M1005 a_203_89# B.t2 vdd vdd pshort w=3u l=0.15u
-+  ad=0.795p pd=6.53u as=0.42p ps=3.28u
-M1006 a_161_725# A.t1 vdd vdd pshort w=3u l=0.15u
-+  ad=0.315p pd=3.21u as=0.42p ps=3.28u
-M1007 a_203_89# B.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.265p pd=2.53u as=0.14p ps=1.28u
-M1008 vdd a_n8_115.t2 a_353_725# vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.315p ps=3.21u
-M1009 a_161_115# a_n8_115.t3 gnd gnd nshort w=1u l=0.15u
-+  ad=0.105p pd=1.21u as=0.14p ps=1.28u
-M1010 vdd A.t2 a_n8_115.t1 vdd pshort w=3u l=0.15u
-+  ad=0.42p pd=3.28u as=0.795p ps=6.53u
-M1011 gnd A.t3 a_353_115# gnd nshort w=1u l=0.15u
-+  ad=0.14p pd=1.28u as=0.105p ps=1.21u
-C0 Y vdd 0.001219fF
-C1 B a_203_89# 0.490894fF
-C2 a_203_89# m1_n35_1379# 0.026952fF
-C3 Y a_203_89# 0.372358fF
-C4 Y m1_n35_1379# 0.026111fF
-C5 m1_n35_0# a_203_89# 0.047670fF
-C6 vdd a_203_89# 0.001312fF
-C7 m1_n35_0# m1_n35_1379# 0.109399fF
-C8 A a_203_89# 0.381787fF
-C9 A B 0.702834fF
-C10 m1_n35_0# Y 0.084075fF
-R0 A.n0 A.t1 644.273
-R1 A.n0 A.t2 506.1
-R2 A A.t3 492.412
-R3 A.n1 A.t0 414.519
-R4 A.n1 A.n0 283.576
-R5 A A.n1 8.576
-R6 a_n8_115.n0 a_n8_115.t2 807.062
-R7 a_n8_115.n0 a_n8_115.t3 565.547
-R8 a_n8_115.t1 a_n8_115.n1 200.857
-R9 a_n8_115.n1 a_n8_115.t0 179.04
-R10 a_n8_115.n1 a_n8_115.n0 117.982
-R11 B.n1 B.t1 686.581
-R12 B.n0 B.t3 671.586
-R13 B.n1 B.t0 563.404
-R14 B.n0 B.t2 556.556
-R15 B B.n1 77.111
-R16 B B.n0 8.935
-R17 Y Y.n0 140.185
-R18 Y Y.n1 54.111
-R19 Y.n1 Y.t2 19.539
-R20 Y.n1 Y.t1 19.011
-R21 Y.n0 Y.t3 14.775
-R22 Y.n0 Y.t0 14.775
-C11 a_203_89# gnd 0.106885fF
-C12 vdd gnd 1.475160fF
-C13 Y.t3 gnd 0.085096fF
-C14 Y.t0 gnd 0.085096fF
-C15 Y.t1 gnd 0.029360fF
-C16 Y.t2 gnd 0.029651fF
-C17 B.t2 gnd 0.313442fF
-C18 B.t3 gnd 0.206623fF
-C19 B.t0 gnd 0.314500fF
-C20 B.t1 gnd 0.201290fF
-C21 a_n8_115.t2 gnd 0.310729fF
-C22 a_n8_115.t3 gnd 0.139870fF
-C23 a_n8_115.t0 gnd 0.321147fF
-C24 a_n8_115.t1 gnd 0.860122fF
-C25 A.t3 gnd 0.228778fF
-C26 A.t2 gnd 0.262129fF
-C27 A.t1 gnd 0.290205fF
-C28 A.t0 gnd 0.129710fF
-.ends
diff --git a/char/Makefile b/char/Makefile
new file mode 100644
index 0000000..658f41a
--- /dev/null
+++ b/char/Makefile
@@ -0,0 +1,20 @@
+SHELL:=csh
+VARIANT:=18T_ms
+
+.PHONY: do clean purge
+
+do:
+	@cd abstract && make ARGS=-extract VARIANT=${VARIANT}
+	cd techfiles && ./genArea.py
+	@cd liberate && make purge do VARIANT=${VARIANT}
+#	@cd liberate && make clean do CORNER=FS && make clean do ARGS=-ecsm CORNER=FS
+
+clean:
+	-@cd ../lib && make clean
+	-@cd abstract && make clean
+	-@cd liberate && make clean
+
+purge:
+	-@cd ../lib && make clean
+	-@cd abstract && make clean
+	-@cd liberate && make purge
diff --git a/char/README b/char/README
new file mode 100644
index 0000000..1f00ef2
--- /dev/null
+++ b/char/README
@@ -0,0 +1 @@
+work in progress
diff --git a/char/abstract/.cadence/xstream/IN/.session b/char/abstract/.cadence/xstream/IN/.session
new file mode 100644
index 0000000..f69a413
--- /dev/null
+++ b/char/abstract/.cadence/xstream/IN/.session
@@ -0,0 +1,814 @@
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
+M:0 DV:1 NT:0 N:1 C:16
+
diff --git a/char/abstract/Makefile b/char/abstract/Makefile
new file mode 100644
index 0000000..b4b7f5f
--- /dev/null
+++ b/char/abstract/Makefile
@@ -0,0 +1,23 @@
+SHELL:=csh
+
+# Valid ARGS:
+# -gui
+# -extract
+# -noexit
+# -debug (gui + noexit)
+
+VARIANT:=12T_hs
+
+.PHONY: do clean
+
+do:
+	@sed -i 's/18T_ms/${VARIANT}/g' lef_gen
+	@sed -i 's/18T_ms/${VARIANT}/g' abstract_SKILL_script
+	@./clean_all
+	@setenv VARIANT ${VARIANT}; \
+	./lef_gen $(ARGS)
+	@sed -i 's/${VARIANT}/18T_ms/g' lef_gen
+	@sed -i 's/${VARIANT}/18T_ms/g' abstract_SKILL_script
+
+clean:
+	@./clean_all
diff --git a/char/abstract/abstract_SKILL_script b/char/abstract/abstract_SKILL_script
new file mode 100644
index 0000000..156059a
--- /dev/null
+++ b/char/abstract/abstract_SKILL_script
@@ -0,0 +1,46 @@
+/*
+ Abstract Skill Generation
+ Oklahoma State University
+ VLSI Computer Architecture Reserch Group
+ Apache 2.0 Licensing
+*/
+absSkillMode()
+absSetOption("NewLibraryName" "library")
+absSetLibrary("library")
+absSetOption("ImportLefFiles" " ../techfiles/sky130_osu_sc.tlef")
+absImportLEF()
+inp = infile("GDSlist")
+absSetOption("ImportGDSIIFiles" gets(_ inp))
+close(inp)
+absSetOption("ImportGDSIILayerMapFile" "../techfiles/s8.layermap")
+absImportGDS()
+absSelectCellFrom("ADDFX1" "XOR2XL")
+absSetBinOption("Core" "PinsTextPinMap" "(li1 li1)(met1 met1)")
+absSetBinOption("Core" "PinsPowerNames" "vdd")
+absSetBinOption("Core" "PinsGroundNames" "gnd")
+absSetBinOption("Core" "PinsClockNames" "clk")
+absSetBinOption("Core" "PinsOutputNames" "Y Q QN S CO")
+#absSetBinOption("Core" "AbstractAdjustBoundaryPinsSig" "true")
+#absSetBinOption("Core" "AbstractAdjustBoundaryPinsPwr" "true")
+#absSetBinOption("Core" "ExtractAntennaMetalArea" "true")
+#absSetBinOption("Core" "ExtractAntennaMetalSideArea" "true")
+#absSetBinOption( "Core" "ExtractLayersSigWeak" "poly (diff (diff andnot poly)) licon1 ")
+absSetBinOption("Core" "ExtractPinLayersSig" "li1 met1 met2 met3 met4 met5 mcon via1 via2 via3 via4")
+absSetBinOption("Core" "ExtractDiffAntennaLayers" "true")
+absSetBinOption("Core" "ExtractAntennaLayers" "li1 met1 met2 met3 met4 met5 mcon via1 via2 via3 via4 poly licon1 (diff (diff andnot poly)) ")
+absSetBinOption("Core" "ExtractAntennaHier" "true")
+absSetBinOption("Core" "ExtractAntennaSizeInput" "true")
+absSetBinOption("Core" "ExtractAntennaSizeOutput" "true")
+absSetBinOption("Core" "ExtractAntennaSizeInout" "true")
+absSetBinOption( "Core" "ExtractAntennaGate" "(poly (poly and diff)) ")
+absSetBinOption( "Core" "ExtractAntennaDrain" "(diff (diff andnot poly)) ")
+absSetBinOption("Core" "ExtractConnectivity" "(poly li1 licon1)(diff li1 licon1)(li1 met1 mcon)(met1 met2 via1)(met2 met3 via2)(met3 met4 via3)(met4 met5 via4)")
+absSetBinOption("Core" "AbstractAdjustPowerRailOp" "gnd abutment 0.3 0 vdd abutment 0.3 -0.18")
+absSetBinOption("Core" "AbstractBlockageCutAroundPin" "li1 met1 met2 met3 met4 met5 mcon via1 via2 via3 via4 ")
+absSetBinOption("Core" "AbstractSiteNameDefine" "12T")
+absSetOption("ExportLEFFile" "sky130_osu_sc_18T_ms.lef")
+absPins()
+absExtract()
+absAbstract()
+absExportLEF()
+absExit()
diff --git a/char/abstract/clean_all b/char/abstract/clean_all
new file mode 100755
index 0000000..84d1f98
--- /dev/null
+++ b/char/abstract/clean_all
@@ -0,0 +1,11 @@
+#!/bin/bash
+
+mkdir -p ../.tmp
+mv abstract_SKILL_script ../.tmp/
+mv lef_gen ../.tmp/
+mv sourceme ../.tmp/
+mv clean_all ../.tmp/
+mv Makefile ../.tmp/
+rm -rf ../abstract/*
+mv ../.tmp/* .
+rm -rf ../.tmp
diff --git a/char/abstract/lef_gen b/char/abstract/lef_gen
new file mode 100755
index 0000000..4355e7e
--- /dev/null
+++ b/char/abstract/lef_gen
@@ -0,0 +1,51 @@
+#!/bin/bash
+
+mkdir -p GDS
+
+extract=0
+gui=0
+noexit=0
+
+while test $# -gt 0
+do
+    case "$1" in
+        -extract) extract=1
+            ;;
+        -gui) gui=1
+            ;;
+        -noexit) noexit=1
+            ;;
+        -debug) noexit=1; gui=1
+            ;;
+    esac
+    shift    
+done
+
+if [ $extract -eq 1 ]
+then
+	cd ../../lib/ 
+	make magic pex TRACKS=${TRACKS}
+	cd -
+fi
+
+cp ../../lib/gds/*.gds GDS/
+ls GDS/* | sed ':a;N;$!ba;s/\n/ /g' | sed "`../techfiles/special_cells -lef_gen`" | sed 's/GDS\/ \|GDS\/$//g' > GDSlist
+
+if [ $noexit -eq 1 ]
+then
+    sed -i '/absExit/d' abstract_SKILL_script
+fi
+
+if [ $gui -eq 1 ]
+then
+    abstract -replay abstract_SKILL_script
+else
+    abstract -nogui -replay abstract_SKILL_script
+fi
+
+if [ $noexit -eq 1 ]
+then
+    echo "absExit()" >> abstract_SKILL_script
+fi
+
+cp sky130_osu_sc_18T_ms.lef ../../outputs/
diff --git a/char/abstract/sourceme b/char/abstract/sourceme
new file mode 100644
index 0000000..e8dbc9e
--- /dev/null
+++ b/char/abstract/sourceme
@@ -0,0 +1,2 @@
+source ../../scripts/cadence.cshrc
+source ../../scripts/magic.cshrc
diff --git a/char/liberate/MODELS/models.sp b/char/liberate/MODELS/models.sp
new file mode 100644
index 0000000..0001af6
--- /dev/null
+++ b/char/liberate/MODELS/models.sp
@@ -0,0 +1,25 @@
+* SPICE
+.LIB TT
+.include "models.all"
+.include "tt_discrete.cor"
+.ENDL TT
+
+.LIB FF
+.include "models.all"
+.include "ff_discrete.cor"
+.ENDL FF
+
+.LIB SS
+.include "models.all"
+.include "ss_discrete.cor"
+.ENDL SS
+
+.LIB FS
+.include "models.all"
+.include "fs_discrete.cor"
+.ENDL FS
+
+.LIB SF
+.include "models.all"
+.include "sf_discrete.cor"
+.ENDL SF
diff --git a/char/liberate/Makefile b/char/liberate/Makefile
new file mode 100644
index 0000000..cd8b616
--- /dev/null
+++ b/char/liberate/Makefile
@@ -0,0 +1,88 @@
+VPATH:=make
+LOG:=./LOG
+RUN_DIR:=$(shell pwd)
+SHELL:=bash
+
+.DEFAULT: all
+.PHONY: all do run clean purge
+
+CORNER:=TT
+TEMP:=25
+VLTG:=1.8
+ARGS:=-ccs
+VARIANT:=18T_ms
+
+USER:=$(shell whoami)
+USER_MAIL:=$(shell echo `ldapsearch -x -LL "(uid=$(USER))" mail | sed -n "s/^mail: //p"`)
+export
+
+define \n
+
+
+endef
+
+ALL_CNR = TT \
+		FF \
+		SS \
+		FS \
+		SF
+
+setup:
+	@mkdir -p $(VPATH) $(LOG) NETLIST LIBRARY LDB DATASHEET VERILOG
+	@cp ../../skywater/s8pdk/V1.3.0/MODELS/spice/* MODELS/
+	@cp ../../calibre/output/spice/* NETLIST/ ; cp ../../calibre/output/pex/* NETLIST/ ; cp ../../calibre/output/pxi/* NETLIST/
+	@cd NETLIST && sed -i '/^.subckt/s/VDD\|GND//g' *.spice && sed -i "/ PROBETYPE=1/d" *.spice && sed -i "/NWDIODE/d" *.spice
+	@cd MODELS && sh ../sedSpice
+	@ls NETLIST/*.spice | sed ':a;N;$$!ba;s/\n/ /g' | sed "`../techfiles/special_cells -libchar`" | sed 's/.spice\|NETLIST\///g' > celllist
+	@touch $(VPATH)/$@
+
+all:
+	@for i in $(ALL_CNR); do \
+		echo "Generating corner $$i"; \
+		$(MAKE) -f $(lastword $(MAKEFILE_LIST)) do CORNER=$$i; \
+	done
+
+run: setup
+	export CORNER=$(CORNER); \
+	export TEMP=$(TEMP); \
+	export VLTG=$(VLTG); \
+	export ARGS=$(ARGS); \
+	export VARIANT=$(VARIANT); \
+	export NAME=`SCRIPTS/getname.tcl`; \
+	printf "*\n.LIB 'models.sp' $(CORNER)" > MODELS/include.sp; \
+	liberate --trio char.tcl |& tee LOG/$$NAME.log; \
+	lc_shell -no_log -f SCRIPTS/lib_to_db.tcl
+ifndef NO_MAIL
+	@echo "" | mail -s "Lib extraction finished for $(CORNER) $(TEMP) $(VLTG) $(ARGS) on `uname -n`" $(USER_MAIL)
+endif
+
+do: run
+	@cp *.lib ../../outputs/
+	@cp *.db ../../outputs/
+	@cp -r DATASHEET ../../outputs/
+	@cp -r VERILOG ../../outputs/
+	@mv *.lib LIBRARY/
+	@mv *.db LIBRARY/
+
+clean:
+	-@rm -f MODELS/*.pm3
+	-@rm -f MODELS/*.cor
+	-@rm -f MODELS/*.ai
+	-@rm -f MODELS/*.va
+	-@rm -f MODELS/*.mod
+	-@rm -f MODELS/fixed_layout_*
+	-@rm -f MODELS/readme
+	-@rm -f MODELS/models.all
+	-@rm -f MODELS/include.sp
+	-@rm -f NETLIST/*
+	-@rm -rf $(VPATH)
+	-@rm -rf altos*
+	-@rm -rf celllist
+
+purge: clean
+	-@rm -rf $(LOG)
+	-@rm -rf LIBRARY
+	-@rm -rf LDB
+	-@rm -rf DATASHEET
+	-@rm -rf VERILOG
+	-@rm -rf NETLIST
diff --git a/char/liberate/README b/char/liberate/README
new file mode 100755
index 0000000..1610307
--- /dev/null
+++ b/char/liberate/README
@@ -0,0 +1 @@
+make ARGS=-ccs|-ecsm|-lvf [CORNER=TT|FF|SS|FS|SF] [TEMP=?] [VLTG=?] [NO_MAIL=please]
diff --git a/char/liberate/SCRIPTS/getname.tcl b/char/liberate/SCRIPTS/getname.tcl
new file mode 100755
index 0000000..caf977c
--- /dev/null
+++ b/char/liberate/SCRIPTS/getname.tcl
@@ -0,0 +1,2 @@
+#!/usr/bin/tclsh
+puts "sky130_osu_sc_$env(VARIANT)_$env(CORNER)_[string map {. P} $env(VLTG)]_$env(TEMP)C[string map {- . " " ""} $env(ARGS)]"
diff --git a/char/liberate/SCRIPTS/lib_to_db.tcl b/char/liberate/SCRIPTS/lib_to_db.tcl
new file mode 100644
index 0000000..d7575bc
--- /dev/null
+++ b/char/liberate/SCRIPTS/lib_to_db.tcl
@@ -0,0 +1,3 @@
+read_lib $env(NAME).lib
+write_lib $env(NAME) -output $env(NAME).db
+quit
diff --git a/char/liberate/TEMPLATE/template_example.tcl b/char/liberate/TEMPLATE/template_example.tcl
new file mode 100755
index 0000000..9edbba4
--- /dev/null
+++ b/char/liberate/TEMPLATE/template_example.tcl
@@ -0,0 +1,44 @@
+# Liberate Template Example Tcl File - Sept 2008
+
+set lowSlew 0.14
+set highSlew 0.86
+
+# Set the maximum output transition time allowed
+set_var max_transition 729.57e-12
+
+set fp [open "celllist"]
+set cells [regexp -all -inline {\S+} [read $fp]]
+#set cells "INVX1"
+
+close $fp
+
+define_template -type delay \
+        -index_1        {0.1000 0.5000 1.2000 3.0000 4.0000 5.0000} \
+        -index_2        {0.0600 0.2400 0.4800 0.9000 1.2000 1.8000} \
+        delay_template
+
+define_template -type power \
+        -index_1        {0.1000 0.5000 1.2000 3.0000 4.0000 5.0000} \
+        -index_2        {0.0600 0.2400 0.4800 0.9000 1.2000 1.8000} \
+        power_template
+
+define_template -type constraint \
+        -index_1  {0.1  2.50  5.00} \
+        -index_2  {0.1  0.90  1.80} \
+        constraint_template
+
+set inputs  {A B C D A0 A1 B0 B1 CI S0 OE}
+set outputs {Y Q QN S CO CON}
+set clocks  {CK}
+set asyncs  {RN SN}
+
+define_cell \
+        -input $inputs  -output $outputs  -clock $clocks  -async $asyncs \
+        -constraint  constraint_template    \
+        -delay       delay_template \
+        -power       power_template \
+        $cells
+
+#set_constraint_criteria -cells {DFFSX1 DFFRX1 DFFX1 DFFNX1} -delay_degrade 0.5
+#set constraint_search_bound_estimation_mode 3
+#set constraint_search_bound 20
diff --git a/char/liberate/char.tcl b/char/liberate/char.tcl
new file mode 100755
index 0000000..8c25bb9
--- /dev/null
+++ b/char/liberate/char.tcl
@@ -0,0 +1,53 @@
+set rundir $env(PWD) 
+set corner $env(CORNER)
+
+set outputfile $env(NAME)
+
+### Define temperature and default voltage ###
+set_operating_condition -voltage $env(VLTG) -temp $env(TEMP)
+
+## Load template information for each cell ##
+source ${rundir}/TEMPLATE/template_example.tcl
+
+
+#set_var extsim_model_include $rundir/MODELS/include.sp
+#define_leafcell -extsim_model -type nmos -pin_position {0 1 2 3} nshort
+#define_leafcell -extsim_model -type pmos -pin_position {0 1 2 3} pshort
+
+set_var parse_ignore_duplicate_subckt 1
+#set_var voltage_map 1
+#set_var pin_based_power 0
+#set_var subtract_hidden_power 2
+#set_var subtract_hidden_power_use_default 3
+#set_var power_subtract_leakage 3
+
+#set_var power_info 2
+#set_var power_info_filename "power.log"
+
+## Load Spice models and subckts ##
+set spicefiles "$rundir/MODELS/include.sp"
+foreach cell $cells {
+    lappend spicefiles ${rundir}/NETLIST/${cell}.spice
+}
+read_spice -format hspice $spicefiles
+
+# VTH0 variation
+define_variation -type systematic  {snvth0  0.1} snvth0
+define_variation -type random      {rnvth0  0.1} rnvth0
+
+##run varietion ##
+char_library $env(ARGS) -cells ${cells} -auto_index -auto_max_capacitance -thread 32
+
+write_library -user_data ../../outputs/areaData.lib -overwrite $env(ARGS) $outputfile
+
+write_ldb ${rundir}/LDB/$outputfile.ldb
+
+write_verilog ${rundir}/VERILOG/$outputfile.v
+
+#write_template test.tcl
+
+write_datasheet -format html -dir ${rundir}/DATASHEET/$outputfile $outputfile
+write_datasheet -format ps -dir ${rundir}/DATASHEET/$outputfile $outputfile
+set tmp1 ${rundir}/DATASHEET/$outputfile/$outputfile.ps
+set tmp2 ${rundir}/DATASHEET/$outputfile/$outputfile.pdf
+exec csh -c "cd ${rundir}/DATASHEET/$outputfile && setenv TEMP `pwd` && ps2pdf $tmp1 $tmp2 && mv *.pdf ../ && mv *.ps ../"
diff --git a/char/liberate/sedSpectre b/char/liberate/sedSpectre
new file mode 100644
index 0000000..6399cbf
--- /dev/null
+++ b/char/liberate/sedSpectre
@@ -0,0 +1,14 @@
+sed -i '38,42d' ?short.pm3
+sed -i '/^ends/d' ?short.pm3
+sed -i 's/model nshort_model/model nshort/' nshort.pm3
+sed -i 's/model pshort_model/model pshort/' pshort.pm3
+sed -i 's/l\*w\*mult/1/' ?short.pm3
+
+sed -i '33,37d' ?short_??.pm3
+sed -i '/^ends/d' ?short_??.pm3
+sed -i 's/model nshort_model/model nshort/' nshort_??.pm3
+sed -i 's/model pshort_model/model pshort/' pshort_??.pm3
+sed -i 's/l\*w\*mult/1/' ?short_??.pm3
+
+sed -i '/^.option scale/d' models.all
+
diff --git a/char/liberate/sedSpice b/char/liberate/sedSpice
new file mode 100644
index 0000000..a985865
--- /dev/null
+++ b/char/liberate/sedSpice
@@ -0,0 +1,3 @@
+sed -i 's|dev/gauss.*||' *
+
+sed -i '/^.SETSOA/d' *
diff --git a/char/liberate/sourceme b/char/liberate/sourceme
new file mode 100644
index 0000000..fd8df55
--- /dev/null
+++ b/char/liberate/sourceme
@@ -0,0 +1,2 @@
+source ../../scripts/synopsys_x64.cshrc
+source ../../scripts/cadence.cshrc
diff --git a/char/sourceme b/char/sourceme
new file mode 100644
index 0000000..8d9c1f8
--- /dev/null
+++ b/char/sourceme
@@ -0,0 +1,4 @@
+source ../scripts/cadence.cshrc
+source ../scripts/magic.cshrc
+source ../scripts/synopsys_x64.cshrc
+source ../scripts/cadence.cshrc
diff --git a/char/techfiles/genArea.py b/char/techfiles/genArea.py
new file mode 100755
index 0000000..7869d0e
--- /dev/null
+++ b/char/techfiles/genArea.py
@@ -0,0 +1,154 @@
+#!/usr/bin/python3
+TOTORO = '''
+         ,--"""",--.__,---[],-------._
+       ,"   __,'            \         \--""""""==;-
+     ," _,-"  "/---.___     \       ___\   ,-'',"
+    /,-'      / ;. ,.--'-.__\  _,-"" ,| `,'   /
+   /``""""-._/,-|:\       []\,' ```-/:;-. `. /
+             `  ;:::      ||       /:,;  `-.
+                =.,'__,---||-.____',.=
+                =(:\_     ||__    ):)=
+               ,"::::`----||::`--':::"._
+             ,':::::::::::||::::::::::::'.
+    .__     ;:::.-.:::::__||___:::::.-.:::\    
+       """-;:::( O )::::>_|| _<::::( O )::::-""
+   =======;:::::`-`:::::::||':::::::`-`:::::\===
+    ,--"";:::_____________||______________::::""
+         ; ::`._(    |    |||     |   )_,'::::\_
+       ,;    :::`--._|____[]|_____|_.-':::::::::
+      ;/ /      :::::::::,||,:::::::::::::::::::
+
+'''
+
+
+
+
+
+
+lefName = "../../outputs/sky130_osu_sc_12T_hs.lef"
+
+f = open(lefName,"r")
+lefFile = f.read()
+macroList = lefFile.split("MACRO")
+
+nameList = []
+#7.2 is height
+widthList = []
+multEleven = []
+
+heightList = []
+areaList = []
+
+#Lists to keep track of the cells that are wrong
+originBad = []
+multBad = []
+
+
+def stringToInt(x):
+    res=0
+    ctr=0
+    flag=1
+    for a in x:
+        if a=='.':
+            ctr=1
+            continue
+        if flag:
+            res=10*res+int(a)
+        else:
+            res=float(res)+int(a)*(10**(2-ctr))
+        if ctr:
+            ctr+=1
+        if ctr>2:
+            flag=0
+    return res
+
+#Parse the LEF for important info
+for i in range(1,len(macroList)):
+    # Lines to calculate the area and log the width and height as well as log 
+    # if the width is a multiple of 11
+    nameList.append(macroList[i].split("\n")[0].strip())
+    sizeLine = macroList[i].split("SIZE")[1].split("\n")[0].split(" ")
+    widthList.append(stringToInt(sizeLine[1]))
+    heightList.append(stringToInt(sizeLine[3]))
+    areaList.append(widthList[i-1] * heightList[i-1])
+
+    if( (widthList[i-1] % 11) == 0):
+        multEleven.append("yes")
+    else:
+        multEleven.append("no")
+
+    
+    #Lines to check the origin
+    originLine = macroList[i].split("ORIGIN")[1].split("\n")[0].split(" ")
+
+    if(float(originLine[1]) != 0 or float(originLine[2]) != 0):
+        print(nameList[i-1] + " Origin not 0 0")
+        originBad.append(nameList[i-1])
+
+
+#A bit of a bad way to do this but
+#This gets the footprint and accounts
+#for cells that start with X
+footprintList = []
+for name in nameList:
+    if("X" in name):
+        nameSplit = name.split("X")
+        tempFoot = ""
+        if(name[0] is "X"):
+            tempFoot = tempFoot + "X"
+
+        for inc in range(len(nameSplit)-1) :
+            tempFoot = tempFoot +  nameSplit[inc]
+
+        footprintList.append(tempFoot)
+    else:
+        footprintList.append(name)
+
+#Print to screen which cells are not a multiple of 11
+for name,width,height,area,mult11 in zip(nameList,widthList,heightList,areaList,multEleven):
+    if(mult11 is "no"):
+        print("______________________________________________________________")
+        print("Cell " + name + " does not have a size that is a multiple of 11")
+        print("Name | Width | Height | Area")
+        print(name,str(width/100),str(height/100),str(area/10000))
+        print("______________________________________________________________")
+        multBad.append(name)
+
+#Report which cells are incorrect to the log
+
+#Incorrect Origin Reporting
+writeReport = open("../../outputs/cellRules.log","w+")
+if(len(originBad) > 0):
+    writeReport.write("The following cells do not have an origin of 0 0\n")
+    writeReport.write("_____________________________________________________\n")
+    for name in originBad:
+        writeReport.write(name + "\n")
+    writeReport.write("\n\n\n")
+#Incorrect Width reporting
+if(len(multBad)>0):
+    writeReport.write("The following cells do not have a width that is a multiple of 11\n")
+    writeReport.write("_____________________________________________________\n")
+    for name in multBad:
+        writeReport.write(name + "\n")
+if(len(originBad) == 0 and len(multBad) == 0):
+    print("ALL IS GOOD HAVE A TOTORO")
+    writeReport.write("All is good :)")
+    writeReport.write(TOTORO)
+    print(TOTORO)
+
+
+
+#Write areaData and footprint to file. Uncomment lines in for loop to add other things
+writeF = open("../../outputs/areaData.lib", "w+")
+
+writeF.write("library (s8_osu130) {\n")
+
+for name,width,height,area,mult11,footprint in zip(nameList,widthList,heightList,areaList,multEleven,footprintList):
+    writeF.write("\n\ncell(" + name + ") {")
+    #writeF.write("\nwidth : " + str(width/100))
+    #writeF.write("\nheight : " + str(height/100))
+    writeF.write("\narea : " + str(area/10000) + ";")
+    writeF.write("\ncell_footprint : " + footprint + ";") 
+    #writeF.write("SizeCorrect : " + str(mult11))
+    writeF.write("\n}")
+writeF.write("\n}")
diff --git a/char/techfiles/s8.layermap b/char/techfiles/s8.layermap
new file mode 100644
index 0000000..8b4252e
--- /dev/null
+++ b/char/techfiles/s8.layermap
@@ -0,0 +1,59 @@
+nwell  drawing 64 20
+dnwell drawing 64 18
+diff   drawing 65 20
+tap    drawing 65 44
+lvtn  drawing 125 44
+hvtp   drawing 78 44
+hvi    drawing 75 20
+tunm   drawing 80 20
+poly   drawing 66 20
+poly   pin 66 16
+poly   label 66 5
+npc    drawing 95 20
+psdm   drawing 94 20
+nsdm   drawing 93 44
+licon1 drawing 66 44
+li1    drawing 67 20
+li1    pin 67 16
+li1    label 67 5
+mcon   drawing 67 44
+met1   drawing 68 20
+met1   pin 68 16
+met1   label 68 5
+via1   drawing 68 44
+met2   drawing 69 20
+met2t  pin 69 16
+met2p  label 69 5
+via2   drawing 69 44
+met3   drawing 70 20
+met3t  pin 70 16
+met3p  label 70 5
+via3   drawing 70 44
+met4   drawing 71 20
+met4t  pin 71 16
+met4p  label 71 5
+via4   drawing 71 44
+met5   drawing 72 20
+met5t  pin 72 16
+met5p  label 72 5
+pad    drawing 76 20
+padt   pin 76 16
+padp   label 76 5
+#bound  standardc 81 4
+text   label 83 44
+hvtr   drawing 18 20
+ncm    drawing 92 44
+rpm    drawing 86 20
+nsm    drawing 61 20
+rdl    drawing 74 20
+vhvi   drawing 74 21
+ldntm  drawing 11 44
+hvntm drawing 125 20
+pmm    drawing 85 44
+pnp    drawing 82 44
+cap    drawing 82 64
+ind    drawing 82 24
+#pwres  res 64 13
+#polyres res 66 13
+#diffres res 65 13
+#diode diode 81 23
diff --git a/char/techfiles/sky130A.tech b/char/techfiles/sky130A.tech
new file mode 100644
index 0000000..6920346
--- /dev/null
+++ b/char/techfiles/sky130A.tech
@@ -0,0 +1,4255 @@
+#----------------------------------------------------------
+# Copyright (c) 2020 R. Timothy Edwards
+# Revisions:  See below
+#
+# This file is an Open Source foundry process describing
+# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
+# process.  The file may be distributed under the terms
+# of the Apache 2.0 license agreement.
+#
+#----------------------------------------------------------
+# This file is designed to be used with magic versions
+# 8.3.24 or newer.
+#----------------------------------------------------------
+tech
+  format 35
+  sky130A
+end
+
+version
+ version 20200508
+ description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC"
+end
+
+#----------------------------------------------------------
+# Status 7/10/20: Rev 1 (alpha):
+# First public release
+#--------------------------------------------------------------
+
+#--------------------------------------------------------------
+# Supported device types
+#--------------------------------------------------------------
+# device name   magic ID layer  description
+#-------------------------------------------------------------
+# nshort    nfet        standard nFET
+# nshort    scnfet      standard nFET in standard cell**
+# npd       npd     special nFET in SRAM cell
+# npass     npass       special nFET in SRAM cell
+# nlowvt    nfetlvt     low Vt nFET
+# sonos_p/e nsonos      SONOS nFET
+# pshort    pfet        standard pFET
+# pshort    scpfet      standard pFET in standard cell**
+# ppu       ppu     special pFET in SRAM cell
+# plowvt    pfetlvt     low Vt pFET
+# phighvt   pfethvt     high Vt pFET
+# ntvnative ---     native nFET
+# phv       mvpfet      thickox pFET
+# nhv       mvnfet      thickox nFET
+# nhvnative mvnnfet     thickox native nFET
+# ndiode    ndiode      n+ diff diode
+# ndiode_h  mvndiode    thickox n+ diff diode
+# pdiode    pdiode      p+ diff diode
+# pdiode_h  mvpdiode    thickox p+ diff diode
+# ndiode_native nndiode     diode with nndiff
+# ndiode_lvt    ndiodelvt   low Vt n+ diff diode
+# pdiode_lvt    pdiodelvt   low Vt p+ diff diode
+# pdiode_hvt    pdiodehvt   high Vt p+ diff diode
+# nwdiode   ---     nwell diode
+# dnwdiode_psub ---     deep nwell diode to substrate
+# dnwdiode_pw   ---     deep nwell diode to pwell
+# xcmimc1   mimcap      MiM cap 1st plate
+# xcmimc2   mimcap2     MiM cap 2nd plate
+# mrdn      rdn     n+ diff resistor
+# mrdn_hv   mvrdn       thickox n+ diff resistor
+# mrdp      rdp     p+ diff resistor
+# mrdp_hv   mvrdp       thickox p+ diff resistor
+# mrl1      rli     local interconnect resistor
+# mrp1      npres       n+ poly resistor
+# xhrpoly_* ppres (*)   p+ poly resistor (300 Ohms/sq)
+# uhrpoly_* xres (*)    p+ poly resistor (2k Ohms/sq)
+# xcnwvc    varactor    varactor (low Vt?)
+# xcnwvc2   varactorhvt high Vt varactor
+# xchvnwc   mvvaractor  thickox varactor
+# xpwres    rpw     pwell resistor (in deep nwell)
+#
+# (*) Note that ppres may extract into some generic type
+# called "xhrpoly", but only specific sizes of xhrpoly are
+# allowed, and these are created from fixed layouts like the
+# types below.
+#
+# (**) nFET and pFET in standard cells are the same as devices
+# outside of the standard cell except for the DRC rule for
+# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
+#
+# To avoid creating a large number of types, a few ID layers are
+# used in conjunction with standard devices types:  "lvt" for
+# low threshold voltage, and "hvt" for high threshold voltage.
+# "dnwell" is used as an identifier layer where appropriate.
+# Layer HVI (thick oxide) is treated differently, and types
+# "mv*" are defined where thick oxide is required.
+#
+#-------------------------------------------------------------
+# The following devices are not extracted but are represented
+# only by script-generated subcells in the PDK.
+#-------------------------------------------------------------
+# nshortesd         ESD nFET
+# nhvesd            ESD thickox nFET
+# nhvnativeesd          ESD native nFET
+# phvesd            ESD thickox pFET
+# fnpass            flash nFET device
+# npnpar1x*         parasitic NPN
+# npn_1x1_2p0_hv        thickox gated parasitic NPN
+# pnppar            parasitic PNP
+# pnppar5x          parasitic PNP
+# xesd_ndiode_h_***     ESD n+ diode
+# xesd_pdiode_h_***     ESD p+ diode
+# reslocsub         local substrate island indicator
+# xcmvpp            Vpp cap
+# xcmvpp_2          Vpp cap
+# xcmvpp_*          Vpp cap
+# xcmvpp*           Vpp cap
+# balun             balun inductor
+# ind4              inductor
+# fuse              metal fuse device
+#--------------------------------------------------------------
+
+#-----------------------------------------------------
+# Tile planes
+#-----------------------------------------------------
+
+planes
+  dwell,dw
+  well,w
+  active,a
+  locali,li1,li
+  metal1,m1
+  metal2,m2
+  metal3,m3
+  cap1,c1
+  metal4,m4
+  cap2,c2
+  metal5,m5
+  metali,mi
+  block,b
+  comment,c
+end
+
+#-----------------------------------------------------
+# Tile types
+#-----------------------------------------------------
+
+types
+# Deep nwell
+  dwell dnwell,dnw
+
+# Wells
+  well nwell,nw
+ -well pwell,pw
+ -well rpw,rpwell
+ -well obswell
+
+# Transistors
+  active nmos,ntransistor,nfet
+ -active scnmos,scntransistor,scnfet
+ -active npd,npdfet,sramnfet
+ -active npass,npassfet,srampassfet
+  active pmos,ptransistor,pfet
+ -active scpmos,scptransistor,scpfet
+ -active ppu,ppufet,srampfet
+ -active nnmos,nntransistor
+  active mvnmos,mvntransistor,mvnfet
+  active mvpmos,mvptransistor,mvpfet
+ -active mvnnmos,mvnntransistor,mvnnfet,nnfet
+ -active varactor,varact,var
+ -active mvvaractor,mvvaract,mvvar
+
+ -active pmoslvt,pfetlvt
+ -active pmoshvt,pfethvt
+ -active nmoslvt,nfetlvt
+ -active varactorhvt,varacthvt,varhvt
+ -active nsonos,sonos
+
+# Diffusions
+  active ndiff,ndiffusion,ndif
+  active pdiff,pdiffusion,pdif
+ -active mvndiff,mvndiffusion,mvndif
+ -active mvpdiff,mvpdiffusion,mvpdif
+  active ndiffc,ndcontact,ndc
+  active pdiffc,pdcontact,pdc
+ -active mvndiffc,mvndcontact,mvndc
+ -active mvpdiffc,mvpdcontact,mvpdc
+  active psubdiff,psubstratepdiff,ppdiff,ppd,psd
+  active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
+ -active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
+ -active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
+  active psubdiffcont,psubstratepcontact,psc
+  active nsubdiffcont,nsubstratencontact,nsc
+ -active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
+ -active mvnsubdiffcont,mvnsubstratencontact,mvnsc
+ -active obsactive
+ -active mvobsactive
+
+# Poly
+  active poly,p,polysilicon
+  active polycont,pc,pcontact,polycut,polyc
+  active xpolycontact,xpolyc,xpc
+
+# Resistors
+ -active npolyres,npres,mrp1
+ -active ppolyres,ppres,xhrpoly
+ -active xpolyres,xpres,xres,uhrpoly
+ -active ndiffres,rnd,rdn,rndiff
+ -active pdiffres,rpd,rdp,rpdiff
+ -active mvndiffres,mvrnd,mvrdn,mvrndiff
+ -active mvpdiffres,mvrpd,mvrdp,mvrpdiff
+ -active rmp
+
+# Diodes
+ -active pdiode,pdi
+ -active ndiode,ndi
+ -active nndiode,nndi
+ -active pdiodec,pdic
+ -active ndiodec,ndic
+ -active nndiodec,nndic
+ -active mvpdiode,mvpdi
+ -active mvndiode,mvndi
+ -active mvpdiodec,mvpdic
+ -active mvndiodec,mvndic
+ -active pdiodelvt,pdilvt
+ -active pdiodehvt,pdihvt
+ -active ndiodelvt,ndilvt
+ -active pdiodelvtc,pdilvtc
+ -active pdiodehvtc,pdihvtc
+ -active ndiodelvtc,ndilvtc
+
+# Local Interconnect 
+  locali locali,li1,li
+ -locali corelocali,coreli1,coreli
+ -locali rlocali,rli1,rli
+  locali viali,vial,lic,licon,m1c,v0
+ -locali obsli1,obsli
+ -locali obsli1c,obslic,obslicon
+
+# Metal 1
+  metal1 metal1,m1,met1
+ -metal1 rmetal1,rm1,rmet1
+  metal1 via1,m2contact,m2cut,m2c,via,v,v1
+ -metal1 obsm1
+ -metal1 padl
+ -metal1 m1fill
+
+# Metal 2
+  metal2 metal2,m2,met2
+ -metal2 rmetal2,rm2,rmet2
+  metal2 via2,m3contact,m3cut,m3c,v2
+ -metal2 obsm2
+ -metal2 m2fill
+
+# Metal 3
+  metal3 metal3,m3,met3
+ -metal3 rmetal3,rm3,rmet3
+ -metal3 obsm3
+  metal3 via3,v3
+ -metal3 m3fill
+
+ -cap1 mimcap,mim,capm
+ -cap1 mimcapcontact,mimcapc,mimcc,capmc
+
+# Metal 4
+  metal4 metal4,m4,met4
+ -metal4 rmetal4,rm4,rmet4
+ -metal4 obsm4
+  metal4 via4,v4
+ -metal4 m4fill
+
+ -cap2 mimcap2,mim2,capm2
+ -cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
+
+# Metal 5
+  metal5 metal5,m5,met5
+ -metal5 rm5,rmetal5,rmet5
+ -metal5 obsm5
+ -metal5 m5fill
+
+ -metal5 mrdlcontact,mrdlc
+ -metali metalrdl,mrdl,metrdl
+ -metali obsmrdl
+
+# Miscellaneous
+ -block  glass
+ -block  fillblock
+ -comment comment
+ -comment obscomment
+
+end
+
+#-----------------------------------------------------
+# Magic contact types
+#-----------------------------------------------------
+
+contact
+  pc       poly       locali
+  ndc      ndiff      locali
+  pdc      pdiff      locali
+  nsc      nsd        locali
+  psc      psd        locali
+  ndic     ndiode     locali
+  ndilvtc  ndiodelvt  locali
+  nndic    nndiode    locali
+  pdic     pdiode     locali
+  pdilvtc  pdiodelvt  locali
+  pdihvtc  pdiodehvt  locali
+  xpc      xpc        locali
+
+  mvndc   mvndiff   locali
+  mvpdc   mvpdiff   locali
+  mvnsc   mvnsd     locali
+  mvpsc   mvpsd     locali
+  mvndic  mvndiode  locali
+  mvpdic  mvpdiode  locali
+
+  lic locali metal1
+  obslic obsli obsm1
+
+  via1   metal1 metal2
+  via2   metal2 metal3
+  via3   metal3 metal4
+  via4   metal4 metal5
+  stackable
+
+  # MiM cap contacts are not stackable!
+  mimcc  mimcap metal4
+  mim2cc mimcap2 metal5
+
+  padl m1 m2 m3 m4 m5 glass
+
+  mrdlc metal5 mrdl
+end
+
+#-----------------------------------------------------
+# Layer aliases
+#-----------------------------------------------------
+
+aliases
+
+  allwellplane     nwell
+  allnwell     nwell,obswell
+
+  allnfets     nfet,npass,npd,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos
+  allpfets     pfet,ppu,scpfet,mvpfet,pfethvt,pfetlvt
+  allfets      allnfets,allpfets,varactor,mvvaractor,varhvt
+
+  allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
+  allnactive       allnactivenonfet,allnfets
+  allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
+  allnactivetap    *nsd,*mvnsd,var,varhvt,mvvar
+
+  allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
+  allpactive       allpactivenonfet,allpfets
+  allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
+  allpactivetap    *psd,*mvpsd
+
+  allactivenonfet  allnactivenonfet,allpactivenonfet
+  allactive    allactivenonfet,allfets
+
+  allactiveres     ndiffres,pdiffres,mvndiffres,mvpdiffres
+
+  allndifflv       *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
+  allpdifflv       *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,pfetlvt,pfethvt
+  alldifflv        allndifflv,allpdifflv
+  allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
+  allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
+  alldifflvnonfet  allndifflvnonfet,allpdifflvnonfet
+
+  allndiffmv       *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
+  allpdiffmv       *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet
+  alldiffmv        allndiffmv,allpdiffmv
+  allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
+  allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet
+  alldiffmvnontap  allndiffmvnontap,allpdiffmvnontap
+  allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
+  allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
+  alldiffmvnonfet  allndiffmvnonfet,allpdiffmvnonfet
+
+  alldiffnonfet    alldifflvnonfet,alldiffmvnonfet
+  alldiff      alldifflv,alldiffmv
+
+  allpolyres       mrp1,xhrpoly,uhrpoly,rmp
+  allpolynonfet    *poly,allpolyres,xpc
+  allpolynonres    *poly,allfets,xpc
+
+  allpoly      allpolynonfet,allfets
+  allpolynoncap    *poly,xpc,allfets,allpolyres
+
+  allndiffcontlv   ndc,nsc,ndic,nndic,ndilvtc
+  allpdiffcontlv   pdc,psc,pdic,pdilvtc,pdihvtc
+  allndiffcontmv   mvndc,mvnsc,mvndic
+  allpdiffcontmv   mvpdc,mvpsc,mvpdic
+  allndiffcont     allndiffcontlv,allndiffcontmv
+  allpdiffcont     allpdiffcontlv,allpdiffcontmv
+  alldiffcontlv    allndiffcontlv,allpdiffcontlv
+  alldiffcontmv    allndiffcontmv,allpdiffcontmv
+  alldiffcont      alldiffcontlv,alldiffcontmv
+
+  allcont   alldiffcont,pc
+
+  allres    allpolyres,allactiveres
+
+  allli     *locali,coreli,rli
+  allm1     *m1,rm1
+  allm2     *m2,rm2
+  allm3     *m3,rm3
+  allm4     *m4,rm4
+  allm5     *m5,rm5
+
+  allpad    padl
+
+  psub      pwell
+  
+end
+
+#-----------------------------------------------------
+# Layer drawing styles
+#-----------------------------------------------------
+
+styles
+ styletype mos
+  dnwell    cwell
+  nwell     nwell
+  pwell     pwell
+  rpwell    pwell   ptransistor_stripes
+  ndiff     ndiffusion
+  pdiff     pdiffusion
+  nsd       ndiff_in_nwell
+  psd       pdiff_in_pwell
+  nfet      ntransistor    ntransistor_stripes
+  scnfet    ntransistor    ntransistor_stripes
+  npass     ntransistor    ntransistor_stripes
+  npd       ntransistor    ntransistor_stripes
+  pfet      ptransistor    ptransistor_stripes
+  scpfet    ptransistor    ptransistor_stripes
+  ppu       ptransistor    ptransistor_stripes
+  var       polysilicon    ndiff_in_nwell
+  ndc       ndiffusion     metal1  contact_X'es
+  pdc       pdiffusion     metal1  contact_X'es
+  nsc       ndiff_in_nwell metal1  contact_X'es
+  psc       pdiff_in_pwell metal1  contact_X'es
+
+  pfetlvt   ptransistor ptransistor_stripes implant1
+  pfethvt   ptransistor ptransistor_stripes implant2
+  nfetlvt   ntransistor ntransistor_stripes implant1
+  nsonos    ntransistor implant3
+  varhvt    polysilicon ndiff_in_nwell implant2
+
+  mvndiff   ndiffusion     hvndiff_mask
+  mvpdiff   pdiffusion     hvpdiff_mask
+  mvnsd     ndiff_in_nwell hvndiff_mask
+  mvpsd     pdiff_in_pwell hvpdiff_mask
+  mvnfet    ntransistor    ntransistor_stripes hvndiff_mask
+  mvnnfet   ntransistor    ndiff_in_nwell hvndiff_mask
+  mvpfet    ptransistor    ptransistor_stripes
+  mvvar     polysilicon    ndiff_in_nwell hvndiff_mask
+  mvndc     ndiffusion     metal1  contact_X'es hvndiff_mask
+  mvpdc     pdiffusion     metal1  contact_X'es hvpdiff_mask
+  mvnsc     ndiff_in_nwell metal1  contact_X'es hvndiff_mask
+  mvpsc     pdiff_in_pwell metal1  contact_X'es hvpdiff_mask
+
+  poly      polysilicon 
+  pc        polysilicon    metal1  contact_X'es
+  npolyres  polysilicon    silicide_block nselect2
+  ppolyres  polysilicon    silicide_block pselect2
+  xpc       polysilicon    pselect2  metal1  contact_X'es
+  rmp       polysilicon    poly_resist_stripes
+
+  pdiode    pdiffusion     pselect2
+  ndiode    ndiffusion     nselect2
+  pdiodec   pdiffusion     pselect2 metal1 contact_X'es
+  ndiodec   ndiffusion     nselect2 metal1 contact_X'es
+
+  nndiode   ndiffusion  nselect2 implant3
+  ndiodelvt ndiffusion  nselect2 implant1
+  pdiodelvt pdiffusion  pselect2 implant1
+  pdiodehvt pdiffusion  pselect2 implant2
+  pdilvtc   pdiffusion  pselect2 implant1 metal1 contact_X'es
+  pdihvtc   pdiffusion  pselect2 implant2 metal1 contact_X'es
+  ndilvtc   ndiffusion  nselect2 implant1 metal1 contact_X'es
+
+  mvpdiode    pdiffusion     pselect2 hvpdiff_mask
+  mvndiode    ndiffusion     nselect2 hvndiff_mask
+  mvpdiodec   pdiffusion     pselect2 metal1 contact_X'es hvpdiff_mask
+  mvndiodec   ndiffusion     nselect2 metal1 contact_X'es hvndiff_mask
+  nndiodec    ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
+
+  locali    metal1
+  coreli    metal1
+  rli       metal1         poly_resist_stripes
+  lic       metal1     metal2 via1arrow
+  obsli     metal1
+  obslic    metal1     metal2 via1arrow
+
+  metal1    metal2
+  m1fill    metal2
+  rm1       metal2         poly_resist_stripes
+  obsm1     metal2
+  m2c       metal2         metal3  via2arrow
+  metal2    metal3
+  m2fill    metal3
+  rm2       metal3         poly_resist_stripes
+  obsm2     metal3
+  m3c       metal3         metal4  via3alt
+  metal3    metal4
+  m3fill    metal4
+  rm3       metal4         poly_resist_stripes
+  obsm3     metal4
+  mimcap    metal3         mems
+  mimcc     metal3         contact_X'es mems
+  mimcap2   metal4         mems
+  mim2cc    metal4         contact_X'es mems
+  via3      metal4         metal5  via4
+  metal4    metal5
+  m4fill    metal5
+  rm4       metal5         poly_resist_stripes
+  obsm4     metal5
+  via4      metal5         metal6  via5
+  metal5    metal6
+  m5fill    metal6
+  rm5       metal6         poly_resist_stripes
+  obsm5     metal6
+  mrdlc     metal6  metal7  via6
+  metalrdl  metal7
+  obsmrdl   metal7
+
+  glass     overglass
+  mrp1      poly_resist    poly_resist_stripes
+  xhrpoly   poly_resist    silicide_block
+  uhrpoly   poly_resist
+  ndiffres  ndiffusion     ndop_stripes
+  pdiffres  pdiffusion     pdop_stripes
+  mvndiffres  ndiffusion hvndiff_mask   ndop_stripes
+  mvpdiffres  pdiffusion hvpdiff_mask   pdop_stripes
+  comment   comment
+  error_p   error_waffle
+  error_s   error_waffle
+  error_ps  error_waffle
+  fillblock cwell
+
+  obswell   cwell
+  obsactive implant4
+
+  padl      metal6 via6 overglass
+
+  magnet    substrate_field_implant
+  rotate    via3alt
+  fence     via5
+end
+
+#-----------------------------------------------------
+# Special paint/erase rules
+#-----------------------------------------------------
+
+compose
+  compose  nfet  poly  ndiff
+  compose  pfet  poly  pdiff
+  compose  var   poly  nsd
+
+  compose  mvnfet  poly  mvndiff
+  compose  mvpfet  poly  mvpdiff
+  compose  mvvar   poly  mvnsd
+  
+  paint  ndc     nwell  pdc
+  paint  nfet    nwell  pfet
+  paint  scnfet  nwell  scpfet
+  paint  ndiff   nwell  pdiff
+  paint  psd     nwell  nsd
+  paint  psc     nwell  nsc
+  paint  npd     nwell  ppu
+
+  paint  pdc     pwell  ndc
+  paint  pfet    pwell  nfet
+  paint  scpfet  pwell  scnfet
+  paint  pdiff   pwell  ndiff
+  paint  nsd     pwell  psd
+  paint  nsc     pwell  psc
+  paint  ppu     pwell  npd
+
+  paint  pdc     coreli pdc
+  paint  ndc     coreli ndc
+  paint  pc  coreli pc
+  paint  nsc     coreli nsc
+  paint  psc     coreli psc
+  paint  viali   coreli viali
+
+  paint  coreli  pdc    pdc
+  paint  coreli  ndc    ndc
+  paint  coreli  pc     pc
+  paint  coreli  nsc    nsc
+  paint  coreli  psc    psc
+  paint  coreli  viali  viali
+
+  paint  m4      obsm4  m4
+  paint  m5      obsm5  m5
+end
+
+#-----------------------------------------------------
+# Electrical connectivity
+#-----------------------------------------------------
+
+connect
+  *nwell,*nsd,*mvnsd,dnwell *nwell,*nsd,*mvnsd,dnwell
+  pwell,*psd,*mvpsd  pwell,*psd,*mvpsd
+  *li,coreli    *li,coreli
+  *m1,m1fill    *m1,m1fill
+  *m2,m2fill    *m2,m2fill
+  *m3,m3fill    *m3,m3fill
+  *m4,m4fill    *m4,m4fill
+  *m5,m5fill    *m5,m5fill
+  *mimcap     *mimcap
+  *mimcap2    *mimcap2
+   allnactivenonfet allnactivenonfet
+   allpactivenonfet allpactivenonfet
+  *poly,xpc,allfets *poly,xpc,allfets
+  # RDL connects to m5 (i.e., padl) through glass cut
+  *mrdl         *mrdl
+  glass         metrdl
+end
+
+#-----------------------------------------------------
+# CIF/GDS output layer definitions
+#-----------------------------------------------------
+# NOTE:  All values in this section MUST be multiples of 25 
+# or else magic will scale below the allowed layout grid size
+
+cifoutput
+
+#----------------------------------------------------------------
+style gdsii
+# NOTE: This section is used for actual GDS output
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#----------------------------------------------------------------
+# Create a temp layer from the cell bounding box for use in
+# generating ID layers.  Note that "boundary", unlike "bbox",
+# requires the FIXED_BBOX property (abutment box) in the cell.
+#----------------------------------------------------------------
+ templayer CELLBOUND
+    boundary
+
+#----------------------------------------------------------------
+# BOUND
+#----------------------------------------------------------------
+ layer  BOUND CELLBOUND
+    calma 81 4
+
+# Create a boundary outside of an abutment box, so that layers
+# can be made to stretch to the abutment box edges.  First strink
+# so that any box that would be so small as to interact with
+# itself will be removed.
+
+ templayer CELLRING CELLBOUND
+    shrink 345
+    grow 545
+    and-not CELLBOUND
+
+#----------------------------------------------------------------
+# DNWELL
+#----------------------------------------------------------------
+
+ layer DNWELL   dnwell
+    calma   64 18
+
+ layer PWRES    rpw
+    and dnwell
+    calma   64 13
+
+#----------------------------------------------------------------
+# NWELL
+#----------------------------------------------------------------
+
+ layer NWELL    allnwell
+    bloat-all rpw dnwell
+    and-not rpw,pwell
+    calma   64 20
+
+ layer WELLTXT
+    labels allnwell noport
+    calma 64 16
+
+ layer WELLPIN
+    labels allnwell port
+    calma 64 5
+
+#----------------------------------------------------------------
+# SUB (text/port only)
+#----------------------------------------------------------------
+
+ layer SUBTXT
+    labels pwell noport
+    calma 122 16
+
+ layer SUBPIN
+    labels pwell port
+    calma 64 59
+
+#----------------------------------------------------------------
+# DIFF
+#----------------------------------------------------------------
+
+ layer DIFF     allnactivenontap,allpactivenontap,allactiveres
+    labels  allnactivenontap,allpactivenontap
+    calma   65 20
+
+#----------------------------------------------------------------
+# TAP
+#----------------------------------------------------------------
+
+ layer TAP  allnactivetap,allpactivetap
+    labels  allnactivetap,allpactivetap
+    calma   65 44
+
+#----------------------------------------------------------------
+# PPLUS, NPLUS (PSDM, NSDM)
+#----------------------------------------------------------------
+
+ templayer basePPLUS pdiffres,mvpdiffres
+    grow    15
+    or  xhrpoly,uhrpoly,xpc
+    grow    110
+    bloat-or allpactivetap * 125 allnactivenontap 0
+    bloat-or allpactivenontap * 125 allnactivetap 0
+    bridge  380 380
+
+ templayer extendPPLUS  basePPLUS,CELLRING
+    grow    185
+    shrink  185
+    and-not CELLRING
+
+ layer PPLUS basePPLUS,extendPPLUS 
+    close   265000
+    calma   94 20
+
+ templayer baseNPLUS ndiffres,mvndiffres
+    grow    125
+    bloat-or allnactivetap * 125 allpactivenontap 0
+    bloat-or allnactivenontap * 125 allpactivetap 0
+    bridge  380 380
+
+ templayer extendNPLUS  baseNPLUS,CELLRING
+    grow    185
+    shrink  185
+    and-not CELLRING
+
+ layer NPLUS baseNPLUS,extendNPLUS
+    close   265000
+    calma   93 44
+
+#----------------------------------------------------------------
+# LVTN
+#----------------------------------------------------------------
+
+ layer LVTN  pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
+        grow 180
+    bridge  380 380
+    grow    185
+    shrink  185
+    close  265000
+    calma 125 44
+
+#----------------------------------------------------------------
+# HVTP
+#----------------------------------------------------------------
+
+ layer HVTP pfethvt,varhvt,*pdiodehvt
+        grow 180
+    bridge  380 380
+    grow    185
+    shrink  185
+    close 265000
+    calma 78 44
+
+#----------------------------------------------------------------
+# SONOS
+#----------------------------------------------------------------
+
+ layer SONOS nsonos
+    grow 100
+    grow-min 410
+    bridge 500 410
+    grow 250
+    shrink 250
+    calma 80 20
+
+#----------------------------------------------------------------
+# SONOS requires COREID around area (areaid.ce).  Also, the
+# coreli layer indicates a cell needing COREID.  Also, devices
+# npd, npass, and ppu indicate a COREID cell.
+#----------------------------------------------------------------
+
+ layer COREID
+    bloat-all nsonos,coreli,ppu,npd,npass CELLBOUND
+    calma 81 2
+
+#----------------------------------------------------------------
+# STDCELL applies to all cells containing scnfet or scpfet.
+#----------------------------------------------------------------
+
+ layer STDCELL scnfet
+    bloat-all scpfet,scnfet CELLBOUND
+    calma 81 4
+
+#----------------------------------------------------------------
+# RPM
+#----------------------------------------------------------------
+
+ layer RPM
+    bloat-all xhrpoly xpc
+    grow 200
+    grow-min 1270
+    grow 420
+    shrink 420
+    calma 86 20
+
+#----------------------------------------------------------------
+# URPM (2kOhms/sq. poly implant)
+#----------------------------------------------------------------
+
+ layer URPM
+    bloat-all uhrpoly xpc
+    grow 200
+    grow-min 1270
+    grow 420
+    shrink 420
+    calma 79 20
+
+#----------------------------------------------------------------
+# LDNTM (Tip implant for SONOS FETs)
+#----------------------------------------------------------------
+
+ layer LDNTM
+    bloat-all nsonos *ndiff
+    grow 185
+    grow    345
+    shrink  345
+    calma 11 44
+
+#----------------------------------------------------------------
+# HVNTM (Tip implant for MV ndiff devices)
+#----------------------------------------------------------------
+
+ templayer hvntm_block *mvpsd
+    grow 185
+
+ layer HVNTM
+    bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
+    bloat-all mvvaractor *mvnsd
+    and-not hvntm_block
+        grow 185
+    grow    345
+    shrink  345
+    calma 125 20
+
+#----------------------------------------------------------------
+# POLY
+#----------------------------------------------------------------
+
+ layer POLY     allpoly
+    calma   66 20
+
+ layer POLYTXT
+    labels  allpoly noport
+    calma   66 16
+
+ layer POLYPIN
+    labels  allpoly port
+    calma   66 5
+
+#----------------------------------------------------------------
+# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26)
+#----------------------------------------------------------------
+
+ templayer baseTHKOX    *mvpsd
+    grow-min 470
+    or alldiffmv,mvvar
+    grow    185
+        bloat-all alldiffmv nwell
+    grow-min 600
+    bridge  700 600
+
+ templayer extendTHKOX  baseTHKOX,CELLRING
+    grow    345
+    shrink  345
+    and-not CELLRING
+
+ layer THKOX    baseTHKOX,extendTHKOX
+    calma   75 20
+
+#----------------------------------------------------------------
+# CONT (LICON)
+#----------------------------------------------------------------
+
+ layer CONT allcont
+    squares-grid 0 170 170
+    calma   66 44
+
+ # Contact for pres is different than other LICON contacts
+ # See rules LICON 1b, 1c (width/length) and 2b (spacing)
+ templayer xpc_horiz xpc
+    shrink 1007
+    grow 1007
+
+ layer CONT xpc
+    and-not xpc_horiz
+    # Force long edge vertical for contacts narrower than 2um
+    # Minimum space is 350 but 520 satisfies no. of contacts rule
+    slots 80 190 520 80 2000 350
+    calma   66 44
+
+ layer CONT xpc
+    and xpc_horiz
+    # Force long edge vertical for contacts wider than 2um
+    # Minimum space is 350 but 520 satisfies no. of contacts rule
+    slots 80 2000 350 80 190 520
+    calma   66 44
+
+#----------------------------------------------------------------
+# NPC (Nitride poly cut)
+# surrounds CONT (LICON) on poly only (i.e., pc)
+#----------------------------------------------------------------
+
+ layer NPC pc
+    squares-grid 0 170 170
+    grow 100
+    bridge 270 270
+    grow 130
+    shrink 130
+    calma  95 20
+
+ # NPC is also generated on xhrpoly and uhrpoly resistors
+
+ layer NPC xpc,xhrpoly,uhrpoly
+        # xpc surrounds precision_resistor by 0.095um
+    grow 95
+    grow 130
+    shrink 130
+    calma  95 20
+
+#----------------------------------------------------------------
+# Device markers
+#----------------------------------------------------------------
+
+ layer DIFFRES rdn,mvrdn,rdp,mvrdp
+    calma 65 13
+
+ layer POLYRES mrp1
+    calma 66 13
+
+ # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
+ layer POLYSHORT rmp
+    calma 66 15
+
+ # POLYRES extends to edge of contact cut
+ layer POLYRES xhrpoly,uhrpoly
+    grow 60
+    and xpc
+    or xhrpoly,uhrpoly
+    calma 66 13
+
+ layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
+        # To be done:  Expand to include anode, cathode, and guard ring
+    calma 81 23
+
+#----------------------------------------------------------------
+# LI
+#----------------------------------------------------------------
+ layer LI allli
+    calma 67 20
+
+ layer LITXT
+    labels *locali,coreli noport
+    calma 67 16
+
+ layer LIPIN
+    labels *locali,coreli port
+    calma 67 5
+
+ layer LIRES rli
+    labels rli
+    calma 67 13
+
+#----------------------------------------------------------------
+# MCON
+#----------------------------------------------------------------
+ layer MCON lic
+    squares-grid 0 170 190
+    calma   67 44
+
+#----------------------------------------------------------------
+# MET1
+#----------------------------------------------------------------
+ layer MET1     allm1,m1fill
+    calma   68 20
+
+ layer MET1TXT
+    labels  allm1 noport
+    calma   68 16
+
+ layer MET1PIN
+    labels  allm1 port
+    calma   68 5
+
+ layer MET1RES rm1
+    labels rm1
+    calma 68 13
+
+#----------------------------------------------------------------
+# VIA1
+#----------------------------------------------------------------
+ layer VIA1     via1
+    squares-grid 55 150 170
+    calma   68 44
+
+#----------------------------------------------------------------
+# MET2
+#----------------------------------------------------------------
+ layer MET2     allm2,m2fill
+    calma   69 20
+
+ layer MET2TXT
+    labels  allm2 noport
+    calma   69 16
+
+ layer MET2PIN
+    labels  allm2 port
+    calma   69 5
+
+ layer MET2RES rm2
+    labels rm2
+    calma 69 13
+
+#----------------------------------------------------------------
+# VIA2
+#----------------------------------------------------------------
+ layer VIA2     via2
+    squares-grid 40 200 200
+    calma   69 44
+
+#----------------------------------------------------------------
+# MET3
+#----------------------------------------------------------------
+ layer MET3     allm3,m3fill
+    calma   70 20
+
+ layer MET3TXT
+    labels  allm3 noport
+    calma   70 16 
+
+ layer MET3PIN
+    labels  allm3 port
+    calma   70 5
+
+ layer MET3RES rm3
+    labels rm3
+    calma 70 13
+
+#----------------------------------------------------------------
+# VIA3
+#----------------------------------------------------------------
+ layer VIA3 via3
+    or mimcc
+    squares-grid 60 200 200
+    calma   70 44
+
+#----------------------------------------------------------------
+# MET4
+#----------------------------------------------------------------
+ layer MET4     allm4,m4fill
+    calma   71 20
+
+ layer MET4TXT
+    labels  allm4 noport
+    calma   71 16
+
+ layer MET4PIN
+    labels  allm4 port
+    calma   71 5
+
+ layer MET4RES rm4
+    labels rm4
+    calma 71 13
+
+#----------------------------------------------------------------
+# VIA4
+#----------------------------------------------------------------
+ layer VIA4 via4
+    or mim2cc
+    squares-grid 190 800 800
+    calma   71 44
+
+#----------------------------------------------------------------
+# MET5
+#----------------------------------------------------------------
+ layer MET5     allm5,m5fill
+    calma   72 20
+
+ layer MET5TXT
+    labels  allm5 noport
+    calma   72 16
+
+ layer MET5PIN
+    labels  allm5 port
+    calma   72 5
+
+ layer MET5RES rm5
+    labels rm5
+    calma 72 13
+
+
+#----------------------------------------------------------------
+# RDL
+#----------------------------------------------------------------
+  layer RDL *metrdl
+    calma   74 20
+
+  layer RDLTXT
+    labels  *metrdl noport
+    calma   74 16
+
+  layer RDLPIN
+    labels  *metrdl port
+    calma   74 5
+
+
+#----------------------------------------------------------------
+# GLASS
+#----------------------------------------------------------------
+ layer GLASS    glass
+    calma   76 20
+
+#----------------------------------------------------------------
+# CAPM
+#----------------------------------------------------------------
+ layer CAPM     *mimcap
+    labels  mimcap
+    calma   89 44
+
+ layer CAPM2    *mimcap2
+    labels  mimcap2
+    calma   97 44
+
+#----------------------------------------------------------------
+# Chip top level marker for DRC latchup rules to check 15um
+# distance to taps (otherwise 6um is used)
+#----------------------------------------------------------------
+
+ layer LOWTAPDENSITY
+    bbox top
+    # Clear 200um for pads + 50um for required high tap density
+    # in critical area.
+    shrink 250000
+    calma   81 14
+
+#----------------------------------------------------------------
+# FILLBLOCK
+#----------------------------------------------------------------
+ layer FILLOBSM1 fillblock
+    calma   62 24
+
+ layer FILLOBSM2 fillblock
+    calma   105 52
+
+ layer FILLOBSM3 fillblock
+    calma   107 24
+
+ layer FILLOBSM4 fillblock
+    calma   112 4
+
+ render DNWELL  cwell       -0.1    0.1
+ render NWELL   nwell        0.0    0.2062
+ render DIFF    ndiffusion   0.2062 0.12
+ render TAP pdiffusion   0.2062 0.12
+ render POLY    polysilicon  0.3262 0.18
+ render CONT    via          0.5062 0.43
+ render LI  metal1       0.9361 0.10
+ render MCON    via          1.0361 0.34
+ render MET1    metal2       1.3761 0.36
+ render VIA1    via          1.7361 0.27
+ render MET2    metal3       2.0061 0.36
+ render VIA2    via          2.3661 0.42
+ render MET3    metal4       2.7861 0.845
+ render VIA3    via          3.6311 0.39
+ render MET4    metal5       4.0211 0.845
+ render VIA4    via          4.8661 0.505
+ render MET5    metal6       5.3711 1.26
+ render CAPM    metal8       2.4661 0.2
+ render CAPM2   metal9       3.7311 0.2
+ render RDL metal7      11.8834 4.0
+
+#----------------------------------------------------------------
+style drc
+#----------------------------------------------------------------
+# NOTE:  This style is used for DRC only, not for GDS output
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+
+ # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
+ templayer dnwell_shrink dnwell
+ shrink 1030
+
+ templayer nwell_missing dnwell
+ grow 400
+ and-not dnwell_shrink
+ and-not nwell
+
+ # SONOS nFET devices must be in deep nwell
+ templayer dnwell_missing nsonos
+ and-not dnwell
+
+ # Define MiM cap bottom plate for spacing rule
+ templayer mim_bottom
+ bloat-all *mimcap *metal3
+
+ # Define MiM2 cap bottom plate for spacing rule
+ templayer mim2_bottom
+ bloat-all *mimcap2 *metal4
+
+ # Note that metal fill is performed by the foundry and so is not
+ # an option for a cifoutput style.
+
+ # Check latchup rule (15um minimum from tap LICON center to any
+ # non-tap diffusion.  Note that to count as a tap, the diffusion
+ # must be contacted to LI
+
+ templayer ptap_reach psc,mvpsc
+ and-not dnwell
+ # grow total is 15um.  grow in 0.84um increments to ensure that
+ # no nwell ring is crossed
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 840
+ and-not nwell,dnwell
+ grow 635
+ and-not nwell,dnwell
+
+ templayer ptap_missing *ndiff,*mvndiff
+ and-not dnwell
+ and-not ptap_reach
+
+ templayer ntap_reach nsc,mvnsc
+ # grow total is 15um.  grow in 1.27um increments to ensure that
+ # no nwell ring is crossed.  There is no difference between
+ # ntaps in and out of deep nwell.
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 1270
+ and nwell
+ grow 945
+ and nwell
+ 
+ templayer ntap_missing *pdiff,*mvpdiff
+ and-not dnwell
+ and-not ntap_reach
+
+ templayer dptap_reach psc,mvpsc
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 840
+ and-not nwell
+ and dnwell
+ grow 635
+ and-not nwell
+ and dnwell
+
+ templayer dptap_missing *ndiff,*mvndiff
+ and dnwell
+ and-not dptap_reach
+
+ templayer m1_small_hole *m1
+ close   140000
+
+ templayer m1_hole_empty m1_small_hole
+ and-not *m1
+
+ templayer m2_small_hole *m2
+ close   140000
+
+ templayer m2_hole_empty m2_small_hole
+ and-not *m2
+
+
+#----------------------------------------------------------------
+style wafflefill
+#----------------------------------------------------------------
+# Style used by scripts for automatically generating fill layers
+#----------------------------------------------------------------
+ scalefactor 10  nanometers
+ options calma-permissive-labels
+ gridlimit 5
+
+#---------------------------------------------------
+# FOM fill (under development)
+#---------------------------------------------------
+ templayer      slots_fom_pass1
+    bbox    top
+        slots   0 4080 1320 0 4080 1320 1360 0
+ templayer      obstruct_fom_pass1 alldiff,allpoly,rpw
+        grow    500
+ templayer  fomfill_pass1 slots_fom_pass1
+        and-not obstruct_fom_pass1
+        shrink  2035
+        grow    2035
+
+ templayer      slots_fom_pass2
+    bbox    top
+        slots   0 2500 1320 0 2500 1320 1360 0
+ templayer      obstruct_fom_pass2 fomfill_pass1
+        grow    820
+    or  alldiff,allpoly,rpw
+        grow    500
+ templayer  fomfill_pass2 slots_fom_pass2
+        and-not obstruct_fom_pass2
+        shrink  1245
+        grow    1245
+
+ templayer      slots_fom_coarse
+    bbox    top
+        slots   0 1500 1320 0 1500 1320 1360 0
+ templayer      obstruct_fom_coarse fomfill_pass1,fomfill_pass2
+        grow    820
+    or  alldiff,allpoly,rpw
+        grow    500
+ templayer  fomfill_coarse slots_fom_coarse
+        and-not obstruct_fom_coarse
+        shrink  745
+        grow    745
+
+ templayer      slots_fom_fine
+    bbox    top
+        slots   0 500 400 0 500 400 160 0
+ templayer      obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
+    grow    820
+    or  alldiff,allpoly,rpw
+        grow    500
+ templayer  fomfill_fine slots_fom_fine
+        and-not obstruct_fom_fine
+        shrink  245
+        grow    245
+
+ layer  FOMMASK    fomfill_pass1 
+    or  fomfill_pass2
+    or  fomfill_coarse
+    or  fomfill_fine
+    calma   23 0
+
+#---------------------------------------------------
+# POLY fill (under development)
+#---------------------------------------------------
+ templayer      slots_poly_pass1
+    bbox    top
+        slots   0 720 360 0 720 360 240 0
+ templayer      obstruct_poly_pass1 alldiff,allpoly,rpw
+        grow    1000
+ templayer  polyfill_pass1 slots_poly_pass1
+        and-not obstruct_poly_pass1
+        shrink  355
+        grow    355
+
+ templayer      slots_poly_coarse
+    bbox    top
+        slots   0 720 360 0 720 360 240 120
+ templayer      obstruct_poly_coarse alldiff,allpoly,rpw
+        grow    640
+    or  polyfill_pass1
+    grow    360
+ templayer  polyfill_coarse slots_poly_coarse
+        and-not obstruct_poly_coarse
+        shrink  355
+        grow    355
+
+ templayer      slots_poly_medium
+    bbox    top
+        slots   0 540 360 0 540 360 240 100
+ templayer      obstruct_poly_medium alldiff,allpoly,rpw
+        grow    650
+    or  polyfill_pass1,polyfill_coarse
+    grow    360
+ templayer  polyfill_medium slots_poly_medium
+        and-not obstruct_poly_medium
+        shrink  265
+        grow    265
+
+ templayer      slots_poly_fine
+    bbox    top
+        slots   0 480 360 0 480 360 240 200
+ templayer      obstruct_poly_fine alldiff,allpoly,rpw
+        grow    650
+    or  polyfill_pass1,polyfill_coarse,polyfill_medium
+    grow    360
+ templayer  polyfill_fine slots_poly_fine
+        and-not obstruct_poly_fine
+        shrink  235
+        grow    235
+
+ layer  POLYMASK    polyfill_pass1 
+    or  polyfill_coarse
+    or  polyfill_medium
+    or  polyfill_fine
+    calma   28 0
+
+#---------------------------------------------------
+# MET1 fill
+#---------------------------------------------------
+ templayer      slots_m1_coarse
+        bbox    top
+        slots   0 2000 200 0 2000 200 700 0
+ templayer      obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock
+        grow    3000
+ templayer  met1fill_coarse slots_m1_coarse
+        and-not obstruct_m1_coarse
+        shrink  995
+        grow    995
+
+ templayer      slots_m1_medium
+        bbox    top
+        slots   0 1000 200 0 1000 200 700 0
+ templayer      obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock
+        grow    2800
+    or  met1fill_coarse
+        grow    200
+ templayer  met1fill_medium slots_m1_medium
+        and-not obstruct_m1_medium
+        shrink  495
+        grow    495
+
+ templayer      slots_m1_fine
+        bbox    top
+        slots   0 580 200 0 580 200 700 0
+ templayer      obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock
+        grow    300
+    or  met1fill_coarse,met1fill_medium
+        grow    200
+ templayer  met1fill_fine slots_m1_fine
+        and-not obstruct_m1_fine
+        shrink  285
+        grow    285
+
+ templayer      slots_m1_veryfine
+        bbox    top
+        slots   0 300 200 0 300 200 100 50
+ templayer      obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock
+        grow    100
+    or  met1fill_coarse,met1fill_medium,met1fill_fine
+        grow    200
+ templayer  met1fill_veryfine slots_m1_veryfine
+        and-not obstruct_m1_veryfine
+        shrink  145
+        grow    145
+
+ layer  MET1MASK met1fill_coarse
+    or  met1fill_medium
+    or  met1fill_fine
+    or  met1fill_veryfine
+    calma   36 0
+
+#---------------------------------------------------
+# MET2 fill
+#---------------------------------------------------
+ templayer      slots_m2_coarse
+        bbox    top
+        slots   0 2000 200 0 2000 200 700 350
+ templayer      obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock
+        grow    3000
+ templayer  met2fill_coarse slots_m2_coarse
+        and-not obstruct_m2
+        shrink  995
+        grow    995
+
+ templayer      slots_m2_medium
+        bbox    top
+        slots   0 1000 200 0 1000 200 700 350
+ templayer      obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock
+        grow    2800
+    or  met2fill_coarse
+        grow    200
+ templayer  met2fill_medium slots_m2_medium
+        and-not obstruct_m2_medium
+        shrink  495
+        grow    495
+
+ templayer      slots_m2_fine
+        bbox    top
+        slots   0 580 200 0 580 200 700 350
+ templayer      obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock
+        grow    300
+    or  met2fill_coarse,met2fill_medium
+        grow    200
+ templayer  met2fill_fine slots_m2_fine
+        and-not obstruct_m2_fine
+        shrink  285
+        grow    285
+
+ templayer      slots_m2_veryfine
+        bbox    top
+        slots   0 300 200 0 300 200 100 100
+ templayer      obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock
+        grow    100
+    or  met2fill_coarse,met2fill_medium,met2fill_fine
+        grow    200
+ templayer  met2fill_veryfine slots_m2_veryfine
+        and-not obstruct_m2_veryfine
+        shrink  145
+        grow    145
+
+ layer  MET2MASK met2fill_coarse
+    or met2fill_medium
+    or met2fill_fine
+    or met2fill_veryfine
+    calma   41 0
+
+#---------------------------------------------------
+# MET3 fill
+#---------------------------------------------------
+ templayer      slots_m3_coarse
+        bbox    top
+        slots   0 2000 300 0 2000 300 700 700
+ templayer      obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock
+        grow    3000
+ templayer  met3fill_coarse slots_m3_coarse
+        and-not obstruct_m3
+        shrink  995
+        grow    995
+
+ templayer      slots_m3_medium
+        bbox    top
+        slots   0 1000 300 0 1000 300 700 700
+ templayer      obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock
+        grow    2700
+    or  met3fill_coarse
+        grow    300
+ templayer  met3fill_medium slots_m3_medium
+        and-not obstruct_m3_medium
+        shrink  495
+        grow    495
+
+ templayer      slots_m3_fine
+        bbox    top
+        slots   0 580 300 0 580 300 700 700
+ templayer      obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock
+        grow    200
+    or  met3fill_coarse,met3fill_medium
+        grow    300
+ templayer  met3fill_fine slots_m3_fine
+        and-not obstruct_m3_fine
+        shrink  285
+        grow    285
+
+ templayer      slots_m3_veryfine
+        bbox    top
+        slots   0 400 300 0 400 300 150 200
+ templayer      obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock
+    or  met3fill_coarse,met3fill_medium,met3fill_fine
+        grow    300
+ templayer  met3fill_veryfine slots_m3_veryfine
+        and-not obstruct_m3_veryfine
+        shrink  195
+        grow    195
+
+ layer  MET3MASK met3fill_coarse
+    or  met3fill_medium
+    or  met3fill_fine
+    or  met3fill_veryfine
+    calma   34 0
+
+#---------------------------------------------------
+# MET4 fill
+#---------------------------------------------------
+ templayer      slots_m4_coarse
+        bbox    top
+        slots   0 2000 300 0 2000 300 700 1050
+ templayer      obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock
+        grow    3000
+ templayer  met4fill_coarse slots_m4_coarse
+        and-not obstruct_m4
+        shrink  995
+        grow    995
+
+ templayer      slots_m4_medium
+        bbox    top
+        slots   0 1000 300 0 1000 300 700 1050
+ templayer      obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock
+        grow    2700
+    or  met4fill_coarse
+        grow    300
+ templayer  met4fill_medium slots_m4_medium
+        and-not obstruct_m4_medium
+        shrink  495
+        grow    495
+
+ templayer      slots_m4_fine
+        bbox    top
+        slots   0 580 300 0 580 300 700 1050
+ templayer      obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock
+        grow    200
+    or  met4fill_coarse,met4fill_medium
+        grow    300
+ templayer  met4fill_fine slots_m4_fine
+        and-not obstruct_m4_fine
+        shrink  285
+        grow    285
+
+ templayer      slots_m4_veryfine
+        bbox    top
+        slots   0 400 300 0 400 300 150 300
+ templayer      obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock
+    or  met4fill_coarse,met4fill_medium,met4fill_fine
+        grow    300
+ templayer  met4fill_veryfine slots_m4_veryfine
+        and-not obstruct_m4_veryfine
+        shrink  195
+        grow    195
+
+ layer  MET4MASK met4fill_coarse
+    or  met4fill_medium
+    or  met4fill_fine
+    or  met4fill_veryfine
+    calma   51 0
+
+#---------------------------------------------------
+# MET5 fill
+#---------------------------------------------------
+ templayer      slots_m5
+        bbox    top
+        slots   0 3000 1600 0 3000 1600 1000 100
+ templayer      obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
+        grow    3000
+ templayer  met5fill_gen slots_m5
+        and-not obstruct_m5
+        shrink  1495
+        grow    1495
+
+ layer  MET5MASK met5fill_gen
+    calma   59 0
+
+end
+
+#-----------------------------------------------------------------------
+cifinput
+#-----------------------------------------------------------------------
+# NOTE:  All values in this section MUST be multiples of 25 
+# or else magic will scale below the allowed layout grid size
+#-----------------------------------------------------------------------
+
+style  vendorimport
+ scalefactor 10 nanometers
+ gridlimit 5
+
+ options ignore-unknown-layer-labels no-reconnect-labels
+
+ ignore NPC
+ ignore SEALID
+ ignore NPNID
+ ignore PNPID
+ ignore CAPID
+ ignore LDNTM
+ ignore HVNTM
+ ignore POLYMOD
+ ignore LOWTAPDENSITY
+
+ layer nwell NWELL,WELLTXT,WELLPIN
+ labels NWELL
+ labels WELLTXT text
+ labels WELLPIN port
+
+ layer pwell SUBTXT,SUBPIN
+ labels SUBTXT text
+ labels SUBPIN port
+
+ layer dnwell DNWELL
+ labels DNWELL
+
+ layer rpw PWRES
+ and DNWELL
+ labels PWRES
+
+ templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not DIODE
+ and-not DIFFRES
+ and-not THKOX
+ and NPLUS
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+ labels TAPPIN port
+
+ layer ndiff ndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer xndifcheck ndifcheck
+ copyup ndifcheck
+
+ templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and-not NWELL
+ and-not PPLUS
+ and-not DIODE
+ and-not DIFFRES
+ and THKOX
+ and NPLUS
+ copyup ndifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvndiff mvndiffarea
+
+ # Copy ndiff areas up for contact checks
+ templayer mvxndifcheck mvndifcheck
+ copyup mvndifcheck
+
+ layer ndiode DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and-not LVTN
+ labels DIFF
+
+ layer ndiodelvt DIFF
+ and NPLUS
+ and DIODE
+ and-not NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and LVTN
+ labels DIFF
+
+ templayer ndiodearea DIODE
+ and NPLUS
+ and-not THKOX
+ and-not NWELL
+ copyup DIODE,NPLUS
+
+ layer ndiffres DIFFRES
+ and NPLUS
+ and-not THKOX
+ labels DIFF
+
+ templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and-not DIODE
+ and-not THKOX
+ and PPLUS
+ copyup pdifcheck
+ labels DIFF 
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer pdiff pdiffarea
+
+ layer mvndiode DIFF
+ and NPLUS
+ and DIODE
+ and THKOX
+ and-not POLY
+ and-not PPLUS
+ and-not LVTN
+ labels DIFF
+
+ layer nndiode DIFF
+ and NPLUS
+ and DIODE
+ and THKOX
+ and-not POLY
+ and-not PPLUS
+ and LVTN
+ labels DIFF
+
+ templayer mvndiodearea DIODE
+ and NPLUS
+ and THKOX
+ and-not NWELL
+ copyup DIODE,NPLUS
+
+ layer mvndiffres DIFFRES
+ and NPLUS
+ and THKOX
+ labels DIFF
+
+ templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
+ and-not POLY
+ and NWELL
+ and-not NPLUS
+ and THKOX
+ and-not DIODE
+ and-not DIFFRES
+ and PPLUS
+ copyup mvpdifcheck
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvpdiff mvpdiffarea
+
+ # Copy pdiff areas up for contact checks
+ templayer xpdifcheck pdifcheck
+ copyup pdifcheck
+
+ layer pdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodelvt DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and LVTN
+ and-not HVTP
+ and DIODE
+ labels DIFF
+
+ layer pdiodehvt DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and HVTP
+ and DIODE
+ labels DIFF
+
+ templayer pdiodearea DIODE
+ and PPLUS
+ and-not THKOX
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff, regardless of the presence of a well.
+
+ templayer pfetarea DIFF
+ and-not NPLUS
+ and-not THKOX
+ and POLY
+
+ layer pfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and-not STDCELL
+ and-not COREID
+ labels DIFF
+
+ layer scpfet pfetarea
+ and-not LVTN
+ and-not HVTP
+ and STDCELL
+ labels DIFF
+
+ layer ppu pfetarea
+ and-not LVTN
+ and-not HVTP
+ and COREID
+ labels DIFF
+
+ layer pfetlvt pfetarea
+ and LVTN
+ labels DIFF
+
+ layer pfethvt pfetarea
+ and HVTP
+ labels DIFF
+
+ # Always force nwell under pfet (nwell encloses pdiff by 0.18)
+ layer nwell pfetarea
+ grow 180
+
+ # Copy mvpdiff areas up for contact checks
+ templayer mvxpdifcheck mvpdifcheck
+ copyup mvpdifcheck
+
+ layer mvpdiode DIFF
+ and PPLUS
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+ and DIODE
+ labels DIFF
+
+ templayer mvpdiodearea DIODE
+ and PPLUS
+ and THKOX
+ copyup DIODE,PPLUS
+
+ # Define pfet areas as known pdiff,
+ # regardless of the presence of a
+ # well.
+
+ templayer mvpfetarea DIFF
+ and-not NPLUS
+ and THKOX
+ and POLY
+
+ layer mvpfet mvpfetarea
+ labels DIFF
+
+ layer pdiff DIFF,DIFFTXT,DIFFPIN
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and-not DIODE
+ and-not DIFFRES
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer pdiffres DIFFRES
+ and PPLUS
+ and NWELL
+ and-not THKOX
+ labels DIFF
+
+ layer nfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not SONOS
+ and-not STDCELL
+ labels DIFF
+
+ layer scnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not NWELL
+ and-not THKOX
+ and-not LVTN
+ and-not SONOS
+ and STDCELL
+ labels DIFF
+
+ layer npd DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not NWELL
+ and COREID
+ labels DIFF
+
+ # layer npass DIFF
+ # and POLY
+ # and-not PPLUS
+ # and NPLUS
+ # and-not NWELL
+ # and COREID
+ # labels DIFF
+
+ layer nfetlvt DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and LVTN
+ and-not SONOS
+ labels DIFF
+
+ layer nsonos DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not THKOX
+ and LVTN
+ and SONOS
+ labels DIFF
+
+ templayer nsdarea TAP
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ copyup nsubcheck
+
+ layer nsd nsdarea
+ labels TAP
+
+ layer nsd TAP,TAPPIN
+ and NPLUS
+ and-not POLY
+ and-not THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer nsdexpand nsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer xnsubcheck nsubcheck
+ copyup nsubcheck
+
+ templayer psdarea TAP
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not pfetexpand
+ copyup psubcheck
+
+ layer psd psdarea
+ labels TAP
+
+ layer psd TAP,TAPPIN
+ and PPLUS
+ and-not POLY
+ and-not THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer psdexpand psdarea
+ grow 500
+
+ layer mvpdiff DIFF,DIFFTXT,DIFFPIN
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and mvpfetexpand
+ labels DIFF
+ labels DIFFTXT text
+ labels DIFFPIN port
+
+ layer mvpdiffres DIFFRES
+ and PPLUS
+ and NWELL
+ and THKOX
+ and-not mvrdpioedge
+ labels DIFF
+
+ layer mvnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and-not LVTN
+ and THKOX
+ labels DIFF
+
+ layer mvnnfet DIFF
+ and POLY
+ and-not PPLUS
+ and NPLUS
+ and LVTN
+ and THKOX
+ labels DIFF
+
+ templayer mvnsdarea TAP
+ and NPLUS
+ and NWELL
+ and-not POLY
+ and-not PPLUS
+ and THKOX
+ copyup mvnsubcheck
+
+ layer mvnsd mvnsdarea
+ labels TAP
+
+ layer mvnsd TAP,TAPPIN
+ and NPLUS
+ and THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer mvnsdexpand mvnsdarea
+ grow 500
+
+ # Copy nsub areas up for contact checks
+ templayer mvxnsubcheck mvnsubcheck
+ copyup mvnsubcheck
+
+ templayer mvpsdarea DIFF
+ and PPLUS
+ and-not NWELL
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+ and-not mvpfetexpand
+ copyup mvpsubcheck
+
+ layer mvpsd mvpsdarea
+ labels DIFF
+
+ layer mvpsd TAP,TAPPIN
+ and PPLUS
+ and THKOX
+ labels TAP
+ labels TAPPIN port
+
+ templayer mvpsdexpand mvpsdarea
+ grow 500
+
+ # Copy psub areas up for contact checks
+ templayer xpsubcheck psubcheck
+ copyup psubcheck
+
+ templayer mvxpsubcheck mvpsubcheck
+ copyup mvpsubcheck
+
+ layer psd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and-not pfetexpand
+ and psdexpand
+
+ layer nsd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and-not THKOX
+ and nsdexpand
+
+ layer mvpsd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and-not mvpfetexpand
+ and mvpsdexpand
+
+ layer mvnsd TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ and THKOX
+ and mvnsdexpand
+
+ templayer hresarea POLY
+ and RPM
+ grow 3000
+
+ templayer uresarea POLY
+ and URPM
+ grow 3000
+
+ templayer diffresarea DIFFRES
+ and-not THKOX
+ grow 3000
+
+ templayer mvdiffresarea DIFFRES
+ and THKOX
+ grow 3000
+
+ templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
+
+ layer pfet POLY
+ and DIFF
+ and diffresarea
+ and-not NPLUS
+ and-not STDCELL
+
+ layer scpfet POLY
+ and DIFF
+ and diffresarea
+ and-not NPLUS
+ and STDCELL
+
+ templayer xpolyterm RPM,URPM
+ and POLY
+ and-not POLYRES
+ # add back the 0.06um contact surround in the direction of the resistor
+ grow 60
+ and POLY
+
+ layer xpc xpolyterm
+
+ templayer polyarea POLY
+ and-not POLYRES
+ and-not POLYSHORT
+ and-not DIFF
+ and-not RPM
+ and-not URPM
+ copyup polycheck
+
+ layer poly polyarea,POLYTXT,POLYPIN
+ labels POLY
+ labels POLYTXT text
+ labels POLYPIN port
+
+ # Copy (non-resistor) poly areas up for contact checks
+ templayer xpolycheck polycheck
+ copyup polycheck
+
+ layer mrp1 POLY
+ and POLYRES
+ and-not RPM
+ and-not URPM
+ labels POLY
+
+ layer rmp POLY
+ and POLYSHORT
+ labels POLY
+
+ layer xhrpoly POLY
+ and POLYRES
+ and RPM
+ and-not URPM
+ and PPLUS
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ layer uhrpoly POLY
+ and POLYRES
+ and URPM
+ and-not RPM
+ and NPC
+ and-not xpolyterm
+ labels POLY
+
+ templayer ndcbase CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and LI
+ and-not THKOX
+
+ layer ndc ndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndcbase
+ labels CONT
+
+ templayer nscbase CONT
+ and DIFF,TAP
+ and NPLUS
+ and NWELL
+ and LI
+ and-not THKOX
+
+ layer nsc nscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nscbase
+ labels CONT
+
+ templayer pdcbase CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and LI
+ and-not THKOX
+
+ layer pdc pdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcbase
+ labels CONT
+
+ templayer pdcnowell CONT
+ and DIFF
+ and PPLUS
+ and pfetexpand
+ and LI
+ and-not THKOX
+
+ layer pdc pdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdcnowell
+ labels CONT
+
+ templayer pscbase CONT
+ and DIFF,TAP
+ and PPLUS
+ and-not NWELL
+ and-not pfetexpand
+ and LI
+ and-not THKOX
+
+ layer psc pscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pscbase
+ labels CONT
+
+ templayer pcbase CONT
+ and POLY
+ and-not DIFF
+ and-not RPM,URPM
+ and LI
+
+ layer pc pcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pcbase
+ labels CONT
+
+ templayer ndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and-not LVTN
+
+ layer ndic ndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndicbase
+ labels CONT
+
+ templayer ndilvtcbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not THKOX
+ and LVTN
+
+ layer ndilvtc ndilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndilvtcbase
+ labels CONT
+
+ templayer pdicbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and-not HVTP
+
+ layer pdic pdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdicbase
+ labels CONT
+
+ templayer pdilvtcbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and LVTN
+ and-not HVTP
+
+ layer pdilvtc pdilvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdilvtcbase
+ labels CONT
+
+ templayer pdihvtcbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and-not THKOX
+ and-not LVTN
+ and HVTP
+
+ layer pdihvtc pdihvtcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdihvtcbase
+ labels CONT
+
+ templayer mvndcbase CONT
+ and DIFF
+ and NPLUS
+ and-not NWELL
+ and LI
+ and THKOX
+
+ layer mvndc mvndcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndcbase
+ labels CONT
+
+ templayer mvnscbase CONT
+ and DIFF,TAP
+ and NPLUS
+ and NWELL
+ and LI
+ and THKOX
+
+ layer mvnsc mvnscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnscbase
+ labels CONT
+
+ templayer mvpdcbase CONT
+ and DIFF
+ and PPLUS
+ and NWELL
+ and LI
+ and THKOX
+
+ layer mvpdc mvpdcbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcbase
+ labels CONT
+
+ templayer mvpdcnowell CONT
+ and DIFF
+ and PPLUS
+ and mvpfetexpand
+ and MET1
+ and THKOX
+
+ layer mvpdc mvpdcnowell
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdcnowell
+ labels CONT
+
+ templayer mvpscbase CONT
+ and DIFF,TAP
+ and PPLUS
+ and-not NWELL
+ and-not mvpfetexpand
+ and LI
+ and THKOX
+
+ layer mvpsc mvpscbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpscbase
+ labels CONT
+
+ templayer mvndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and-not LVTN
+ and THKOX
+
+ layer mvndic mvndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndicbase
+ labels CONT
+
+ templayer nndicbase CONT
+ and DIFF
+ and NPLUS
+ and DIODE
+ and-not POLY
+ and-not PPLUS
+ and LVTN
+ and THKOX
+
+ layer nndic nndicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nndicbase
+ labels CONT
+
+ templayer mvpdicbase CONT
+ and DIFF
+ and PPLUS
+ and DIODE
+ and-not POLY
+ and-not NPLUS
+ and THKOX
+
+ layer mvpdic mvpdicbase
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdicbase
+ labels CONT
+
+ layer locali LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and-not COREID
+ labels LI
+ labels LITXT text
+ labels LIPIN port
+
+ layer coreli LI,LITXT,LIPIN
+ and-not LIRES,LISHORT
+ and COREID
+ labels LI
+ labels LITXT text
+ labels LIPIN port
+
+ layer rli LI
+ and LIRES,LISHORT
+ labels LIRES,LISHORT
+
+ layer lic MCON
+ grow 95
+ shrink 95
+ shrink 85
+ grow 85
+ or MCON
+ labels MCON
+
+ layer m1 MET1,MET1TXT,MET1PIN
+ and-not MET1RES,MET1SHORT
+ labels MET1
+ labels MET1TXT text
+ labels MET1PIN port
+
+ layer rm1 MET1
+ and MET1RES,MET1SHORT
+ labels MET1RES,MET1SHORT
+
+ layer m1fill MET1FILL
+ labels MET1FILL
+
+ layer mimcap MET3
+ and CAPM
+ labels CAPM
+
+ layer mimcc VIA3
+ and CAPM
+ grow 60
+ grow 40
+ shrink 40
+ labels CAPM
+
+ layer mimcap2 MET4
+ and CAPM2
+ labels CAPM2
+
+ layer mim2cc VIA4
+ and CAPM2
+ grow 190
+ grow 210
+ shrink 210
+ labels CAPM2
+
+
+ templayer m2cbase VIA1
+ grow 55
+
+ layer m2c m2cbase
+ grow 30
+ shrink 30
+ shrink 130
+ grow 130
+ or m2cbase
+
+ layer m2 MET2,MET2TXT,MET2PIN
+ and-not MET2RES,MET2SHORT
+ labels MET2
+ labels MET2TXT text
+ labels MET2PIN port
+
+ layer rm2 MET2
+ and MET2RES,MET2SHORT
+ labels MET2RES,MET2SHORT
+
+ layer m2fill MET2FILL
+ labels MET2FILL
+
+ templayer m3cbase VIA2
+ grow 40
+
+ layer m3c m3cbase
+ grow 60
+ shrink 60
+ shrink 140 
+ grow 140
+ or m3cbase
+
+ layer m3 MET3,MET3TXT,MET3PIN
+ and-not MET3RES,MET3SHORT
+ and-not CAPM
+ labels MET3
+ labels MET3TXT text
+ labels MET3PIN port
+
+ layer rm3 MET3
+ and MET3RES,MET3SHORT
+ labels MET3RES,MET3SHORT
+
+ layer m3fill MET3FILL
+ labels MET3FILL
+
+
+ templayer via3base VIA3
+ and-not CAPM
+ grow 60
+
+ layer via3 via3base
+ grow 40
+ shrink 40
+ shrink 160
+ grow 160
+ or via3base
+
+ layer m4 MET4,MET4TXT,MET4PIN
+ and-not MET4RES,MET4SHORT
+ and-not CAPM2
+ labels MET4
+ labels MET4TXT text
+ labels MET4PIN port
+
+ layer rm4 MET4
+ and MET4RES,MET4SHORT
+ labels MET4RES,MET4SHORT
+
+ layer m4fill MET4FILL
+ labels MET4FILL
+
+ layer m5 MET5,MET5TXT,MET5PIN
+ and-not MET5RES,MET5SHORT
+ labels MET5
+ labels MET5TXT text
+ labels MET5PIN port
+
+ layer rm5 MET5
+ and MET5RES,MET5SHORT
+ labels MET5RES,MET5SHORT
+
+ layer m5fill MET5FILL
+ labels MET5FILL
+
+ templayer via4base VIA4
+ and-not CAPM2
+ grow 190
+
+ layer via4 via4base
+ grow 210
+ shrink 210
+ shrink 590
+ grow 590
+ or via4base
+
+ layer metrdl RDL,RDLTXT,RDLPIN
+ labels RDL
+ labels RDLTXT text
+ labels RDLPIN port
+
+ # Find diffusion not covered in
+ # NPLUS or PPLUS and pull it into
+ # the next layer up
+
+ templayer gentrans DIFF
+ and-not PPLUS
+ and-not NPLUS
+ and POLY
+ copyup DIFF,POLY
+
+ templayer gendiff DIFF,TAP
+ and-not PPLUS
+ and-not NPLUS
+ and-not POLY
+ copyup DIFF
+
+ # Handle contacts found by copyup
+
+ templayer ndiccopy CONT
+ and LI
+ and DIODE
+ and NPLUS
+ and-not THKOX
+
+ layer ndic ndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndiccopy
+ labels CONT
+
+ templayer mvndiccopy CONT
+ and LI
+ and DIODE
+ and NPLUS
+ and THKOX
+
+ layer mvndic mvndiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndiccopy
+ labels CONT
+
+ templayer pdiccopy CONT
+ and LI
+ and DIODE
+ and PPLUS
+ and-not THKOX
+
+ layer pdic pdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdiccopy
+ labels CONT
+
+ templayer mvpdiccopy CONT
+ and LI
+ and DIODE
+ and PPLUS
+ and THKOX
+
+ layer mvpdic mvpdiccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdiccopy
+ labels CONT
+
+ templayer ndccopy CONT
+ and ndifcheck
+
+ layer ndc ndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or ndccopy
+ labels CONT
+
+ templayer mvndccopy CONT
+ and mvndifcheck
+
+ layer mvndc mvndccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvndccopy
+ labels CONT
+
+ templayer pdccopy CONT
+ and pdifcheck
+
+ layer pdc pdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pdccopy
+ labels CONT
+
+ templayer mvpdccopy CONT
+ and mvpdifcheck
+
+ layer mvpdc mvpdccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpdccopy
+ labels CONT
+
+ templayer pccopy CONT
+ and polycheck
+
+ layer pc pccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or pccopy
+ labels CONT
+
+ templayer nsccopy CONT
+ and nsubcheck
+
+ layer nsc nsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or nsccopy
+ labels CONT
+
+ templayer mvnsccopy CONT
+ and mvnsubcheck
+
+ layer mvnsc mvnsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvnsccopy
+ labels CONT
+
+ templayer psccopy CONT
+ and psubcheck
+
+ layer psc psccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or psccopy
+ labels CONT
+
+ templayer mvpsccopy CONT
+ and mvpsubcheck
+
+ layer mvpsc mvpsccopy
+ grow 85
+ shrink 85
+ shrink 85
+ grow 85
+ or mvpsccopy
+ labels CONT
+
+ # Find contacts not covered in
+ # metal and pull them into the
+ # next layer up
+ 
+ templayer gencont CONT
+ and LI
+ and-not DIFF,TAP
+ and-not POLY
+ and-not DIODE
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT,LI
+
+ templayer barecont CONT
+ and-not LI
+ and-not nsubcheck
+ and-not psubcheck
+ and-not mvnsubcheck
+ and-not mvpsubcheck
+ copyup CONT
+
+ layer glass GLASS,PADTXT,PADPIN
+ labels GLASS
+ labels PADTXT text
+ labels PADPIN port
+
+ templayer boundary BOUND,STDCELL,PADCELL
+ boundary
+
+ layer comment LVSTEXT
+ labels LVSTEXT text
+
+ layer comment TTEXT
+ labels TTEXT text
+
+ layer fillblock  FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+ labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
+
+# MOS Varactor
+
+ layer var POLY
+ and TAP
+ and NPLUS
+ and NWELL
+ and-not THKOX
+ and-not HVTP
+ # NOTE:  Else forms a varactor that is not in the vendor netlist.
+ and-not COREID
+ labels POLY
+
+ layer varhvt POLY
+ and TAP
+ and NPLUS
+ and NWELL
+ and-not THKOX
+ and HVTP
+ labels POLY
+
+ layer mvvar POLY
+ and TAP
+ and NPLUS
+ and NWELL
+ and THKOX
+ labels POLY
+
+ calma NWELL 64 20
+ calma DIFF 65 20
+ calma DNWELL 64 18
+ calma PWRES 64 13
+ calma TAP  65 44
+ # LVTN
+ calma LVTN 125 44
+ # HVTP
+ calma HVTP 78 44
+ # SONOS (TUNM)
+ calma SONOS 80 20
+ # NPLUS = NSDM
+ calma NPLUS 93 44
+ # PPLUS = PSDM
+ calma PPLUS 94 20
+ # HVI
+ calma THKOX 75 20
+ # NPC
+ calma NPC 95 20
+ # P+ POLY MASK
+ calma RPM 86 20
+ calma URPM 79 20
+ calma LDNTM 11 44
+ calma HVNTM 125 20
+ # Poly resistor ID mark
+ calma POLYRES 66 13
+ # Diffusion resistor ID mark
+ calma DIFFRES 65 13
+ calma POLY 66 20
+ calma POLYMOD 66 83
+ # Diode ID mark
+ calma DIODE 81 23
+ # Bipolar NPN mark
+ calma NPNID 82 20
+ # Bipolar PNP mark
+ calma PNPID 82 20
+ # Capacitor ID
+ calma CAPID 82 64
+ # Core area ID mark
+ calma COREID 81 2
+ # Standard cell ID mark
+ calma STDCELL 81 4
+ # Padframe cell ID mark
+ calma PADCELL 81 3
+ # Seal ring ID mark
+ calma SEALID 81 1
+ # Low tap density ID mark
+ calma LOWTAPDENSITY 81 14
+ 
+ # LICON
+ calma CONT 66 44
+ calma LI   67 20
+ calma MCON 67 44
+
+ calma MET1 68 20
+ calma VIA1 68 44
+ calma MET2 69 20
+ calma VIA2 69 44
+ calma MET3 70 20
+ calma VIA3 70 44
+ calma MET4 71 20
+ calma VIA4 71 44
+ calma MET5 72 20
+ calma RDL 74 20
+ calma GLASS 76 20
+
+ calma SUBPIN  64 59
+ calma PADPIN  76 5
+ calma DIFFPIN 65 6
+ calma TAPPIN  65 5
+ calma WELLPIN  64 5
+ calma LIPIN 67 5
+ calma POLYPIN 66 5
+ calma MET1PIN 68 5
+ calma MET2PIN 69 5
+ calma MET3PIN 70 5
+ calma MET4PIN 71 5
+ calma MET5PIN 72 5
+ calma RDLPIN 74 5
+
+ calma LIRES 67 13
+ calma MET1RES 68 13
+ calma MET2RES 69 13
+ calma MET3RES 70 13
+ calma MET4RES 71 13
+ calma MET5RES 72 13
+
+ calma MET1FILL 68 28
+ calma MET2FILL 69 28
+ calma MET3FILL 70 28
+ calma MET4FILL 71 28
+ calma MET5FILL 72 28
+
+ calma POLYSHORT 66 15
+ calma LISHORT 67 15
+ calma MET1SHORT 68 15
+ calma MET2SHORT 69 15
+ calma MET3SHORT 70 15
+ calma MET4SHORT 71 15
+ calma MET5SHORT 72 15
+
+ calma SUBTXT 122 16
+ calma PADTXT 76 16
+ calma DIFFTXT 65 16
+ calma POLYTXT 66 16
+ calma WELLTXT 64 16
+ calma LITXT 67 16
+ calma MET1TXT 68 16
+ calma MET2TXT 69 16
+ calma MET3TXT 70 16
+ calma MET4TXT 71 16
+ calma MET5TXT 72 16
+ calma RDLPIN 74 16
+
+ calma BOUND 235 4
+
+ calma LVSTEXT 83 44
+
+ calma CAPM 89 44
+ calma CAPM2 97 44
+
+ calma FILLOBSM1  62  24
+ calma FILLOBSM2  105 52
+ calma FILLOBSM3  107 24
+ calma FILLOBSM4  112 4
+
+end
+
+#-----------------------------------------------------
+# Digital flow maze router cost parameters
+#-----------------------------------------------------
+
+mzrouter
+end
+
+#-----------------------------------------------------
+# Vendor DRC rules
+#-----------------------------------------------------
+
+drc
+
+ style drc variants (fast),(full),(routing)
+
+ scalefactor 10 
+
+ cifstyle drc
+
+ variants (fast),(full)
+
+#-----------------------------
+# DNWELL
+#-----------------------------
+
+ width dnwell 3000 "Deep N-well width < %d (Dnwell 2)"
+ spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (Dnwell 3)"
+ spacing dnwell allnwell 4500 surround_ok \
+    "Deep N-well spacing to N-well < %d (Nwell 7)"
+ cifmaxwidth nwell_missing 0 bend_illegal \
+    "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (Nwell 5a, 7)"
+ cifmaxwidth dnwell_missing 0 bend_illegal \
+    "SONOS nFET must be in Deep N-well (Tunm 6a)"
+
+#-----------------------------
+# NWELL
+#-----------------------------
+
+ width allnwell 840 "N-well width < %d (Nwell 1)"
+ spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (Nwell 2a)"
+
+#-----------------------------
+# DIFF
+#-----------------------------
+
+ width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,ppu,*psd,*pdiode,pdiffres \
+    150 "Diffusion width < %d (Diff/tap 1)"
+ width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode 290 \
+    "MV Diffusion width < %d (Diff/tap 14)"
+ width *mvnsd,*mvpsd 150 "MV Tap width < %d (Diff/tap 1)"
+ extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (Diff/tap 16)"
+ extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (Diff/tap 16)"
+ extend *psd *ndiff 290 "Butting tap length < %d (Diff/tap 4)"
+ extend *nsd *pdiff 290 "Butting tap length < %d (Diff/tap 4)"
+ width mvpdiffres 150 "MV P-Diffusion resistor width < %d (Diff/tap 14a)"
+ spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok \
+    "Diffusion spacing < %d (Diff/tap 3)"
+ spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
+    "MV Diffusion spacing < %d (Diff/tap 15a)"
+ spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
+    "MV Diffusion to MV tap spacing < %d (Diff/tap 3)"
+ spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
+    touching_ok "MV P-Diffusion to MV N-tap spacing < %d (Diff/tap 15b)"
+ spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
+    "MV Diffusion in N-well to P-tap spacing < %d (Diff/tap 20 + Diff/tap 17,19)"
+ spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
+    "N-Diffusion spacing to N-well < %d (Diff/tap 9)"
+ spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
+    "N-Diffusion spacing to N-well < %d (Diff/tap 9)"
+ spacing *psd allnwell 130 touching_illegal \
+    "P-tap spacing to N-well < %d (Diff/tap 11)"
+ spacing *mvpsd allnwell 130 touching_illegal \
+    "P-tap spacing to N-well < %d (Diff/tap 11)"
+ surround *nsd allnwell 180 absence_illegal \
+    "N-well overlap of N-tap < %d (Diff/tap 10)"
+ surround *mvnsd allnwell 330 absence_illegal \
+    "N-well overlap of MV N-tap < %d (Diff/tap 19)"
+ surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
+    "N-well overlap of P-Diffusion < %d (Diff/tap 8)"
+ surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal \
+    "N-well overlap of P-Diffusion < %d (Diff/tap 17)"
+ surround mvvar allnwell 560 absence_illegal \
+    "N-well overlap of MV varactor < %d (LVTN 10 + LVTN 4b)"
+ spacing *mvndiode *mvndiode 1070 touching_ok \
+    "MV N-diode spacing < %d (HVNTM.2 + 2 * HVNTM.3)"
+
+ # Butting junction rules
+ edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
+    "N-Diffusion to P-tap spacing < %d across butted junction"
+ edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
+    "N-Diffusion to P-tap spacing < %d across butted junction"
+ edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
+    "P-Diffusion to N-tap spacing < %d across butted junction"
+ edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
+    "P-Diffusion to N-tap spacing < %d across butted junction"
+
+ edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
+    "MV N-Diffusion to MV P-tap spacing < %d across butted junction"
+ edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
+    "MV N-Diffusion to MV P-tap spacing < %d across butted junction"
+ edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
+    "MV P-Diffusion to MV N-tap spacing < %d across butted junction"
+ edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
+    "MV P-Diffusion to MV N-tap spacing < %d across butted junction"
+
+ variants (full)
+
+ # Latchup rules
+ cifmaxwidth ptap_missing 0 bend_illegal \
+    "N-diff distance to P-tap must be < 15.0um (LU 2)"
+ cifmaxwidth dptap_missing 0 bend_illegal \
+    "N-diff distance to P-tap in deep Nwell must be < 15.0um (LU 2.1)"
+ cifmaxwidth ntap_missing 0 bend_illegal \
+    "P-diff distance to N-tap must be < 15.0um (LU 3)"
+
+ variants *
+
+#-----------------------------
+# POLY
+#-----------------------------
+
+ width allpoly 150 "Poly width < %d (Poly 1a)"
+ spacing allpoly allpoly 210 touching_ok "Poly spacing < %d (Poly 2)"
+ spacing allpolynonfet alldifflvnonfet 75 corner_ok allfets \
+    "Poly spacing to Diffusion < %d (Poly 4a)"
+ spacing npres *nsd 480 touching_illegal \
+    "Poly resistor spacing to N-tap < %d (Poly 9)"
+ overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nmos < %d (Poly 7)"
+ overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
+    "N-Diffusion overhang of nmos < %d (Poly 7)"
+ overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (Poly 7)"
+ overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (Poly 7)"
+ overhang *poly allfets 130 "Poly overhang of transistor < %d (Poly 8)"
+ rect_only allfets "No bends in transistors (Poly 11)"
+ rect_only xhrpoly,uhrpoly "No bends in poly resistors (Poly 11)"
+ extend  xpc/a xhrpoly,uhrpoly 2160 \
+    "Poly contact extends poly resistor by < %d (LIcon 1c + LI 5)"
+ spacing xhrpoly,uhrpoly xhrpoly,uhrpoly 1240 touching_illegal \
+    "Distance between precision resistors < %d (RPM 2 + 2 * RPM 3)"
+
+#--------------------------------------------------------------------
+# NPC (Nitride Poly Cut)
+#--------------------------------------------------------------------
+
+# Layer NPC is defined automatically around poly contacts (grow 0.1um)
+
+#--------------------------------------------------------------------
+# CONT (LICON, contact between poly/diff and LI)
+#--------------------------------------------------------------------
+
+ width ndc/li 170 "N-diffusion contact width < %d (LIcon 1)"
+ width nsc/li 170 "N-tap contact width     < %d (LIcon 1)"
+ width pdc/li 170 "P-diffusion contact width < %d (LIcon 1)"
+ width psc/li 170 "P-tap contact width     < %d (LIcon 1)"
+ width ndic/li 170 "N-diode contact width < %d (LIcon 1)"
+ width pdic/li 170 "P-diode contact width < %d (LIcon 1)"
+ width pc/li  170 "Poly contact width        < %d (LIcon 1)"
+
+ width xpc/li  350 "Poly resistor contact width < %d (LIcon 1b + 2 * LI 5)"
+
+ width mvndc/li 170 "N-diffusion contact width < %d (LIcon 1)"
+ width mvnsc/li 170 "N-tap contact width     < %d (LIcon 1)"
+ width mvpdc/li 170 "P-diffusion contact width < %d (LIcon 1)"
+ width mvpsc/li 170 "P-tap contact width     < %d (LIcon 1)"
+ width mvndic/li 170 "N-diode contact width < %d (LIcon 1)"
+ width mvpdic/li 170 "P-diode contact width < %d (LIcon 1)"
+
+ spacing allpdiffcont allndiffcont 170 touching_illegal \
+    "Diffusion contact spacing < %d (LIcon 2)"
+ spacing allndiffcont allndiffcont 170 touching_ok \
+    "Diffusion contact spacing < %d (LIcon 2)"
+ spacing allpdiffcont allpdiffcont 170 touching_ok \
+    "Diffusion contact spacing < %d (LIcon 2)"
+ spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (LIcon 2)"
+
+ spacing pc alldiff 190 touching_illegal \
+    "Poly contact spacing to diffusion < %d (LIcon 14)"
+ spacing pc allpfets 235 touching_illegal \
+    "Poly contact spacing to pFET < %d (LIcon 9 + PSDM 5a)"
+
+ spacing ndc,pdc nfet,pfet 55 touching_illegal \
+    "Diffusion contact to gate < %d (LIcon 11)"
+ spacing ndc,pdc scnfet,npd,npass,scpfet,ppu 50 touching_illegal \
+    "Diffusion contact to standard cell gate < %d (LIcon 11)"
+ spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \
+    "Diffusion contact to gate < %d (LIcon 11)"
+ spacing ndc,mvndc rnd,mvrnd 60 touching_illegal "Diffusion contact to rndiff < %d ()"
+ spacing pdc,mvpdc rdp,mvrdp 60 touching_illegal "Diffusion contact to rndiff < %d ()"
+ spacing nsc varactor,varhvt 250 touching_illegal \
+    "Diffusion contact to varactor gate < %d (LIcon 10)"
+ spacing mvnsc mvvar 250 touching_illegal \
+    "Diffusion contact to varactor gate < %d (LIcon 10)"
+
+ surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt 40 absence_illegal \
+    "N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)"
+ surround pdc/a *pdiff,pfet,scpfet,ppu,pfethvt,pfetlvt 40 absence_illegal \
+    "P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)"
+ surround ndic/a *ndi 40 absence_illegal \
+    "N-diode overlap of N-diode contact < %d (LIcon 5a)"
+ surround pdic/a *pdi 40 absence_illegal \
+    "P-diode overlap of N-diode contact < %d (LIcon 5a)"
+
+ surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt 60 directional \
+    "N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)"
+ surround pdc/a *pdiff,pfet,scpfet,ppu,pfethvt,pfetlvt 60 directional \
+    "P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)"
+ surround ndic/a *ndi 60 directional \
+    "N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+ surround pdic/a *pdi 60 directional \
+    "P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+
+ surround nsc/a *nsd 120 directional \
+    "N-tap overlap of N-tap contact < %d in one direction (LIcon 7)"
+ surround psc/a *psd 120 directional \
+    "P-tap overlap of P-tap contact < %d in one direction (LIcon 7)"
+
+ surround mvndc/a *mvndiff,mvnfet 40 absence_illegal \
+    "N-diffusion overlap of N-diffusion contact < %d (LIcon 5a)"
+ surround mvpdc/a *mvpdiff,mvpfet 40 absence_illegal \
+    "P-diffusion overlap of P-diffusion contact < %d (LIcon 5a)"
+ surround mvndic/a *mvndi 40 absence_illegal \
+    "N-diode overlap of N-diode contact < %d (LIcon 5a)"
+ surround mvpdic/a *mvpdi 40 absence_illegal \
+    "P-diode overlap of N-diode contact < %d (LIcon 5a)"
+
+ surround mvndc/a *mvndiff,mvnfet 60 directional \
+    "N-diffusion overlap of N-diffusion contact < %d in one direction (LIcon 5c)"
+ surround mvpdc/a *mvpdiff,mvpfet 60 directional \
+    "P-diffusion overlap of P-diffusion contact < %d in one direction (LIcon 5c)"
+ surround mvndic/a *mvndi 60 directional \
+    "N-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+ surround mvpdic/a *mvpdi 60 directional \
+    "P-diode overlap of N-diode contact < %d in one direction (LIcon 5c)"
+
+ surround mvnsc/a *mvnsd 120 directional \
+    "N-tap overlap of N-tap contact < %d in one direction (LIcon 7)"
+ surround mvpsc/a *mvpsd 120 directional \
+    "P-tap overlap of P-tap contact < %d in one direction (LIcon 7)"
+
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
+    "Poly overlap of poly contact < %d (LIcon 8)"
+ surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
+    "Poly overlap of poly contact < %d in one direction (LIcon 8a)"
+
+ exact_overlap ndc/a,pdc/a,psc/a,nsc/a,pc/a,ndic/a,pdic/a
+ exact_overlap mvndc/a,mvpdc/a,mvpsc/a,mvnsc/a,mvndic/a,mvpdic/a
+
+#-------------------------------------------------------------
+# LI - Local interconnect layer
+#-------------------------------------------------------------
+
+ width *li,rli 170 "Local interconnect width < %d (LI 1)"
+ width coreli 140 "Core local interconnect width < %d (LI c1)"
+ spacing allli allli,*obsli 170 touching_ok  "Local interconnect spacing < %d (LI 3)"
+ spacing coreli allli,*obsli 140 touching_ok  "Core local interconnect spacing < %d (LI c2)"
+
+ surround pc/li *li 80 directional \
+    "Local interconnect overlap of poly contact < %d in one direction (LI 5)"
+
+ surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
+    *li,rli 80 directional \
+    "Local interconnect overlap of diffusion contact < %d in one direction (LI 5)"
+
+ area allli,*obsli 56100 170 "Local interconnect minimum area < %a (LI 6)"
+
+#-------------------------------------------------------------
+# MCON - Contact between local interconnect and metal1
+#-------------------------------------------------------------
+
+ width lic/m1 170 "Mcon width < %d (Mcon 1)"
+ spacing lic/m1 lic/m1,obslic/m1 170 touching_ok "Mcon spacing < %d (Mcon 2)"
+
+ exact_overlap lic/m1
+
+#-------------------------------------------------------------
+# METAL1 -
+#-------------------------------------------------------------
+
+ width *m1,rm1 140 "Metal1 width < %d (Met1 1)"
+ spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (Met1 2)"
+ area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (Met1 6)"
+
+ surround lic/m1 *met1 30 absence_illegal \
+    "Metal1 overlap of local interconnect contact < %d (Met1 4)"
+ surround lic/m1 *met1 60 directional \
+    "Metal1 overlap of local interconnect contact < %d in one direction (Met1 5)"
+
+variants (fast),(full)
+ widespacing allm1 3000 allm1,*obsm1 280 touching_ok \
+    "Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)"
+ widespacing *obsm1 3000 allm1 280 touching_ok \
+    "Metal1 > 3um spacing to unrelated m1 < %d (Met1 3a)"
+
+variants (full)
+ cifmaxwidth m1_hole_empty 0 bend_illegal \
+    "Min area of metal1 holes > 0.14um^2 (Met1 7)"
+variants *
+
+#--------------------------------------------------
+# VIA1
+#--------------------------------------------------
+
+ width v1/m1 260 "Via1 width < %d (Via 1a + 2 * Via 4a)"
+ spacing v1 v1 60 touching_ok "Via1 spacing < %d (Via 2 - 2 * Via 4a)"
+ surround v1/m1 *m1 30 directional \
+    "Metal1 overlap of Via1 < %d in one direction (Via 5a - Via 4a)"
+ surround v1/m2 *m2 30 directional \
+    "Metal2 overlap of Via1 < %d in one direction (Met2 5 - Met2 4)"
+
+ exact_overlap v1/m2
+
+#--------------------------------------------------
+# METAL2 - 
+#--------------------------------------------------
+
+ width allm2 140 "Metal2 width < %d (Met2 1)"
+ spacing allm2  allm2,obsm2 140 touching_ok       "Metal2 spacing < %d (Met2 2)"
+ area allm2,obsm2 67600 140 "Metal2 minimum area < %a (Met2 6)"
+
+variants (fast),(full)
+ widespacing allm2 3000 allm2,obsm2  280 touching_ok \
+    "Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)"
+ widespacing obsm2 3000 allm2  280 touching_ok \
+    "Metal2 > 3um spacing to unrelated m2 < %d (Met2 3)"
+
+variants (full)
+ cifmaxwidth m2_hole_empty 0 bend_illegal \
+    "Min area of metal2 holes > 0.14um^2 (Met2 7)"
+variants *
+
+#--------------------------------------------------
+# VIA2
+#--------------------------------------------------
+
+ width v2/m2 280 "Via2 width < %d (Via2 1a + 2 * Via2 4)"
+
+ spacing v2 v2 120 touching_ok "Via2 spacing < 0.24um (Via2 2 - 2 * Via2 4)"
+
+ surround v2/m2 *m2 45 directional \
+    "Metal2 overlap of Via2 < %d in one direction (Via2 4a - Via2 4)"
+ surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of Via2 < %d (Met3 4)"
+
+ exact_overlap v2/m2
+
+#--------------------------------------------------
+# METAL3 - 
+#--------------------------------------------------
+
+ width allm3 300 "Metal3 width < %d (Met3 1)"
+ spacing allm3 allm3,obsm3  300 touching_ok "Metal3 spacing < %d (Met3 2)"
+ area allm3,obsm3 240000 300 "Metal3 minimum area < %a (Met3 6)"
+
+variants (fast),(full)
+ widespacing allm3 3000 allm3,obsm3  400 touching_ok \
+    "Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)"
+ widespacing obsm3 3000 allm3  400 touching_ok \
+    "Metal3 > 3um spacing to unrelated m3 < %d (Met3 3d)"
+variants *
+
+
+#--------------------------------------------------
+# VIA3 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v3/m3 320 "Via3 width < %d (Via3 1 + 2 * Via3 4)"
+ spacing v3 v3 80 touching_ok "Via3 spacing < %d (Via3 2 - 2 * Via3 4)"
+ surround v3/m3 *m3 30 directional \
+    "Metal3 overlap of Via3 in one direction < %d (Via3 5 - Via3 4)"
+ surround v3/m4 *m4 5 absence_illegal \
+    "Metal4 overlap of Via3 < %d (Met4 3 - Via3 4)"
+
+ exact_overlap v3/m3
+
+#-----------------------------
+# METAL4 - METAL4 Module
+#-----------------------------
+
+variants *
+
+ width allm4 300 "Metal4 width < %d (Met4 1)"
+ spacing allm4  allm4,obsm4 300 touching_ok      "Metal4 spacing < %d (Met4 2)"
+ area allm4,obsm4 240000 300 "Metal4 minimum area < %a (Met4 4a)"
+
+variants (fast),(full)
+ widespacing allm4 3000 allm4,obsm4  400 touching_ok \
+    "Metal4 > 3um spacing to unrelated m4 < %d (S2M4)"
+ widespacing obsm4 3000 allm4  400 touching_ok \
+    "Metal4 > 3um spacing to unrelated m4 < %d (S2M4)"
+variants *
+
+#--------------------------------------------------
+# VIA4 - Requires METAL5 Module
+#--------------------------------------------------
+
+ width v4/m4 1180 "Via4 width < %d (Via4 1 + 2 * Via4 4)"
+ spacing v4 v4 420 touching_ok "Via4 spacing < %d (Via4 2 - 2 * Via4 4)"
+ surround v4/m5 *m5 120 absence_illegal \
+    "Metal5 overlap of Via4 < %d (Met5 3 - Via4 4)"
+
+ exact_overlap v4/m4
+
+#-----------------------------
+# METAL5 - METAL5 Module
+#-----------------------------
+
+ width allm5 1600 "Metal5 width < %d (Met5 1)"
+ spacing allm5  allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (Met5 2)"
+ area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (Met5 4)"
+
+
+
+variants (full)
+
+ width metrdl 10000 "RDL width < %d (Rdl 1)"
+ spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (Rdl 2)"
+ surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (Rdl 3)"
+ spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (Rdl 6)"
+
+variants *
+
+
+#--------------------------------------------------
+# NMOS, PMOS
+#--------------------------------------------------
+
+ extend allfets *poly 420 "Transistor width < %d (Diff/tap 2)"
+ # Except:  Note that standard cells allow transistor width minimum 0.36um
+ width pfetlvt 350 "LVT PMOS gate length < %d (Poly 1b)"
+
+ spacing *nsd,*mvnsd allpolynonfet 55 touching_illegal \
+    "N-tap spacing to field poly < %d (Poly 5)"
+ spacing *psd,*mvpsd allpolynonfet 55 touching_illegal \
+    "P-tap spacing to field poly < %d (Poly 5)"
+
+ # Full edge rule required to describe FET to butted tap distance
+ edge4way *psd *ndiff 300 *ndiff *psd 300 \
+    "Butting P-tap spacing to NMOS gate < %d (Poly 6)"
+ edge4way *nsd *pdiff 300 *pdiff *nsd 300 \
+    "Butting N-tap spacing to PMOS gate < %d (Poly 6)"
+ edge4way *mvpsd *mvndiff 300 *mvndiff *mvpsd 300 \
+    "Butting MV P-tap spacing to MV NMOS gate < %d (Poly 6)"
+ edge4way *mvnsd *mvpdiff 300 *mvpdiff *mvnsd 300 \
+    "Butting MV N-tap spacing to MV PMOS gate < %d (Poly 6)"
+
+ # No LV FETs in HV diff
+ spacing pfet,scpfet,ppu,pfetlvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
+    "LV P-diffusion to MV P-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
+    "LV N-diffusion to MV N-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ # No HV FETs in LV diff
+ spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal \
+    "MV P-diffusion to LV P-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
+    "MV N-diffusion to LV N-diffusion < %d (Diff/tap 23 + Diff/tap 22)"
+
+ # Minimum length of MV FETs.  Note that this is larger than the minimum
+ # width (0.29um), so an edge rule is required
+
+ edge4way mvndiff mvnfet 500 mvnfet 0 0 \
+    "MV NMOS minimum length < %d (Poly 13)"
+
+ edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
+    "MV Varactor minimum length < %d (Poly 13)"
+
+ edge4way mvpdiff mvpfet 500 mvpfet 0 0 \
+    "MV PMOS minimum length < %d (Poly 13)"
+
+#--------------------------------------------------
+# mrp1 (N+ poly resistor)
+#--------------------------------------------------
+
+  width mrp1 330 "mrp1 resistor width < %d (Poly 3)"
+
+#--------------------------------------------------
+# xhrpoly (P+ poly resistor)
+#--------------------------------------------------
+
+  width xhrpoly 350 "xhrpoly resistor width < %d (P+ Poly 1a)"
+  # NOTE: xhrpoly resistor requires choice of discrete widths 0.35, 0.69, ... up to 1.27.
+
+#--------------------------------------------------
+# uhrpoly (P+ poly resistor, 2kOhm/sq)
+#--------------------------------------------------
+
+  width uhrpoly 350 "uhrpoly resistor width < %d"
+  spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
+    "xhrpoly/uhrpoly resistor spacing to diffusion < %d (Poly 9)"
+
+#------------------------------------
+# MOS Varactor device rules
+#------------------------------------
+
+ overhang *nsd var,varhvt 250 \
+ "N-Tap overhang of Varactor < %d (Var 4)"
+
+ overhang *mvnsd mvvar 250 \
+ "N-Tap overhang of Varactor < %d (Var 4)"
+
+ width var,varhvt,mvvar 180 "Varactor length < %d (Var 1)"
+ extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (Var 2)"
+
+#-----------------------------------------------------------
+# MiM CAP (CAPM) - 
+#-----------------------------------------------------------
+
+ width *mimcap 2000 "MiM cap width < %d (Capm 1)"
+ spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (Capm 2a)"
+ spacing *mimcap via2/m3 1270 touching_illegal \
+    "MiM cap spacing to via2 < %d (Capm 5)"
+ surround *mimcc *mimcap 200 absence_illegal \
+    "MiM cap must surround MiM cap contact by %d (Capm 4)"
+ rect_only *mimcap "MiM cap must be rectangular (Capm 7)
+
+ surround *mimcap *metal3/m3 140 absence_illegal \
+    "Metal3 must surround MiM cap by %d (Capm 3)"
+ spacing via2 *mimcap 50 touching_illegal "MiM cap cannot overlap via2 (Capm 8)"
+ spacing via3 *mimcap 50 touching_illegal "MiM cap cannot overlap via3 (Capm 8)"
+ # (resolve scaling issue!)
+ # cifspacing mim_bottom mim_bottom 1200 touching_ok \
+ #  "MiM cap bottom plate spacing < %d (Capm 2b)"
+
+ # MiM cap contact rules (VIA3)
+
+ width mimcc/m3 320 "MiM cap contact width < %d (Via3 1 + 2 * Via3 4)"
+ spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (Via3 2 - 2 * Via3 4)"
+ surround mimcc/m4 *m4 5 directional \
+    "Metal4 overlap of MiM cap contact in one direction < %d (Met4 3 - Via3 4)"
+ exact_overlap mimcc/m3
+
+ width *mimcap2 2000 "MiM cap width < %d (Cap2m 1)"
+ spacing *mimcap2 *mimcap2 840 touching_ok "MiM cap spacing < %d (Cap2m 2a)"
+ spacing *mimcap2 via3/m4 1270 touching_illegal \
+    "MiM cap spacing to via3 < %d (Cap2m 5)"
+ surround *mim2cc *mimcap2 200 absence_illegal \
+    "MiM cap must surround MiM cap contact by %d (Cap2m 4)"
+ rect_only *mimcap2 "MiM cap must be rectangular (Cap2m 7)
+
+ surround *mimcap2 *metal4/m4 140 absence_illegal \
+    "Metal4 must surround MiM cap by %d (Cap2m 3)"
+ spacing via3 *mimcap2 50 touching_illegal "MiM cap cannot overlap via3 (Cap2m 8)"
+ spacing via4 *mimcap2 50 touching_illegal "MiM cap cannot overlap via4 (Cap2m 8)"
+ # (resolve scaling issue!)
+ # cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
+ #  "MiM2 cap bottom plate spacing < %d (Cap2m 2b)"
+
+ # MiM cap contact rules (VIA4)
+
+ width mim2cc/m4 1180 "MiM2 cap contact width < %d (Via4 1 + 2 * Via4 4)"
+ spacing mim2cc mim2cc 420 touching_ok \
+    "MiM2 cap contact spacing < %d (Via4 2 - 2 * Via4 4)"
+ surround mim2cc/m5 *m5 120 absence_illegal \
+    "Metal5 overlap of MiM2 cap contact < %d (Met5 3 - Via4 4)"
+ exact_overlap mim2cc/m4
+
+
+#----------------------------
+# End DRC style
+#----------------------------
+
+end
+
+#----------------------------
+# LEF format definitions
+#----------------------------
+
+lef
+
+ masterslice pwell  pwell PWELL substrate
+ masterslice nwell  nwell NWELL
+
+ routing li li1 LI1 LI li
+
+ routing m1 met1 MET1 m1
+ routing m2 met2 MET2 m2
+ routing m3 met3 MET3 m3
+ routing m4 met4 MET4 m4
+ routing m5 met5 MET5 m5
+ routing mrdl   met6 MET6 m6 MRDL METRDL
+
+ cut lic  mcon MCON Mcon
+ cut m2c  via via1 VIA VIA1 cont2 via12
+ cut m3c  via2 VIA2 cont3 via23
+ cut via3 via3 VIA3 cont4 via34
+ cut via4 via4 VIA4 cont5 via45
+
+ obs obsli   li1
+ obs obsm1   met1
+ obs obsm2   met2
+ obs obsm3   met3
+
+ obs obsm4   met4
+ obs obsm5   met5
+ obs obsmrdl met6
+
+ obs obslic mcon
+
+end
+
+#-----------------------------------------------------
+# Device and Parasitic extraction
+#-----------------------------------------------------
+
+extract
+ style ngspice variants (lvs),(sim),(si)
+ cscale 1
+ # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
+ # dimensions must be in units of microns in the extract file.
+ # Use extract style "ngspice(si)" to override this and produce
+ # a file with SI units for length/area.
+
+ variants (lvs),(sim),(si)
+ lambda 1.0
+ variants *
+
+ units  microns
+ step   7
+ sidehalo 2
+
+ # NOTE:  MiM cap layers have been purposely put out of order,
+ # may want to reconsider.
+
+ planeorder dwell   0
+ planeorder well    1
+ planeorder active  2
+ planeorder locali  3
+ planeorder metal1  4
+ planeorder metal2  5
+ planeorder metal3  6
+ planeorder metal4  7
+ planeorder metal5  8
+ planeorder metali  9
+ planeorder block      10
+ planeorder comment    11
+ planeorder cap1       12
+ planeorder cap2       13
+
+ height dnwell      -0.1    0.1
+ height nwell,pwell  0.0    0.2062
+ height alldiff      0.2062 0.12
+ height allpoly      0.3262 0.18
+ height alldiffcont  0.3262 0.61
+ height pc       0.5062 0.43
+ height allli        0.9361 0.10
+ height lic      1.0361 0.34
+ height allm1        1.3761 0.36
+ height v1       1.7361 0.27
+ height allm2        2.0061 0.36
+ height v2       2.3661 0.42
+ height allm3        2.7861 0.845
+ height v3       3.6311 0.39
+ height allm4        4.0211 0.845
+ height v4       4.8661 0.505
+ height allm5        5.3711 1.26
+ height mimcap       2.4661 0.2
+ height mimcap2      3.7311 0.2
+ height mimcc        2.6661 0.12
+ height mim2cc       3.9311 0.09
+ height mrdlc        6.6311 5.2523
+ height mrdl        11.8834 4.0
+
+ # Antenna check parameters
+ # Note that checks w/diode diffusion are not modeled
+ model partial
+ antenna poly sidewall 50 none
+ antenna allcont surface 3 none
+ antenna li sidewall 75 0 450
+ antenna lic surface 3 0 18
+ antenna m1,m2,m3 sidewall 400 2600 400
+ antenna v1 surface 3 0 18
+ antenna v2 surface 6 0 36
+ antenna m4,m5 sidewall 400 2600 400
+ antenna v3,v4 surface 6 0 36
+
+ tiedown alldiffnonfet
+
+ substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
+
+# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
+
+# Resistances are in milliohms per square
+# Optional 3rd argument is the corner adjustment fraction
+# Device values come from trtc.cor (typical corner)
+ resist (dnwell)/dwell          2200000
+ resist (pwell)/well            3050000
+ resist (nwell)/well            1700000
+ resist (rpw)/well              3050000 0.5
+ resist (*ndiff,nsd)/active      120000
+ resist (*pdiff,*psd)/active     197000
+ resist (*mvndiff,mvnsd)/active  114000
+ resist (*mvpdiff,*mvpsd)/active 191000
+
+ resist ndiffres/active     120000 0.5
+ resist pdiffres/active     197000 0.5
+ resist mvndiffres/active   114000 0.5
+ resist mvpdiffres/active   191000 0.5
+ resist mrp1/active      48200 0.5
+ resist xhrpoly/active          319800 0.5
+ resist uhrpoly/active         2000000 0.5
+
+ resist (allpolynonres)/active   48200
+ resist rmp/active           48200
+
+ resist (allli)/locali       12200
+ resist (allm1)/metal1         125
+ resist (allm2)/metal2         125
+ resist (allm3)/metal3              47
+ resist (allm4)/metal4          47
+ resist (allm5)/metal5          29
+ resist mrdl/metali          5
+
+ contact ndc,nsc         15000
+ contact pdc,psc         15000
+ contact mvndc,mvnsc         15000
+ contact mvpdc,mvpsc         15000
+ contact pc          15000
+ contact lic            152000
+ contact m2c              4500
+ contact m3c              3410
+ contact mimcc            4500
+ contact mim2cc           3410
+ contact via3             3410
+ contact via4              380
+ contact mrdlc               6
+
+#-------------------------------------------------------------------------
+# Parasitic capacitance values:  Use document (...)
+#-------------------------------------------------------------------------
+# This uses the new "default" definitions that determine the intervening
+# planes from the planeorder stack, take care of the reflexive sideoverlap
+# definitions, and generally clean up the section and make it more readable.
+#
+# Also uses "units microns" statement.  All values are taken from the
+# document PEX/xRC/cap_models.  Fringe capacitance values are approximated.
+# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
+#-------------------------------------------------------------------------
+# Remember that device capacitances to substrate are taken care of by the
+# models.  Thus, active and poly definitions ignore all "fet" types.
+# fet types are excluded when computing parasitic capacitance to
+# active from layers above them because poly is a shield; fet types are
+# included for parasitics from layers above to poly.  Resistor types
+# should be removed from all parasitic capacitance calculations, or else
+# they just create floating caps.  Technically, the capacitance probably
+# should be split between the two terminals.  Unsure of the correct model.
+#-------------------------------------------------------------------------
+
+#n-well
+# NOTE:  This value not found in PEX files
+defaultareacap     nwell well 120
+
+#n-active 
+# Rely on device models to capture *ndiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allnactivenonfet active 790
+# defaultperimeter   allnactivenonfet active 280
+
+#p-active
+# Rely on device models to capture *pdiff area cap
+# Do not extract parasitics from resistors
+# defaultareacap     allpactivenonfet active 810
+# defaultperimeter   allpactivenonfet active 300
+
+#poly
+# Do not extract parasitics from resistors
+# defaultsidewall    allpolynonfet active  22
+# defaultareacap     allpolynonfet active  106
+# defaultperimeter   allpolynonfet active   57
+
+ defaultsidewall    *poly active  23
+ defaultareacap     *poly active nwell,obswell,pwell well  106
+ defaultperimeter   *poly active nwell,obswell,pwell well  55
+
+#locali
+ defaultsidewall    allli locali       33
+ defaultareacap     allli locali nwell,obswell,pwell well  37
+ defaultperimeter   allli locali nwell,obswell,pwell well  55
+ defaultoverlap     allli locali nwell well 37
+
+#locali->diff
+ defaultoverlap     allli locali allactivenonfet active 37
+ defaultsideoverlap allli locali allactivenonfet active 55
+
+#locali->poly
+ defaultoverlap     allli locali allpolynonres active 94
+ defaultsideoverlap allli locali allpolynonres active 52
+ defaultsideoverlap *poly active allli locali 25
+
+#metal1
+ defaultsidewall    allm1 metal1      45
+ defaultareacap     allm1 metal1 nwell,obswell,pwell well  26
+ defaultperimeter   allm1 metal1 nwell,obswell,pwell well  41
+ defaultoverlap     allm1 metal1 nwell well 26
+
+#metal1->diff
+ defaultoverlap     allm1 metal1 allactivenonfet active 26
+ defaultsideoverlap allm1 metal1 allactivenonfet active 41
+
+#metal1->poly
+ defaultoverlap     allm1 metal1 allpolynonres active 45
+ defaultsideoverlap allm1 metal1 allpolynonres active 47
+ defaultsideoverlap *poly active allm1 metal1 17
+
+#metal1->locali
+ defaultoverlap     allm1 metal1 allli locali 114
+ defaultsideoverlap allm1 metal1 allli locali 59
+ defaultsideoverlap allli locali allm1 metal1 35
+
+#metal2
+ defaultsidewall    allm2 metal2      50
+ defaultareacap     allm2 metal2 nwell,obswell,pwell well 17
+ defaultperimeter   allm2 metal2 nwell,obswell,pwell well 41
+ defaultoverlap     allm2 metal2 nwell well 38
+
+#metal2->diff
+ defaultoverlap     allm2 metal2 allactivenonfet active 17
+ defaultsideoverlap allm2 metal2 allactivenonfet active 41
+
+#metal2->poly
+ defaultoverlap     allm2 metal2 allpolynonres active 24
+ defaultsideoverlap allm2 metal2 allpolynonres active 41
+ defaultsideoverlap *poly active allm2 metal2 11
+
+#metal2->locali
+ defaultoverlap     allm2 metal2 allli locali 38
+ defaultsideoverlap allm2 metal2 allli locali 46
+ defaultsideoverlap allli locali allm2 metal2 22
+
+#metal2->metal1
+ defaultoverlap     allm2 metal2 allm1 metal1 134
+ defaultsideoverlap allm2 metal2 allm1 metal1 67
+ defaultsideoverlap allm1 metal1 allm2 metal2 48
+
+#metal3
+ defaultsidewall    allm3 metal3     63
+ defaultoverlap     allm3 metal3 nwell well 12
+ defaultareacap     allm3 metal3 nwell,obswell,pwell well 12
+ defaultperimeter   allm3 metal3 nwell,obswell,pwell well 41
+
+#metal3->diff
+ defaultoverlap     allm3 metal3 allactive active 12
+ defaultsideoverlap allm3 metal3 allactive active 41
+
+#metal3->poly
+ defaultoverlap     allm3 metal3 allpolynonres active 16
+ defaultsideoverlap allm3 metal3 allpolynonres active 44
+ defaultsideoverlap *poly active allm3 metal3 9
+
+#metal3->locali
+ defaultoverlap     allm3 metal3 allli locali 21
+ defaultsideoverlap allm3 metal3 allli locali 47
+ defaultsideoverlap allli locali allm3 metal3 15
+
+#metal3->metal1
+ defaultoverlap     allm3 metal3 allm1 metal1 35
+ defaultsideoverlap allm3 metal3 allm1 metal1 55
+ defaultsideoverlap allm1 metal1 allm3 metal3 27
+
+#metal3->metal2
+ defaultoverlap     allm3 metal3 allm2 metal2 86
+ defaultsideoverlap allm3 metal3 allm2 metal2 70
+ defaultsideoverlap allm2 metal2 allm3 metal3 44
+
+#metal4
+ defaultsidewall    allm4 metal4       67
+# defaultareacap     alltopm metal4 well  6
+ areacap            allm4/m4 8
+ defaultoverlap     allm4 metal4 nwell well 8
+ defaultperimeter   allm4 metal4 well  37
+
+#metal4->diff
+ defaultoverlap     allm4 metal4 allactivenonfet active 8
+ defaultsideoverlap allm4 metal4 allactivenonfet active 37
+
+#metal4->poly
+ defaultoverlap     allm4 metal4 allpolynonres active 10
+ defaultsideoverlap allm4 metal4 allpolynonres active 38
+ defaultsideoverlap *poly active allm4 metal4 6
+
+#metal4->locali
+ defaultoverlap     allm4 metal4 allli locali 12
+ defaultsideoverlap allm4 metal4 allli locali 40
+ defaultsideoverlap allli locali allm4 metal4 10
+
+#metal4->metal1
+ defaultoverlap     allm4 metal4 allm1 metal1 15
+ defaultsideoverlap allm4 metal4 allm1 metal1 43
+ defaultsideoverlap allm1 metal1 allm4 metal4 16
+
+#metal4->metal2
+ defaultoverlap     allm4 metal4 allm2 metal2 20
+ defaultsideoverlap allm4 metal4 allm2 metal2 46
+ defaultsideoverlap allm2 metal2 allm4 metal4 22
+
+#metal4->metal3
+ defaultoverlap     allm4 metal4 allm3 metal3 84
+ defaultsideoverlap allm4 metal4 allm3 metal3 71
+ defaultsideoverlap allm3 metal3 allm4 metal4 43
+
+#metal5
+ defaultsidewall    allm5 metal5       127
+# defaultareacap     allm5 metal5 well  6
+ areacap            allm5/m5 6
+ defaultoverlap     allm5 metal5 nwell well 6
+ defaultperimeter   allm5 metal5 well  39
+
+#metal5->diff
+ defaultoverlap     allm5 metal5 allactivenonfet active 6
+ defaultsideoverlap allm5 metal5 allactivenonfet active 39
+
+#metal5->poly
+ defaultoverlap     allm5 metal5 allpolynonres active 7
+ defaultsideoverlap allm5 metal5 allpolynonres active 40
+ defaultsideoverlap *poly active allm5 metal5 6
+
+#metal5->locali
+ defaultoverlap     allm5 metal5 allli locali 8
+ defaultsideoverlap allm5 metal5 allli locali 41
+ defaultsideoverlap allli locali allm5 metal5 8
+
+#metal5->metal1
+ defaultoverlap     allm5 metal5 allm1 metal1 9
+ defaultsideoverlap allm5 metal5 allm1 metal1 43
+ defaultsideoverlap allm1 metal1 allm5 metal5 12
+
+#metal5->metal2
+ defaultoverlap     allm5 metal5 allm2 metal2 11
+ defaultsideoverlap allm5 metal5 allm2 metal2 46
+ defaultsideoverlap allm2 metal2 allm5 metal5 16
+
+#metal5->metal3
+ defaultoverlap     allm5 metal5 allm3 metal3 20
+ defaultsideoverlap allm5 metal5 allm3 metal3 54
+ defaultsideoverlap allm3 metal3 allm5 metal5 28
+
+#metal5->metal4
+ defaultoverlap     allm5 metal5 allm4 metal4 68
+ defaultsideoverlap allm5 metal5 allm4 metal4 83
+ defaultsideoverlap allm4 metal4 allm5 metal5 47
+
+
+# Devices:  Use document (...)
+
+variants (sim)
+
+ device msubcircuit pshort pfet,scpfet *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit ppu ppu *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit plowvt pfetlvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+ device msubcircuit phighvt pfethvt *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
+
+ device msubcircuit nshort nfet,scnfet,npd,npass *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit npd npd *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit npass npass *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit nlowvt nfetlvt *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device msubcircuit sonos_e nsonos *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
+ device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w
+ device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w
+ device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w
+
+ device msubcircuit phv mvpfet *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
+ device msubcircuit nhv mvnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
+ device msubcircuit nhvnative mvnnfet *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
+
+ device rsubcircuit short rmp     *poly  space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rli1    *li,coreli space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rmetal1 *metal1 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rmetal2 *metal2 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rmetal3 *metal3 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rm4 *m4 space/w,pwell,nwell error l=l w=w
+ device rsubcircuit short rm5 *m5 space/w,pwell,nwell error l=l w=w
+
+ device rsubcircuit xhrpoly  xhrpoly xpc pwell,space/w error l=l w=w
+ device rsubcircuit uhrpoly  uhrpoly xpc pwell,space/w error l=l w=w
+ device rsubcircuit mrp1     mrp1    *poly pwell,space/w error  l=l w=w
+
+ device rsubcircuit mrdn     ndiffres *ndiff pwell,space/w  error l=l w=w
+ device rsubcircuit mrdp     pdiffres *pdiff nwell    error l=l w=w
+ device rsubcircuit xpwres   rpw       pwell dnwell error l=l w=w
+
+ device rsubcircuit mrdn_hv  mvndiffres *mvndiff pwell,space/w error l=l w=w
+ device rsubcircuit mrdp_hv  mvpdiffres *mvpdiff nwell   error l=l w=w
+
+ device subcircuit  pdiode *pdiode nwell a=a p=p
+ device msubcircuit ndiode *ndiode pwell,space/w a=a p=p
+ device subcircuit  pdiode_h *mvpdiode nwell a=a p=p
+ device msubcircuit ndiode_h *mvndiode pwell,space/w a=a p=p
+
+ # These are parasitic devices
+ device msubcircuit ndiode_lvt *ndiodelvt pwell,space/w a=a p=p
+ device subcircuit  pdiode_lvt *pdiodelvt nwell a=a p=p
+ device subcircuit  pdiode_hvt *pdiodehvt nwell a=a p=p
+ device msubcircuit ndiode_native *nndiode pwell,space/w a=a p=p
+
+ device subcircuit xcmimc1 *mimcap  m3 nwell,pwell,space/w error a=a p=p s=subs
+ device subcircuit xcmimc2 *mimcap2 m4,mimcc/m4 nwell,pwell,space/w error a=a p=p s=subs
+
+ variants (lvs),(si)
+
+ device mosfet pshort scpfet,pfet pdiff,pdiffres,pdc nwell 
+ device mosfet ppu ppu pdiff,pdiffres,pdc nwell 
+ device mosfet plowvt pfetlvt pdiff,pdiffres,pdc nwell 
+ device mosfet phighvt pfethvt pdiff,pdiffres,pdc nwell 
+ device mosfet nshort scnfet,npd,npass,nfet ndiff,ndiffres,ndc pwell,space/w
+ device mosfet npd npd ndiff,ndiffres,ndc pwell,space/w
+ device mosfet npass npass ndiff,ndiffres,ndc pwell,space/w
+ device mosfet nlowvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
+ device mosfet sonos_e nsonos ndiff,ndiffres,ndc pwell,space/w
+ device mosfet phv mvpfet mvpdiff,mvpdiffres,mvpdc nwell 
+ device mosfet nhv mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
+ device mosfet nhvnative mvnnfet *mvndiff,mvndiffres pwell,space/w
+
+ # These devices always extract as subcircuits
+ device subcircuit xcnwvc varactor *nndiff nwell error l=l w=w
+ device subcircuit xcnwvc2 varhvt *nndiff nwell error l=l w=w
+ device subcircuit xchvnwc mvvaractor *mvnndiff nwell error l=l w=w
+
+ device resistor short rmp     *poly
+ device resistor short rli1    *li,coreli
+ device resistor short rmetal1 *metal1
+ device resistor short rmetal2 *metal2
+ device resistor short rmetal3 *metal3
+ device resistor short rm4 *m4
+ device resistor short rm5 *m5
+
+ device resistor xhrpoly xhrpoly xpc 
+ device resistor uhrpoly uhrpoly xpc 
+ device resistor mrp1 mrp1       *poly 
+ device resistor mrdn  ndiffres *ndiff 
+ device resistor mrdp  pdiffres *pdiff 
+ device resistor mrdn_hv   mvndiffres *mvndiff 
+ device resistor mrdp_hv   mvpdiffres *mvpdiff 
+ device resistor xpwres   rpw    pwell
+
+ device pdiode pdiode *pdiode nwell a=a p=p
+ device ndiode ndiode *ndiode pwell,space/w a=a p=p
+ device pdiode pdiode_h *mvpdiode nwell a=a p=p
+ device ndiode ndiode_h *mvndiode pwell,space/w a=a p=p
+
+ # These are parasitic devices
+ device ndiode ndiode_lvt *ndiodelvt pwell,space/w a=a p=p
+ device pdiode pdiode_lvt *pdiodelvt nwell a=a p=p
+ device pdiode pdiode_hvt *pdiodehvt nwell a=a p=p
+ device ndiode ndiode_native *nndiode pwell,space/w a=a p=p
+
+ device subcircuit  pdiode_h *mvpdiode nwell a=a p=p
+ device msubcircuit ndiode_h *mvndiode pwell,space/w a=a p=p
+
+
+ device capacitor xcmimc1 *mimcap  *m3 1
+ device capacitor xcmimc2 *mimcap2 *m4 1
+
+end
+
+#-----------------------------------------------------
+# Wiring tool definitions
+#-----------------------------------------------------
+
+wiring
+ # All wiring values are in nanometers
+ scalefactor 10
+
+ contact lic 170 li 0  0 m1 30 60
+ contact v1  260 m1 0 30 m2  0 30  
+ contact v2  280 m2 0 45 m3 25  0
+ contact v3  320 m3 0 30 m4  5  5
+ contact v4 1180 m4 0    m5 120 
+
+ contact pc  170  poly 50 80 li 0 80
+ contact pdc 170 pdiff 40 60 li 0 80
+ contact ndc 170 ndiff 40 60 li 0 80
+ contact psc 170   psd 40 60 li 0 80
+ contact nsc 170   nsd 40 60 li 0 80
+
+end
+
+#-----------------------------------------------------
+# Plain old router. . . 
+#-----------------------------------------------------
+
+router
+end
+
+#------------------------------------------------------------
+# Plowing (restored in magic 8.2, need to fill this section)
+#------------------------------------------------------------
+
+plowing
+end
+
+#-----------------------------------------------------------------
+# No special plot layers defined (use default PNM color choices)
+#-----------------------------------------------------------------
+
+plot
+  style pnm
+     default
+     draw fillblock no_color_at_all
+     draw nwell cwell
+end
diff --git a/char/techfiles/sky130_osu_sc.tlef b/char/techfiles/sky130_osu_sc.tlef
new file mode 100644
index 0000000..88761ac
--- /dev/null
+++ b/char/techfiles/sky130_osu_sc.tlef
@@ -0,0 +1,781 @@
+# Copyright 2020 The SkyWater PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+VERSION 5.7 ;
+
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+UNITS
+  TIME NANOSECONDS 1 ;
+  CAPACITANCE PICOFARADS 1 ;
+  RESISTANCE OHMS 1 ;
+  DATABASE MICRONS 1000 ;
+END UNITS
+
+MANUFACTURINGGRID 0.005 ;
+
+SITE 18T
+  SYMMETRY X Y ;
+  CLASS CORE ;
+  SIZE 0.11 BY 6.66 ;
+END 18T
+
+SITE 15T
+  SYMMETRY X Y ;
+  CLASS CORE ;
+  SIZE 0.11 BY 5.55 ;
+END 15T
+
+SITE 12T
+  SYMMETRY X Y ;
+  CLASS CORE ;
+  SIZE 0.11 BY 4.44 ;
+END 12T
+
+SITE 9T
+  SYMMETRY X Y ;
+  CLASS CORE ;
+  SIZE 0.11 BY 3.33 ;
+END 9T
+
+LAYER diff
+    TYPE MASTERSLICE ;
+END diff
+
+LAYER poly
+    TYPE MASTERSLICE ;
+END poly
+
+# NOTE:
+# The use of li1 as a routing layer is commented
+# out and replaced with a definition of li1 as a
+# non-routing layer. This is done to ensure good
+# results regardless of tool used.
+#
+# If li1 is enabled as a routing layer take note
+# of its resistance compared to that of metal1.
+
+#LAYER licon1
+#    TYPE CUT ;
+#END licon1
+
+LAYER li1
+  TYPE MASTERSLICE ;
+END li1
+
+#LAYER li1
+#  TYPE ROUTING ;
+#  DIRECTION VERTICAL ;
+
+#  PITCH 0.48 ;
+#  MINWIDTH 0.17 ;
+
+#  WIDTH 0.17 ;          # LI 1
+  # SPACING  0.17 ;     # LI 2
+#  SPACINGTABLE
+#     PARALLELRUNLENGTH 0
+#     WIDTH 0 0.17 ;
+#  AREA 0.0561 ;         # LI 6
+#  THICKNESS 0.1 ;
+#  EDGECAPACITANCE 40.697E-6 ;
+#  CAPACITANCE CPERSQDIST 36.9866E-6 ;
+ # RESISTANCE RPERSQ 12.2 ;
+
+#  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 75 ) ( 0.0125 75 ) ( 0.0225 85.125 ) ( 22.5 10200 ) ) ;
+#END li1
+
+LAYER mcon
+  TYPE CUT ;
+END mcon
+
+LAYER met1
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+
+  PITCH 0.37 ;
+  MINENCLOSEDAREA 0.14 ;
+  MINWIDTH 0.14 ;
+
+  WIDTH 0.14 ;                     # Met1 1
+  # SPACING 0.14 ;                 # Met1 2
+  # SPACING 0.28 RANGE 3.001 100 ; # Met1 3b
+  SPACINGTABLE
+     PARALLELRUNLENGTH 0
+     WIDTH 0 0.14
+     WIDTH 3 0.28 ;
+  AREA 0.083 ;                     # Met1 6
+  THICKNESS 0.35 ;
+
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
+
+  EDGECAPACITANCE 40.567E-6 ;
+  CAPACITANCE CPERSQDIST 25.7784E-6 ;
+  DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
+  ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
+
+  RESISTANCE RPERSQ 0.125 ;
+END met1
+
+LAYER via
+  TYPE CUT ;
+  WIDTH 0.15 ;                  # Via 1a
+  SPACING 0.17 ;                # Via 2
+  ENCLOSURE BELOW 0.055 0.085 ; # Via 4a / Via 5a
+  ENCLOSURE ABOVE 0.055 0.085 ; # Met2 4 / Met2 5
+
+  ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
+  DCCURRENTDENSITY AVERAGE 0.29 ; # mA per via Iavg_max at Tj = 90oC
+END via
+
+LAYER met2
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+
+  PITCH 0.48 ;
+  MINENCLOSEDAREA 0.14 ;
+  MINWIDTH 0.14 ;
+
+  WIDTH 0.14 ;                        # Met2 1
+  # SPACING  0.14 ;                   # Met2 2
+  # SPACING  0.28 RANGE 3.001 100 ;   # Met2 3b
+  SPACINGTABLE
+     PARALLELRUNLENGTH 0
+     WIDTH 0 0.14
+     WIDTH 3 0.28 ;
+  AREA 0.0676 ;                       # Met2 6
+  THICKNESS 0.35 ;
+
+  EDGECAPACITANCE 37.759E-6 ;
+  CAPACITANCE CPERSQDIST 16.9423E-6 ;
+  RESISTANCE RPERSQ 0.125 ;
+  DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
+  ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
+END met2
+
+# ******** Layer via2, type routing, number 44 **************
+LAYER via2
+  TYPE CUT ;
+  WIDTH 0.2 ;                   # Via2 1
+  SPACING 0.2 ;                 # Via2 2
+  ENCLOSURE BELOW 0.04 0.085 ;  # Via2 4
+  ENCLOSURE ABOVE 0.065 0.065 ; # Met3 4
+  ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
+  DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
+END via2
+
+LAYER met3
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+
+  PITCH 0.74 ;
+  MINWIDTH 0.3 ;
+
+  WIDTH 0.3 ;              # Met3 1
+  # SPACING 0.3 ;          # Met3 2
+  SPACINGTABLE
+     PARALLELRUNLENGTH 0
+     WIDTH 0 0.3
+     WIDTH 3 0.4 ;
+  AREA 0.24 ;              # Met3 6
+  THICKNESS 0.8 ;
+
+  EDGECAPACITANCE 40.989E-6 ;
+  CAPACITANCE CPERSQDIST 12.3729E-6 ;
+  RESISTANCE RPERSQ 0.047 ;
+  DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
+  ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
+
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
+END met3
+
+LAYER via3
+  TYPE CUT ;
+  WIDTH 0.2 ;                   # Via3 1
+  SPACING 0.2 ;                 # Via3 2
+  ENCLOSURE BELOW 0.06 0.09 ;   # Via3 4 / Via3 5
+  ENCLOSURE ABOVE 0.065 0.065 ; # Met4 3
+  ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
+  DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
+END via3
+
+LAYER met4
+  TYPE ROUTING ;
+  DIRECTION VERTICAL ;
+
+  PITCH 0.96 ;
+  MINWIDTH 0.3 ;
+
+  WIDTH 0.3 ;             # Met4 1
+  # SPACING  0.3 ;             # Met4 2
+  SPACINGTABLE
+     PARALLELRUNLENGTH 0
+     WIDTH 0 0.3
+     WIDTH 3 0.4 ;
+  AREA 0.24 ;              # Met4 4a
+
+  THICKNESS 0.8 ;
+
+  EDGECAPACITANCE 36.676E-6 ;
+  CAPACITANCE CPERSQDIST 8.41537E-6 ;
+  RESISTANCE RPERSQ 0.047 ;
+  DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
+  ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
+
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
+END met4
+
+LAYER via4
+  TYPE CUT ;
+
+  WIDTH 0.8 ;                 # Via4 1
+  SPACING 0.8 ;               # Via4 2
+  ENCLOSURE BELOW 0.19 0.19 ; # Via4 4
+  ENCLOSURE ABOVE 0.31 0.31 ; # Met5 3
+  ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
+  DCCURRENTDENSITY AVERAGE 2.49 ; # mA per via Iavg_max at Tj = 90oC
+END via4
+
+LAYER met5
+  TYPE ROUTING ;
+  DIRECTION HORIZONTAL ;
+
+  PITCH 3.33 ;
+  MINWIDTH 1.6 ;
+
+  WIDTH 1.6 ;            # Met5 1
+  #SPACING  1.6 ;        # Met5 2
+  SPACINGTABLE
+     PARALLELRUNLENGTH 0
+     WIDTH 0 1.6 ;
+  AREA 4 ;               # Met5 4
+
+  THICKNESS 1.2 ;
+
+  EDGECAPACITANCE 38.851E-6 ;
+  CAPACITANCE CPERSQDIST 6.32063E-6 ;
+  RESISTANCE RPERSQ 0.0285 ;
+  DCCURRENTDENSITY AVERAGE 10.17 ; # mA/um Iavg_max at Tj = 90oC
+  ACCURRENTDENSITY RMS 22.34 ; # mA/um Irms_max at Tj = 90oC
+
+  ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
+END met5
+
+
+### Routing via cells section   ###
+# Plus via rule, metals are along the prefered direction
+VIA L1M1_PR DEFAULT
+  LAYER mcon ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER li1 ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+  RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR
+
+VIARULE L1M1_PR GENERATE
+  LAYER li1 ;
+  ENCLOSURE 0 0 ;
+  LAYER met1 ;
+  ENCLOSURE 0.06 0.03 ;
+  LAYER mcon ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  SPACING 0.36 BY 0.36 ;
+END L1M1_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA L1M1_PR_R DEFAULT
+  LAYER mcon ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER li1 ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+  RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_R
+
+VIARULE L1M1_PR_R GENERATE
+  LAYER li1 ;
+  ENCLOSURE 0 0 ;
+  LAYER met1 ;
+  ENCLOSURE 0.03 0.06 ;
+  LAYER mcon ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  SPACING 0.36 BY 0.36 ;
+END L1M1_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA L1M1_PR_M DEFAULT
+  LAYER mcon ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER li1 ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+  RECT -0.115 -0.145 0.115 0.145 ;
+END L1M1_PR_M
+
+VIARULE L1M1_PR_M GENERATE
+  LAYER li1 ;
+  ENCLOSURE 0 0 ;
+  LAYER met1 ;
+  ENCLOSURE 0.03 0.06 ;
+  LAYER mcon ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  SPACING 0.36 BY 0.36 ;
+END L1M1_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA L1M1_PR_MR DEFAULT
+  LAYER mcon ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER li1 ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+  RECT -0.145 -0.115 0.145 0.115 ;
+END L1M1_PR_MR
+
+VIARULE L1M1_PR_MR GENERATE
+  LAYER li1 ;
+  ENCLOSURE 0 0 ;
+  LAYER met1 ;
+  ENCLOSURE 0.06 0.03 ;
+  LAYER mcon ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  SPACING 0.36 BY 0.36 ;
+END L1M1_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA L1M1_PR_C DEFAULT
+  LAYER mcon ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER li1 ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  LAYER met1 ;
+  RECT -0.145 -0.145 0.145 0.145 ;
+END L1M1_PR_C
+
+VIARULE L1M1_PR_C GENERATE
+  LAYER li1 ;
+  ENCLOSURE 0 0 ;
+  LAYER met1 ;
+  ENCLOSURE 0.06 0.06 ;
+  LAYER mcon ;
+  RECT -0.085 -0.085 0.085 0.085 ;
+  SPACING 0.36 BY 0.36 ;
+END L1M1_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M1M2_PR DEFAULT
+  LAYER via ;
+  RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met1 ;
+  RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER met2 ;
+  RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR
+
+VIARULE M1M2_PR GENERATE
+  LAYER met1 ;
+  ENCLOSURE 0.085 0.055 ;
+  LAYER met2 ;
+  ENCLOSURE 0.055 0.085 ;
+  LAYER via ;
+  RECT -0.075 -0.075 0.075 0.075 ;
+  SPACING 0.32 BY 0.32 ;
+END M1M2_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M1M2_PR_R DEFAULT
+  LAYER via ;
+  RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met1 ;
+  RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER met2 ;
+  RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_R
+
+VIARULE M1M2_PR_R GENERATE
+  LAYER met1 ;
+  ENCLOSURE 0.055 0.085 ;
+  LAYER met2 ;
+  ENCLOSURE 0.085 0.055 ;
+  LAYER via ;
+  RECT -0.075 -0.075 0.075 0.075 ;
+  SPACING 0.32 BY 0.32 ;
+END M1M2_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M1M2_PR_M DEFAULT
+  LAYER via ;
+  RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met1 ;
+  RECT -0.16 -0.13 0.16 0.13 ;
+  LAYER met2 ;
+  RECT -0.16 -0.13 0.16 0.13 ;
+END M1M2_PR_M
+
+VIARULE M1M2_PR_M GENERATE
+  LAYER met1 ;
+  ENCLOSURE 0.085 0.055 ;
+  LAYER met2 ;
+  ENCLOSURE 0.085 0.055 ;
+  LAYER via ;
+  RECT -0.075 -0.075 0.075 0.075 ;
+  SPACING 0.32 BY 0.32 ;
+END M1M2_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M1M2_PR_MR DEFAULT
+  LAYER via ;
+  RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met1 ;
+  RECT -0.13 -0.16 0.13 0.16 ;
+  LAYER met2 ;
+  RECT -0.13 -0.16 0.13 0.16 ;
+END M1M2_PR_MR
+
+VIARULE M1M2_PR_MR GENERATE
+  LAYER met1 ;
+  ENCLOSURE 0.055 0.085 ;
+  LAYER met2 ;
+  ENCLOSURE 0.055 0.085 ;
+  LAYER via ;
+  RECT -0.075 -0.075 0.075 0.075 ;
+  SPACING 0.32 BY 0.32 ;
+END M1M2_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M1M2_PR_C DEFAULT
+  LAYER via ;
+  RECT -0.075 -0.075 0.075 0.075 ;
+  LAYER met1 ;
+  RECT -0.16 -0.16 0.16 0.16 ;
+  LAYER met2 ;
+  RECT -0.16 -0.16 0.16 0.16 ;
+END M1M2_PR_C
+
+VIARULE M1M2_PR_C GENERATE
+  LAYER met1 ;
+  ENCLOSURE 0.085 0.085 ;
+  LAYER met2 ;
+  ENCLOSURE 0.085 0.085 ;
+  LAYER via ;
+  RECT -0.075 -0.075 0.075 0.075 ;
+  SPACING 0.32 BY 0.32 ;
+END M1M2_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M2M3_PR DEFAULT
+  LAYER via2 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met2 ;
+  RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER met3 ;
+  RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR
+
+VIARULE M2M3_PR GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.04 0.085 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065 0.065 ;
+  LAYER via2 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  SPACING 0.4 BY 0.4 ;
+END M2M3_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M2M3_PR_R DEFAULT
+  LAYER via2 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met2 ;
+  RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER met3 ;
+  RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_R
+
+VIARULE M2M3_PR_R GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.085 0.04 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065 0.065 ;
+  LAYER via2 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  SPACING 0.4 BY 0.4 ;
+END M2M3_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M2M3_PR_M DEFAULT
+  LAYER via2 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met2 ;
+  RECT -0.14 -0.185 0.14 0.185 ;
+  LAYER met3 ;
+  RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_M
+
+VIARULE M2M3_PR_M GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.04 0.085 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065 0.065 ;
+  LAYER via2 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  SPACING 0.4 BY 0.4 ;
+END M2M3_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M2M3_PR_MR DEFAULT
+  LAYER via2 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met2 ;
+  RECT -0.185 -0.14 0.185 0.14 ;
+  LAYER met3 ;
+  RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_MR
+
+VIARULE M2M3_PR_MR GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.085 0.04 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065 0.065 ;
+  LAYER via2 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  SPACING 0.4 BY 0.4 ;
+END M2M3_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M2M3_PR_C DEFAULT
+  LAYER via2 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met2 ;
+  RECT -0.185 -0.185 0.185 0.185 ;
+  LAYER met3 ;
+  RECT -0.165 -0.165 0.165 0.165 ;
+END M2M3_PR_C
+
+VIARULE M2M3_PR_C GENERATE
+  LAYER met2 ;
+  ENCLOSURE 0.085 0.085 ;
+  LAYER met3 ;
+  ENCLOSURE 0.065 0.065 ;
+  LAYER via2 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  SPACING 0.4 BY 0.4 ;
+END M2M3_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M3M4_PR DEFAULT
+  LAYER via3 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+  RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER met4 ;
+  RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR
+
+VIARULE M3M4_PR GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.09 0.06 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065 0.065 ;
+  LAYER via3 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  SPACING 0.4 BY 0.4 ;
+END M3M4_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M3M4_PR_R DEFAULT
+  LAYER via3 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+  RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER met4 ;
+  RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_R
+
+VIARULE M3M4_PR_R GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.06 0.09 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065 0.065 ;
+  LAYER via3 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  SPACING 0.4 BY 0.4 ;
+END M3M4_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M3M4_PR_M DEFAULT
+  LAYER via3 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+  RECT -0.19 -0.16 0.19 0.16 ;
+  LAYER met4 ;
+  RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_M
+
+VIARULE M3M4_PR_M GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.09 0.06 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065 0.065 ;
+  LAYER via3 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  SPACING 0.4 BY 0.4 ;
+END M3M4_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M3M4_PR_MR DEFAULT
+  LAYER via3 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+  RECT -0.16 -0.19 0.16 0.19 ;
+  LAYER met4 ;
+  RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_MR
+
+VIARULE M3M4_PR_MR GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.06 0.09 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065 0.065 ;
+  LAYER via3 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  SPACING 0.4 BY 0.4 ;
+END M3M4_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M3M4_PR_C DEFAULT
+  LAYER via3 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  LAYER met3 ;
+  RECT -0.19 -0.19 0.19 0.19 ;
+  LAYER met4 ;
+  RECT -0.165 -0.165 0.165 0.165 ;
+END M3M4_PR_C
+
+VIARULE M3M4_PR_C GENERATE
+  LAYER met3 ;
+  ENCLOSURE 0.09 0.09 ;
+  LAYER met4 ;
+  ENCLOSURE 0.065 0.065 ;
+  LAYER via3 ;
+  RECT -0.1 -0.1 0.1 0.1 ;
+  SPACING 0.4 BY 0.4 ;
+END M3M4_PR_C
+
+# Plus via rule, metals are along the prefered direction
+VIA M4M5_PR DEFAULT
+  LAYER via4 ;
+  RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met4 ;
+  RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER met5 ;
+  RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR
+
+VIARULE M4M5_PR GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.19 0.19 ;
+  LAYER met5 ;
+  ENCLOSURE 0.31 0.31 ;
+  LAYER via4 ;
+  RECT -0.4 -0.4 0.4 0.4 ;
+  SPACING 1.6 BY 1.6 ;
+END M4M5_PR
+
+# Plus via rule, metals are along the non prefered direction
+VIA M4M5_PR_R DEFAULT
+  LAYER via4 ;
+  RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met4 ;
+  RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER met5 ;
+  RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_R
+
+VIARULE M4M5_PR_R GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.19 0.19 ;
+  LAYER met5 ;
+  ENCLOSURE 0.31 0.31 ;
+  LAYER via4 ;
+  RECT -0.4 -0.4 0.4 0.4 ;
+  SPACING 1.6 BY 1.6 ;
+END M4M5_PR_R
+
+# Minus via rule, lower layer metal is along prefered direction
+VIA M4M5_PR_M DEFAULT
+  LAYER via4 ;
+  RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met4 ;
+  RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER met5 ;
+  RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_M
+
+VIARULE M4M5_PR_M GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.19 0.19 ;
+  LAYER met5 ;
+  ENCLOSURE 0.31 0.31 ;
+  LAYER via4 ;
+  RECT -0.4 -0.4 0.4 0.4 ;
+  SPACING 1.6 BY 1.6 ;
+END M4M5_PR_M
+
+# Minus via rule, upper layer metal is along prefered direction
+VIA M4M5_PR_MR DEFAULT
+  LAYER via4 ;
+  RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met4 ;
+  RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER met5 ;
+  RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_MR
+
+VIARULE M4M5_PR_MR GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.19 0.19 ;
+  LAYER met5 ;
+  ENCLOSURE 0.31 0.31 ;
+  LAYER via4 ;
+  RECT -0.4 -0.4 0.4 0.4 ;
+  SPACING 1.6 BY 1.6 ;
+END M4M5_PR_MR
+
+# Centered via rule, we really do not want to use it
+VIA M4M5_PR_C DEFAULT
+  LAYER via4 ;
+  RECT -0.4 -0.4 0.4 0.4 ;
+  LAYER met4 ;
+  RECT -0.59 -0.59 0.59 0.59 ;
+  LAYER met5 ;
+  RECT -0.71 -0.71 0.71 0.71 ;
+END M4M5_PR_C
+
+VIARULE M4M5_PR_C GENERATE
+  LAYER met4 ;
+  ENCLOSURE 0.19 0.19 ;
+  LAYER met5 ;
+  ENCLOSURE 0.31 0.31 ;
+  LAYER via4 ;
+  RECT -0.4 -0.4 0.4 0.4 ;
+  SPACING 1.6 BY 1.6 ;
+END M4M5_PR_C
+###  end of single via cells   ###
+
+END LIBRARY
diff --git a/char/techfiles/special_cells b/char/techfiles/special_cells
new file mode 100755
index 0000000..191a0a0
--- /dev/null
+++ b/char/techfiles/special_cells
@@ -0,0 +1,23 @@
+#!/bin/bash
+
+unfinished_cells=""
+physical_cells="DECAPXL DECAPX1 FILLX1 FILLX2 FILLX4 FILLX8 FILLX16 FILLX32"
+test_cells="test final"
+
+res="s/\("
+for x in ${unfinished_cells}; do res="${res}${x}\\|"; done
+for x in ${test_cells}; do res="${res}${x}\\|"; done
+
+if [ $1 == "-lef_gen" ]
+then
+true
+fi
+
+if [ $1 == "-libchar" ]
+then
+for x in ${physical_cells}; do res="${res}${x}\\|"; done
+fi
+
+res="${res}nosuchfile\\)[^ ]*//g"
+
+echo ${res}
diff --git a/disclaimer.txt b/disclaimer.txt
deleted file mode 100644
index 568f0cd..0000000
--- a/disclaimer.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-James E. Stine, Jr., Ph.D.

-Earl and Caronlyn Glimp Professor

-Oklahoma State University

-Electrical and Computer Engineering Deapartment

-VLSI Computer Architecture Research Group

-

-Re:  Work with Google/SkyWater/eFabless Technologies

-

-We are currently working with Google (www.google.com), Skywater

-Technologies (www.skywatertechnology.com) in Bloomington, MN and

-eFabless (efabless.com) in San Jose, CA.  For this project, we are

-creating software that allows integrated circuits to be created using

-something called standard-cell libraries

-(en.wikipedia.org/wiki/Standard_cell).

-

-These cells allow digital logic designs (e.g., microprocessors) to be

-fabricated and operate at a certain speeds or frequencies (i.e., Mhz).

-Based on the current assessment of our library, it appears that we can

-create microprocessors from this library that operate approximately at

-350MHz or more.  We believe the classification of this technology to

-fall within the 3A001 ECCN of the EAR.

-

-The United States through the Export Administration Regulations (EAR)

-has specific classification laws that relate to microprocessors,

-circuits, and communication devices.  They specifically state in their

-document "Commerce Control List, Supplement No. 1 Part 774, Dated May

-23, 2019" the following:

-

-"Microprocessor microcircuits, microcomputer microcircuits and

-microcontroller microcircuits, manufactured from a compound

-semiconductor and operating at a clock frequency exceeding 40 MHz"

-

-The library and any work that Oklahoma State University provides

-should only be utilized within the guidelines defined by the EAR as

-regulated by the United States Department of Commerce and distributed

-to those involved who understand that this library is only utilized

-for educational/academic intentions.

-

-

-

-

diff --git a/flow/pnr/.gitignore b/flow/pnr/.gitignore
new file mode 100644
index 0000000..4fde0b3
--- /dev/null
+++ b/flow/pnr/.gitignore
@@ -0,0 +1,11 @@
+innovus.logv*
+innovus.log*
+innovus.cmd*
+LOG
+DBS
+RPT
+FF
+timingReports
+mult_pad_via_layer*
+make
+checkDesign
diff --git a/flow/pnr/COPYRIGHT b/flow/pnr/COPYRIGHT
new file mode 100755
index 0000000..7c5e172
--- /dev/null
+++ b/flow/pnr/COPYRIGHT
@@ -0,0 +1,33 @@
+###############################################################################
+#                       CADENCE COPYRIGHT NOTICE
+#         © 2008-2013 Cadence Design Systems, Inc. All rights reserved.
+#------------------------------------------------------------------------------
+#
+# This Foundation Flow is provided as an example of how to perform specialized
+# tasks.
+#
+# This work may not be copied, re-published, uploaded, or distributed in any way,
+# in any medium, whether in whole or in part, without prior written permission
+# from Cadence. Notwithstanding any restrictions herein, subject to compliance
+# with the terms and conditions of the Cadence software license agreement under
+# which this material was provided, this material may be copied and internally
+# distributed solely for internal purposes for use with Cadence tools.
+#
+# This work is Cadence intellectual property and may under no circumstances be
+# given to third parties, neither in original nor in modified versions, without
+# explicit written permission from Cadence. The information contained herein is
+# the proprietary and confidential information of Cadence or its licensors, and
+# is supplied subject to, and may be used only by Cadence's current customers
+# in accordance with, a previously executed license agreement between Cadence
+# and its customer.
+#
+#------------------------------------------------------------------------------
+# THIS MATERIAL IS PROVIDED BY CADENCE "AS IS" AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+# IN NO EVENT SHALL CADENCE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL
+# OR CONSEQUENTIAL DAMAGES HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT  (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS  MATERIAL, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+###############################################################################
diff --git a/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/hier.fp b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/hier.fp
new file mode 100755
index 0000000..ecd0b13
--- /dev/null
+++ b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/hier.fp
@@ -0,0 +1,1972 @@
+###############################################################
+#  Generated by:      Cadence Encounter 11.11-e047_1
+#  OS:                Linux x86_64(Host ID sjfnl688)
+#  Generated on:      Tue Mar 20 08:24:26 2012
+#  Design:            tdsp_core
+#  Command:           saveFPlan hier.fp
+###############################################################
+
+Version: 8
+
+Head Box: 0.0000 0.0000 141.8000 153.9000
+IO Box: 0.0000 0.0000 141.8000 153.9000
+Core Box: 0.0000 0.0000 141.8000 153.9000
+UseStdUtil: false
+
+######################################################
+#  DesignRoutingHalo: <space> <bottomLayerName> <topLayerName>
+######################################################
+
+######################################################
+#  Core Rows Parameters:                             #
+######################################################
+Row Spacing = 0.000000
+Row SpacingType = 0
+Row Flip = 1
+Core Row Site: CoreSite 
+
+##############################################################################
+#  DefRow: <name> <site> <x> <y> <orient> <num_x> <num_y> <step_x> <step_y>  #
+##############################################################################
+DefRow: ROW_89 CoreSite 0.0000 152.1900 FS 709 1 0.2000 0.0000
+DefRow: ROW_88 CoreSite 0.0000 150.4800 N 709 1 0.2000 0.0000
+DefRow: ROW_87 CoreSite 0.0000 148.7700 FS 709 1 0.2000 0.0000
+DefRow: ROW_86 CoreSite 0.0000 147.0600 N 709 1 0.2000 0.0000
+DefRow: ROW_85 CoreSite 0.0000 145.3500 FS 709 1 0.2000 0.0000
+DefRow: ROW_84 CoreSite 0.0000 143.6400 N 709 1 0.2000 0.0000
+DefRow: ROW_83 CoreSite 0.0000 141.9300 FS 709 1 0.2000 0.0000
+DefRow: ROW_82 CoreSite 0.0000 140.2200 N 709 1 0.2000 0.0000
+DefRow: ROW_81 CoreSite 0.0000 138.5100 FS 709 1 0.2000 0.0000
+DefRow: ROW_80 CoreSite 0.0000 136.8000 N 709 1 0.2000 0.0000
+DefRow: ROW_79 CoreSite 0.0000 135.0900 FS 709 1 0.2000 0.0000
+DefRow: ROW_78 CoreSite 0.0000 133.3800 N 709 1 0.2000 0.0000
+DefRow: ROW_77 CoreSite 0.0000 131.6700 FS 709 1 0.2000 0.0000
+DefRow: ROW_76 CoreSite 0.0000 129.9600 N 709 1 0.2000 0.0000
+DefRow: ROW_75 CoreSite 0.0000 128.2500 FS 709 1 0.2000 0.0000
+DefRow: ROW_74 CoreSite 0.0000 126.5400 N 709 1 0.2000 0.0000
+DefRow: ROW_73 CoreSite 0.0000 124.8300 FS 709 1 0.2000 0.0000
+DefRow: ROW_72 CoreSite 0.0000 123.1200 N 709 1 0.2000 0.0000
+DefRow: ROW_71 CoreSite 0.0000 121.4100 FS 709 1 0.2000 0.0000
+DefRow: ROW_70 CoreSite 0.0000 119.7000 N 709 1 0.2000 0.0000
+DefRow: ROW_69 CoreSite 0.0000 117.9900 FS 709 1 0.2000 0.0000
+DefRow: ROW_68 CoreSite 0.0000 116.2800 N 709 1 0.2000 0.0000
+DefRow: ROW_67 CoreSite 0.0000 114.5700 FS 709 1 0.2000 0.0000
+DefRow: ROW_66 CoreSite 0.0000 112.8600 N 709 1 0.2000 0.0000
+DefRow: ROW_65 CoreSite 0.0000 111.1500 FS 709 1 0.2000 0.0000
+DefRow: ROW_64 CoreSite 0.0000 109.4400 N 709 1 0.2000 0.0000
+DefRow: ROW_63 CoreSite 0.0000 107.7300 FS 709 1 0.2000 0.0000
+DefRow: ROW_62 CoreSite 0.0000 106.0200 N 709 1 0.2000 0.0000
+DefRow: ROW_61 CoreSite 0.0000 104.3100 FS 709 1 0.2000 0.0000
+DefRow: ROW_60 CoreSite 0.0000 102.6000 N 709 1 0.2000 0.0000
+DefRow: ROW_59 CoreSite 0.0000 100.8900 FS 709 1 0.2000 0.0000
+DefRow: ROW_58 CoreSite 0.0000 99.1800 N 709 1 0.2000 0.0000
+DefRow: ROW_57 CoreSite 0.0000 97.4700 FS 709 1 0.2000 0.0000
+DefRow: ROW_56 CoreSite 0.0000 95.7600 N 709 1 0.2000 0.0000
+DefRow: ROW_55 CoreSite 0.0000 94.0500 FS 709 1 0.2000 0.0000
+DefRow: ROW_54 CoreSite 0.0000 92.3400 N 709 1 0.2000 0.0000
+DefRow: ROW_53 CoreSite 0.0000 90.6300 FS 709 1 0.2000 0.0000
+DefRow: ROW_52 CoreSite 0.0000 88.9200 N 709 1 0.2000 0.0000
+DefRow: ROW_51 CoreSite 0.0000 87.2100 FS 709 1 0.2000 0.0000
+DefRow: ROW_50 CoreSite 0.0000 85.5000 N 709 1 0.2000 0.0000
+DefRow: ROW_49 CoreSite 0.0000 83.7900 FS 709 1 0.2000 0.0000
+DefRow: ROW_48 CoreSite 0.0000 82.0800 N 709 1 0.2000 0.0000
+DefRow: ROW_47 CoreSite 0.0000 80.3700 FS 709 1 0.2000 0.0000
+DefRow: ROW_46 CoreSite 0.0000 78.6600 N 709 1 0.2000 0.0000
+DefRow: ROW_45 CoreSite 0.0000 76.9500 FS 709 1 0.2000 0.0000
+DefRow: ROW_44 CoreSite 0.0000 75.2400 N 709 1 0.2000 0.0000
+DefRow: ROW_43 CoreSite 0.0000 73.5300 FS 709 1 0.2000 0.0000
+DefRow: ROW_42 CoreSite 0.0000 71.8200 N 709 1 0.2000 0.0000
+DefRow: ROW_41 CoreSite 0.0000 70.1100 FS 709 1 0.2000 0.0000
+DefRow: ROW_40 CoreSite 0.0000 68.4000 N 709 1 0.2000 0.0000
+DefRow: ROW_39 CoreSite 0.0000 66.6900 FS 709 1 0.2000 0.0000
+DefRow: ROW_38 CoreSite 0.0000 64.9800 N 709 1 0.2000 0.0000
+DefRow: ROW_37 CoreSite 0.0000 63.2700 FS 709 1 0.2000 0.0000
+DefRow: ROW_36 CoreSite 0.0000 61.5600 N 709 1 0.2000 0.0000
+DefRow: ROW_35 CoreSite 0.0000 59.8500 FS 709 1 0.2000 0.0000
+DefRow: ROW_34 CoreSite 0.0000 58.1400 N 709 1 0.2000 0.0000
+DefRow: ROW_33 CoreSite 0.0000 56.4300 FS 709 1 0.2000 0.0000
+DefRow: ROW_32 CoreSite 0.0000 54.7200 N 709 1 0.2000 0.0000
+DefRow: ROW_31 CoreSite 0.0000 53.0100 FS 709 1 0.2000 0.0000
+DefRow: ROW_30 CoreSite 0.0000 51.3000 N 709 1 0.2000 0.0000
+DefRow: ROW_29 CoreSite 0.0000 49.5900 FS 709 1 0.2000 0.0000
+DefRow: ROW_28 CoreSite 0.0000 47.8800 N 709 1 0.2000 0.0000
+DefRow: ROW_27 CoreSite 0.0000 46.1700 FS 709 1 0.2000 0.0000
+DefRow: ROW_26 CoreSite 0.0000 44.4600 N 709 1 0.2000 0.0000
+DefRow: ROW_25 CoreSite 0.0000 42.7500 FS 709 1 0.2000 0.0000
+DefRow: ROW_24 CoreSite 0.0000 41.0400 N 709 1 0.2000 0.0000
+DefRow: ROW_23 CoreSite 0.0000 39.3300 FS 709 1 0.2000 0.0000
+DefRow: ROW_22 CoreSite 0.0000 37.6200 N 709 1 0.2000 0.0000
+DefRow: ROW_21 CoreSite 0.0000 35.9100 FS 709 1 0.2000 0.0000
+DefRow: ROW_20 CoreSite 0.0000 34.2000 N 709 1 0.2000 0.0000
+DefRow: ROW_19 CoreSite 0.0000 32.4900 FS 709 1 0.2000 0.0000
+DefRow: ROW_18 CoreSite 0.0000 30.7800 N 709 1 0.2000 0.0000
+DefRow: ROW_17 CoreSite 0.0000 29.0700 FS 709 1 0.2000 0.0000
+DefRow: ROW_16 CoreSite 0.0000 27.3600 N 709 1 0.2000 0.0000
+DefRow: ROW_15 CoreSite 0.0000 25.6500 FS 709 1 0.2000 0.0000
+DefRow: ROW_14 CoreSite 0.0000 23.9400 N 709 1 0.2000 0.0000
+DefRow: ROW_13 CoreSite 0.0000 22.2300 FS 709 1 0.2000 0.0000
+DefRow: ROW_12 CoreSite 0.0000 20.5200 N 709 1 0.2000 0.0000
+DefRow: ROW_11 CoreSite 0.0000 18.8100 FS 709 1 0.2000 0.0000
+DefRow: ROW_10 CoreSite 0.0000 17.1000 N 709 1 0.2000 0.0000
+DefRow: ROW_9 CoreSite 0.0000 15.3900 FS 709 1 0.2000 0.0000
+DefRow: ROW_8 CoreSite 0.0000 13.6800 N 709 1 0.2000 0.0000
+DefRow: ROW_7 CoreSite 0.0000 11.9700 FS 709 1 0.2000 0.0000
+DefRow: ROW_6 CoreSite 0.0000 10.2600 N 709 1 0.2000 0.0000
+DefRow: ROW_5 CoreSite 0.0000 8.5500 FS 709 1 0.2000 0.0000
+DefRow: ROW_4 CoreSite 0.0000 6.8400 N 709 1 0.2000 0.0000
+DefRow: ROW_3 CoreSite 0.0000 5.1300 FS 709 1 0.2000 0.0000
+DefRow: ROW_2 CoreSite 0.0000 3.4200 N 709 1 0.2000 0.0000
+DefRow: ROW_1 CoreSite 0.0000 1.7100 FS 709 1 0.2000 0.0000
+DefRow: ROW_0 CoreSite 0.0000 0.0000 N 709 1 0.2000 0.0000
+
+######################################################
+#  Track: dir start number space layer_num layer1 ...#
+######################################################
+Track: X 0.1000 709 0.2000 1 9
+Track: Y 0.4750 404 0.3800 1 9
+Track: Y 0.3800 539 0.2850 1 8
+Track: X 0.1000 709 0.2000 1 8
+Track: X 0.1000 709 0.2000 1 7
+Track: Y 0.3800 539 0.2850 1 7
+Track: Y 0.0950 810 0.1900 1 6
+Track: X 0.1000 709 0.2000 1 6
+Track: X 0.1000 709 0.2000 1 5
+Track: Y 0.0950 810 0.1900 1 5
+Track: Y 0.0950 810 0.1900 1 4
+Track: X 0.1000 709 0.2000 1 4
+Track: X 0.1000 709 0.2000 1 3
+Track: Y 0.0950 810 0.1900 1 3
+Track: Y 0.0950 810 0.1900 1 2
+Track: X 0.1000 709 0.2000 1 2
+Track: X 0.1000 709 0.2000 1 1
+Track: Y 0.0950 810 0.1900 1 1
+
+######################################################
+#  GCellGrid: dir start number space                 #
+######################################################
+GCellGrid: Y 0.0000 2 1.8950
+GCellGrid: Y 1.8950 73 2.1000
+GCellGrid: Y 153.0950 2 0.8050
+GCellGrid: X 0.0000 2 1.9300
+GCellGrid: X 1.9300 67 2.1000
+GCellGrid: X 140.5300 2 1.2700
+
+######################################################
+#  SpareCell: cellName                               #
+#  SpareInst: instName                               #
+######################################################
+
+###############################1p########################
+#  <SelectiveBlockage>                                #
+#     <cell name="cell_name" />                     #
+#  </SelectiveBlockage                                #
+#######################################################
+
+######################################################
+#  ScanGroup: groupName startPin stopPin             #
+######################################################
+
+######################################################
+#  JtagCell:  leafCellName                           #
+#  JtagInst:  <instName | HInstName>                 #
+######################################################
+
+######################################################################################
+#  BlackBox: -cell <cell_name> { -size <x> <y> |  -area <um^2> | \                  #
+#            -gatecount <count> <areapergate> <utilization> | \                     #
+#            {-gateArea <gateAreaValue> [-macroArea <macroAreaValue>]} } \          #
+#            [-minwidth <w> | -minheight <h> | -fixedwidh <w> | -fixedheight <h>] \ #
+#            [-aspectratio <ratio>]                                                  #
+#            [-boxList <nrConstraintBox>                                             #
+#              ConstraintBox: <llx> <lly> <urx> <ury>                                #
+#              ... ]                                                                 #
+######################################################################################
+
+#######################################################################################
+#  <Blackboxes>                                                                       #
+#     <Blackbox  cell=name  width=N height=N                                          #
+#                { area=A | gatecount=N areaPerGate=A cellUtil=F |                    #
+#                  gateArea=F {macroArea=F | macorList='str'} includeMacroArea={0|1}} #
+#                [minWidth=N | minHeight=N | fixedWidh=N | fixedHeight=N]             #
+#                [aspectRatio=R] >                                                    #
+#         <Box llx=float lly=float urx=float ury=float /> ...                         #
+#     </Blackbox>                                                                     #
+#  </Blackboxes>                                                                      #
+#######################################################################################
+
+#########################################################
+#  PhysicalNet: <name> [-pwr|-gnd|-tiehi|-tielo]        #
+#########################################################
+PhysicalNet: VDD -pwr
+PhysicalNet: AVdd -pwr
+PhysicalNet: VSS -gnd
+PhysicalNet: AVss -gnd
+PhysicalNet: Avdd -pwr
+PhysicalNet: Avss -gnd
+
+#########################################################
+#  PhysicalInstance: <name> <cell> <orient> <llx> <lly> #
+#########################################################
+
+#####################################################################
+#  Group: <group_name> <nrHinst> [-isPhyHier]                       #
+#    <inst_name>                                                    #
+#    ...                                                            #
+#####################################################################
+
+#####################################################################
+#  Fence:  <name> <llx> <lly> <urx> <ury> <nrConstraintBox>         #
+#    ConstraintBox: <llx> <lly> <urx> <ury>                         #
+#    ...                                                            #
+#  Region: <name> <llx> <lly> <urx> <ury> <nrConstraintBox>         #
+#    ConstraintBox: <llx> <lly> <urx> <ury>                         #
+#    ...                                                            #
+#  Guide:  <name> <llx> <lly> <urx> <ury> <nrConstraintBox>         #
+#    ConstraintBox: <llx> <lly> <urx> <ury>                         #
+#    ...                                                            #
+#  SoftGuide: <name>                                                #
+#    ...                                                            #
+#####################################################################
+Fence: MPY_32_INST 0.8000 0.0000 82.4000 88.9200 0
+
+###########################################################################
+#  <Constraints>                                                          #
+#     <Constraint  type="fence|guide|region|softguide"                    #
+#                  readonly=1  name="blk_name">                           #
+#       <Box llx=1 lly=2 urx=3 ury=4 /> ...                               #
+#     </Constraint>                                                       #
+#  </Constraints>                                                         #
+###########################################################################
+<Constraints>
+    <Constraint type="Fence" name="MPY_32_INST" llx=0.8000 lly=0.0000 urx=82.4000 ury=88.9200 nrBox=0 >
+    </Constraint>
+</Constraints>
+
+###########################################################################
+#  <HierarchicalPartitions>                                               #
+#     <NetGroup name="group_name" nets=val spacing=val isOptOrder=val     #
+#         isAltLayer=val isPffGroup=val isSpreadPin=val                   #
+#         isExcludeAllLayer=val isExcludeSameLayer=val >                  #
+#         <Net name="net_name" /> ...                                     #
+#     </NetGroup>                                                         #
+#     <Partition name="ptn_name"  hinst="name"                            #
+#         coreToLeft=fval coreToRight=fval coreToTop=fval                 #
+#         coreToBottom=val pinSpacingNorth=val pinSpacingWest=val         #
+#         pinSpacingSouth=val pinSpacingEast=val  blockedLayers=xval >    #
+#         <TrackHalfPitch Horizontal=val Vertical=val />                  #
+#         <SpacingHalo left=10.0 right=11.0 top=11.0 bottom=11.0 />       #
+#         <Clone hinst="hinst_name" orient=R0|R90|... />                  #
+#         <PinLayer side="N|W|S|E" Metal1=yes Metal2=yes ... />           #
+#         <RowSize cellHeight=1.0 railWidth=1.0 />                        #
+#         <RoutingHalo sideSize=11.0 bottomLayer=M1 topLayer=M2  />       #
+#         <SpacingHalo left=11.0 right=11.0 top=11.0 bottom=11.0 />       #
+#     </Partition>                                                        #
+#     <CellPinGroup name="group_name" cell="cell_name" pins=nr            #
+#         spacing=val isOptOrder=val isAltLayer=val isSpreadPin=val       #
+#         isExcludeAllLayer=val isExcludeSameLayer=val >                  #
+#         <GroupFTerm name="term_name" /> ...                             #
+#     </CellPinGroup>                                                     #
+#     <PartitionPinBlockage layerMap=x llx=1 lly=2 urx=3 ury=4 name="n" />#
+#     <PinGuide name="name" boxes=num layerPriority=val cell="name" >     #
+#        <Box llx=11.0 lly=22.0 urx=33.0 ury=44.0 layer=id /> ...         #
+#     </PinGuide>                                                         #
+#     <CellPtnCut name="name" cuts=Num >                                  #
+#        <Box llx=11.0 lly=22.0 urx=33.0 ury=44.0 /> ...                  #
+#     </CellPtnCut>                                                       #
+#  </HierarchicalPartitions>                                              #
+###########################################################################
+<HierarchicalPartitions>
+    <TrackHalfPitch Horizontal=0 Vertical=1 />
+    <Partition name="mult_32" hinst="MPY_32_INST" coreToLeft=0.0000 coreToRight=0.0000 coreToTop=0.0000 coreToBottom=0.0000 pinSpacingNorth=2 pinSpacingWest=2 pinSpacingSouth=2 pinSpacingEast=2 blockedLayers=0x1ff >
+	<PinLayer side="N" Metal2=yes Metal4=yes Metal6=yes />
+	<PinLayer side="W" Metal3=yes Metal5=yes />
+	<PinLayer side="S" Metal2=yes Metal4=yes Metal6=yes />
+	<PinLayer side="E" Metal3=yes Metal5=yes />
+	<RowSize cellHeight=1.7100 railWidth=0.0000 />
+    </Partition>
+    <Partition name="tdsp_core" hinst="" coreToLeft=0.0000 coreToRight=0.0000 coreToTop=0.0000 coreToBottom=0.0000 pinSpacingNorth=2 pinSpacingWest=2 pinSpacingSouth=2 pinSpacingEast=2 blockedLayers=0x1ff >
+	<PinLayer side="N" Metal2=yes Metal4=yes Metal6=yes />
+	<PinLayer side="W" Metal3=yes Metal5=yes />
+	<PinLayer side="S" Metal2=yes Metal4=yes Metal6=yes />
+	<PinLayer side="E" Metal3=yes Metal5=yes />
+	<RowSize cellHeight=1.7100 railWidth=0.0000 />
+    </Partition>
+</HierarchicalPartitions>
+
+######################################################
+#  Instance: <name> <orient> <llx> <lly>             #
+######################################################
+
+#################################################################
+#  Block: <name> <orient> [<llx> <lly>]                         #
+#         [<haloLeftMargin>  <haloBottomMargin>                 #
+#          <haloRightMargin> <haloTopMargin> <haloFromInstBox>] #
+#         [<IsInstDefCovered> <IsInstPreplaced>]                #
+#                                                               #
+#  Block with INT_MAX loc is for recording the halo block with  #
+#  non-prePlaced status                                         #
+#################################################################
+
+######################################################
+#  BlockLayerObstruct: <name> <layerX> ...           #
+######################################################
+
+######################################################
+#  FeedthroughBuffer: <instName>                     #
+######################################################
+
+#################################################################
+#  <PlacementBlockages>                                         #
+#     <Blockage name="blk_name" type="hard|soft|partial">       #
+#       <Attr density=1.2 inst="inst_name" pushdown=yes />      #
+#       <Box llx=1 lly=2 urx=3 ury=4 /> ...                     #
+#     </Blockage>                                               #
+#  </PlacementBlockages>                                        #
+#################################################################
+
+#################################################################
+#  <SizeBlockages>                                             #
+#     <Blockage name="blk_name">                              #
+#       <Box llx=1 lly=2 urx=3 ury=4 /> ...                     #
+#     </Blockage>                                               #
+#  </SizeBlockages>                                            #
+#################################################################
+
+###########################################################################
+#  <RouteBlockages>                                                       #
+#     <Blockage name="blk_name" type="User|RouteGuide|PtnCut|WideWire">   #
+#       <Attr spacing=1.2 drw=1.2 inst="name" pushdown=yes fills=yes />   #
+#       <Layer type="route|cut|masterslice" id=layerNo />                 #
+#       <Box llx=1 lly=2 urx=3 ury=4 /> ...                               #
+#       <Poly points=nr x0=1 y0=1 x1=2 y2=2 ...  />                       #
+#     </Blockage>                                                         #
+#  </RouteBlockages>                                                      #
+###########################################################################
+
+######################################################
+#  PrerouteAsObstruct: <layer_treated_as_obstruct>   #
+######################################################
+PrerouteAsObstruct: 0x3
+
+######################################################
+#  NetWeight: <net_name> <weight (in integer)>       #
+######################################################
+
+#################################################################
+#  SprFile: <file_name>                                         #
+#################################################################
+SprFile: hier.fp.spr
+
+##############################################################################
+#  <IOPins>                                                                  #
+#    <Pin name="pin_name" type="clock|power|ground|analog"                   #
+#         status="covered|fixed|placed" is_special=1 >                       #
+#      <Port>                                                                #
+#        <Pref x=1 y=2 side="N|S|W|E|U|D" width=w depth=d orientation=val /> #
+#        <Via name="via_name" x=1 y=2 />...                                  #
+#        <Layer id=id spacing=1.2 drw=1.2>                                   #
+#          <Box llx=1 lly=2 urx=3 ury=4 /> ...                               #
+#          <Poly points=nr x0=1 y0=1 x1=2 y2=2 ...           />              #
+#        </Layer> ...                                                        #
+#      </Port>  ...                                                          #
+#      <Antenna model=num type="name" value=float_num layer=num /> ...       #
+#    </Pin> ...                                                              #
+#  </IOPins>                                                                 #
+##############################################################################
+
+<IOPins>
+  <Pin name="clk" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=108.7750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=108.7400 urx=0.2900 ury=108.8100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="reset" status="fixed" >
+    <Port>
+      <Pref x=14.7000 y=0.0000 side=S width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=14.6650 lly=0.0000 urx=14.7350 ury=0.2900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="as" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=132.5250 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=132.4900 urx=0.2900 ury=132.5600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="read" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=130.8150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=130.7800 urx=0.2900 ury=130.8500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="write" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=127.3950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=127.3600 urx=0.2900 ury=127.4300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="write_h" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=77.0450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=77.0100 urx=0.2900 ury=77.0800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[7]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=111.8150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=111.7800 urx=0.2900 ury=111.8500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[6]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=107.0650 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=107.0300 urx=0.2900 ury=107.1000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[5]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=104.2150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=104.1800 urx=0.2900 ury=104.2500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[4]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=111.8150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=111.7800 urx=0.2900 ury=111.8500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[3]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=113.9050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=113.8700 urx=0.2900 ury=113.9400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[2]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=118.6550 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=118.6200 urx=0.2900 ury=118.6900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[1]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=115.2350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=115.2000 urx=0.2900 ury=115.2700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[0]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=120.7450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=120.7100 urx=0.2900 ury=120.7800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[15]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.7950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=81.7600 urx=0.2900 ury=81.8300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[14]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=72.4850 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=72.4500 urx=0.2900 ury=72.5200 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[13]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.7950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=81.7600 urx=0.2900 ury=81.8300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[12]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=72.6750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=72.6400 urx=0.2900 ury=72.7100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[11]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=66.9750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=66.9400 urx=0.2900 ury=67.0100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[10]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=66.4050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=66.3700 urx=0.2900 ury=66.4400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[9]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=73.0550 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=73.0200 urx=0.2900 ury=73.0900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[8]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=73.4350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=73.4000 urx=0.2900 ury=73.4700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[7]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=82.7450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=82.7100 urx=0.2900 ury=82.7800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[6]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=79.3250 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=79.2900 urx=0.2900 ury=79.3600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[5]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.4150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=81.3800 urx=0.2900 ury=81.4500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[4]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=82.7450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=82.7100 urx=0.2900 ury=82.7800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[3]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=73.4350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=73.4000 urx=0.2900 ury=73.4700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[2]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=84.8350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=84.8000 urx=0.2900 ury=84.8700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[1]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=77.9950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=77.9600 urx=0.2900 ury=78.0300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[0]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.4150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=81.3800 urx=0.2900 ury=81.4500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[15]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=104.2150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=104.1800 urx=0.2900 ury=104.2500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[14]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=91.2950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=91.2600 urx=0.2900 ury=91.3300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[13]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.0350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=81.0000 urx=0.2900 ury=81.0700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[12]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=79.7050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=79.6700 urx=0.2900 ury=79.7400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[11]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=87.8750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=87.8400 urx=0.2900 ury=87.9100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[10]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=86.5450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=86.5100 urx=0.2900 ury=86.5800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[9]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=83.1250 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=83.0900 urx=0.2900 ury=83.1600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[8]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=83.1250 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=83.0900 urx=0.2900 ury=83.1600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[7]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=103.6450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=103.6100 urx=0.2900 ury=103.6800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[6]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=110.4850 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=110.4500 urx=0.2900 ury=110.5200 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[5]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=107.0650 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=107.0300 urx=0.2900 ury=107.1000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[4]" status="fixed" >
+    <Port>
+      <Pref x=52.3000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=52.2650 lly=153.6100 urx=52.3350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[3]" status="fixed" >
+    <Port>
+      <Pref x=44.1000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=44.0650 lly=153.6100 urx=44.1350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[2]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=113.9050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=113.8700 urx=0.2900 ury=113.9400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[1]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=122.0750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=122.0400 urx=0.2900 ury=122.1100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[0]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=117.3250 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=117.2900 urx=0.2900 ury=117.3600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_as" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=77.0450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=77.0100 urx=0.2900 ury=77.0800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_read" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=76.6650 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=76.6300 urx=0.2900 ury=76.7000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_write" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=76.6650 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=76.6300 urx=0.2900 ury=76.7000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_write_h" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=76.2850 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=76.2500 urx=0.2900 ury=76.3200 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_address[8]" status="fixed" >
+    <Port>
+      <Pref x=59.7000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=59.6650 lly=153.6100 urx=59.7350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_address[7]" status="fixed" >
+    <Port>
+      <Pref x=62.1000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=62.0650 lly=153.6100 urx=62.1350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_address[6]" status="fixed" >
+    <Port>
+      <Pref x=60.1000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=60.0650 lly=153.6100 urx=60.1350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_address[5]" status="fixed" >
+    <Port>
+      <Pref x=66.7000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=66.6650 lly=153.6100 urx=66.7350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_address[4]" status="fixed" >
+    <Port>
+      <Pref x=64.3000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=64.2650 lly=153.6100 urx=64.3350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_address[3]" status="fixed" >
+    <Port>
+      <Pref x=69.5000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=69.4650 lly=153.6100 urx=69.5350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_address[2]" status="fixed" >
+    <Port>
+      <Pref x=62.1000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=4 >
+        <Box llx=62.0650 lly=153.6100 urx=62.1350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_address[1]" status="fixed" >
+    <Port>
+      <Pref x=57.7000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=57.6650 lly=153.6100 urx=57.7350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="p_address[0]" status="fixed" >
+    <Port>
+      <Pref x=55.5000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=55.4650 lly=153.6100 urx=55.5350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[15]" status="fixed" >
+    <Port>
+      <Pref x=36.9000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=36.8650 lly=153.6100 urx=36.9350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[14]" status="fixed" >
+    <Port>
+      <Pref x=45.1000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=45.0650 lly=153.6100 urx=45.1350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[13]" status="fixed" >
+    <Port>
+      <Pref x=40.9000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=40.8650 lly=153.6100 urx=40.9350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[12]" status="fixed" >
+    <Port>
+      <Pref x=43.1000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=43.0650 lly=153.6100 urx=43.1350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[11]" status="fixed" >
+    <Port>
+      <Pref x=54.3000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=54.2650 lly=153.6100 urx=54.3350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[10]" status="fixed" >
+    <Port>
+      <Pref x=48.7000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=48.6650 lly=153.6100 urx=48.7350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[9]" status="fixed" >
+    <Port>
+      <Pref x=53.7000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=4 >
+        <Box llx=53.6650 lly=153.6100 urx=53.7350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[8]" status="fixed" >
+    <Port>
+      <Pref x=56.9000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=56.8650 lly=153.6100 urx=56.9350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[7]" status="fixed" >
+    <Port>
+      <Pref x=61.5000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=6 >
+        <Box llx=61.4650 lly=153.6100 urx=61.5350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[6]" status="fixed" >
+    <Port>
+      <Pref x=58.9000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=6 >
+        <Box llx=58.8650 lly=153.6100 urx=58.9350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[5]" status="fixed" >
+    <Port>
+      <Pref x=66.7000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=6 >
+        <Box llx=66.6650 lly=153.6100 urx=66.7350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[4]" status="fixed" >
+    <Port>
+      <Pref x=61.7000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=61.6650 lly=153.6100 urx=61.7350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[3]" status="fixed" >
+    <Port>
+      <Pref x=61.9000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=6 >
+        <Box llx=61.8650 lly=153.6100 urx=61.9350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[2]" status="fixed" >
+    <Port>
+      <Pref x=53.9000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=53.8650 lly=153.6100 urx=53.9350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[1]" status="fixed" >
+    <Port>
+      <Pref x=46.1000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=46.0650 lly=153.6100 urx=46.1350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_in[0]" status="fixed" >
+    <Port>
+      <Pref x=58.5000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=6 >
+        <Box llx=58.4650 lly=153.6100 urx=58.5350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[15]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=78.3750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=78.3400 urx=0.2900 ury=78.4100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[14]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=75.9050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=75.8700 urx=0.2900 ury=75.9400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[13]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=78.3750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=78.3400 urx=0.2900 ury=78.4100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[12]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=75.7150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=75.6800 urx=0.2900 ury=75.7500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[11]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=78.7550 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=78.7200 urx=0.2900 ury=78.7900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[10]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=75.5250 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=75.4900 urx=0.2900 ury=75.5600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[9]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=78.7550 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=78.7200 urx=0.2900 ury=78.7900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[8]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=75.3350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=75.3000 urx=0.2900 ury=75.3700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[7]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=75.1450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=75.1100 urx=0.2900 ury=75.1800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[6]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=79.1350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=79.1000 urx=0.2900 ury=79.1700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[5]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=74.9550 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=74.9200 urx=0.2900 ury=74.9900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[4]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=74.7650 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=74.7300 urx=0.2900 ury=74.8000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[3]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=74.5750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=74.5400 urx=0.2900 ury=74.6100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[2]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=80.0850 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=80.0500 urx=0.2900 ury=80.1200 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[1]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=80.0850 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=80.0500 urx=0.2900 ury=80.1200 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="rom_data_out[0]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=73.8150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=73.7800 urx=0.2900 ury=73.8500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="bus_grant" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=127.2050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=127.1700 urx=0.2900 ury=127.2400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="bus_request" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=129.1050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=129.0700 urx=0.2900 ury=129.1400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_address[2]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=115.4250 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=115.3900 urx=0.2900 ury=115.4600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_address[1]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=118.8450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=118.8100 urx=0.2900 ury=118.8800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_address[0]" status="fixed" >
+    <Port>
+      <Pref x=32.7000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=32.6650 lly=153.6100 urx=32.7350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[15]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=118.4650 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=118.4300 urx=141.8000 ury=118.5000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[14]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=92.2450 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=92.2100 urx=141.8000 ury=92.2800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[13]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=92.2450 side=E width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=141.5100 lly=92.2100 urx=141.8000 ury=92.2800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[12]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=90.9150 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=90.8800 urx=141.8000 ury=90.9500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[11]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=92.6250 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=92.5900 urx=141.8000 ury=92.6600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[10]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=92.6250 side=E width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=141.5100 lly=92.5900 urx=141.8000 ury=92.6600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[9]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=84.6450 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=84.6100 urx=141.8000 ury=84.6800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[8]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=91.8650 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=91.8300 urx=141.8000 ury=91.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[7]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=91.8650 side=E width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=141.5100 lly=91.8300 urx=141.8000 ury=91.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[6]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=93.0050 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=92.9700 urx=141.8000 ury=93.0400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[5]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=103.4550 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=103.4200 urx=141.8000 ury=103.4900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[4]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=104.7850 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=104.7500 urx=141.8000 ury=104.8200 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[3]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=109.9150 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=109.8800 urx=141.8000 ury=109.9500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[2]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=111.0550 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=111.0200 urx=141.8000 ury=111.0900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[1]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=104.7850 side=E width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=141.5100 lly=104.7500 urx=141.8000 ury=104.8200 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_in[0]" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=112.3850 side=E width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=141.5100 lly=112.3500 urx=141.8000 ury=112.4200 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[15]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=77.6150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=77.5800 urx=0.2900 ury=77.6500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[14]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=77.6150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=77.5800 urx=0.2900 ury=77.6500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[13]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=74.1950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=74.1600 urx=0.2900 ury=74.2300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[12]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=70.7750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=70.7400 urx=0.2900 ury=70.8100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[11]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=77.9950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=77.9600 urx=0.2900 ury=78.0300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[10]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=74.1950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=74.1600 urx=0.2900 ury=74.2300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[9]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=79.7050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=79.6700 urx=0.2900 ury=79.7400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[8]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=72.8650 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=72.8300 urx=0.2900 ury=72.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[7]" status="fixed" >
+    <Port>
+      <Pref x=69.9000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=69.8650 lly=153.6100 urx=69.9350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[6]" status="fixed" >
+    <Port>
+      <Pref x=58.1000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=58.0650 lly=153.6100 urx=58.1350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[5]" status="fixed" >
+    <Port>
+      <Pref x=67.1000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=67.0650 lly=153.6100 urx=67.1350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[4]" status="fixed" >
+    <Port>
+      <Pref x=64.7000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=64.6650 lly=153.6100 urx=64.7350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[3]" status="fixed" >
+    <Port>
+      <Pref x=72.1000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=72.0650 lly=153.6100 urx=72.1350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[2]" status="fixed" >
+    <Port>
+      <Pref x=77.5000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=77.4650 lly=153.6100 urx=77.5350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[1]" status="fixed" >
+    <Port>
+      <Pref x=55.9000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=55.8650 lly=153.6100 urx=55.9350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_pad_data_out[0]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.0350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=81.0000 urx=0.2900 ury=81.0700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_as" status="fixed" >
+    <Port>
+      <Pref x=49.3000 y=153.9000 side=N width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=49.2650 lly=153.6100 urx=49.3350 ury=153.9000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_read" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=80.4650 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=80.4300 urx=0.2900 ury=80.5000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_write" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=73.8150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=73.7800 urx=0.2900 ury=73.8500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="port_write_h" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=80.4650 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=80.4300 urx=0.2900 ury=80.5000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_sdi[2]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=120.3650 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=120.3300 urx=0.2900 ury=120.4000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_sdi[1]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=97.3750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=97.3400 urx=0.2900 ury=97.4100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_sdi[0]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=151.1450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=151.1100 urx=0.2900 ury=151.1800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_sdo[2]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=93.9550 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=93.9200 urx=0.2900 ury=93.9900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_sdo[1]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=71.1550 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=71.1200 urx=0.2900 ury=71.1900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_sdo[0]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=76.0950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=76.0600 urx=0.2900 ury=76.1300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="bio" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=143.3550 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=143.3200 urx=0.2900 ury=143.3900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="int" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=1.0450 side=E width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=141.5100 lly=1.0100 urx=141.8000 ury=1.0800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="RC_CG_TEST_PORT" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=71.3450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=71.3100 urx=0.2900 ury=71.3800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="SRPG_PG_in" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=1.4250 side=E width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=141.5100 lly=1.3900 urx=141.8000 ury=1.4600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="SRPG_PG_in_1" status="fixed" >
+    <Port>
+      <Pref x=141.8000 y=1.8050 side=E width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=141.5100 lly=1.7700 urx=141.8000 ury=1.8400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="DFT_sen" status="fixed" >
+    <Port>
+      <Pref x=8.1000 y=0.0000 side=S width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=8.0650 lly=0.0000 urx=8.1350 ury=0.2900 />
+      </Layer>
+    </Port>
+  </Pin>
+</IOPins>
+
+####################################################################################################
+#  PGPin: <pin> <net> {in|out|inout} {pwr|gnd|-} {placed|fixed|-} <x> <y> <side> <layerId> <nrBox> #
+#    PinBox: <llx> <lly> <urx> <ury>                                                               #
+#    PinPoly: <nrPts> <x1> <y1> <x2> <y2>...<xn> <yn>                                              #
+####################################################################################################
+PGPin: VSS VSS inout gnd fixed 141.8000 150.4800 E 1 1
+  PinBox: 141.7400 150.4200 141.8000 150.5400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 150.4800 W 1 1
+  PinBox: 0.0000 150.4200 0.0600 150.5400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 153.9000 E 1 1
+  PinBox: 141.7400 153.8400 141.8000 153.9600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 153.9000 W 1 1
+  PinBox: 0.0000 153.8400 0.0600 153.9600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 30.9000 0.0000 S 6 1
+  PinBox: 29.4000 0.0000 32.4000 0.0700 -lyr 6
+PGPin: VSS VSS inout gnd fixed 30.9000 153.9000 N 6 1
+  PinBox: 29.4000 153.8300 32.4000 153.9000 -lyr 6
+PGPin: VSS VSS inout gnd fixed 73.9000 0.0000 S 6 1
+  PinBox: 72.4000 0.0000 75.4000 0.0700 -lyr 6
+PGPin: VSS VSS inout gnd fixed 73.9000 153.9000 N 6 1
+  PinBox: 72.4000 153.8300 75.4000 153.9000 -lyr 6
+PGPin: VSS VSS inout gnd fixed 116.9000 0.0000 S 6 1
+  PinBox: 115.4000 0.0000 118.4000 0.0700 -lyr 6
+PGPin: VSS VSS inout gnd fixed 116.9000 153.9000 N 6 1
+  PinBox: 115.4000 153.8300 118.4000 153.9000 -lyr 6
+PGPin: VSS VSS inout gnd fixed 141.8000 116.2800 E 1 1
+  PinBox: 141.7400 116.2200 141.8000 116.3400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 116.2800 W 1 1
+  PinBox: 0.0000 116.2200 0.0600 116.3400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 112.8600 E 1 1
+  PinBox: 141.7400 112.8000 141.8000 112.9200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 112.8600 W 1 1
+  PinBox: 0.0000 112.8000 0.0600 112.9200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 106.0200 E 1 1
+  PinBox: 141.7400 105.9600 141.8000 106.0800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 106.0200 W 1 1
+  PinBox: 0.0000 105.9600 0.0600 106.0800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 109.4400 E 1 1
+  PinBox: 141.7400 109.3800 141.8000 109.5000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 109.4400 W 1 1
+  PinBox: 0.0000 109.3800 0.0600 109.5000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 119.7000 E 1 1
+  PinBox: 141.7400 119.6400 141.8000 119.7600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 119.7000 W 1 1
+  PinBox: 0.0000 119.6400 0.0600 119.7600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 123.1200 E 1 1
+  PinBox: 141.7400 123.0600 141.8000 123.1800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 123.1200 W 1 1
+  PinBox: 0.0000 123.0600 0.0600 123.1800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 147.0600 E 1 1
+  PinBox: 141.7400 147.0000 141.8000 147.1200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 147.0600 W 1 1
+  PinBox: 0.0000 147.0000 0.0600 147.1200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 143.6400 E 1 1
+  PinBox: 141.7400 143.5800 141.8000 143.7000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 143.6400 W 1 1
+  PinBox: 0.0000 143.5800 0.0600 143.7000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 140.2200 E 1 1
+  PinBox: 141.7400 140.1600 141.8000 140.2800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 140.2200 W 1 1
+  PinBox: 0.0000 140.1600 0.0600 140.2800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 136.8000 E 1 1
+  PinBox: 141.7400 136.7400 141.8000 136.8600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 136.8000 W 1 1
+  PinBox: 0.0000 136.7400 0.0600 136.8600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 133.3800 E 1 1
+  PinBox: 141.7400 133.3200 141.8000 133.4400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 133.3800 W 1 1
+  PinBox: 0.0000 133.3200 0.0600 133.4400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 129.9600 E 1 1
+  PinBox: 141.7400 129.9000 141.8000 130.0200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 129.9600 W 1 1
+  PinBox: 0.0000 129.9000 0.0600 130.0200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 126.5400 E 1 1
+  PinBox: 141.7400 126.4800 141.8000 126.6000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 126.5400 W 1 1
+  PinBox: 0.0000 126.4800 0.0600 126.6000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 61.5600 E 1 1
+  PinBox: 141.7400 61.5000 141.8000 61.6200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 61.5600 W 1 1
+  PinBox: 0.0000 61.5000 0.0600 61.6200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 71.8200 E 1 1
+  PinBox: 141.7400 71.7600 141.8000 71.8800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 71.8200 W 1 1
+  PinBox: 0.0000 71.7600 0.0600 71.8800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 68.4000 E 1 1
+  PinBox: 141.7400 68.3400 141.8000 68.4600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 68.4000 W 1 1
+  PinBox: 0.0000 68.3400 0.0600 68.4600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 64.9800 E 1 1
+  PinBox: 141.7400 64.9200 141.8000 65.0400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 64.9800 W 1 1
+  PinBox: 0.0000 64.9200 0.0600 65.0400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 75.2400 E 1 1
+  PinBox: 141.7400 75.1800 141.8000 75.3000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 75.2400 W 1 1
+  PinBox: 0.0000 75.1800 0.0600 75.3000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 78.6600 E 1 1
+  PinBox: 141.7400 78.6000 141.8000 78.7200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 78.6600 W 1 1
+  PinBox: 0.0000 78.6000 0.0600 78.7200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 92.3400 E 1 1
+  PinBox: 141.7400 92.2800 141.8000 92.4000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 92.3400 W 1 1
+  PinBox: 0.0000 92.2800 0.0600 92.4000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 88.9200 E 1 1
+  PinBox: 141.7400 88.8600 141.8000 88.9800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 88.9200 W 1 1
+  PinBox: 0.0000 88.8600 0.0600 88.9800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 85.5000 E 1 1
+  PinBox: 141.7400 85.4400 141.8000 85.5600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 85.5000 W 1 1
+  PinBox: 0.0000 85.4400 0.0600 85.5600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 82.0800 E 1 1
+  PinBox: 141.7400 82.0200 141.8000 82.1400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 82.0800 W 1 1
+  PinBox: 0.0000 82.0200 0.0600 82.1400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 102.6000 E 1 1
+  PinBox: 141.7400 102.5400 141.8000 102.6600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 102.6000 W 1 1
+  PinBox: 0.0000 102.5400 0.0600 102.6600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 99.1800 E 1 1
+  PinBox: 141.7400 99.1200 141.8000 99.2400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 99.1800 W 1 1
+  PinBox: 0.0000 99.1200 0.0600 99.2400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 95.7600 E 1 1
+  PinBox: 141.7400 95.7000 141.8000 95.8200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 95.7600 W 1 1
+  PinBox: 0.0000 95.7000 0.0600 95.8200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 23.9400 E 1 1
+  PinBox: 141.7400 23.8800 141.8000 24.0000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 23.9400 W 1 1
+  PinBox: 0.0000 23.8800 0.0600 24.0000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 17.1000 E 1 1
+  PinBox: 141.7400 17.0400 141.8000 17.1600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 17.1000 W 1 1
+  PinBox: 0.0000 17.0400 0.0600 17.1600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 20.5200 E 1 1
+  PinBox: 141.7400 20.4600 141.8000 20.5800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 20.5200 W 1 1
+  PinBox: 0.0000 20.4600 0.0600 20.5800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 13.6800 E 1 1
+  PinBox: 141.7400 13.6200 141.8000 13.7400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 13.6800 W 1 1
+  PinBox: 0.0000 13.6200 0.0600 13.7400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 27.3600 E 1 1
+  PinBox: 141.7400 27.3000 141.8000 27.4200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 27.3600 W 1 1
+  PinBox: 0.0000 27.3000 0.0600 27.4200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 34.2000 E 1 1
+  PinBox: 141.7400 34.1400 141.8000 34.2600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 34.2000 W 1 1
+  PinBox: 0.0000 34.1400 0.0600 34.2600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 30.7800 E 1 1
+  PinBox: 141.7400 30.7200 141.8000 30.8400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 30.7800 W 1 1
+  PinBox: 0.0000 30.7200 0.0600 30.8400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 51.3000 E 1 1
+  PinBox: 141.7400 51.2400 141.8000 51.3600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 51.3000 W 1 1
+  PinBox: 0.0000 51.2400 0.0600 51.3600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 54.7200 E 1 1
+  PinBox: 141.7400 54.6600 141.8000 54.7800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 54.7200 W 1 1
+  PinBox: 0.0000 54.6600 0.0600 54.7800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 47.8800 E 1 1
+  PinBox: 141.7400 47.8200 141.8000 47.9400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 47.8800 W 1 1
+  PinBox: 0.0000 47.8200 0.0600 47.9400 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 44.4600 E 1 1
+  PinBox: 141.7400 44.4000 141.8000 44.5200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 44.4600 W 1 1
+  PinBox: 0.0000 44.4000 0.0600 44.5200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 37.6200 E 1 1
+  PinBox: 141.7400 37.5600 141.8000 37.6800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 37.6200 W 1 1
+  PinBox: 0.0000 37.5600 0.0600 37.6800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 41.0400 E 1 1
+  PinBox: 141.7400 40.9800 141.8000 41.1000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 41.0400 W 1 1
+  PinBox: 0.0000 40.9800 0.0600 41.1000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 58.1400 E 1 1
+  PinBox: 141.7400 58.0800 141.8000 58.2000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 58.1400 W 1 1
+  PinBox: 0.0000 58.0800 0.0600 58.2000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 6.8400 E 1 1
+  PinBox: 141.7400 6.7800 141.8000 6.9000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 6.8400 W 1 1
+  PinBox: 0.0000 6.7800 0.0600 6.9000 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 10.2600 E 1 1
+  PinBox: 141.7400 10.2000 141.8000 10.3200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 10.2600 W 1 1
+  PinBox: 0.0000 10.2000 0.0600 10.3200 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 3.4200 E 1 1
+  PinBox: 141.7400 3.3600 141.8000 3.4800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 3.4200 W 1 1
+  PinBox: 0.0000 3.3600 0.0600 3.4800 -lyr 1
+PGPin: VSS VSS inout gnd fixed 141.8000 0.0000 E 1 1
+  PinBox: 141.7400 -0.0600 141.8000 0.0600 -lyr 1
+PGPin: VSS VSS inout gnd fixed 0.0000 0.0000 W 1 1
+  PinBox: 0.0000 -0.0600 0.0600 0.0600 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 152.1900 E 1 1
+  PinBox: 141.7400 152.1300 141.8000 152.2500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 152.1900 W 1 1
+  PinBox: 0.0000 152.1300 0.0600 152.2500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 26.9000 0.0000 S 6 1
+  PinBox: 25.4000 0.0000 28.4000 0.0700 -lyr 6
+PGPin: VDD VDD inout pwr fixed 26.9000 153.9000 N 6 1
+  PinBox: 25.4000 153.8300 28.4000 153.9000 -lyr 6
+PGPin: VDD VDD inout pwr fixed 69.9000 0.0000 S 6 1
+  PinBox: 68.4000 0.0000 71.4000 0.0700 -lyr 6
+PGPin: VDD VDD inout pwr fixed 69.9000 153.9000 N 6 1
+  PinBox: 68.4000 153.8300 71.4000 153.9000 -lyr 6
+PGPin: VDD VDD inout pwr fixed 112.9000 0.0000 S 6 1
+  PinBox: 111.4000 0.0000 114.4000 0.0700 -lyr 6
+PGPin: VDD VDD inout pwr fixed 112.9000 153.9000 N 6 1
+  PinBox: 111.4000 153.8300 114.4000 153.9000 -lyr 6
+PGPin: VDD VDD inout pwr fixed 141.8000 148.7700 E 1 1
+  PinBox: 141.7400 148.7100 141.8000 148.8300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 148.7700 W 1 1
+  PinBox: 0.0000 148.7100 0.0600 148.8300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 117.9900 E 1 1
+  PinBox: 141.7400 117.9300 141.8000 118.0500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 117.9900 W 1 1
+  PinBox: 0.0000 117.9300 0.0600 118.0500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 114.5700 E 1 1
+  PinBox: 141.7400 114.5100 141.8000 114.6300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 114.5700 W 1 1
+  PinBox: 0.0000 114.5100 0.0600 114.6300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 111.1500 E 1 1
+  PinBox: 141.7400 111.0900 141.8000 111.2100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 111.1500 W 1 1
+  PinBox: 0.0000 111.0900 0.0600 111.2100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 107.7300 E 1 1
+  PinBox: 141.7400 107.6700 141.8000 107.7900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 107.7300 W 1 1
+  PinBox: 0.0000 107.6700 0.0600 107.7900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 104.3100 E 1 1
+  PinBox: 141.7400 104.2500 141.8000 104.3700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 104.3100 W 1 1
+  PinBox: 0.0000 104.2500 0.0600 104.3700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 124.8300 E 1 1
+  PinBox: 141.7400 124.7700 141.8000 124.8900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 124.8300 W 1 1
+  PinBox: 0.0000 124.7700 0.0600 124.8900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 121.4100 E 1 1
+  PinBox: 141.7400 121.3500 141.8000 121.4700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 121.4100 W 1 1
+  PinBox: 0.0000 121.3500 0.0600 121.4700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 145.3500 E 1 1
+  PinBox: 141.7400 145.2900 141.8000 145.4100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 145.3500 W 1 1
+  PinBox: 0.0000 145.2900 0.0600 145.4100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 131.6700 E 1 1
+  PinBox: 141.7400 131.6100 141.8000 131.7300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 131.6700 W 1 1
+  PinBox: 0.0000 131.6100 0.0600 131.7300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 141.9300 E 1 1
+  PinBox: 141.7400 141.8700 141.8000 141.9900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 141.9300 W 1 1
+  PinBox: 0.0000 141.8700 0.0600 141.9900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 138.5100 E 1 1
+  PinBox: 141.7400 138.4500 141.8000 138.5700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 138.5100 W 1 1
+  PinBox: 0.0000 138.4500 0.0600 138.5700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 135.0900 E 1 1
+  PinBox: 141.7400 135.0300 141.8000 135.1500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 135.0900 W 1 1
+  PinBox: 0.0000 135.0300 0.0600 135.1500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 128.2500 E 1 1
+  PinBox: 141.7400 128.1900 141.8000 128.3100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 128.2500 W 1 1
+  PinBox: 0.0000 128.1900 0.0600 128.3100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 59.8500 E 1 1
+  PinBox: 141.7400 59.7900 141.8000 59.9100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 59.8500 W 1 1
+  PinBox: 0.0000 59.7900 0.0600 59.9100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 63.2700 E 1 1
+  PinBox: 141.7400 63.2100 141.8000 63.3300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 63.2700 W 1 1
+  PinBox: 0.0000 63.2100 0.0600 63.3300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 73.5300 E 1 1
+  PinBox: 141.7400 73.4700 141.8000 73.5900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 73.5300 W 1 1
+  PinBox: 0.0000 73.4700 0.0600 73.5900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 70.1100 E 1 1
+  PinBox: 141.7400 70.0500 141.8000 70.1700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 70.1100 W 1 1
+  PinBox: 0.0000 70.0500 0.0600 70.1700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 66.6900 E 1 1
+  PinBox: 141.7400 66.6300 141.8000 66.7500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 66.6900 W 1 1
+  PinBox: 0.0000 66.6300 0.0600 66.7500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 76.9500 E 1 1
+  PinBox: 141.7400 76.8900 141.8000 77.0100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 76.9500 W 1 1
+  PinBox: 0.0000 76.8900 0.0600 77.0100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 80.3700 E 1 1
+  PinBox: 141.7400 80.3100 141.8000 80.4300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 80.3700 W 1 1
+  PinBox: 0.0000 80.3100 0.0600 80.4300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 90.6300 E 1 1
+  PinBox: 141.7400 90.5700 141.8000 90.6900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 90.6300 W 1 1
+  PinBox: 0.0000 90.5700 0.0600 90.6900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 87.2100 E 1 1
+  PinBox: 141.7400 87.1500 141.8000 87.2700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 87.2100 W 1 1
+  PinBox: 0.0000 87.1500 0.0600 87.2700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 83.7900 E 1 1
+  PinBox: 141.7400 83.7300 141.8000 83.8500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 83.7900 W 1 1
+  PinBox: 0.0000 83.7300 0.0600 83.8500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 97.4700 E 1 1
+  PinBox: 141.7400 97.4100 141.8000 97.5300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 97.4700 W 1 1
+  PinBox: 0.0000 97.4100 0.0600 97.5300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 100.8900 E 1 1
+  PinBox: 141.7400 100.8300 141.8000 100.9500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 100.8900 W 1 1
+  PinBox: 0.0000 100.8300 0.0600 100.9500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 94.0500 E 1 1
+  PinBox: 141.7400 93.9900 141.8000 94.1100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 94.0500 W 1 1
+  PinBox: 0.0000 93.9900 0.0600 94.1100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 25.6500 E 1 1
+  PinBox: 141.7400 25.5900 141.8000 25.7100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 25.6500 W 1 1
+  PinBox: 0.0000 25.5900 0.0600 25.7100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 15.3900 E 1 1
+  PinBox: 141.7400 15.3300 141.8000 15.4500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 15.3900 W 1 1
+  PinBox: 0.0000 15.3300 0.0600 15.4500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 18.8100 E 1 1
+  PinBox: 141.7400 18.7500 141.8000 18.8700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 18.8100 W 1 1
+  PinBox: 0.0000 18.7500 0.0600 18.8700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 22.2300 E 1 1
+  PinBox: 141.7400 22.1700 141.8000 22.2900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 22.2300 W 1 1
+  PinBox: 0.0000 22.1700 0.0600 22.2900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 29.0700 E 1 1
+  PinBox: 141.7400 29.0100 141.8000 29.1300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 29.0700 W 1 1
+  PinBox: 0.0000 29.0100 0.0600 29.1300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 32.4900 E 1 1
+  PinBox: 141.7400 32.4300 141.8000 32.5500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 32.4900 W 1 1
+  PinBox: 0.0000 32.4300 0.0600 32.5500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 35.9100 E 1 1
+  PinBox: 141.7400 35.8500 141.8000 35.9700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 35.9100 W 1 1
+  PinBox: 0.0000 35.8500 0.0600 35.9700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 49.5900 E 1 1
+  PinBox: 141.7400 49.5300 141.8000 49.6500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 49.5900 W 1 1
+  PinBox: 0.0000 49.5300 0.0600 49.6500 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 53.0100 E 1 1
+  PinBox: 141.7400 52.9500 141.8000 53.0700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 53.0100 W 1 1
+  PinBox: 0.0000 52.9500 0.0600 53.0700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 46.1700 E 1 1
+  PinBox: 141.7400 46.1100 141.8000 46.2300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 46.1700 W 1 1
+  PinBox: 0.0000 46.1100 0.0600 46.2300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 39.3300 E 1 1
+  PinBox: 141.7400 39.2700 141.8000 39.3900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 39.3300 W 1 1
+  PinBox: 0.0000 39.2700 0.0600 39.3900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 42.7500 E 1 1
+  PinBox: 141.7400 42.6900 141.8000 42.8100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 42.7500 W 1 1
+  PinBox: 0.0000 42.6900 0.0600 42.8100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 56.4300 E 1 1
+  PinBox: 141.7400 56.3700 141.8000 56.4900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 56.4300 W 1 1
+  PinBox: 0.0000 56.3700 0.0600 56.4900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 8.5500 E 1 1
+  PinBox: 141.7400 8.4900 141.8000 8.6100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 8.5500 W 1 1
+  PinBox: 0.0000 8.4900 0.0600 8.6100 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 11.9700 E 1 1
+  PinBox: 141.7400 11.9100 141.8000 12.0300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 11.9700 W 1 1
+  PinBox: 0.0000 11.9100 0.0600 12.0300 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 5.1300 E 1 1
+  PinBox: 141.7400 5.0700 141.8000 5.1900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 5.1300 W 1 1
+  PinBox: 0.0000 5.0700 0.0600 5.1900 -lyr 1
+PGPin: VDD VDD inout pwr fixed 141.8000 1.7100 E 1 1
+  PinBox: 141.7400 1.6500 141.8000 1.7700 -lyr 1
+PGPin: VDD VDD inout pwr fixed 0.0000 1.7100 W 1 1
+  PinBox: 0.0000 1.6500 0.0600 1.7700 -lyr 1
+
+#################################################################
+#  PartitionPinFile: <file_name>                                #
+#################################################################
+PartitionPinFile: hier.fp.ptn
+
+#####################################################################
+#  <Property>                                                       #
+#     <obj_type name="inst_name" >                                  #
+#       <prop name="name" type=type_name value=val />               #
+#       <Attr name="name" type=type_name value=val />               #
+#     </obj_type>                                                   #
+#  </Property>                                                      #
+#  where:                                                           #
+#       type is data type: Box, String, Int, PTR, Loc, double, Bits #
+#       obj_type are: inst, Design, instTerm, Bump, cell, net       #
+#####################################################################
+<Properties>
+  <Design name="tdsp_core">
+  </Design>
+</Properties>
+
+###########################################################$############################################################################################
+#  GlobalNetConnection: <net_name> {-pin|-inst|-net} <base_name_pattern> -type {pgpin|net|tiehi|tielo} {-all|-module <name>|-region <box>} [-override] #
+########################################################################################################################################################
+GlobalNetConnection: 1'b0 -net SRPG_PG_in_1 -type net -all
+GlobalNetConnection: 1'b0 -net SRPG_PG_in -type net -all
+GlobalNetConnection: 1'b0 -net int -type net -all
+GlobalNetConnection: VDD -pin VDD -inst * -type pgpin -all
+GlobalNetConnection: VSS -pin VSS -inst * -type pgpin -all
+
+################################################################################
+#  NetProperties: <net_name> [-special] [-def_prop {int|dbl|str} <value>]...   #
+################################################################################
+
+##################################################################################
+#    Feedthru info:                                                              #
+# <Feedthrus>                                                                    #
+#   <Feedthru>                                                                   #
+#       <tsv llx=n lly=n urx=n ury=n />                                          #
+#       <stackvia layer=z llx=n lly=n urx=n ury=n />                             #
+#       <bump front=name back=name  />                                           #
+#   </Feedthru>                                                                  #
+#   <Feedthru>                                                                   #
+#   <...>                                                                        #
+#   </Feedthru>                                                                  #
+# </Feedthrus>                                                                   #
+################################################################################
diff --git a/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/hier.fp.ptn b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/hier.fp.ptn
new file mode 100755
index 0000000..0b055e3
--- /dev/null
+++ b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/hier.fp.ptn
@@ -0,0 +1,16 @@
+###############################################################
+#  Generated by:      Cadence Encounter 11.11-e047_1
+#  OS:                Linux x86_64(Host ID sjfnl688)
+#  Generated on:      Tue Mar 20 08:24:26 2012
+#  Design:            tdsp_core
+#  Command:           saveFPlan hier.fp
+###############################################################
+
+PartitionPins: mult_32 
+
+#######################################################################################
+#  IOPin: <pinName> <x> <y> <side> <layerId> <width> <depth> {placed|fixed|cover} <nrBox> #
+#    PinBox: <llx> <lly> <urx> <ury>                                                  #
+#    PinPoly: <nrPt> <x1> <y1> <x2> <y2> ...<xn> <yn>                                 #
+#######################################################################################
+#######################################################################################
diff --git a/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/hier.fp.spr b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/hier.fp.spr
new file mode 100755
index 0000000..c17cca7
--- /dev/null
+++ b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/hier.fp.spr
@@ -0,0 +1,115 @@
+Version 4.1
+Micron 2000
+LAYERS 29
+Poly
+Metal1
+Metal2
+Metal3
+Metal4
+Metal5
+Metal6
+Metal7
+Metal8
+Metal9
+Cont
+Via1
+Via2
+Via3
+Via4
+Via5
+Via6
+Via7
+Via8
+Oxide
+Nhvt
+Nimp
+Phvt
+Pimp
+Nzvt
+Nlvt
+Plvt
+SiProt
+OVERLAP
+VIAS 5
+M5_M4_1 M5_M4 Metal5/Via4/Metal4 0 1 0 140 140 280 280 21 1 -2870 -70 2870 70 
+1
+0 -3000 -120 3000 120 
+1
+0 -3000 -120 3000 120 
+M4_M3_1 M4_M3 Metal4/Via3/Metal3 0 1 0 140 140 280 280 21 1 -2870 -70 2870 70 
+1
+0 -3000 -120 3000 120 
+1
+0 -3000 -120 3000 120 
+M3_M2_1 M3_M2 Metal3/Via2/Metal2 0 1 0 140 140 280 280 21 1 -2870 -70 2870 70 
+1
+0 -3000 -120 3000 120 
+1
+0 -3000 -120 3000 120 
+M2_M1_1 M2_M1 Metal2/Via1/Metal1 0 1 0 140 140 280 280 21 1 -2870 -70 2870 70 
+1
+0 -3000 -120 3000 120 
+1
+0 -3000 -120 3000 120 
+M6_M5_2 M6_M5 Metal6/Via5/Metal5 0 1 0 140 140 280 280 21 1 -2870 -70 2870 70 
+1
+0 -3000 -120 3000 120 
+1
+0 -3000 -120 3000 120 
+SPECIALNETS
+0 0 1 Avss
+0 0 1 Avdd
+0 0 1 AVss
+49 690 1 VSS
+  49 0 0
+W3 6000 307800 6 010 2 0
+X3 86000 58800 0
+W46 283600 240 1 100 3 0
+Y46 6840 0 -120
+V138 0 0 3 0
+Y46 6840 58800 -120
+Y46 *	144800 *
+Y46 6840 230800 -120
+V138 1 0 3 0
+Y46 6840 58800 -120
+Y46 *	144800 *
+Y46 6840 230800 -120
+V138 2 0 3 0
+Y46 6840 58800 -120
+Y46 *	144800 *
+Y46 6840 230800 -120
+V138 3 0 3 0
+Y46 6840 58800 -120
+Y46 *	144800 *
+Y46 6840 230800 -120
+V138 4 0 3 0
+Y46 6840 58800 -120
+Y46 *	144800 *
+Y46 6840 230800 -120
+0 0 1 AVdd
+48 675 1 VDD
+  48 0 0
+W3 6000 307800 6 010 2 0
+X3 86000 50800 0
+W45 283600 240 1 100 3 0
+Y45 6840 0 3300
+V135 0 0 3 0
+Y45 6840 50800 3300
+Y45 *	136800 *
+Y45 6840 222800 3300
+V135 1 0 3 0
+Y45 6840 50800 3300
+Y45 *	136800 *
+Y45 6840 222800 3300
+V135 2 0 3 0
+Y45 6840 50800 3300
+Y45 *	136800 *
+Y45 6840 222800 3300
+V135 3 0 3 0
+Y45 6840 50800 3300
+Y45 *	136800 *
+Y45 6840 222800 3300
+V135 4 0 3 0
+Y45 6840 50800 3300
+Y45 *	136800 *
+Y45 6840 222800 3300
diff --git a/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/postcts.sdc b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/postcts.sdc
new file mode 100755
index 0000000..d024763
--- /dev/null
+++ b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/postcts.sdc
@@ -0,0 +1,3 @@
+set_propagated_clock [all_clocks]
+reset_clock_tree_latency [all_clocks]
+set_clock_uncertainty -setup 0.05 [all_clocks]
diff --git a/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/prects.sdc b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/prects.sdc
new file mode 100755
index 0000000..d468b34
--- /dev/null
+++ b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/prects.sdc
@@ -0,0 +1,190 @@
+#/**************************************************
+# * Timing constraint file for partition tdsp_core         
+# * With clock latency adjustments                
+# **************************************************/
+create_clock -name {m_tdsp_clk} -period 3.300 -waveform { 0.000 1.600 } [list [get_ports {clk}]]
+set_max_capacitance 0.012 [get_ports {clk}]
+set_max_capacitance 0.259 [get_ports {reset}]
+set_max_capacitance 0.051 [get_ports {t_data_in[15]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[14]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[13]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[12]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[11]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[10]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[9]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[8]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[7]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[6]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[5]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[4]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[3]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[2]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[1]}]
+set_max_capacitance 0.051 [get_ports {t_data_in[0]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[15]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[14]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[13]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[12]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[11]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[10]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[9]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[8]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[7]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[6]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[5]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[4]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[3]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[2]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[1]}]
+set_max_capacitance 0.063 [get_ports {rom_data_in[0]}]
+set_max_capacitance 0.025 [get_ports {bus_grant}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[15]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[14]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[13]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[12]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[11]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[10]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[9]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[8]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[7]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[6]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[5]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[4]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[3]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[2]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[1]}]
+set_max_capacitance 0.259 [get_ports {port_pad_data_in[0]}]
+set_max_capacitance 0.053 [get_ports {t_sdi[2]}]
+set_max_capacitance 0.053 [get_ports {t_sdi[1]}]
+set_max_capacitance 0.053 [get_ports {t_sdi[0]}]
+set_max_capacitance 0.053 [get_ports {bio}]
+set_max_capacitance 0.259 [get_ports {RC_CG_TEST_PORT}]
+set_max_capacitance 0.259 [get_ports {DFT_sen}]
+set_max_transition 1.000 [current_design]
+set_max_transition 0.766 [get_ports {as}]
+set_max_transition 0.767 [get_ports {read}]
+set_max_transition 0.794 [get_ports {write}]
+set_max_transition 0.502 [get_ports {address[7]}]
+set_max_transition 0.503 [get_ports {address[6]}]
+set_max_transition 0.503 [get_ports {address[5]}]
+set_max_transition 0.503 [get_ports {address[4]}]
+set_max_transition 0.501 [get_ports {address[3]}]
+set_max_transition 0.503 [get_ports {address[2]}]
+set_max_transition 0.502 [get_ports {address[1]}]
+set_max_transition 0.514 [get_ports {address[0]}]
+set_max_transition 0.514 [get_ports {t_data_out[15]}]
+set_max_transition 0.515 [get_ports {t_data_out[14]}]
+set_max_transition 0.507 [get_ports {t_data_out[13]}]
+set_max_transition 0.512 [get_ports {t_data_out[12]}]
+set_max_transition 0.520 [get_ports {t_data_out[11]}]
+set_max_transition 0.520 [get_ports {t_data_out[10]}]
+set_max_transition 0.517 [get_ports {t_data_out[9]}]
+set_max_transition 0.512 [get_ports {t_data_out[8]}]
+set_max_transition 0.513 [get_ports {t_data_out[7]}]
+set_max_transition 0.512 [get_ports {t_data_out[6]}]
+set_max_transition 0.516 [get_ports {t_data_out[5]}]
+set_max_transition 0.520 [get_ports {t_data_out[4]}]
+set_max_transition 0.511 [get_ports {t_data_out[3]}]
+set_max_transition 0.518 [get_ports {t_data_out[2]}]
+set_max_transition 0.518 [get_ports {t_data_out[1]}]
+set_max_transition 0.517 [get_ports {t_data_out[0]}]
+set_max_transition 0.505 [get_ports {p_address[8]}]
+set_max_transition 0.507 [get_ports {p_address[7]}]
+set_max_transition 0.507 [get_ports {p_address[6]}]
+set_max_transition 0.508 [get_ports {p_address[5]}]
+set_max_transition 0.506 [get_ports {p_address[4]}]
+set_max_transition 0.506 [get_ports {p_address[3]}]
+set_max_transition 0.506 [get_ports {p_address[2]}]
+set_max_transition 0.508 [get_ports {p_address[1]}]
+set_max_transition 0.507 [get_ports {p_address[0]}]
+set_max_transition 0.787 [get_ports {bus_request}]
+set_max_transition 0.840 [get_ports {port_address[2]}]
+set_max_transition 0.832 [get_ports {port_address[1]}]
+set_max_transition 0.844 [get_ports {port_address[0]}]
+set_max_transition 0.848 [get_ports {port_pad_data_out[15]}]
+set_max_transition 0.828 [get_ports {port_pad_data_out[14]}]
+set_max_transition 0.820 [get_ports {port_pad_data_out[13]}]
+set_max_transition 0.824 [get_ports {port_pad_data_out[12]}]
+set_max_transition 0.837 [get_ports {port_pad_data_out[11]}]
+set_max_transition 0.832 [get_ports {port_pad_data_out[10]}]
+set_max_transition 0.829 [get_ports {port_pad_data_out[9]}]
+set_max_transition 0.830 [get_ports {port_pad_data_out[8]}]
+set_max_transition 0.835 [get_ports {port_pad_data_out[7]}]
+set_max_transition 0.829 [get_ports {port_pad_data_out[6]}]
+set_max_transition 0.821 [get_ports {port_pad_data_out[5]}]
+set_max_transition 0.813 [get_ports {port_pad_data_out[4]}]
+set_max_transition 0.829 [get_ports {port_pad_data_out[3]}]
+set_max_transition 0.817 [get_ports {port_pad_data_out[2]}]
+set_max_transition 0.815 [get_ports {port_pad_data_out[1]}]
+set_max_transition 0.816 [get_ports {port_pad_data_out[0]}]
+set_max_transition 0.815 [get_ports {port_as}]
+set_max_transition 1.200 [get_ports {t_sdo[2]}]
+set_max_transition 1.200 [get_ports {t_sdo[1]}]
+set_max_transition 1.200 [get_ports {t_sdo[0]}]
+set_false_path -setup -to [get_ports {t_sdo[2]}]
+set_false_path -setup -to [get_ports {t_sdo[1]}]
+set_false_path -setup -to [get_ports {t_sdo[0]}]
+set_false_path -hold -from [get_ports {reset}]
+set_false_path -hold -from [get_ports {port_pad_data_in[15]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[14]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[13]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[12]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[11]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[10]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[9]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[8]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[7]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[6]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[5]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[4]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[3]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[2]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[1]}]
+set_false_path -hold -from [get_ports {port_pad_data_in[0]}]
+set_false_path -hold -from [get_ports {RC_CG_TEST_PORT}]
+set_false_path -hold -from [get_ports {DFT_sen}]
+set_false_path -hold -to [get_ports {port_pad_data_out[15]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[14]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[13]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[12]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[11]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[10]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[9]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[8]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[7]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[6]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[5]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[4]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[3]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[2]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[1]}]
+set_false_path -hold -to [get_ports {port_pad_data_out[0]}]
+set_false_path -hold -to [get_ports {t_sdo[2]}]
+set_false_path -hold -to [get_ports {t_sdo[1]}]
+set_false_path -hold -to [get_ports {t_sdo[0]}]
+
+set_clock_latency 1.000 \
+   [get_clocks {m_tdsp_clk}] 
+
+set_clock_uncertainty 0.200 -setup [list [get_clocks {m_tdsp_clk}] ] 
+set_multicycle_path 3 -setup \
+  -to [get_pins {EXECUTE_INST/p_reg*/state_remap/DFF/D}] 
+set_multicycle_path 3 -setup \
+  -to [get_pins {EXECUTE_INST/acc*/state_remap/DFF/D}] 
+set_multicycle_path 3 -setup \
+  -to [get_pins {EXECUTE_INST/ov_flag*/state_remap/DFF/D}] 
+set_multicycle_path 3 -hold \
+  -to [get_pins {EXECUTE_INST/p_reg*/state_remap/DFF/D}] 
+set_multicycle_path 3 -hold \
+  -to [get_pins {EXECUTE_INST/acc*/state_remap/DFF/D}] 
+set_multicycle_path 3 -hold \
+  -to [get_pins {EXECUTE_INST/ov_flag*/state_remap/DFF/D}] 
+#set_multicycle_path 3 -setup \
+#  -to [list [get_pins {EXECUTE_INST/p_reg*/D}] \
+#            [get_pins {EXECUTE_INST/acc_reg*/D}] \
+#            [get_pins {EXECUTE_INST/ov_flag_reg/D}] \
+#      ] 
+
+set_input_delay 2.5 -clock m_tdsp_clk [all_inputs]
+set_output_delay 0.5 -clock m_tdsp_clk [all_outputs]
+
diff --git a/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/tdsp_core.ctstch b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/tdsp_core.ctstch
new file mode 100755
index 0000000..db6c4fb
--- /dev/null
+++ b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/tdsp_core.ctstch
@@ -0,0 +1,31 @@
+#
+#MacroModel Section
+#
+
+
+#
+#Clock Section
+#
+
+#-----------------------------------------------------------
+# Generated from TEST_CONTROL_INST/g136/ZN
+#-----------------------------------------------------------
+AutoCTSRootPin   clk
+MaxDelay         950ps
+MinDelay         950ps
+MaxSkew          300ps
+SinkMaxTran      200ps
+BufMaxTran       200ps
+Obstruction      NO
+DetailReport     YES
+PadBufAfterGate     NO
+LevelBalanced     NO
+RouteClkNet      YES
+#PostOpt          NO
+#OptAddBuffer     NO
+#OptAddBufferLimit  50
+NoGating         NO
+Buffer BUFFD2BWP BUFFD3BWP BUFFD4BWP BUFFD6BWP BUFFD8BWP BUFFD12BWP INVD1BWP INVD2BWP INVD3BWP INVD4BWP INVD6BWP INVD8BWP INVD12BWP 
+END
+
+
diff --git a/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/tdsp_core.fp b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/tdsp_core.fp
new file mode 100755
index 0000000..4026cd2
--- /dev/null
+++ b/flow/pnr/EXAMPLES/INNOVUS/DESIGN/DATA/tdsp_core.fp
@@ -0,0 +1,1909 @@
+###############################################################
+#  Generated by:      Cadence Encounter 09.10-p004_1
+#  OS:                Linux x86_64(Host ID xv40opt01)
+#  Generated on:      Sun Jan 31 13:30:30 2010
+#  Command:           savePartition -dir PARTITION -def -scanDef
+###############################################################
+
+Version: 8
+
+Head Box: 0.0000 0.0000 141.8000 153.9000
+IO Box: 0.0000 0.0000 141.8000 153.9000
+Core Box: 0.0000 0.0000 141.8000 153.9000
+UseStdUtil: false
+
+######################################################
+#  DesignRoutingHalo: <space> <bottomLayerName> <topLayerName>
+######################################################
+
+######################################################
+#  Core Rows Parameters:                             #
+######################################################
+Row Spacing = 0.000000
+Row SpacingType = 0
+Row Flip = 1
+Core Row Site: CoreSite 
+
+##############################################################################
+#  DefRow: <name> <site> <x> <y> <orient> <num_x> <num_y> <step_x> <step_y>  #
+##############################################################################
+DefRow: ROW_0 CoreSite 0.0000 0.0000 N 709 1 0.2000 0.0000
+DefRow: ROW_1 CoreSite 0.0000 1.7100 FS 709 1 0.2000 0.0000
+DefRow: ROW_2 CoreSite 0.0000 3.4200 N 709 1 0.2000 0.0000
+DefRow: ROW_3 CoreSite 0.0000 5.1300 FS 709 1 0.2000 0.0000
+DefRow: ROW_4 CoreSite 0.0000 6.8400 N 709 1 0.2000 0.0000
+DefRow: ROW_5 CoreSite 0.0000 8.5500 FS 709 1 0.2000 0.0000
+DefRow: ROW_6 CoreSite 0.0000 10.2600 N 709 1 0.2000 0.0000
+DefRow: ROW_7 CoreSite 0.0000 11.9700 FS 709 1 0.2000 0.0000
+DefRow: ROW_8 CoreSite 0.0000 13.6800 N 709 1 0.2000 0.0000
+DefRow: ROW_9 CoreSite 0.0000 15.3900 FS 709 1 0.2000 0.0000
+DefRow: ROW_10 CoreSite 0.0000 17.1000 N 709 1 0.2000 0.0000
+DefRow: ROW_11 CoreSite 0.0000 18.8100 FS 709 1 0.2000 0.0000
+DefRow: ROW_12 CoreSite 0.0000 20.5200 N 709 1 0.2000 0.0000
+DefRow: ROW_13 CoreSite 0.0000 22.2300 FS 709 1 0.2000 0.0000
+DefRow: ROW_14 CoreSite 0.0000 23.9400 N 709 1 0.2000 0.0000
+DefRow: ROW_15 CoreSite 0.0000 25.6500 FS 709 1 0.2000 0.0000
+DefRow: ROW_16 CoreSite 0.0000 27.3600 N 709 1 0.2000 0.0000
+DefRow: ROW_17 CoreSite 0.0000 29.0700 FS 709 1 0.2000 0.0000
+DefRow: ROW_18 CoreSite 0.0000 30.7800 N 709 1 0.2000 0.0000
+DefRow: ROW_19 CoreSite 0.0000 32.4900 FS 709 1 0.2000 0.0000
+DefRow: ROW_20 CoreSite 0.0000 34.2000 N 709 1 0.2000 0.0000
+DefRow: ROW_21 CoreSite 0.0000 35.9100 FS 709 1 0.2000 0.0000
+DefRow: ROW_22 CoreSite 0.0000 37.6200 N 709 1 0.2000 0.0000
+DefRow: ROW_23 CoreSite 0.0000 39.3300 FS 709 1 0.2000 0.0000
+DefRow: ROW_24 CoreSite 0.0000 41.0400 N 709 1 0.2000 0.0000
+DefRow: ROW_25 CoreSite 0.0000 42.7500 FS 709 1 0.2000 0.0000
+DefRow: ROW_26 CoreSite 0.0000 44.4600 N 709 1 0.2000 0.0000
+DefRow: ROW_27 CoreSite 0.0000 46.1700 FS 709 1 0.2000 0.0000
+DefRow: ROW_28 CoreSite 0.0000 47.8800 N 709 1 0.2000 0.0000
+DefRow: ROW_29 CoreSite 0.0000 49.5900 FS 709 1 0.2000 0.0000
+DefRow: ROW_30 CoreSite 0.0000 51.3000 N 709 1 0.2000 0.0000
+DefRow: ROW_31 CoreSite 0.0000 53.0100 FS 709 1 0.2000 0.0000
+DefRow: ROW_32 CoreSite 0.0000 54.7200 N 709 1 0.2000 0.0000
+DefRow: ROW_33 CoreSite 0.0000 56.4300 FS 709 1 0.2000 0.0000
+DefRow: ROW_34 CoreSite 0.0000 58.1400 N 709 1 0.2000 0.0000
+DefRow: ROW_35 CoreSite 0.0000 59.8500 FS 709 1 0.2000 0.0000
+DefRow: ROW_36 CoreSite 0.0000 61.5600 N 709 1 0.2000 0.0000
+DefRow: ROW_37 CoreSite 0.0000 63.2700 FS 709 1 0.2000 0.0000
+DefRow: ROW_38 CoreSite 0.0000 64.9800 N 709 1 0.2000 0.0000
+DefRow: ROW_39 CoreSite 0.0000 66.6900 FS 709 1 0.2000 0.0000
+DefRow: ROW_40 CoreSite 0.0000 68.4000 N 709 1 0.2000 0.0000
+DefRow: ROW_41 CoreSite 0.0000 70.1100 FS 709 1 0.2000 0.0000
+DefRow: ROW_42 CoreSite 0.0000 71.8200 N 709 1 0.2000 0.0000
+DefRow: ROW_43 CoreSite 0.0000 73.5300 FS 709 1 0.2000 0.0000
+DefRow: ROW_44 CoreSite 0.0000 75.2400 N 709 1 0.2000 0.0000
+DefRow: ROW_45 CoreSite 0.0000 76.9500 FS 709 1 0.2000 0.0000
+DefRow: ROW_46 CoreSite 0.0000 78.6600 N 709 1 0.2000 0.0000
+DefRow: ROW_47 CoreSite 0.0000 80.3700 FS 709 1 0.2000 0.0000
+DefRow: ROW_48 CoreSite 0.0000 82.0800 N 709 1 0.2000 0.0000
+DefRow: ROW_49 CoreSite 0.0000 83.7900 FS 709 1 0.2000 0.0000
+DefRow: ROW_50 CoreSite 0.0000 85.5000 N 709 1 0.2000 0.0000
+DefRow: ROW_51 CoreSite 0.0000 87.2100 FS 709 1 0.2000 0.0000
+DefRow: ROW_52 CoreSite 0.0000 88.9200 N 709 1 0.2000 0.0000
+DefRow: ROW_53 CoreSite 0.0000 90.6300 FS 709 1 0.2000 0.0000
+DefRow: ROW_54 CoreSite 0.0000 92.3400 N 709 1 0.2000 0.0000
+DefRow: ROW_55 CoreSite 0.0000 94.0500 FS 709 1 0.2000 0.0000
+DefRow: ROW_56 CoreSite 0.0000 95.7600 N 709 1 0.2000 0.0000
+DefRow: ROW_57 CoreSite 0.0000 97.4700 FS 709 1 0.2000 0.0000
+DefRow: ROW_58 CoreSite 0.0000 99.1800 N 709 1 0.2000 0.0000
+DefRow: ROW_59 CoreSite 0.0000 100.8900 FS 709 1 0.2000 0.0000
+DefRow: ROW_60 CoreSite 0.0000 102.6000 N 709 1 0.2000 0.0000
+DefRow: ROW_61 CoreSite 0.0000 104.3100 FS 709 1 0.2000 0.0000
+DefRow: ROW_62 CoreSite 0.0000 106.0200 N 709 1 0.2000 0.0000
+DefRow: ROW_63 CoreSite 0.0000 107.7300 FS 709 1 0.2000 0.0000
+DefRow: ROW_64 CoreSite 0.0000 109.4400 N 709 1 0.2000 0.0000
+DefRow: ROW_65 CoreSite 0.0000 111.1500 FS 709 1 0.2000 0.0000
+DefRow: ROW_66 CoreSite 0.0000 112.8600 N 709 1 0.2000 0.0000
+DefRow: ROW_67 CoreSite 0.0000 114.5700 FS 709 1 0.2000 0.0000
+DefRow: ROW_68 CoreSite 0.0000 116.2800 N 709 1 0.2000 0.0000
+DefRow: ROW_69 CoreSite 0.0000 117.9900 FS 709 1 0.2000 0.0000
+DefRow: ROW_70 CoreSite 0.0000 119.7000 N 709 1 0.2000 0.0000
+DefRow: ROW_71 CoreSite 0.0000 121.4100 FS 709 1 0.2000 0.0000
+DefRow: ROW_72 CoreSite 0.0000 123.1200 N 709 1 0.2000 0.0000
+DefRow: ROW_73 CoreSite 0.0000 124.8300 FS 709 1 0.2000 0.0000
+DefRow: ROW_74 CoreSite 0.0000 126.5400 N 709 1 0.2000 0.0000
+DefRow: ROW_75 CoreSite 0.0000 128.2500 FS 709 1 0.2000 0.0000
+DefRow: ROW_76 CoreSite 0.0000 129.9600 N 709 1 0.2000 0.0000
+DefRow: ROW_77 CoreSite 0.0000 131.6700 FS 709 1 0.2000 0.0000
+DefRow: ROW_78 CoreSite 0.0000 133.3800 N 709 1 0.2000 0.0000
+DefRow: ROW_79 CoreSite 0.0000 135.0900 FS 709 1 0.2000 0.0000
+DefRow: ROW_80 CoreSite 0.0000 136.8000 N 709 1 0.2000 0.0000
+DefRow: ROW_81 CoreSite 0.0000 138.5100 FS 709 1 0.2000 0.0000
+DefRow: ROW_82 CoreSite 0.0000 140.2200 N 709 1 0.2000 0.0000
+DefRow: ROW_83 CoreSite 0.0000 141.9300 FS 709 1 0.2000 0.0000
+DefRow: ROW_84 CoreSite 0.0000 143.6400 N 709 1 0.2000 0.0000
+DefRow: ROW_85 CoreSite 0.0000 145.3500 FS 709 1 0.2000 0.0000
+DefRow: ROW_86 CoreSite 0.0000 147.0600 N 709 1 0.2000 0.0000
+DefRow: ROW_87 CoreSite 0.0000 148.7700 FS 709 1 0.2000 0.0000
+DefRow: ROW_88 CoreSite 0.0000 150.4800 N 709 1 0.2000 0.0000
+DefRow: ROW_89 CoreSite 0.0000 152.1900 FS 709 1 0.2000 0.0000
+
+######################################################
+#  Track: dir start number space layer_num layer1 ...#
+######################################################
+Track: X 0.1000 709 0.2000 1 9
+Track: Y 0.2850 405 0.3800 1 9
+Track: Y 0.2850 540 0.2850 1 8
+Track: X 0.1000 709 0.2000 1 8
+Track: X 0.1000 709 0.2000 1 7
+Track: Y 0.2850 540 0.2850 1 7
+Track: Y 0.0950 810 0.1900 1 6
+Track: X 0.1000 709 0.2000 1 6
+Track: X 0.1000 709 0.2000 1 5
+Track: Y 0.0950 810 0.1900 1 5
+Track: Y 0.0950 810 0.1900 1 4
+Track: X 0.1000 709 0.2000 1 4
+Track: X 0.1000 709 0.2000 1 3
+Track: Y 0.0950 810 0.1900 1 3
+Track: Y 0.0950 810 0.1900 1 2
+Track: X 0.1000 709 0.2000 1 2
+Track: X 0.1000 709 0.2000 1 1
+Track: Y 0.0950 810 0.1900 1 1
+
+######################################################
+#  GCellGrid: dir start number space                 #
+######################################################
+GCellGrid: Y 0.0000 2 1.8950
+GCellGrid: Y 1.8950 73 2.1000
+GCellGrid: Y 153.0950 2 0.8050
+GCellGrid: X 0.0000 2 1.9300
+GCellGrid: X 1.9300 67 2.1000
+GCellGrid: X 140.5300 2 1.2700
+
+######################################################
+#  SpareCell: cellName                               #
+#  SpareInst: instName                               #
+######################################################
+
+######################################################
+#  ScanGroup: groupName startPin stopPin             #
+######################################################
+
+######################################################
+#  JtagCell:  leafCellName                           #
+#  JtagInst:  <instName | HInstName>                 #
+######################################################
+
+######################################################################################
+#  BlackBox: -cell <cell_name> { -size <x> <y> |  -area <um^2> | \                  #
+#            -gatecount <count> <areapergate> <utilization> | \                     #
+#            {-gateArea <gateAreaValue> [-macroArea <macroAreaValue>]} } \          #
+#            [-minwidth <w> | -minheight <h> | -fixedwidh <w> | -fixedheight <h>] \ #
+#            [-aspectratio <ratio>]                                                  #
+#            [-boxList <nrConstraintBox>                                             #
+#              ConstraintBox: <llx> <lly> <urx> <ury>                                #
+#              ... ]                                                                 #
+######################################################################################
+
+#########################################################
+#  PhysicalNet: <name> [-pwr|-gnd|-tiehi|-tielo]        #
+#########################################################
+PhysicalNet: Avdd -pwr
+PhysicalNet: Avss -gnd
+PhysicalNet: AVss -gnd
+PhysicalNet: VSS -gnd
+PhysicalNet: AVdd -pwr
+PhysicalNet: VDD -pwr
+
+#########################################################
+#  PhysicalInstance: <name> <cell> <orient> <llx> <lly> #
+#########################################################
+
+#####################################################################
+#  Group: <group_name> <nrHinst> [-isPhyHier]                       #
+#    <inst_name>                                                    #
+#    ...                                                            #
+#####################################################################
+
+#####################################################################
+#  Fence:  <name> <llx> <lly> <urx> <ury> <nrConstraintBox>         #
+#    ConstraintBox: <llx> <lly> <urx> <ury>                         #
+#    ...                                                            #
+#  Region: <name> <llx> <lly> <urx> <ury> <nrConstraintBox>         #
+#    ConstraintBox: <llx> <lly> <urx> <ury>                         #
+#    ...                                                            #
+#  Guide:  <name> <llx> <lly> <urx> <ury> <nrConstraintBox>         #
+#    ConstraintBox: <llx> <lly> <urx> <ury>                         #
+#    ...                                                            #
+#  SoftGuide: <name>                                                #
+#    ...                                                            #
+#####################################################################
+
+###########################################################################
+#  <Constraints>                                                          #
+#     <Constraint  type="fence|guide|region|softguide"                    #
+#                  readonly=1  name="blk_name">                           #
+#       <Box llx=1 lly=2 urx=3 ury=4 /> ...                               #
+#     </Constraint>                                                       #
+#  </Constraints>                                                         #
+###########################################################################
+###########################################################################
+#  <HierarchicalPartitions>                                               #
+#     <NetGroup name="group_name" nets=val spacing=val isOptOrder=val isAltLayer=val isPffGroup=val > #
+#         <Net name="net_name" /> ...                                     #
+#     </NetGroup>                                                         #
+#     <Partition name="ptn_name"  hinst="name"                            #
+#         coreToLeft=fval coreToRight=fval coreToTop=fval coreToBottom=fval   #
+#         pinSpacingNorth=val pinSpacingWest=val pinSpacingSouth=val      #
+#         pinSpacingEast=val  blockedLayers=xval >       #
+#         <TrackHalfPitch Horizontal=val Vertical=val />                  #
+#         <SpacingHalo left=10.0 right=11.0 top=11.0 bottom=11.0 />       #
+#         <Clone hinst="hinst_name" orient=R0|R90|... />                  #
+#         <PinLayer side="N|W|S|E" Metal1=yes Metal2=yes ... />           #
+#         <RowSize cellHeight=1.0 railWidth=1.0 />                        #
+#         <RoutingHalo sideSize=11.0 bottomLayer=M1 topLayer=M2  />       #
+#         <SpacingHalo left=11.0 right=11.0 top=11.0 bottom=11.0 />       #
+#     </Partition>                                                        #
+#     <CellPinGroup name="group_name" cell="cell_name"                    #
+#                       pins=nr spacing=val isOptOrder=1 isAltLayer=1 >   #
+#         <GroupFTerm name="term_name" /> ...                             #
+#     </CellPinGroup>                                                     #
+#     <PartitionPinBlockage layerMap=x llx=1 lly=2 urx=3 ury=4 name="n" />#
+#     <PinGuide name="name" boxes=num cell="name" >                       #
+#        <Box llx=11.0 lly=22.0 urx=33.0 ury=44.0 layer=id /> ...         #
+#     </PinGuide>                                                         #
+#     <CellPtnCut name="name" cuts=Num >                                  #
+#        <Box llx=11.0 lly=22.0 urx=33.0 ury=44.0 /> ...                  #
+#     </CellPtnCut>                                                       #
+#  </HierarchicalPartitions>                                              #
+###########################################################################
+<HierarchicalPartitions>
+    <Partition name="tdsp_core" hinst="" coreToLeft=0.0000 coreToRight=0.0000 coreToTop=0.0000 coreToBottom=0.0000 pinSpacingNorth=2 pinSpacingWest=2 pinSpacingSouth=2 pinSpacingEast=2 blockedLayers=0x1ff >
+	<PinLayer side="N" Metal2=yes Metal4=yes Metal6=yes />
+	<PinLayer side="W" Metal3=yes Metal5=yes />
+	<PinLayer side="S" Metal2=yes Metal4=yes Metal6=yes />
+	<PinLayer side="E" Metal3=yes Metal5=yes />
+	<RowSize cellHeight=1.7100 railWidth=0.0000 />
+    </Partition>
+</HierarchicalPartitions>
+
+######################################################
+#  Instance: <name> <orient> <llx> <lly>             #
+######################################################
+
+#################################################################
+#  Block: <name> <orient> [<llx> <lly>]                         #
+#         [<haloLeftMargin>  <haloBottomMargin>                 #
+#          <haloRightMargin> <haloTopMargin> <haloFromInstBox>] #
+#         [<IsInstDefCovered> <IsInstPreplaced>]                #
+#                                                               #
+#  Block with INT_MAX loc is for recording the halo block with  #
+#  non-prePlaced status                                         #
+#################################################################
+
+######################################################
+#  BlockLayerObstruct: <name> <layerX> ...           #
+######################################################
+
+######################################################
+#  FeedthroughBuffer: <instName>                     #
+######################################################
+
+#################################################################
+#  <PlacementBlockages>                                         #
+#     <Blockage name="blk_name" type="hard|soft|partial">       #
+#       <Attr density=1.2 inst="inst_name" pushdown=yes />      #
+#       <Box llx=1 lly=2 urx=3 ury=4 /> ...                     #
+#     </Blockage>                                               #
+#  </PlacementBlockages>                                        #
+#################################################################
+
+###########################################################################
+#  <RouteBlockages>                                                       #
+#     <Blockage name="blk_name" type="User|RouteGuide|PtnCut|WideWire">   #
+#       <Attr spacing=1.2 drw=1.2 inst="name" pushdown=yes fills=yes />   #
+#       <Layer type="route|cut|masterslice" id=layerNo />                 #
+#       <Box llx=1 lly=2 urx=3 ury=4 /> ...                               #
+#       <Poly points=nr x0=1 y0=1 x1=2 y2=2 ...  />                       #
+#     </Blockage>                                                         #
+#  </RouteBlockages>                                                      #
+###########################################################################
+
+######################################################
+#  PrerouteAsObstruct: <layer_treated_as_obstruct>   #
+######################################################
+PrerouteAsObstruct: 0x3
+
+######################################################
+#  NetWeight: <net_name> <weight (in integer)>       #
+######################################################
+
+#################################################################
+#  SprFile: <file_name>                                         #
+#################################################################
+SprFile: tdsp_core.fp.spr
+
+##########################################################################
+#  <IOPins>                                                              #
+#    <Pin name="pin_name" type="clock|power|ground|analog"               #
+#         status="covered|fixed|placed" is_special=1 >                   #
+#      <Port>                                                            #
+#        <Pref x=1 y=2 side="N|S|W|E|U|D" width=w depth=d />             #
+#        <Via name="via_name" x=1 y=2 /> ...                             #
+#        <Layer id=id spacing=1.2 drw=1.2>                               #
+#          <Box llx=1 lly=2 urx=3 ury=4 /> ...                           #
+#          <Poly points=nr x0=1 y0=1 x1=2 y2=2 ...           />          #
+#        </Layer> ...                                                    #
+#      </Port>  ...                                                      #
+#      <Antenna model=num type="name" value=float_num layer=num /> ...   #
+#    </Pin> ...                                                          #
+#  </IOPins>                                                             #
+##########################################################################
+
+<IOPins>
+  <Pin name="clk" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=108.7750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=108.7400 urx=0.2900 ury=108.8100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="reset" status="fixed" >
+    <Port>
+      <Pref x=14.7000 y=0.0000 side=S width=0.0700 depth=0.2900 />
+      <Layer id=2 >
+        <Box llx=14.6650 lly=0.0000 urx=14.7350 ury=0.2900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="as" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=132.5250 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=132.4900 urx=0.2900 ury=132.5600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="read" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=130.8150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=130.7800 urx=0.2900 ury=130.8500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="write" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=127.3950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=127.3600 urx=0.2900 ury=127.4300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="write_h" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=77.0450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=77.0100 urx=0.2900 ury=77.0800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[7]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=111.8150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=111.7800 urx=0.2900 ury=111.8500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[6]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=107.0650 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=107.0300 urx=0.2900 ury=107.1000 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[5]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=104.2150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=104.1800 urx=0.2900 ury=104.2500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[4]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=111.8150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=111.7800 urx=0.2900 ury=111.8500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[3]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=113.9050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=113.8700 urx=0.2900 ury=113.9400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[2]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=118.6550 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=118.6200 urx=0.2900 ury=118.6900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[1]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=115.2350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=115.2000 urx=0.2900 ury=115.2700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="address[0]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=120.7450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=120.7100 urx=0.2900 ury=120.7800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[15]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.7950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=81.7600 urx=0.2900 ury=81.8300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[14]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=72.4850 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=72.4500 urx=0.2900 ury=72.5200 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[13]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.7950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=81.7600 urx=0.2900 ury=81.8300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[12]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=72.6750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=72.6400 urx=0.2900 ury=72.7100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[11]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=66.9750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=66.9400 urx=0.2900 ury=67.0100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[10]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=66.4050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=66.3700 urx=0.2900 ury=66.4400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[9]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=73.0550 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=73.0200 urx=0.2900 ury=73.0900 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[8]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=73.4350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=73.4000 urx=0.2900 ury=73.4700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[7]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=82.7450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=82.7100 urx=0.2900 ury=82.7800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[6]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=79.3250 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=79.2900 urx=0.2900 ury=79.3600 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[5]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.4150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=81.3800 urx=0.2900 ury=81.4500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[4]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=82.7450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=82.7100 urx=0.2900 ury=82.7800 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[3]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=73.4350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=73.4000 urx=0.2900 ury=73.4700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[2]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=84.8350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=84.8000 urx=0.2900 ury=84.8700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[1]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=77.9950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=77.9600 urx=0.2900 ury=78.0300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_in[0]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.4150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=81.3800 urx=0.2900 ury=81.4500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[15]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=104.2150 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=104.1800 urx=0.2900 ury=104.2500 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[14]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=91.2950 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=91.2600 urx=0.2900 ury=91.3300 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[13]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=81.0350 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=81.0000 urx=0.2900 ury=81.0700 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[12]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=79.7050 side=W width=0.0700 depth=0.2900 />
+      <Layer id=5 >
+        <Box llx=0.0000 lly=79.6700 urx=0.2900 ury=79.7400 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[11]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=87.8750 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=87.8400 urx=0.2900 ury=87.9100 />
+      </Layer>
+    </Port>
+  </Pin>
+  <Pin name="t_data_out[10]" status="fixed" >
+    <Port>
+      <Pref x=0.0000 y=86.5450 side=W width=0.0700 depth=0.2900 />
+      <Layer id=3 >
+        <Box llx=0.0000 lly=86.5100 urx=0.2900 ury=86.5800 />
+      </Layer>