diff --git a/verilog/sky130_osu_sc.v b/verilog/sky130_osu_sc.v
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@@ -0,0 +1,1667 @@
+// Verilog for library /import/okita1/tdene/final_final/osugooglelib/char/liberate/VERILOG/sky130_osu_sc.v created by Liberate 19.2.1.215 on Wed Apr 15 19:42:51 CDT 2020 for SDF version 2.1
+
+// type: ADDF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_ADDFX1 (CO, S, A, B, CI);
+	output CO, S;
+	input A, B, CI;
+
+	// Function
+	wire A__bar, B__bar, CI__bar;
+	wire int_fwire_0, int_fwire_1, int_fwire_2;
+	wire int_fwire_3, int_fwire_4, int_fwire_5;
+	wire int_fwire_6;
+
+	and (int_fwire_0, B, CI);
+	and (int_fwire_1, A, CI);
+	and (int_fwire_2, A, B);
+	or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_3, A__bar, B__bar, CI);
+	not (CI__bar, CI);
+	and (int_fwire_4, A__bar, B, CI__bar);
+	and (int_fwire_5, A, B__bar, CI__bar);
+	and (int_fwire_6, A, B, CI);
+	or (S, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(A => CO) = 0;
+		if ((~B & CI))
+			(A => CO) = 0;
+		ifnone (A => CO) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(B => CO) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(CI => CO) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & CI))
+			(A => S) = 0;
+		if ((~B & ~CI))
+			(A => S) = 0;
+		ifnone (A => S) = 0;
+		if ((B & ~CI))
+			(A => S) = 0;
+		if ((~B & CI))
+			(A => S) = 0;
+		if ((A & CI))
+			(B => S) = 0;
+		if ((~A & ~CI))
+			(B => S) = 0;
+		ifnone (B => S) = 0;
+		if ((A & ~CI))
+			(B => S) = 0;
+		if ((~A & CI))
+			(B => S) = 0;
+		if ((A & B))
+			(CI => S) = 0;
+		if ((~A & ~B))
+			(CI => S) = 0;
+		ifnone (CI => S) = 0;
+		if ((A & ~B))
+			(CI => S) = 0;
+		if ((~A & B))
+			(CI => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: ADDF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_ADDFXL (CO, S, A, B, CI);
+	output CO, S;
+	input A, B, CI;
+
+	// Function
+	or (CO, B, CI);
+	buf (S, 1'b1);
+
+	// Timing
+	specify
+		if ((B & ~CI))
+			(posedge A => (CO+:1'b1)) = 0;
+		if ((~B & CI))
+			(posedge A => (CO+:1'b1)) = 0;
+		ifnone (posedge A => (CO+:1'b1)) = 0;
+		if ((A & ~CI))
+			(B => CO) = 0;
+		if ((~A & CI))
+			(posedge B => (CO+:1'b1)) = 0;
+		if ((~A & ~CI))
+			(negedge B => (CO+:1'b0)) = 0;
+		ifnone (B => CO) = 0;
+		if ((A & ~B))
+			(CI => CO) = 0;
+		if ((~A & B))
+			(posedge CI => (CO+:1'b1)) = 0;
+		if ((~A & ~B))
+			(negedge CI => (CO+:1'b0)) = 0;
+		ifnone (CI => CO) = 0;
+		if ((B & CI))
+			(posedge A => (S+:1'b1)) = 0;
+		if ((~B & ~CI))
+			(posedge A => (S+:1'b1)) = 0;
+		ifnone (posedge A => (S+:1'b1)) = 0;
+		if ((A & CI))
+			(posedge B => (S+:1'b1)) = 0;
+		if ((~A & ~CI))
+			(posedge B => (S+:1'b1)) = 0;
+		ifnone (posedge B => (S+:1'b1)) = 0;
+		if ((A & B))
+			(posedge CI => (S+:1'b1)) = 0;
+		if ((~A & ~B))
+			(posedge CI => (S+:1'b1)) = 0;
+		ifnone (posedge CI => (S+:1'b1)) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: ADDH 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_ADDHX1 (CO, S, A, B);
+	output CO, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	and (CO, A, B);
+	not (B__bar, B);
+	not (A__bar, A);
+	or (S, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		ifnone (posedge A => (S+:1'b1)) = 0;
+		(A => S) = 0;
+		ifnone (posedge B => (S+:1'b1)) = 0;
+		(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: ADDH 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_ADDHXL (CO, S, A, B);
+	output CO, S;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	and (CO, A, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B);
+	not (B__bar, B);
+	and (int_fwire_1, A, B__bar);
+	or (S, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A => CO) = 0;
+		(B => CO) = 0;
+		if (~B)
+			(A => S) = 0;
+		if (B)
+			(A => S) = 0;
+		if (~A)
+			(B => S) = 0;
+		if (A)
+			(B => S) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: AND2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_AND2X1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: AND2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_AND2X2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: AND2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_AND2X4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: AND2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_AND2X8 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: AND2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_AND2XL (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	and (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: AND3 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_AND3XL (Y, A, B, C);
+	output Y;
+	input A, B, C;
+
+	// Function
+	wire A__bar, B__bar, C__bar;
+
+	not (C__bar, C);
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar, C__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+		(C => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: ANT 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_ANT (A);
+	input A;
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: AOI21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_AOI21XL (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0, int_fwire_1;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	and (int_fwire_0, A1__bar, B0__bar);
+	not (A0__bar, A0);
+	and (int_fwire_1, A0__bar, B0__bar);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		if ((~A0 & ~A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: BUF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_BUFX1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: BUF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_BUFX2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: BUF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_BUFX4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: BUF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_BUFX6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: BUF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_BUFX8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: BUF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_BUFXL (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: CLKBUF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_CLKBUFX1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: CLKINV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_CLKINVX1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: CLKINV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_CLKINVX2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: CLKINV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_CLKINVX4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: DFFN 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_DFFNXL (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_clk, int_fwire_IQ, int_fwire_IQN;
+	wire xcr_0;
+
+	not (int_fwire_clk, delayed_CK);
+	altos_dff_err (xcr_0, int_fwire_clk, delayed_D);
+	altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(negedge CK => (Q+:D)) = 0;
+		(negedge CK => (QN-:D)) = 0;
+		$setuphold (negedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (negedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+		$width (posedge CK &&& ~D, 0, 0, notifier);
+		$width (negedge CK &&& ~D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: DFFR 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_DFFRXL (Q, QN, D, RN, CK);
+	output Q, QN;
+	input D, RN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+	wire xcr_0;
+
+	not (int_fwire_r, RN);
+	altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+	altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, RN);
+	not (D__bar, D);
+	and (adacond1, D__bar, RN);
+
+	specify
+		if (CK)
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (Q+:1'b0)) = 0;
+		ifnone (negedge RN => (Q+:1'b0)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		if ((~CK & ~D))
+			(negedge RN => (QN-:1'b0)) = 0;
+		ifnone (negedge RN => (QN-:1'b0)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+		$recovery (posedge RN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+		$hold (posedge CK, posedge RN, 0, notifier);
+		$width (negedge RN &&& CK, 0, 0, notifier);
+		$width (negedge RN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: DFFS 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_DFFSXL (Q, QN, D, SN, CK);
+	output Q, QN;
+	input D, SN, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+	wire xcr_0;
+
+	not (int_fwire_s, SN);
+	altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+	altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+
+	// Additional timing wires
+	wire adacond0, adacond1, D__bar;
+
+
+	// Additional timing gates
+	and (adacond0, D, SN);
+	not (D__bar, D);
+	and (adacond1, D__bar, SN);
+
+	specify
+		if (CK)
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (Q+:1'b1)) = 0;
+		ifnone (negedge SN => (Q+:1'b1)) = 0;
+		(posedge CK => (Q+:D)) = 0;
+		if (CK)
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		if ((~CK & ~D))
+			(negedge SN => (QN-:1'b1)) = 0;
+		ifnone (negedge SN => (QN-:1'b1)) = 0;
+		(posedge CK => (QN-:D)) = 0;
+		$setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+		$recovery (posedge SN, posedge CK, 0, notifier);
+		$hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+		$hold (posedge CK, posedge SN, 0, notifier);
+		$width (negedge SN &&& CK, 0, 0, notifier);
+		$width (negedge SN &&& ~CK, 0, 0, notifier);
+		$width (posedge CK &&& adacond0, 0, 0, notifier);
+		$width (negedge CK &&& adacond0, 0, 0, notifier);
+		$width (posedge CK &&& adacond1, 0, 0, notifier);
+		$width (negedge CK &&& adacond1, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: DFF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_DFFXL (Q, QN, D, CK);
+	output Q, QN;
+	input D, CK;
+	reg notifier;
+	wire delayed_D, delayed_CK;
+
+	// Function
+	wire delayed_D__bar, int_fwire_0, int_fwire_d;
+	wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+	not (delayed_D__bar, delayed_D);
+	and (int_fwire_0, delayed_D__bar, int_fwire_IQ);
+	or (int_fwire_d, delayed_D, int_fwire_0);
+	altos_dff_err (xcr_0, delayed_CK, int_fwire_d);
+	altos_dff (int_fwire_IQ, notifier, delayed_CK, int_fwire_d, xcr_0);
+	buf (Q, int_fwire_IQ);
+	not (int_fwire_IQN, int_fwire_IQ);
+	buf (QN, int_fwire_IQN);
+
+	// Timing
+	specify
+		(posedge CK => (Q+:((D) || (!D && int_fwire_IQ)))) = 0;
+		(posedge CK => (QN-:((D) || (!D && int_fwire_IQ)))) = 0;
+		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+		$width (posedge CK &&& D, 0, 0, notifier);
+		$width (negedge CK &&& D, 0, 0, notifier);
+	endspecify
+endmodule
+`endcelldefine
+
+// type: DLY1 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_DLY1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: DLY2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_DLY2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: DLY3 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_DLY3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: DLY4 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_DLY4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	buf (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: INV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_INVX1 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: INV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_INVX10 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: INV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_INVX2 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: INV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_INVX3 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: INV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_INVX4 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: INV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_INVX6 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: INV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_INVX8 (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: INV 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_INVXL (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	not (Y, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: NAND2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_NAND2X1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: NAND2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_NAND2XL (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: NAND3 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_NAND3X1 (Y, A, B, C);
+	output Y;
+	input A, B, C;
+
+	// Function
+	wire A__bar, B__bar, C__bar;
+
+	not (C__bar, C);
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar, C__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+		(C => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: NAND3 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_NAND3XL (Y, A, B, C);
+	output Y;
+	input A, B, C;
+
+	// Function
+	wire A__bar, B__bar, C__bar;
+
+	not (C__bar, C);
+	not (B__bar, B);
+	not (A__bar, A);
+	or (Y, A__bar, B__bar, C__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+		(C => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: NOR2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_NOR2X1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: NOR2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_NOR2XL (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (Y, A__bar, B__bar);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: OAI21 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_OAI21XL (Y, A0, A1, B0);
+	output Y;
+	input A0, A1, B0;
+
+	// Function
+	wire A0__bar, A1__bar, B0__bar;
+	wire int_fwire_0;
+
+	not (B0__bar, B0);
+	not (A1__bar, A1);
+	not (A0__bar, A0);
+	and (int_fwire_0, A0__bar, A1__bar);
+	or (Y, int_fwire_0, B0__bar);
+
+	// Timing
+	specify
+		(A0 => Y) = 0;
+		(A1 => Y) = 0;
+		if ((A0 & A1))
+			(B0 => Y) = 0;
+		if ((A0 & ~A1))
+			(B0 => Y) = 0;
+		if ((~A0 & A1))
+			(B0 => Y) = 0;
+		ifnone (B0 => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: OR2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_OR2X1 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: OR2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_OR2X2 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+		ifnone (posedge A => (Y+:1'b1)) = 0;
+		ifnone (posedge B => (Y+:1'b1)) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: OR2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_OR2X4 (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: OR2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_OR2XL (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	or (Y, A, B);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: TBUF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_TBUFXL (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	bufif1 (Y, 1'b1, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(negedge A => (Y:1)) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: TIEHI 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_TIEHI (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b1);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: TIELO 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_TIELO (Y);
+	output Y;
+
+	// Function
+	buf (Y, 1'b0);
+
+	// Timing
+	specify
+	endspecify
+endmodule
+`endcelldefine
+
+// type: TNBUF 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_TNBUFXL (Y, A);
+	output Y;
+	input A;
+
+	// Function
+	bufif0 (Y, 1'b1, A);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		(negedge A => (Y:1)) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: XNOR2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_XNOR2XL (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, B__bar, int_fwire_0;
+	wire int_fwire_1;
+
+	not (B__bar, B);
+	not (A__bar, A);
+	and (int_fwire_0, A__bar, B__bar);
+	and (int_fwire_1, A, B);
+	or (Y, int_fwire_1, int_fwire_0);
+
+	// Timing
+	specify
+		if (B)
+			(A => Y) = 0;
+		if (~B)
+			(A => Y) = 0;
+		if (A)
+			(B => Y) = 0;
+		if (~A)
+			(B => Y) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+// type: XOR2 
+`timescale 1ns/10ps
+`celldefine
+module sky130_osu_sc_XOR2XL (Y, A, B);
+	output Y;
+	input A, B;
+
+	// Function
+	wire A__bar, int_fwire_enable;
+
+	not (A__bar, A);
+	and (int_fwire_enable, A__bar, B);
+	bufif0 (Y, 1'b1, int_fwire_enable);
+
+	// Timing
+	specify
+		(A => Y) = 0;
+		ifnone (posedge A => (Y-:1'b0)) = 0;
+		(negedge A => (Y:1)) = 0;
+		ifnone (negedge B => (Y+:1'b0)) = 0;
+		(B => Y) = 0;
+		(posedge B => (Y:1)) = 0;
+	endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+	output q;
+	reg q;
+	input v, clk, d;
+
+	table
+		* ? ? : ? : x;
+		? 1 0 : ? : 0;
+		? 1 1 : ? : 1;
+		? x 0 : 0 : -;
+		? x 1 : 1 : -;
+		? 0 ? : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+	output q;
+	reg q;
+	input clk, d;
+
+	table
+		(0x) ? : ? : 0;
+		(1x) ? : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+	output q;
+	reg q;
+	input v, clk, d, xcr;
+
+	table
+		*  ?   ? ? : ? : x;
+		? (x1) 0 0 : ? : 0;
+		? (x1) 1 0 : ? : 1;
+		? (x1) 0 1 : 0 : 0;
+		? (x1) 1 1 : 1 : 1;
+		? (x1) ? x : ? : -;
+		? (bx) 0 ? : 0 : -;
+		? (bx) 1 ? : 1 : -;
+		? (x0) b ? : ? : -;
+		? (x0) ? x : ? : -;
+		? (01) 0 ? : ? : 0;
+		? (01) 1 ? : ? : 1;
+		? (10) ? ? : ? : -;
+		?  b   * ? : ? : -;
+		?  ?   ? * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+	output q;
+	reg q;
+	input clk, d, r;
+
+	table
+		 ?   0 (0x) : ? : -;
+		 ?   0 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 0  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 0  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, r, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 0;
+		?  b   ? (1?) ? : 0 : -;
+		?  x   0 (1?) ? : 0 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 0 : -;
+		? (x1) 0  ?   0 : ? : 0;
+		? (x1) 1  0   0 : ? : 1;
+		? (x1) 0  ?   1 : 0 : 0;
+		? (x1) 1  0   1 : 1 : 1;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 0  ?   ? : 0 : -;
+		? (bx) 1  0   ? : 1 : -;
+		? (x0) 0  ?   ? : ? : -;
+		? (x0) 1  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 0  ?   ? : ? : 0;
+		? (01) 1  0   ? : ? : 1;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+	output q;
+	reg q;
+	input clk, d, s;
+
+	table
+		 ?   1 (0x) : ? : -;
+		 ?   1 (x0) : ? : -;
+		(0x) ?  0   : ? : 0;
+		(0x) 1  x   : ? : 0;
+		(1x) ?  0   : ? : 1;
+		(1x) 1  x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, xcr;
+
+	table
+		*  ?   ?  ?   ? : ? : x;
+		?  ?   ?  1   ? : ? : 1;
+		?  b   ? (1?) ? : 1 : -;
+		?  x   1 (1?) ? : 1 : -;
+		?  ?   ? (10) ? : ? : -;
+		?  ?   ? (x0) ? : ? : -;
+		?  ?   ? (0x) ? : 1 : -;
+		? (x1) 0  0   0 : ? : 0;
+		? (x1) 1  ?   0 : ? : 1;
+		? (x1) 1  ?   1 : 1 : 1;
+		? (x1) 0  0   1 : 0 : 0;
+		? (x1) ?  ?   x : ? : -;
+		? (bx) 1  ?   ? : 1 : -;
+		? (bx) 0  0   ? : 0 : -;
+		? (x0) 1  ?   ? : ? : -;
+		? (x0) 0  0   ? : ? : -;
+		? (x0) ?  0   x : ? : -;
+		? (01) 1  ?   ? : ? : 1;
+		? (01) 0  0   ? : ? : 0;
+		? (10) ?  ?   ? : ? : -;
+		?  b   *  ?   ? : ? : -;
+		?  ?   ?  ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+	output q;
+	reg q;
+	input clk, d, s, r;
+
+	table
+		 ?   1 (0x)  ?   : ? : -;
+		 ?   0  ?   (0x) : ? : -;
+		 ?   0  ?   (x0) : ? : -;
+		(0x) ?  0    0   : ? : 0;
+		(0x) 1  x    0   : ? : 0;
+		(0x) 0  0    x   : ? : 0;
+		(1x) ?  0    0   : ? : 1;
+		(1x) 1  x    0   : ? : 1;
+		(1x) 0  0    x   : ? : 1;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   ?   1   ? : ? : 0;
+		?  ?   ?   1   0   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+	output q;
+	reg q;
+	input v, clk, d, s, r, xcr;
+
+	table
+	//	v,  clk, d, s, r : q' : q;
+
+		*  ?   ?   ?   ?   ? : ? : x;
+		?  ?   ?   0   1   ? : ? : 0;
+		?  ?   ?   1   ?   ? : ? : 1;
+		?  b   ? (1?)  0   ? : 1 : -;
+		?  x   1 (1?)  0   ? : 1 : -;
+		?  ?   ? (10)  0   ? : ? : -;
+		?  ?   ? (x0)  0   ? : ? : -;
+		?  ?   ? (0x)  0   ? : 1 : -;
+		?  b   ?  0   (1?) ? : 0 : -;
+		?  x   0  0   (1?) ? : 0 : -;
+		?  ?   ?  0   (10) ? : ? : -;
+		?  ?   ?  0   (x0) ? : ? : -;
+		?  ?   ?  0   (0x) ? : 0 : -;
+		? (x1) 0  0    ?   0 : ? : 0;
+		? (x1) 1  ?    0   0 : ? : 1;
+		? (x1) 0  0    ?   1 : 0 : 0;
+		? (x1) 1  ?    0   1 : 1 : 1;
+		? (x1) ?  ?    0   x : ? : -;
+		? (x1) ?  0    ?   x : ? : -;
+		? (1x) 0  0    ?   ? : 0 : -;
+		? (1x) 1  ?    0   ? : 1 : -;
+		? (x0) 0  0    ?   ? : ? : -;
+		? (x0) 1  ?    0   ? : ? : -;
+		? (x0) ?  0    0   x : ? : -;
+		? (0x) 0  0    ?   ? : 0 : -;
+		? (0x) 1  ?    0   ? : 1 : -;
+		? (01) 0  0    ?   ? : ? : 0;
+		? (01) 1  ?    0   ? : ? : 1;
+		? (10) ?  0    ?   ? : ? : -;
+		? (10) ?  ?    0   ? : ? : -;
+		?  b   *  0    ?   ? : ? : -;
+		?  b   *  ?    0   ? : ? : -;
+		?  ?   ?  ?    ?   * : ? : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+	output q;
+	reg q;
+	input v, clk, d, r;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 0;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 0 : -;
+		? 1 0 0 : ? : 0;
+		? 1 0 x : ? : 0;
+		? 1 1 0 : ? : 1;
+		? x 0 0 : 0 : -;
+		? x 0 x : 0 : -;
+		? x 1 0 : 1 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+	output q;
+	reg q;
+	input v, clk, d, s;
+
+	table
+		* ? ? ? : ? : x;
+		? ? ? 1 : ? : 1;
+		? 0 ? 0 : ? : -;
+		? 0 ? x : 1 : -;
+		? 1 1 0 : ? : 1;
+		? 1 1 x : ? : 1;
+		? 1 0 0 : ? : 0;
+		? x 1 0 : 1 : -;
+		? x 1 x : 1 : -;
+		? x 0 0 : 0 : -;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 0 : ? : 1;
+		? ? ? ? 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+	output q;
+	reg q;
+	input v, clk, d, s, r;
+
+	table
+		* ? ? ? ? : ? : x;
+		? 1 1 ? 0 : ? : 1;
+		? 1 0 0 ? : ? : 0;
+		? ? ? 1 ? : ? : 1;
+		? ? ? 0 1 : ? : 0;
+		? 0 * ? ? : ? : -;
+		? 0 ? * 0 : 1 : 1;
+		? 0 ? 0 * : 0 : 0;
+		? * 1 ? 0 : 1 : 1;
+		? * 0 0 ? : 0 : 0;
+		? ? 1 * 0 : 1 : 1;
+		? ? 0 0 * : 0 : 0;
+	endtable
+endprimitive
+`endif
diff --git a/verilog/sky130_osu_sc_addfx1.v b/verilog/sky130_osu_sc_addfx1.v
index 5b8a214..63957ab 100644
--- a/verilog/sky130_osu_sc_addfx1.v
+++ b/verilog/sky130_osu_sc_addfx1.v
@@ -1,7 +1,7 @@
 // type: ADDF 
 `timescale 1ns/10ps
 `celldefine
-module ADDFX1 (CO, S, A, B, CI);
+module sky130_osu_sc_ADDFX1 (CO, S, A, B, CI);
 	output CO, S;
 	input A, B, CI;
 
diff --git a/verilog/sky130_osu_sc_addfxl.v b/verilog/sky130_osu_sc_addfxl.v
index 05dcac7..bf8d0f8 100644
--- a/verilog/sky130_osu_sc_addfxl.v
+++ b/verilog/sky130_osu_sc_addfxl.v
@@ -1,7 +1,7 @@
 // type: ADDF 
 `timescale 1ns/10ps
 `celldefine
-module ADDFXL (CO, S, A, B, CI);
+module sky130_osu_sc_ADDFXL (CO, S, A, B, CI);
 	output CO, S;
 	input A, B, CI;
 
diff --git a/verilog/sky130_osu_sc_addhx1.v b/verilog/sky130_osu_sc_addhx1.v
index f9f0c26..5ce7258 100644
--- a/verilog/sky130_osu_sc_addhx1.v
+++ b/verilog/sky130_osu_sc_addhx1.v
@@ -1,7 +1,7 @@
 // type: ADDH 
 `timescale 1ns/10ps
 `celldefine
-module ADDHX1 (CO, S, A, B);
+module sky130_osu_sc_ADDHX1 (CO, S, A, B);
 	output CO, S;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_addhxl.v b/verilog/sky130_osu_sc_addhxl.v
index 4844c70..bf74ba5 100644
--- a/verilog/sky130_osu_sc_addhxl.v
+++ b/verilog/sky130_osu_sc_addhxl.v
@@ -1,7 +1,7 @@
 // type: ADDH 
 `timescale 1ns/10ps
 `celldefine
-module ADDHXL (CO, S, A, B);
+module sky130_osu_sc_ADDHXL (CO, S, A, B);
 	output CO, S;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_and2x1.v b/verilog/sky130_osu_sc_and2x1.v
index 85562b5..0908289 100644
--- a/verilog/sky130_osu_sc_and2x1.v
+++ b/verilog/sky130_osu_sc_and2x1.v
@@ -1,7 +1,7 @@
 // type: AND2 
 `timescale 1ns/10ps
 `celldefine
-module AND2X1 (Y, A, B);
+module sky130_osu_sc_AND2X1 (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_and2x2.v b/verilog/sky130_osu_sc_and2x2.v
index 5ee348a..5e99dde 100644
--- a/verilog/sky130_osu_sc_and2x2.v
+++ b/verilog/sky130_osu_sc_and2x2.v
@@ -1,7 +1,7 @@
 // type: AND2 
 `timescale 1ns/10ps
 `celldefine
-module AND2X2 (Y, A, B);
+module sky130_osu_sc_AND2X2 (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_and2x4.v b/verilog/sky130_osu_sc_and2x4.v
index 38b6682..9d6a9b5 100644
--- a/verilog/sky130_osu_sc_and2x4.v
+++ b/verilog/sky130_osu_sc_and2x4.v
@@ -1,7 +1,7 @@
 // type: AND2 
 `timescale 1ns/10ps
 `celldefine
-module AND2X4 (Y, A, B);
+module sky130_osu_sc_AND2X4 (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_and2x8.v b/verilog/sky130_osu_sc_and2x8.v
index ed2e119..d8e8e18 100644
--- a/verilog/sky130_osu_sc_and2x8.v
+++ b/verilog/sky130_osu_sc_and2x8.v
@@ -1,7 +1,7 @@
 // type: AND2 
 `timescale 1ns/10ps
 `celldefine
-module AND2X8 (Y, A, B);
+module sky130_osu_sc_AND2X8 (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_and2xl.v b/verilog/sky130_osu_sc_and2xl.v
index 201e4bd..93f7ffe 100644
--- a/verilog/sky130_osu_sc_and2xl.v
+++ b/verilog/sky130_osu_sc_and2xl.v
@@ -1,7 +1,7 @@
 // type: AND2 
 `timescale 1ns/10ps
 `celldefine
-module AND2XL (Y, A, B);
+module sky130_osu_sc_AND2XL (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_and3xl.v b/verilog/sky130_osu_sc_and3xl.v
index 86f303e..0a70da8 100644
--- a/verilog/sky130_osu_sc_and3xl.v
+++ b/verilog/sky130_osu_sc_and3xl.v
@@ -1,7 +1,7 @@
 // type: AND3 
 `timescale 1ns/10ps
 `celldefine
-module AND3XL (Y, A, B, C);
+module sky130_osu_sc_AND3XL (Y, A, B, C);
 	output Y;
 	input A, B, C;
 
diff --git a/verilog/sky130_osu_sc_ant.v b/verilog/sky130_osu_sc_ant.v
index 472073b..819bb37 100644
--- a/verilog/sky130_osu_sc_ant.v
+++ b/verilog/sky130_osu_sc_ant.v
@@ -1,7 +1,7 @@
 // type: ANT 
 `timescale 1ns/10ps
 `celldefine
-module ANT (A);
+module sky130_osu_sc_ANT (A);
 	input A;
 	// Timing
 	specify
diff --git a/verilog/sky130_osu_sc_aoi21xl.v b/verilog/sky130_osu_sc_aoi21xl.v
index 9395a2f..a844c60 100644
--- a/verilog/sky130_osu_sc_aoi21xl.v
+++ b/verilog/sky130_osu_sc_aoi21xl.v
@@ -1,7 +1,7 @@
 // type: AOI21 
 `timescale 1ns/10ps
 `celldefine
-module AOI21XL (Y, A0, A1, B0);
+module sky130_osu_sc_AOI21XL (Y, A0, A1, B0);
 	output Y;
 	input A0, A1, B0;
 
diff --git a/verilog/sky130_osu_sc_bufx1.v b/verilog/sky130_osu_sc_bufx1.v
index 0e39291..26ad94d 100644
--- a/verilog/sky130_osu_sc_bufx1.v
+++ b/verilog/sky130_osu_sc_bufx1.v
@@ -1,7 +1,7 @@
 // type: BUF 
 `timescale 1ns/10ps
 `celldefine
-module BUFX1 (Y, A);
+module sky130_osu_sc_BUFX1 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_bufx2.v b/verilog/sky130_osu_sc_bufx2.v
index 35126a6..8e4f72d 100644
--- a/verilog/sky130_osu_sc_bufx2.v
+++ b/verilog/sky130_osu_sc_bufx2.v
@@ -1,7 +1,7 @@
 // type: BUF 
 `timescale 1ns/10ps
 `celldefine
-module BUFX2 (Y, A);
+module sky130_osu_sc_BUFX2 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_bufx4.v b/verilog/sky130_osu_sc_bufx4.v
index 31285b4..f72d38e 100644
--- a/verilog/sky130_osu_sc_bufx4.v
+++ b/verilog/sky130_osu_sc_bufx4.v
@@ -1,7 +1,7 @@
 // type: BUF 
 `timescale 1ns/10ps
 `celldefine
-module BUFX4 (Y, A);
+module sky130_osu_sc_BUFX4 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_bufx6.v b/verilog/sky130_osu_sc_bufx6.v
index 926c81b..08715f3 100644
--- a/verilog/sky130_osu_sc_bufx6.v
+++ b/verilog/sky130_osu_sc_bufx6.v
@@ -1,7 +1,7 @@
 // type: BUF 
 `timescale 1ns/10ps
 `celldefine
-module BUFX6 (Y, A);
+module sky130_osu_sc_BUFX6 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_bufx8.v b/verilog/sky130_osu_sc_bufx8.v
index d81c32f..870d6b2 100644
--- a/verilog/sky130_osu_sc_bufx8.v
+++ b/verilog/sky130_osu_sc_bufx8.v
@@ -1,7 +1,7 @@
 // type: BUF 
 `timescale 1ns/10ps
 `celldefine
-module BUFX8 (Y, A);
+module sky130_osu_sc_BUFX8 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_bufxl.v b/verilog/sky130_osu_sc_bufxl.v
index 6dde6e9..78bf4c8 100644
--- a/verilog/sky130_osu_sc_bufxl.v
+++ b/verilog/sky130_osu_sc_bufxl.v
@@ -1,7 +1,7 @@
 // type: BUF 
 `timescale 1ns/10ps
 `celldefine
-module BUFXL (Y, A);
+module sky130_osu_sc_BUFXL (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_clkbufx1.v b/verilog/sky130_osu_sc_clkbufx1.v
index 9550a02..c13e5de 100644
--- a/verilog/sky130_osu_sc_clkbufx1.v
+++ b/verilog/sky130_osu_sc_clkbufx1.v
@@ -1,7 +1,7 @@
 // type: CLKBUF 
 `timescale 1ns/10ps
 `celldefine
-module CLKBUFX1 (Y, A);
+module sky130_osu_sc_CLKBUFX1 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_clkinvx1.v b/verilog/sky130_osu_sc_clkinvx1.v
index c0fb04b..6549ee9 100644
--- a/verilog/sky130_osu_sc_clkinvx1.v
+++ b/verilog/sky130_osu_sc_clkinvx1.v
@@ -1,7 +1,7 @@
 // type: CLKINV 
 `timescale 1ns/10ps
 `celldefine
-module CLKINVX1 (Y, A);
+module sky130_osu_sc_CLKINVX1 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_clkinvx2.v b/verilog/sky130_osu_sc_clkinvx2.v
index 9e48ff4..328aa9a 100644
--- a/verilog/sky130_osu_sc_clkinvx2.v
+++ b/verilog/sky130_osu_sc_clkinvx2.v
@@ -1,7 +1,7 @@
 // type: CLKINV 
 `timescale 1ns/10ps
 `celldefine
-module CLKINVX2 (Y, A);
+module sky130_osu_sc_CLKINVX2 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_clkinvx4.v b/verilog/sky130_osu_sc_clkinvx4.v
index 6817a57..4be1991 100644
--- a/verilog/sky130_osu_sc_clkinvx4.v
+++ b/verilog/sky130_osu_sc_clkinvx4.v
@@ -1,7 +1,7 @@
 // type: CLKINV 
 `timescale 1ns/10ps
 `celldefine
-module CLKINVX4 (Y, A);
+module sky130_osu_sc_CLKINVX4 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_dffnxl.v b/verilog/sky130_osu_sc_dffnxl.v
index 5fedeef..4038e6c 100644
--- a/verilog/sky130_osu_sc_dffnxl.v
+++ b/verilog/sky130_osu_sc_dffnxl.v
@@ -1,7 +1,7 @@
 // type: DFFN 
 `timescale 1ns/10ps
 `celldefine
-module DFFNXL (Q, QN, D, CK);
+module sky130_osu_sc_DFFNXL (Q, QN, D, CK);
 	output Q, QN;
 	input D, CK;
 	reg notifier;
diff --git a/verilog/sky130_osu_sc_dffrxl.v b/verilog/sky130_osu_sc_dffrxl.v
index 230c134..6d100ae 100644
--- a/verilog/sky130_osu_sc_dffrxl.v
+++ b/verilog/sky130_osu_sc_dffrxl.v
@@ -1,7 +1,7 @@
 // type: DFFR 
 `timescale 1ns/10ps
 `celldefine
-module DFFRXL (Q, QN, D, RN, CK);
+module sky130_osu_sc_DFFRXL (Q, QN, D, RN, CK);
 	output Q, QN;
 	input D, RN, CK;
 	reg notifier;
diff --git a/verilog/sky130_osu_sc_dffsxl.v b/verilog/sky130_osu_sc_dffsxl.v
index 45f9995..5b0199b 100644
--- a/verilog/sky130_osu_sc_dffsxl.v
+++ b/verilog/sky130_osu_sc_dffsxl.v
@@ -1,7 +1,7 @@
 // type: DFFS 
 `timescale 1ns/10ps
 `celldefine
-module DFFSXL (Q, QN, D, SN, CK);
+module sky130_osu_sc_DFFSXL (Q, QN, D, SN, CK);
 	output Q, QN;
 	input D, SN, CK;
 	reg notifier;
diff --git a/verilog/sky130_osu_sc_dffxl.v b/verilog/sky130_osu_sc_dffxl.v
index 01db9d7..2a1b2b0 100644
--- a/verilog/sky130_osu_sc_dffxl.v
+++ b/verilog/sky130_osu_sc_dffxl.v
@@ -1,7 +1,7 @@
 // type: DFF 
 `timescale 1ns/10ps
 `celldefine
-module DFFXL (Q, QN, D, CK);
+module sky130_osu_sc_DFFXL (Q, QN, D, CK);
 	output Q, QN;
 	input D, CK;
 	reg notifier;
diff --git a/verilog/sky130_osu_sc_dly1.v b/verilog/sky130_osu_sc_dly1.v
index 805e87b..4257917 100644
--- a/verilog/sky130_osu_sc_dly1.v
+++ b/verilog/sky130_osu_sc_dly1.v
@@ -1,7 +1,7 @@
 // type: DLY1 
 `timescale 1ns/10ps
 `celldefine
-module DLY1 (Y, A);
+module sky130_osu_sc_DLY1 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_dly2.v b/verilog/sky130_osu_sc_dly2.v
index dea6e9f..3a2e662 100644
--- a/verilog/sky130_osu_sc_dly2.v
+++ b/verilog/sky130_osu_sc_dly2.v
@@ -1,7 +1,7 @@
 // type: DLY2 
 `timescale 1ns/10ps
 `celldefine
-module DLY2 (Y, A);
+module sky130_osu_sc_DLY2 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_dly3.v b/verilog/sky130_osu_sc_dly3.v
index c9b2116..90c3504 100644
--- a/verilog/sky130_osu_sc_dly3.v
+++ b/verilog/sky130_osu_sc_dly3.v
@@ -1,7 +1,7 @@
 // type: DLY3 
 `timescale 1ns/10ps
 `celldefine
-module DLY3 (Y, A);
+module sky130_osu_sc_DLY3 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_dly4.v b/verilog/sky130_osu_sc_dly4.v
index a703499..fe9663f 100644
--- a/verilog/sky130_osu_sc_dly4.v
+++ b/verilog/sky130_osu_sc_dly4.v
@@ -1,7 +1,7 @@
 // type: DLY4 
 `timescale 1ns/10ps
 `celldefine
-module DLY4 (Y, A);
+module sky130_osu_sc_DLY4 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_invx1.v b/verilog/sky130_osu_sc_invx1.v
index 16b0250..d54092a 100644
--- a/verilog/sky130_osu_sc_invx1.v
+++ b/verilog/sky130_osu_sc_invx1.v
@@ -1,7 +1,7 @@
 // type: INV 
 `timescale 1ns/10ps
 `celldefine
-module INVX1 (Y, A);
+module sky130_osu_sc_INVX1 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_invx10.v b/verilog/sky130_osu_sc_invx10.v
index 4dd24fc..95e169a 100644
--- a/verilog/sky130_osu_sc_invx10.v
+++ b/verilog/sky130_osu_sc_invx10.v
@@ -1,7 +1,7 @@
 // type: INV 
 `timescale 1ns/10ps
 `celldefine
-module INVX10 (Y, A);
+module sky130_osu_sc_INVX10 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_invx2.v b/verilog/sky130_osu_sc_invx2.v
index e259cd7..7588ce2 100644
--- a/verilog/sky130_osu_sc_invx2.v
+++ b/verilog/sky130_osu_sc_invx2.v
@@ -1,7 +1,7 @@
 // type: INV 
 `timescale 1ns/10ps
 `celldefine
-module INVX2 (Y, A);
+module sky130_osu_sc_INVX2 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_invx3.v b/verilog/sky130_osu_sc_invx3.v
index 34cd10d..dd64263 100644
--- a/verilog/sky130_osu_sc_invx3.v
+++ b/verilog/sky130_osu_sc_invx3.v
@@ -1,7 +1,7 @@
 // type: INV 
 `timescale 1ns/10ps
 `celldefine
-module INVX3 (Y, A);
+module sky130_osu_sc_INVX3 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_invx4.v b/verilog/sky130_osu_sc_invx4.v
index ec6995a..2822fae 100644
--- a/verilog/sky130_osu_sc_invx4.v
+++ b/verilog/sky130_osu_sc_invx4.v
@@ -1,7 +1,7 @@
 // type: INV 
 `timescale 1ns/10ps
 `celldefine
-module INVX4 (Y, A);
+module sky130_osu_sc_INVX4 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_invx6.v b/verilog/sky130_osu_sc_invx6.v
index 7f3da23..49fbb3c 100644
--- a/verilog/sky130_osu_sc_invx6.v
+++ b/verilog/sky130_osu_sc_invx6.v
@@ -1,7 +1,7 @@
 // type: INV 
 `timescale 1ns/10ps
 `celldefine
-module INVX6 (Y, A);
+module sky130_osu_sc_INVX6 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_invx8.v b/verilog/sky130_osu_sc_invx8.v
index f5cf36a..e8515a1 100644
--- a/verilog/sky130_osu_sc_invx8.v
+++ b/verilog/sky130_osu_sc_invx8.v
@@ -1,7 +1,7 @@
 // type: INV 
 `timescale 1ns/10ps
 `celldefine
-module INVX8 (Y, A);
+module sky130_osu_sc_INVX8 (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_invxl.v b/verilog/sky130_osu_sc_invxl.v
index 1a3084e..2a43a09 100644
--- a/verilog/sky130_osu_sc_invxl.v
+++ b/verilog/sky130_osu_sc_invxl.v
@@ -1,7 +1,7 @@
 // type: INV 
 `timescale 1ns/10ps
 `celldefine
-module INVXL (Y, A);
+module sky130_osu_sc_INVXL (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_nand2x1.v b/verilog/sky130_osu_sc_nand2x1.v
index a44c3a3..563ed73 100644
--- a/verilog/sky130_osu_sc_nand2x1.v
+++ b/verilog/sky130_osu_sc_nand2x1.v
@@ -1,7 +1,7 @@
 // type: NAND2 
 `timescale 1ns/10ps
 `celldefine
-module NAND2X1 (Y, A, B);
+module sky130_osu_sc_NAND2X1 (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_nand2xl.v b/verilog/sky130_osu_sc_nand2xl.v
index 7e9af58..f4a70b0 100644
--- a/verilog/sky130_osu_sc_nand2xl.v
+++ b/verilog/sky130_osu_sc_nand2xl.v
@@ -1,7 +1,7 @@
 // type: NAND2 
 `timescale 1ns/10ps
 `celldefine
-module NAND2XL (Y, A, B);
+module sky130_osu_sc_NAND2XL (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_nand3x1.v b/verilog/sky130_osu_sc_nand3x1.v
index f0f2dbc..713c0c4 100644
--- a/verilog/sky130_osu_sc_nand3x1.v
+++ b/verilog/sky130_osu_sc_nand3x1.v
@@ -1,7 +1,7 @@
 // type: NAND3 
 `timescale 1ns/10ps
 `celldefine
-module NAND3X1 (Y, A, B, C);
+module sky130_osu_sc_NAND3X1 (Y, A, B, C);
 	output Y;
 	input A, B, C;
 
diff --git a/verilog/sky130_osu_sc_nand3xl.v b/verilog/sky130_osu_sc_nand3xl.v
index f221c67..7ca337f 100644
--- a/verilog/sky130_osu_sc_nand3xl.v
+++ b/verilog/sky130_osu_sc_nand3xl.v
@@ -1,7 +1,7 @@
 // type: NAND3 
 `timescale 1ns/10ps
 `celldefine
-module NAND3XL (Y, A, B, C);
+module sky130_osu_sc_NAND3XL (Y, A, B, C);
 	output Y;
 	input A, B, C;
 
diff --git a/verilog/sky130_osu_sc_nor2x1.v b/verilog/sky130_osu_sc_nor2x1.v
index 836dbf6..c8065e6 100644
--- a/verilog/sky130_osu_sc_nor2x1.v
+++ b/verilog/sky130_osu_sc_nor2x1.v
@@ -1,7 +1,7 @@
 // type: NOR2 
 `timescale 1ns/10ps
 `celldefine
-module NOR2X1 (Y, A, B);
+module sky130_osu_sc_NOR2X1 (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_nor2xl.v b/verilog/sky130_osu_sc_nor2xl.v
index 6469c1a..fe88af6 100644
--- a/verilog/sky130_osu_sc_nor2xl.v
+++ b/verilog/sky130_osu_sc_nor2xl.v
@@ -1,7 +1,7 @@
 // type: NOR2 
 `timescale 1ns/10ps
 `celldefine
-module NOR2XL (Y, A, B);
+module sky130_osu_sc_NOR2XL (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_oai21xl.v b/verilog/sky130_osu_sc_oai21xl.v
index 5a6a646..e8da812 100644
--- a/verilog/sky130_osu_sc_oai21xl.v
+++ b/verilog/sky130_osu_sc_oai21xl.v
@@ -1,7 +1,7 @@
 // type: OAI21 
 `timescale 1ns/10ps
 `celldefine
-module OAI21XL (Y, A0, A1, B0);
+module sky130_osu_sc_OAI21XL (Y, A0, A1, B0);
 	output Y;
 	input A0, A1, B0;
 
diff --git a/verilog/sky130_osu_sc_or2x1.v b/verilog/sky130_osu_sc_or2x1.v
index 75d0287..43c1d87 100644
--- a/verilog/sky130_osu_sc_or2x1.v
+++ b/verilog/sky130_osu_sc_or2x1.v
@@ -1,7 +1,7 @@
 // type: OR2 
 `timescale 1ns/10ps
 `celldefine
-module OR2X1 (Y, A, B);
+module sky130_osu_sc_OR2X1 (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_or2x2.v b/verilog/sky130_osu_sc_or2x2.v
index 0a86467..5bb5488 100644
--- a/verilog/sky130_osu_sc_or2x2.v
+++ b/verilog/sky130_osu_sc_or2x2.v
@@ -1,7 +1,7 @@
 // type: OR2 
 `timescale 1ns/10ps
 `celldefine
-module OR2X2 (Y, A, B);
+module sky130_osu_sc_OR2X2 (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_or2x4.v b/verilog/sky130_osu_sc_or2x4.v
index 92bbe0e..9df6f64 100644
--- a/verilog/sky130_osu_sc_or2x4.v
+++ b/verilog/sky130_osu_sc_or2x4.v
@@ -1,7 +1,7 @@
 // type: OR2 
 `timescale 1ns/10ps
 `celldefine
-module OR2X4 (Y, A, B);
+module sky130_osu_sc_OR2X4 (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_or2xl.v b/verilog/sky130_osu_sc_or2xl.v
index 524c5b0..591fed9 100644
--- a/verilog/sky130_osu_sc_or2xl.v
+++ b/verilog/sky130_osu_sc_or2xl.v
@@ -1,7 +1,7 @@
 // type: OR2 
 `timescale 1ns/10ps
 `celldefine
-module OR2XL (Y, A, B);
+module sky130_osu_sc_OR2XL (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_tbufxl.v b/verilog/sky130_osu_sc_tbufxl.v
index 7885ff8..c0c3b70 100644
--- a/verilog/sky130_osu_sc_tbufxl.v
+++ b/verilog/sky130_osu_sc_tbufxl.v
@@ -1,7 +1,7 @@
 // type: TBUF 
 `timescale 1ns/10ps
 `celldefine
-module TBUFXL (Y, A);
+module sky130_osu_sc_TBUFXL (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_tiehi.v b/verilog/sky130_osu_sc_tiehi.v
index 84f2164..a82fd56 100644
--- a/verilog/sky130_osu_sc_tiehi.v
+++ b/verilog/sky130_osu_sc_tiehi.v
@@ -1,7 +1,7 @@
 // type: TIEHI 
 `timescale 1ns/10ps
 `celldefine
-module TIEHI (Y);
+module sky130_osu_sc_TIEHI (Y);
 	output Y;
 
 	// Function
diff --git a/verilog/sky130_osu_sc_tielo.v b/verilog/sky130_osu_sc_tielo.v
index f83e915..2ab72ff 100644
--- a/verilog/sky130_osu_sc_tielo.v
+++ b/verilog/sky130_osu_sc_tielo.v
@@ -1,7 +1,7 @@
 // type: TIELO 
 `timescale 1ns/10ps
 `celldefine
-module TIELO (Y);
+module sky130_osu_sc_TIELO (Y);
 	output Y;
 
 	// Function
diff --git a/verilog/sky130_osu_sc_tnbufxl.v b/verilog/sky130_osu_sc_tnbufxl.v
index f065eb1..45ad180 100644
--- a/verilog/sky130_osu_sc_tnbufxl.v
+++ b/verilog/sky130_osu_sc_tnbufxl.v
@@ -1,7 +1,7 @@
 // type: TNBUF 
 `timescale 1ns/10ps
 `celldefine
-module TNBUFXL (Y, A);
+module sky130_osu_sc_TNBUFXL (Y, A);
 	output Y;
 	input A;
 
diff --git a/verilog/sky130_osu_sc_xnor2xl.v b/verilog/sky130_osu_sc_xnor2xl.v
index 281f57d..0d26f62 100644
--- a/verilog/sky130_osu_sc_xnor2xl.v
+++ b/verilog/sky130_osu_sc_xnor2xl.v
@@ -1,7 +1,7 @@
 // type: XNOR2 
 `timescale 1ns/10ps
 `celldefine
-module XNOR2XL (Y, A, B);
+module sky130_osu_sc_XNOR2XL (Y, A, B);
 	output Y;
 	input A, B;
 
diff --git a/verilog/sky130_osu_sc_xor2xl.v b/verilog/sky130_osu_sc_xor2xl.v
index 4bddfac..549ddc0 100644
--- a/verilog/sky130_osu_sc_xor2xl.v
+++ b/verilog/sky130_osu_sc_xor2xl.v
@@ -1,7 +1,7 @@
 // type: XOR2 
 `timescale 1ns/10ps
 `celldefine
-module XOR2XL (Y, A, B);
+module sky130_osu_sc_XOR2XL (Y, A, B);
 	output Y;
 	input A, B;