)]}'
{
  "commit": "1cd268a4b1c27b591dd1ab0f66c03a2514c7394c",
  "tree": "685f06739e8cb3749b7e245980d9bfa1f1cb0e96",
  "parents": [
    "d94c22085c9411f6e0643fbdcb97371de90c8238",
    "c3d24b3b50d46c552c712cc770f48ffbbc0bd07f"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing usage of cell reserved word.\n\n`cell` is a Verilog reserved word.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}