| { |
| "area": 28.7712, |
| "cell_footprint": "sky130_fd_sc_ms__dlclkp", |
| "cell_leakage_power": 47.72789, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 42.0184314, |
| "when": "!GATE&CLK" |
| }, |
| { |
| "value": 44.2209931, |
| "when": "GATE&!CLK" |
| }, |
| { |
| "value": 42.83579, |
| "when": "GATE&CLK" |
| }, |
| { |
| "value": 47.727891, |
| "when": "!GATE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01285, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
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| 0.01735, |
| 0.02602, |
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| ] |
| }, |
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| 0.0343044, |
| 0.049206, |
| 0.071574 |
| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "min_pulse_width_low": 0.09577, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.0028, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| 0.040038, |
| 0.0452264, |
| 0.0530212, |
| 0.0647256, |
| 0.0822966 |
| ] |
| }, |
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| ], |
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| 0.031949, |
| 0.0398869, |
| 0.0518063, |
| 0.0697004 |
| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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| [ |
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| 0.30138 |
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| [ |
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| 0.37462, |
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| [ |
| 0.35705, |
| 0.35705, |
| 0.35119, |
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| 0.34533, |
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| 0.4215, |
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| 0.3922, |
| 0.40392, |
| 0.4215, |
| 0.44494, |
| 0.46837, |
| 0.49181 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
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| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "values": [ |
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| 0.22228, |
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| [ |
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| 0.22521 |
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| [ |
| 0.02013, |
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| 0.02599, |
| 0.05529, |
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| 0.16662, |
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| [ |
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| 0.14318, |
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| [ |
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| 0.00255, |
| 0.03771, |
| 0.0758, |
| 0.11681, |
| 0.1549 |
| ] |
| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
| "fall_constraint,sethold_template_fall10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
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| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| -0.3578, |
| -0.38124, |
| -0.40467 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
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| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
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| ], |
| "values": [ |
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| 0.01134, |
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| 0.01134, |
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| [ |
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| [ |
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| [ |
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| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x14": { |
| "index_1": [ |
| 0.01, |
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| 0.02602, |
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| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1, |
| 1.5 |
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| 0, |
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| 0.258, |
| 0.387, |
| 0.5805, |
| 0.87075 |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_transition,delay_template13x14": { |
| "index_1": [ |
| 0.01, |
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| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.0, |
| 0.00671, |
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| 0.11467, |
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| 0.258, |
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| ], |
| "values": [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| 0.1692, |
| 0.23, |
| 0.3238, |
| 0.4663, |
| 0.6842, |
| 1.008, |
| 1.4993 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
