)]}'
{
  "commit": "f01d3320f30a058f602586ec73c9ebdab413926d",
  "tree": "a80b02188edc166e17ad92920e5d589bae16d1ac",
  "parents": [
    "c0c9162191d84a8a1fae5b8690a67f46a966f77e",
    "e905472a13b5d175e91b3c5e9f58fb03015f2a8a"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Wed Oct 28 20:06:40 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Wed Oct 28 20:06:40 2020 -0700"
  },
  "message": "verilog: Fixing power pins usage in non-powerpin mode.\n\nPreviously even when `USE_POWER_PIN` was not defined, the drive strength\nwrappers where still defining the power pins as ports.\n\nFixes https://github.com/google/skywater-pdk/issues/181\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}