{
  "area": 54.3456,
  "cell_footprint": "sedfxbp",
  "cell_leakage_power": 0.0,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002234,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002128,
    "internal_power": {
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        "index_1": [
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          0.02602,
          0.03903,
          0.05855,
          0.08782,
          0.13172,
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.0,
    "min_pulse_width_high": 1.109034,
    "min_pulse_width_low": 1.608856,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.00234
  },
  "pin D": {
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    "clock": "false",
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    "fall_capacitance": 0.001477,
    "internal_power": {
      "fall_power hidden_pwr_template13": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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          0.0056238,
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    },
    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001614,
    "timing": [
      {
        "clk_width": 2e-08,
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            1.0,
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              3.4321757
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
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            0.0625,
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            0.25,
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint vio_10_10_1": {
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            0.25,
            0.5,
            0.75,
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            0.5,
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          "values": [
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              -2.7462097,
              -2.8992044,
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
          "index_1": [
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            0.03125,
            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
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          "index_2": [
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            0.5,
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            1.0,
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin DE": {
    "capacitance": 0.00287,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.002662,
    "internal_power": {
      "fall_power hidden_pwr_template13": {
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          0.02602,
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          0.13172,
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003077,
    "timing": [
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        "fall_constraint vio_10_10_1": {
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        "fall_constraint vio_10_10_1": {
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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              -1.4907246,
              -1.507196,
              -1.5324238,
              -1.5743346,
              -1.6496113,
              -1.7623229,
              -1.8616068,
              -1.9572286,
              -2.0394226,
              -2.1203958
            ],
            [
              -1.3865579,
              -1.4005879,
              -1.4245951,
              -1.4738301,
              -1.5381205,
              -1.6544942,
              -1.7549987,
              -1.8493997,
              -1.9352559,
              -2.0162291
            ],
            [
              -1.2848326,
              -1.3061869,
              -1.326532,
              -1.3660013,
              -1.4388366,
              -1.5564309,
              -1.6593769,
              -1.7549987,
              -1.8310892,
              -1.9145038
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "test_cell": {
    "ff IQ,IQ_N": {
      "clocked_on": "CLK",
      "next_state": "(D&DE) | (IQ&!DE)"
    },
    "pin CLK": {
      "direction": "input"
    },
    "pin D": {
      "direction": "input"
    },
    "pin DE": {
      "direction": "input"
    },
    "pin Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin Q_N": {
      "direction": "output",
      "function": "IQ_N",
      "signal_type": "test_scan_out_inverted"
    },
    "pin SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    }
  }
}