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  "area": 41.5584,
  "cell_footprint": "sdfxtp",
  "cell_leakage_power": 0.0,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "(D&!SCE) | (SCD&SCE)"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
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    "clock": "true",
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    "fall_capacitance": 0.002478,
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    "related_power_pin": "VPWR",
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    "max_transition": 1.0,
    "nextstate_type": "data",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
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        "sim_opt": "runlvl=5 accurate=1",
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  "pin Q": {
    "direction": "output",
    "function": "IQ",
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        "fall_constraint vio_10_10_1": {
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "test_cell": {
    "ff IQ,IQ_N": {
      "clocked_on": "CLK",
      "next_state": "D"
    },
    "pin CLK": {
      "direction": "input"
    },
    "pin D": {
      "direction": "input"
    },
    "pin Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    }
  }
}