{
  "area": 36.7632,
  "cell_footprint": "sdfxtp",
  "cell_leakage_power": 0.0,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "(D&!SCE) | (SCD&SCE)"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002944,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.0028,
    "internal_power": {
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          0.29634,
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.0,
    "min_pulse_width_high": 0.057759,
    "min_pulse_width_low": 0.128064,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003089
  },
  "pin D": {
    "capacitance": 0.002017,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001933,
    "internal_power": {
      "fall_power hidden_pwr_template13": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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          0.0123393,
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    },
    "max_transition": 1.0,
    "nextstate_type": "data",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002101,
    "timing": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint vio_10_10_1": {
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": {
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        "index_2": [
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        "values": [
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      "related_pin": "CLK",
      "rise_power pwr_template13x7": {
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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              -0.2042988,
              -0.2059264,
              -0.2038919
            ],
            [
              -0.1438822,
              -0.1481465,
              -0.1550638,
              -0.1676777,
              -0.1880228,
              -0.2091816,
              -0.2217956,
              -0.2270853,
              -0.2299336,
              -0.2291198
            ],
            [
              -0.1654479,
              -0.1697122,
              -0.1766296,
              -0.1892435,
              -0.2095885,
              -0.2319681,
              -0.2433613,
              -0.2510924,
              -0.2539408,
              -0.2543477
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "test_cell": {
    "ff IQ,IQ_N": {
      "clocked_on": "CLK",
      "next_state": "D"
    },
    "pin CLK": {
      "direction": "input"
    },
    "pin D": {
      "direction": "input"
    },
    "pin Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    }
  }
}