| { |
| "area": 44.7552, |
| "cell_footprint": "sdfxbp", |
| "cell_leakage_power": 0.0, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPWR" |
| }, |
| "pin CLK": { |
| "capacitance": 0.002918, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002761, |
| "internal_power": { |
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| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
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| 0.0448586 |
| ] |
| }, |
| "rise_power hidden_pwr_template13": { |
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| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "min_pulse_width_high": 0.076434, |
| "min_pulse_width_low": 0.203861, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.003075 |
| }, |
| "pin D": { |
| "capacitance": 0.001905, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.001805, |
| "internal_power": { |
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| 0.0155834 |
| ] |
| }, |
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| } |
| }, |
| "max_transition": 1.0, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002005, |
| "timing": [ |
| { |
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| [ |
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| [ |
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| [ |
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| 0.5484681, |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint vio_10_10_1": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
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| 0.125, |
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| 0.75, |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
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| }, |
| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin Q": { |
| "direction": "output", |
| "function": "IQ", |
| "internal_power": { |
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| [ |
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| 0.3889629, |
| 0.4430807, |
| 0.4947572, |
| 0.5427715 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint vio_10_10_1": { |
| "index_1": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "values": [ |
| [ |
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| [ |
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| [ |
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| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "fall_constraint vio_10_10_1": { |
| "index_1": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
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| 0.5, |
| 0.75, |
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| [ |
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| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint vio_10_10_1": { |
| "index_1": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
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| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
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| "values": [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "test_cell": { |
| "ff IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "D" |
| }, |
| "pin CLK": { |
| "direction": "input" |
| }, |
| "pin D": { |
| "direction": "input" |
| }, |
| "pin Q": { |
| "direction": "output", |
| "function": "IQ", |
| "signal_type": "test_scan_out" |
| }, |
| "pin Q_N": { |
| "direction": "output", |
| "function": "IQ_N", |
| "signal_type": "test_scan_out_inverted" |
| }, |
| "pin SCD": { |
| "direction": "input", |
| "signal_type": "test_scan_in" |
| }, |
| "pin SCE": { |
| "direction": "input", |
| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
