{
  "area": 44.7552,
  "cell_footprint": "sdfxbp",
  "cell_leakage_power": 0.0,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "(D&!SCE) | (SCD&SCE)"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002935,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002773,
    "internal_power": {
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        "index_1": [
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          0.02602,
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          0.05855,
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          0.13172,
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          0.29634,
          0.44449,
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.0,
    "min_pulse_width_high": 0.055562,
    "min_pulse_width_low": 0.131359,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003096
  },
  "pin D": {
    "capacitance": 0.001964,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001876,
    "internal_power": {
      "fall_power hidden_pwr_template13": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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          0.0121446,
          0.0187737,
          0.0287495
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      }
    },
    "max_transition": 1.0,
    "nextstate_type": "data",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002053,
    "timing": [
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              0.5545716,
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        "related_pin": "CLK",
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint vio_10_10_1": {
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        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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            0.125,
            0.25,
            0.5,
            0.75,
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": {
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        "index_2": [
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      "related_pin": "CLK",
      "rise_power pwr_template13x8": {
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        "values": [
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            ],
            [
              -0.0865091,
              -0.0907734,
              -0.0976908,
              -0.109084,
              -0.1233255,
              -0.1322773,
              -0.1326842,
              -0.1269876,
              -0.1176289,
              -0.1058288
            ],
            [
              -0.1141784,
              -0.117222,
              -0.1241393,
              -0.1355326,
              -0.1497741,
              -0.1599466,
              -0.1603535,
              -0.1558776,
              -0.1465189,
              -0.1359395
            ],
            [
              -0.1418477,
              -0.146112,
              -0.1518086,
              -0.1632018,
              -0.1774434,
              -0.1876159,
              -0.1892435,
              -0.1847676,
              -0.1778503,
              -0.1672708
            ],
            [
              -0.1707376,
              -0.175002,
              -0.1806986,
              -0.1920918,
              -0.2063333,
              -0.2177266,
              -0.2181335,
              -0.2148783,
              -0.2079609,
              -0.1973815
            ],
            [
              -0.1996276,
              -0.2038919,
              -0.2108092,
              -0.2209818,
              -0.2352233,
              -0.2466165,
              -0.2482441,
              -0.2449889,
              -0.2380716,
              -0.2287129
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "test_cell": {
    "ff IQ,IQ_N": {
      "clocked_on": "CLK",
      "next_state": "D"
    },
    "pin CLK": {
      "direction": "input"
    },
    "pin D": {
      "direction": "input"
    },
    "pin Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin Q_N": {
      "direction": "output",
      "function": "IQ_N",
      "signal_type": "test_scan_out_inverted"
    },
    "pin SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    }
  }
}