| { | |
| "area": 9.5904, | |
| "cell_footprint": "nand4", | |
| "cell_leakage_power": 0.0, | |
| "pg_pin VGND": { | |
| "pg_type": "primary_ground", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin VNB": { | |
| "pg_type": "primary_ground", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin VPB": { | |
| "pg_type": "primary_power", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin VPWR": { | |
| "pg_type": "primary_power", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin A": { | |
| "capacitance": 0.00309, | |
| "clock": "false", | |
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| "internal_power": { | |
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| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR" | |
| }, | |
| "pin B": { | |
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| "clock": "false", | |
| "direction": "input", | |
| "internal_power": { | |
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| }, | |
| "max_transition": 1.0, | |
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| "related_power_pin": "VPWR" | |
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| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
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| "clock": "false", | |
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| "internal_power": { | |
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| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR" | |
| }, | |
| "pin Y": { | |
| "direction": "output", | |
| "function": "(!A) | (!B) | (!C) | (!D)", | |
| "internal_power": [ | |
| { | |
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| "related_pin": "A", | |
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| "when": "(B&C&D)" | |
| }, | |
| { | |
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