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"cell_footprint": "dlrtp", | |
"cell_leakage_power": 0.0, | |
"latch IQ,IQ_N": { | |
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"data_in": "D", | |
"enable": "GATE" | |
}, | |
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"voltage_name": "VGND" | |
}, | |
"pg_pin VNB": { | |
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"voltage_name": "VNB" | |
}, | |
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"voltage_name": "VPB" | |
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"pg_pin VPWR": { | |
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"voltage_name": "VPWR" | |
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"clock": "false", | |
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