blob: 8bdb17b2d2ffb482a36271988754a2ae1d2367ab [file] [log] [blame]
{
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"clock_gating_integrated_cell": "latch_posedge",
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"voltage_name": "VGND"
},
"pg_pin VNB": {
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"voltage_name": "VNB"
},
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"voltage_name": "VPB"
},
"pg_pin VPWR": {
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},
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},
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},
"pin M0": {
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"internal_node": "M0",
"related_ground_pin": "VNB",
"related_power_pin": "VPWR"
},
"statetable \"CLK GATE\",\"M0\"": {
"table": "L L : - : L ,L H : - : H ,H - : - : N"
}
}