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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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        "related_pin": "CLK",
        "rise_constraint,vio_10_10_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "test_cell": {
    "ff,IQ,IQ_N": {
      "clocked_on": "CLK",
      "next_state": "(D&DE) | (IQ&!DE)"
    },
    "pin,CLK": {
      "direction": "input"
    },
    "pin,D": {
      "direction": "input"
    },
    "pin,DE": {
      "direction": "input"
    },
    "pin,Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin,Q_N": {
      "direction": "output",
      "function": "IQ_N",
      "signal_type": "test_scan_out_inverted"
    },
    "pin,SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin,SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    }
  }
}