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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_ms / e905472a13b5d175e91b3c5e9f58fb03015f2a8a / . / cells / sdlclkp / sky130_fd_sc_ms__sdlclkp_2__ss_n40C_1v60_ccsnoise.lib.json
blob: c31edfb3d1c93666a64325fbddd1a3a09c17af3b [file] [log] [blame]
{
"area": 27.1728,
"cell_footprint": "sky130_fd_sc_ms__sdlclkp",
"cell_leakage_power": 0.0,
"clock_gating_integrated_cell": "latch_posedge_precontrol",
"pg_pin,VGND": {
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"related_bias_pin": "VPB",
"voltage_name": "VGND"
},
"pg_pin,VNB": {
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"physical_connection": "device_layer",
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},
"pg_pin,VPB": {
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},
"pg_pin,VPWR": {
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},
"pin,CLK": {
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"is_inverting": "true",
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"miller_cap_fall": 0.00074,
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"output_voltage_fall": {
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},
"statetable,CLK GATE SCE,M0": {
"table": [
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"L L H : - : H",
"L H L : - : H",
"L H H : - : H",
"H - - : - : N"
]
}
}