| { |
| "area": 28.7712, |
| "cell_footprint": "sky130_fd_sc_ms__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01291, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| }, |
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| "min_pulse_width_low": 0.2569, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.00275, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
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| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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| ] |
| }, |
| "related_pin": "CLK", |
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| 0.75, |
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| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
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| 0.03125, |
| 0.0625, |
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| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x12": { |
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| 0.31972, |
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| 1.00763, |
| 1.50007 |
| ], |
| [ |
| 0.03801, |
| 0.0664, |
| 0.07885, |
| 0.09691, |
| 0.12367, |
| 0.16434, |
| 0.22553, |
| 0.31922, |
| 0.46348, |
| 0.68077, |
| 1.00973, |
| 1.50285 |
| ], |
| [ |
| 0.03799, |
| 0.0664, |
| 0.07881, |
| 0.09693, |
| 0.12363, |
| 0.16436, |
| 0.2256, |
| 0.3192, |
| 0.4635, |
| 0.68077, |
| 1.00974, |
| 1.50275 |
| ], |
| [ |
| 0.03803, |
| 0.0664, |
| 0.07888, |
| 0.09699, |
| 0.12354, |
| 0.16443, |
| 0.22579, |
| 0.31916, |
| 0.46353, |
| 0.68056, |
| 1.00954, |
| 1.50437 |
| ], |
| [ |
| 0.03803, |
| 0.06641, |
| 0.07886, |
| 0.09696, |
| 0.12358, |
| 0.16443, |
| 0.22604, |
| 0.31913, |
| 0.46353, |
| 0.68103, |
| 1.00695, |
| 1.49942 |
| ], |
| [ |
| 0.03801, |
| 0.06648, |
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| 0.12371, |
| 0.16416, |
| 0.22596, |
| 0.3192, |
| 0.46345, |
| 0.68102, |
| 1.00919, |
| 1.49961 |
| ], |
| [ |
| 0.03801, |
| 0.06652, |
| 0.07888, |
| 0.09707, |
| 0.12383, |
| 0.16439, |
| 0.22532, |
| 0.31981, |
| 0.46286, |
| 0.68068, |
| 1.00745, |
| 1.50025 |
| ], |
| [ |
| 0.03799, |
| 0.06652, |
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| 0.16416, |
| 0.22593, |
| 0.31949, |
| 0.46321, |
| 0.68068, |
| 1.00804, |
| 1.49906 |
| ], |
| [ |
| 0.03905, |
| 0.06701, |
| 0.07945, |
| 0.09748, |
| 0.12413, |
| 0.16436, |
| 0.22546, |
| 0.31992, |
| 0.46349, |
| 0.68141, |
| 1.00729, |
| 1.49934 |
| ], |
| [ |
| 0.04207, |
| 0.07022, |
| 0.08242, |
| 0.1001, |
| 0.12618, |
| 0.16594, |
| 0.2266, |
| 0.31988, |
| 0.46331, |
| 0.68118, |
| 1.00893, |
| 1.5 |
| ], |
| [ |
| 0.04611, |
| 0.07484, |
| 0.08711, |
| 0.10477, |
| 0.13048, |
| 0.16978, |
| 0.22943, |
| 0.322, |
| 0.4641, |
| 0.6813, |
| 1.0072, |
| 1.4999 |
| ], |
| [ |
| 0.0516, |
| 0.0812, |
| 0.0934, |
| 0.111, |
| 0.1366, |
| 0.1752, |
| 0.2343, |
| 0.3255, |
| 0.466, |
| 0.6828, |
| 1.008, |
| 1.501 |
| ], |
| [ |
| 0.0596, |
| 0.09, |
| 0.1022, |
| 0.1197, |
| 0.1446, |
| 0.1826, |
| 0.2409, |
| 0.331, |
| 0.4705, |
| 0.684, |
| 1.0091, |
| 1.5042 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
