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| "cell_footprint": "sky130_fd_sc_ms__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
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| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
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| "related_power_pin": "VPWR" |
| }, |
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| }, |
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| "timing_type": "setup_rising" |
| }, |
| { |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 0.05086, |
| 0.06913, |
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| 0.13952, |
| 0.2044, |
| 0.30158, |
| 0.44879, |
| 0.66815, |
| 0.99763, |
| 1.49313 |
| ], |
| [ |
| 0.01296, |
| 0.0389, |
| 0.05095, |
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| 0.09716, |
| 0.13961, |
| 0.20406, |
| 0.30134, |
| 0.44775, |
| 0.66873, |
| 0.99805, |
| 1.49694 |
| ], |
| [ |
| 0.01299, |
| 0.03895, |
| 0.05089, |
| 0.06915, |
| 0.09689, |
| 0.13967, |
| 0.20407, |
| 0.3013, |
| 0.44786, |
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| 0.99801, |
| 1.49705 |
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| [ |
| 0.01309, |
| 0.03905, |
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| 0.30186, |
| 0.44774, |
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| 0.30133, |
| 0.44793, |
| 0.66839, |
| 0.99774, |
| 1.49326 |
| ], |
| [ |
| 0.01482, |
| 0.04082, |
| 0.05287, |
| 0.07052, |
| 0.09798, |
| 0.1399, |
| 0.20417, |
| 0.30142, |
| 0.44848, |
| 0.66909, |
| 0.99755, |
| 1.49398 |
| ], |
| [ |
| 0.01642, |
| 0.04252, |
| 0.0543, |
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| 0.20483, |
| 0.30172, |
| 0.4484, |
| 0.6689, |
| 0.99834, |
| 1.49401 |
| ], |
| [ |
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| 0.04507, |
| 0.05702, |
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| 0.10142, |
| 0.14257, |
| 0.20607, |
| 0.30266, |
| 0.44838, |
| 0.66757, |
| 1.00053, |
| 1.49414 |
| ], |
| [ |
| 0.02227, |
| 0.04855, |
| 0.06074, |
| 0.07842, |
| 0.10513, |
| 0.14614, |
| 0.20876, |
| 0.30465, |
| 0.44955, |
| 0.66894, |
| 0.99729, |
| 1.49225 |
| ], |
| [ |
| 0.0269, |
| 0.05316, |
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| 0.08357, |
| 0.11036, |
| 0.15137, |
| 0.21376, |
| 0.30864, |
| 0.45299, |
| 0.67132, |
| 1.00068, |
| 1.49186 |
| ], |
| [ |
| 0.03314, |
| 0.05935, |
| 0.07191, |
| 0.09024, |
| 0.11755, |
| 0.15866, |
| 0.22109, |
| 0.31675, |
| 0.45998, |
| 0.6765, |
| 1.0036, |
| 1.4943 |
| ], |
| [ |
| 0.0416, |
| 0.0677, |
| 0.0805, |
| 0.0991, |
| 0.127, |
| 0.1684, |
| 0.2314, |
| 0.3277, |
| 0.4723, |
| 0.6898, |
| 1.0127, |
| 1.5016 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
