{
  "area": 51.1488,
  "cell_footprint": "sedfxtp",
  "cell_leakage_power": 0.0,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
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    "clock": "true",
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    "fall_capacitance": 0.002577,
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      "rise_power hidden_pwr_template13": {
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    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001925,
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint vio_10_10_1": {
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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        "sim_opt": "runlvl=5 accurate=1",
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        "violation_delay_degrade_pct": 10
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    ]
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  "pin DE": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
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              -0.0822285,
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin SCE": {
    "capacitance": 0.003057,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.003106,
    "internal_power": {
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        "values": [
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          0.0085485
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      },
      "rise_power hidden_pwr_template13": {
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          0.13172,
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        "values": [
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    },
    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003009,
    "timing": [
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          "values": [
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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          "values": [
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint vio_10_10_1": {
          "index_1": [
            0.01,
            0.03125,
            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
            1.25,
            1.5
          ],
          "index_2": [
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            0.0625,
            0.125,
            0.25,
            0.5,
            0.75,
            1.0,
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            1.5
          ],
          "values": [
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              -0.2610696,
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              -0.6103861,
              -0.6645039,
              -0.7125182
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            [
              -0.243166,
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              -0.265334,
              -0.2938171,
              -0.3520039,
              -0.4512878,
              -0.528599,
              -0.5912617,
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            [
              -0.2171243,
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              -0.4988952,
              -0.553013,
              -0.602248
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
          "index_1": [
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            0.0625,
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            0.5,
            0.75,
            1.0,
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          "index_2": [
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            1.0,
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          "values": [
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              -0.4665547,
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              -0.4417337,
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              -0.3526224,
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            [
              -0.2749043,
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              -0.298293,
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              -0.3605488,
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              -0.4480325,
              -0.4765156,
              -0.5025573,
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            [
              -0.2439798,
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              -0.4171081,
              -0.4468118,
              -0.4716328,
              -0.4940124
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            [
              -0.2154967,
              -0.2246439,
              -0.2388854,
              -0.2637064,
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              -0.4171081,
              -0.4443704,
              -0.4655293
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "test_cell": {
    "ff IQ,IQ_N": {
      "clocked_on": "CLK",
      "next_state": "(D&DE) | (IQ&!DE)"
    },
    "pin CLK": {
      "direction": "input"
    },
    "pin D": {
      "direction": "input"
    },
    "pin DE": {
      "direction": "input"
    },
    "pin Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    }
  }
}