blob: 35429d6fc7fda70191c661ad96421a7ce67d6da3 [file] [log] [blame]
{
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"clock_gating_integrated_cell": "latch_posedge_precontrol",
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"voltage_name": "VGND"
},
"pg_pin VNB": {
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},
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"pg_pin VPWR": {
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]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}