blob: 877d79bb1fbc059b88557115b1d345acf7f4ba4c [file] [log] [blame]
{
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"clock_gating_integrated_cell": "latch_posedge_precontrol",
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"voltage_name": "VGND"
},
"pg_pin VNB": {
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"voltage_name": "VNB"
},
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},
"pg_pin VPWR": {
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"state_function": "(CLK*M0)",
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-0.04147,
-0.0737,
-0.11178,
-0.14694,
-0.18503
],
[
-0.00631,
-0.00339,
-0.00339,
-0.00631,
-0.01803,
-0.04733,
-0.08249,
-0.11764,
-0.15573,
-0.19381
],
[
-0.02096,
-0.01803,
-0.0151,
-0.01803,
-0.02975,
-0.05905,
-0.09421,
-0.12936,
-0.16745,
-0.20553
],
[
-0.03268,
-0.02682,
-0.02682,
-0.02975,
-0.03854,
-0.06784,
-0.10299,
-0.13815,
-0.17624,
-0.21432
],
[
-0.03268,
-0.02975,
-0.02682,
-0.02975,
-0.03854,
-0.06784,
-0.10006,
-0.13815,
-0.17331,
-0.21139
],
[
-0.02389,
-0.02096,
-0.01803,
-0.01803,
-0.02975,
-0.05612,
-0.09128,
-0.12643,
-0.16452,
-0.2026
],
[
-0.00924,
-0.00339,
-0.00046,
-0.00339,
-0.01217,
-0.04147,
-0.0737,
-0.10885,
-0.14694,
-0.18503
],
[
0.01126,
0.01419,
0.01712,
0.01712,
0.00833,
-0.02096,
-0.05612,
-0.09128,
-0.12643,
-0.16452
],
[
0.03177,
0.03763,
0.04056,
0.04056,
0.02884,
-0.00046,
-0.03268,
-0.06784,
-0.10592,
-0.14401
]
]
},
"timing_type": "hold_rising"
}
]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}