{
  "area": 39.96,
  "cell_footprint": "sdfxtp",
  "cell_leakage_power": 0.0,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "(D&!SCE) | (SCD&SCE)"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002819,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002671,
    "internal_power": {
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        "index_1": [
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          0.02602,
          0.03903,
          0.05855,
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          0.13172,
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          0.29634,
          0.44449,
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          1.5
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        "values": [
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      },
      "rise_power hidden_pwr_template13": {
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        "values": [
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    "max_transition": 1.0,
    "min_pulse_width_high": 0.130261,
    "min_pulse_width_low": 0.429055,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002966
  },
  "pin D": {
    "capacitance": 0.001857,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001726,
    "internal_power": {
      "fall_power hidden_pwr_template13": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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          0.0013947,
          0.0013937,
          0.0014063,
          0.0014393
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    },
    "max_transition": 1.0,
    "nextstate_type": "data",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001988,
    "timing": [
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        "fall_constraint vio_10_10_1": {
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        "related_pin": "CLK",
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint vio_10_10_1": {
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": {
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        "index_2": [
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        "values": [
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      "related_pin": "CLK",
      "rise_power pwr_template13x7": {
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              -0.043166,
              -0.0667663,
              -0.1115254,
              -0.1888366,
              -0.2478372,
              -0.2946309,
              -0.3365417,
              -0.372349
            ],
            [
              -0.0120462,
              -0.0199727,
              -0.0305521,
              -0.0541523,
              -0.0989115,
              -0.1762227,
              -0.2340026,
              -0.2820169,
              -0.322707,
              -0.3585143
            ],
            [
              -0.0018737,
              -0.0085794,
              -0.0203796,
              -0.0427591,
              -0.0875182,
              -0.1648294,
              -0.2226094,
              -0.2706237,
              -0.3113138,
              -0.3471211
            ]
          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "test_cell": {
    "ff IQ,IQ_N": {
      "clocked_on": "CLK",
      "next_state": "D"
    },
    "pin CLK": {
      "direction": "input"
    },
    "pin D": {
      "direction": "input"
    },
    "pin Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    }
  }
}