{
  "area": 46.3536,
  "cell_footprint": "sdfstp",
  "cell_leakage_power": 0.0,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "(D&!SCE) | (SCD&SCE)",
    "preset": "!SET_B"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002805,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002661,
    "internal_power": {
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
    "min_pulse_width_high": 0.144541,
    "min_pulse_width_low": 0.52133,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.002949
  },
  "pin D": {
    "capacitance": 0.001801,
    "clock": "false",
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    "fall_capacitance": 0.00168,
    "internal_power": {
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
    "nextstate_type": "data",
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001922,
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint vio_10_10_1": {
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": [
      {
        "fall_power scalar": {
          "values": [
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        },
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          "index_2": [
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      },
      {
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        "violation_delay_degrade_pct": 10
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        "fall_constraint vio_10_10_1": {
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        "rise_constraint vio_10_10_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
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    ]
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  "pin SET_B": {
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    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.003091,
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          0.03903,
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          0.08782,
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003246,
    "timing": [
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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              -0.1424499
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              -0.269403,
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              -0.2270853,
              -0.2169128,
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              -0.3174173,
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              -0.2763203,
              -0.2661478,
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              -0.2543477
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              -0.3170104,
              -0.3056172,
              -0.2991068,
              -0.2950378
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            [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "recovery_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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            0.5,
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          "index_2": [
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          "values": [
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            [
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            [
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            [
              0.340737,
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            [
              0.3887513,
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            [
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              0.4202943,
              0.4097148,
              0.3946595,
              0.3755351,
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              0.3344382,
              0.3230449,
              0.3165345,
              0.3112448
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            [
              0.4628073,
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              0.4443014,
              0.4292461,
              0.4101217,
              0.3853008,
              0.3690247,
              0.3576315,
              0.3511211,
              0.3458314
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            [
              0.4937318,
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              0.4752259,
              0.4601706,
              0.4410462,
              0.4162253,
              0.3999492,
              0.388556,
              0.3808249,
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          ]
        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "removal_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint pulse_width_template13": {
          "index_1": [
            0.01,
            0.01735,
            0.02602,
            0.03903,
            0.05855,
            0.08782,
            0.13172,
            0.19757,
            0.29634,
            0.44449,
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            1.0,
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          ],
          "values": [
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          ]
        },
        "related_output_pin": "Q",
        "related_pin": "SET_B",
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "min_pulse_width",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "test_cell": {
    "ff IQ,IQ_N": {
      "clocked_on": "CLK",
      "next_state": "D",
      "preset": "!SET_B"
    },
    "pin CLK": {
      "direction": "input"
    },
    "pin D": {
      "direction": "input"
    },
    "pin Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    },
    "pin SET_B": {
      "direction": "input"
    }
  }
}