| { |
| "area": 31.968, |
| "cell_footprint": "dfxtp", |
| "cell_leakage_power": 0.0, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "D" |
| }, |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPWR" |
| }, |
| "pin CLK": { |
| "capacitance": 0.002976, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002828, |
| "internal_power": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
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| 0.1285325 |
| ] |
| }, |
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| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "min_pulse_width_high": 0.067645, |
| "min_pulse_width_low": 0.119276, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.003125 |
| }, |
| "pin D": { |
| "capacitance": 0.001955, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.002099, |
| "internal_power": { |
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| 0.0439605 |
| ] |
| }, |
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| ], |
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| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00181, |
| "timing": [ |
| { |
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| [ |
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| [ |
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| [ |
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| [ |
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| 0.3478659, |
| 0.4019837, |
| 0.4536602 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint vio_10_10_1": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
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| 0.125, |
| 0.25, |
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| 0.75, |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "fall_constraint vio_10_10_1": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
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| }, |
| "related_pin": "CLK", |
| "rise_constraint vio_10_10_1": { |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin Q": { |
| "direction": "output", |
| "function": "IQ", |
| "internal_power": { |
| "fall_power pwr_template13x9": { |
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| 0.01, |
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