| { |
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| "cell_footprint": "dfxtp", |
| "cell_leakage_power": 0.0, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "D" |
| }, |
| "pg_pin VGND": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
| "pg_type": "primary_power", |
| "voltage_name": "VPWR" |
| }, |
| "pin CLK": { |
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| "clock": "true", |
| "direction": "input", |
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| "internal_power": { |
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| }, |
| "max_transition": 1.0, |
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| "min_pulse_width_low": 0.670728, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002582 |
| }, |
| "pin D": { |
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| "clock": "false", |
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| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
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| }, |
| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
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| }, |
| { |
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| } |
| ] |
| }, |
| "pin Q": { |
| "direction": "output", |
| "function": "IQ", |
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