{
  "area": 39.96,
  "cell_footprint": "dfstp",
  "cell_leakage_power": 0.0,
  "driver_waveform_fall": "ramp",
  "driver_waveform_rise": "ramp",
  "ff IQ,IQ_N": {
    "clocked_on": "CLK",
    "next_state": "D",
    "preset": "!SET_B"
  },
  "pg_pin VGND": {
    "pg_type": "primary_ground",
    "voltage_name": "VGND"
  },
  "pg_pin VNB": {
    "pg_type": "primary_ground",
    "voltage_name": "VNB"
  },
  "pg_pin VPB": {
    "pg_type": "primary_power",
    "voltage_name": "VPB"
  },
  "pg_pin VPWR": {
    "pg_type": "primary_power",
    "voltage_name": "VPWR"
  },
  "pin CLK": {
    "capacitance": 0.002865,
    "clock": "true",
    "direction": "input",
    "fall_capacitance": 0.002724,
    "internal_power": {
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          0.05855,
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          0.13172,
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          0.29634,
          0.44449,
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        "values": [
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      "rise_power hidden_pwr_template13": {
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    "max_transition": 1.0,
    "min_pulse_width_high": 0.16761,
    "min_pulse_width_low": 0.41807,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003007
  },
  "pin D": {
    "capacitance": 0.001705,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.001563,
    "internal_power": {
      "fall_power hidden_pwr_template13": {
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    },
    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.001847,
    "timing": [
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "setup_rising",
        "violation_delay_degrade_pct": 10
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      {
        "fall_constraint vio_10_10_1": {
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          ]
        },
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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          "values": [
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin Q": {
    "direction": "output",
    "function": "IQ",
    "internal_power": [
      {
        "fall_power scalar": {
          "values": [
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          ]
        },
        "related_pin": "SET_B",
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          "index_2": [
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          "values": [
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      },
      {
        "fall_power pwr_template13x7": {
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          "index_2": [
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              0.7619042,
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              0.0721383,
              0.1153069,
              0.2053237,
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              0.7614097,
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              0.1152863,
              0.2056618,
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        "timing_sense": "non_unate",
        "timing_type": "rising_edge"
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    "capacitance": 0.003164,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.003064,
    "internal_power": {
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        "values": [
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      "rise_power hidden_pwr_template13": {
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        "values": [
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    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003263,
    "timing": [
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        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "recovery_rising",
        "violation_delay_degrade_pct": 10
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      {
        "related_pin": "CLK",
        "rise_constraint vio_10_10_1": {
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            0.25,
            0.5,
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              0.4540671,
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              0.4211081,
              0.3999492,
              0.3848939,
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "removal_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint pulse_width_template13": {
          "index_1": [
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            0.01735,
            0.02602,
            0.03903,
            0.05855,
            0.08782,
            0.13172,
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            0.44449,
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          "values": [
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        },
        "related_output_pin": "Q",
        "related_pin": "SET_B",
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "min_pulse_width",
        "violation_delay_degrade_pct": 10
      }
    ]
  }
}