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  "area": 31.968,
  "cell_footprint": "sky130_fd_sc_ms__sdlclkp",
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  "clock_gating_integrated_cell": "latch_posedge_precontrol",
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    "voltage_name": "VGND"
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        "related_pin": "CLK",
        "rise_constraint,sethold_template_rise10x10": {
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        "timing_type": "setup_rising"
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      {
        "fall_constraint,sethold_template_fall10x10": {
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              -0.39286,
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        },
        "timing_type": "hold_rising"
      }
    ]
  },
  "statetable,CLK GATE SCE,M0": {
    "table": [
      "L L L : - : L",
      "L L H : - : H",
      "L H L : - : H",
      "L H H : - : H",
      "H - - : - : N"
    ]
  }
}