)]}'
{
  "commit": "d94c22085c9411f6e0643fbdcb97371de90c8238",
  "tree": "2022856eb941e986e05e0e601bf2bae925414911",
  "parents": [
    "89f626bf51b35cf4bf85bf8d7ea0c87df450f5d3",
    "ab46bcad7c521f54ddb18c3546559bb1d6cc4b38"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing include path.\n\nThe include lines previously had,\n`include \"sky130_fd_sc_hd__o221a.pp.functional.v\"`\nbut the actual filename is\n`include \"sky130_fd_sc_hd__o221a.functional.pp.v\"`.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
  "tree_diff": []
}