| { |
| "area": 54.3456, |
| "cell_footprint": "sky130_fd_sc_ms__sedfxtp", |
| "cell_leakage_power": 105.6292, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&DE&!SCE) | (IQ&!DE&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 76.841296, |
| "when": "!D&!SCE&!SCD&CLK" |
| }, |
| { |
| "value": 83.0683078, |
| "when": "D&!SCE&!SCD&CLK" |
| }, |
| { |
| "value": 149.9625029, |
| "when": "D&SCE&!SCD&CLK" |
| }, |
| { |
| "value": 94.1564977, |
| "when": "D&!SCE&SCD&CLK" |
| }, |
| { |
| "value": 108.5893899, |
| "when": "D&!SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 116.7658752, |
| "when": "!D&SCE&!SCD&CLK" |
| }, |
| { |
| "value": 95.9027346, |
| "when": "!D&!SCE&SCD&CLK" |
| }, |
| { |
| "value": 93.3054025, |
| "when": "!D&!SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 146.868004, |
| "when": "!D&SCE&SCD&CLK" |
| }, |
| { |
| "value": 96.5218803, |
| "when": "!D&SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 147.9456415, |
| "when": "D&SCE&SCD&CLK" |
| }, |
| { |
| "value": 97.6017702, |
| "when": "D&SCE&!SCD&!CLK" |
| }, |
| { |
| "value": 90.6926729, |
| "when": "D&!SCE&SCD&!CLK" |
| }, |
| { |
| "value": 105.9802628, |
| "when": "!D&SCE&SCD&!CLK" |
| }, |
| { |
| "value": 91.1022013, |
| "when": "D&SCE&SCD&!CLK" |
| }, |
| { |
| "value": 94.7622993, |
| "when": "!D&!SCE&SCD&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002736, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002638, |
| "internal_power": { |
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| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
| "values": [ |
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| 0.0235609, |
| 0.0233793, |
| 0.0232972, |
| 0.0232074, |
| 0.0234346, |
| 0.0238086, |
| 0.0248684, |
| 0.026491, |
| 0.0295703, |
| 0.0342219, |
| 0.0412322, |
| 0.0517822 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
| "values": [ |
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| 0.019762, |
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| 0.0221366, |
| 0.0253288, |
| 0.0301451, |
| 0.0373978, |
| 0.0483061 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "min_pulse_width_high": 0.178595, |
| "min_pulse_width_low": 0.175299, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002833 |
| }, |
| "pin,D": { |
| "capacitance": 0.00206, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.001947, |
| "internal_power": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
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| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
| "values": [ |
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| 0.0123381, |
| 0.0122054, |
| 0.0120381, |
| 0.0120946, |
| 0.0122106, |
| 0.0125228, |
| 0.0130226, |
| 0.0141017, |
| 0.0157519, |
| 0.0182585, |
| 0.0220502 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
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| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
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| ], |
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| 0.0105386, |
| 0.0116609, |
| 0.0133745, |
| 0.0159749, |
| 0.019906 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002172, |
| "timing": [ |
| { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
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| 0.5, |
| 0.75, |
| 1.0, |
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| [ |
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| [ |
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| [ |
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| 0.5049297, |
| 0.5602682, |
| 0.6119447, |
| 0.6575176 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
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| "index_2": [ |
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| 0.75, |
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| [ |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| "index_1": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
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| 0.75, |
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| [ |
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| [ |
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| [ |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
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| 0.75, |
| 1.0, |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
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| "timing_type": "hold_rising", |
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| } |
| ] |
| }, |
| "test_cell": { |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&DE) | (IQ&!DE)" |
| }, |
| "pin,CLK": { |
| "direction": "input" |
| }, |
| "pin,D": { |
| "direction": "input" |
| }, |
| "pin,DE": { |
| "direction": "input" |
| }, |
| "pin,Q": { |
| "direction": "output", |
| "function": "IQ", |
| "signal_type": "test_scan_out" |
| }, |
| "pin,SCD": { |
| "direction": "input", |
| "signal_type": "test_scan_in" |
| }, |
| "pin,SCE": { |
| "direction": "input", |
| "signal_type": "test_scan_enable" |
| } |
| } |
| } |
