tree 4989e4d48069ee613de7f0dd5596fe82808ef8bc
parent c3d24b3b50d46c552c712cc770f48ffbbc0bd07f
author Tim 'mithro' Ansell <me@mith.ro> 1601658062 -0700
committer Tim 'mithro' Ansell <tansell@google.com> 1601658062 -0700

verilog: Fixing ordering of ports in primitives.

Verilog requires the first signal in a primitive's pin list must be the output.

Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>