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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "hold_rising",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "pin,SET_B": {
    "capacitance": 0.003802,
    "clock": "false",
    "direction": "input",
    "fall_capacitance": 0.003724,
    "internal_power": {
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        "index_1": [
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        "values": [
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      "rise_power,hidden_pwr_template13": {
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        "values": [
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    "max_transition": 1.0,
    "related_ground_pin": "VGND",
    "related_power_pin": "VPWR",
    "rise_capacitance": 0.003879,
    "timing": [
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        "related_pin": "CLK",
        "rise_constraint,vio_10_10_1": {
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        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "recovery_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "related_pin": "CLK",
        "rise_constraint,vio_10_10_1": {
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          "values": [
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        },
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "removal_rising",
        "violation_delay_degrade_pct": 10
      },
      {
        "fall_constraint,pulse_width_template13": {
          "index_1": [
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          "values": [
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        },
        "related_output_pin": "Q",
        "related_pin": "SET_B",
        "sim_opt": "runlvl=5 accurate=1",
        "timing_type": "min_pulse_width",
        "violation_delay_degrade_pct": 10
      }
    ]
  },
  "test_cell": {
    "ff,IQ,IQ_N": {
      "clocked_on": "CLK",
      "next_state": "D",
      "preset": "!SET_B"
    },
    "pin,CLK": {
      "direction": "input"
    },
    "pin,D": {
      "direction": "input"
    },
    "pin,Q": {
      "direction": "output",
      "function": "IQ",
      "signal_type": "test_scan_out"
    },
    "pin,Q_N": {
      "direction": "output",
      "function": "IQ_N",
      "signal_type": "test_scan_out_inverted"
    },
    "pin,SCD": {
      "direction": "input",
      "signal_type": "test_scan_in"
    },
    "pin,SCE": {
      "direction": "input",
      "signal_type": "test_scan_enable"
    },
    "pin,SET_B": {
      "direction": "input"
    }
  }
}