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foss-eda-tools / skywater-pdk / libs / sky130_fd_sc_ms / 996ed051cd68601340734ee924fc3322e510e873 / . / cells / sdlclkp / sky130_fd_sc_ms__sdlclkp_2__tt_025C_1v80_ccsnoise.lib.json
blob: d84fb9d4864995ea4d3d46389a31e78f55ce27e2 [file] [log] [blame]
{
"area": 27.1728,
"cell_footprint": "sdlclkp",
"cell_leakage_power": 0.0,
"clock_gating_integrated_cell": "latch_posedge_precontrol",
"pg_pin VGND": {
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"voltage_name": "VGND"
},
"pg_pin VNB": {
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},
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},
"pg_pin VPWR": {
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},
"pin CLK": {
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]
]
},
"timing_type": "setup_rising"
},
{
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"index_1": [
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0.125,
0.25,
0.5,
0.75,
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],
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0.03125,
0.0625,
0.125,
0.25,
0.5,
0.75,
1.0,
1.25,
1.5
],
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},
"related_pin": "CLK",
"rise_constraint sethold_template_rise10x10": {
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0.01,
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0.0625,
0.125,
0.25,
0.5,
0.75,
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],
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],
[
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],
[
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],
[
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]
},
"timing_type": "hold_rising"
}
]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}