{
  "comp_attribute voltage_map": [
    [
      "VPWR",
      1.8
    ],
    [
      "VSS",
      0.0
    ],
    [
      "VGND",
      0.0
    ],
    [
      "VNB",
      0.0
    ],
    [
      "VPB",
      1.8
    ]
  ],
  "default_arc_mode": "worst_edges",
  "define": [
    {
      "attribute_name": "switching_power_split_model",
      "attribute_type": "string",
      "group_name": "library"
    },
    {
      "attribute_name": "driver_model",
      "attribute_type": "string",
      "group_name": "library"
    },
    {
      "attribute_name": "tran_timestep",
      "attribute_type": "string",
      "group_name": "library"
    },
    {
      "attribute_name": "leakage_sim_opt",
      "attribute_type": "string",
      "group_name": "library"
    },
    {
      "attribute_name": "default_arc_mode",
      "attribute_type": "string",
      "group_name": "library"
    },
    {
      "attribute_name": "def_sim_opt",
      "attribute_type": "string",
      "group_name": "library"
    },
    {
      "attribute_name": "simulator",
      "attribute_type": "string",
      "group_name": "library"
    },
    {
      "attribute_name": "violation_delay_degrade_pct",
      "attribute_type": "string",
      "group_name": "timing"
    },
    {
      "attribute_name": "sim_opt",
      "attribute_type": "string",
      "group_name": "timing"
    }
  ],
  "driver_model": "ramp",
  "leakage_sim_opt": "runlvl=5 accurate=1 method=gear absh=1e-14 absmos=1e-12 relmos=0.01 absi=1e-5 runlvl=5 accurate=1 method=gear absh=1e-14 absmos=1e-12 relmos=0.01 absi=1e-5 runlvl=5 accurate=1 method=gear absh=1e-14 absmos=1e-12 relmos=0.01 absi=1e-5",
  "lu_table_template delay_template13x11": {
    "index_1": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "index_2": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11
    ],
    "variable_1": "input_net_transition",
    "variable_2": "total_output_net_capacitance"
  },
  "lu_table_template delay_template13x13": {
    "index_1": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "index_2": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "variable_1": "input_net_transition",
    "variable_2": "total_output_net_capacitance"
  },
  "lu_table_template delay_template13x14": {
    "index_1": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "index_2": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13,
      14
    ],
    "variable_1": "input_net_transition",
    "variable_2": "total_output_net_capacitance"
  },
  "lu_table_template delay_template13x8": {
    "index_1": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "index_2": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8
    ],
    "variable_1": "input_net_transition",
    "variable_2": "total_output_net_capacitance"
  },
  "lu_table_template delay_template13x9": {
    "index_1": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "index_2": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9
    ],
    "variable_1": "input_net_transition",
    "variable_2": "total_output_net_capacitance"
  },
  "nom_temperature": 100.0,
  "nom_voltage": 1.8,
  "operating_conditions tt_100C_1v80": {
    "process": 1.0,
    "temperature": 100.0,
    "tree_type": "balanced_tree",
    "voltage": 1.8
  },
  "operating_conditions typ_ind": {
    "process": 1,
    "temperature": 100,
    "tree_type": "balanced_tree",
    "voltage": 1.8
  },
  "power_lut_template pwr_template13x11": {
    "index_1": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "index_2": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11
    ],
    "variable_1": "input_transition_time",
    "variable_2": "total_output_net_capacitance"
  },
  "power_lut_template pwr_template13x13": {
    "index_1": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "index_2": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "variable_1": "input_transition_time",
    "variable_2": "total_output_net_capacitance"
  },
  "power_lut_template pwr_template13x14": {
    "index_1": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "index_2": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13,
      14
    ],
    "variable_1": "input_transition_time",
    "variable_2": "total_output_net_capacitance"
  },
  "power_lut_template pwr_template13x8": {
    "index_1": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "index_2": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8
    ],
    "variable_1": "input_transition_time",
    "variable_2": "total_output_net_capacitance"
  },
  "power_lut_template pwr_template13x9": {
    "index_1": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9,
      10,
      11,
      12,
      13
    ],
    "index_2": [
      1,
      2,
      3,
      4,
      5,
      6,
      7,
      8,
      9
    ],
    "variable_1": "input_transition_time",
    "variable_2": "total_output_net_capacitance"
  },
  "switching_power_split_model": "true",
  "tran_timestep": 1e-12
}