blob: 4a47168f64cfae7641cd706bc72e4d5290a903e8 [file] [log] [blame]
{
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"clock_gating_integrated_cell": "latch_posedge_precontrol",
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"voltage_name": "VGND"
},
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"voltage_name": "VNB"
},
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},
"pg_pin VPWR": {
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},
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"state_function": "(CLK*M0)",
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-0.00503,
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-0.0812,
-0.1105
],
[
0.00083,
0.00376,
0.00669,
0.00669,
0.00083,
-0.01675,
-0.03726,
-0.06363,
-0.08999,
-0.11929
],
[
-0.01675,
-0.01382,
-0.01089,
-0.00796,
-0.01382,
-0.0314,
-0.05484,
-0.07828,
-0.10757,
-0.13394
],
[
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-0.02847,
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-0.04898,
-0.07242,
-0.09878,
-0.12515,
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],
[
-0.05777,
-0.05484,
-0.04898,
-0.04605,
-0.04898,
-0.06656,
-0.08999,
-0.11343,
-0.14273,
-0.1691
],
[
-0.06363,
-0.0607,
-0.05484,
-0.05191,
-0.05484,
-0.07242,
-0.09292,
-0.11929,
-0.14566,
-0.17496
],
[
-0.06363,
-0.05777,
-0.05484,
-0.05191,
-0.05191,
-0.06949,
-0.09292,
-0.11636,
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-0.17203
],
[
-0.05777,
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-0.06363,
-0.08413,
-0.1105,
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-0.16617
],
[
-0.04898,
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-0.03433,
-0.03726,
-0.05484,
-0.07535,
-0.10171,
-0.12808,
-0.15738
]
]
},
"timing_type": "hold_rising"
}
]
},
"statetable \"CLK GATE SCE\",\"M0\"": {
"table": "L L L : - : L ,L L H : - : H ,L H L : - : H ,L H H : - : H ,H - - : - : N"
}
}